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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Driver for the NVIDIA Tegra pinmux
0004  *
0005  * Copyright (c) 2011-2012, NVIDIA CORPORATION.  All rights reserved.
0006  *
0007  * Derived from code:
0008  * Copyright (C) 2010 Google, Inc.
0009  * Copyright (C) 2010 NVIDIA Corporation
0010  * Copyright (C) 2009-2011 ST-Ericsson AB
0011  */
0012 
0013 #include <linux/err.h>
0014 #include <linux/init.h>
0015 #include <linux/io.h>
0016 #include <linux/of.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/pinctrl/machine.h>
0019 #include <linux/pinctrl/pinctrl.h>
0020 #include <linux/pinctrl/pinmux.h>
0021 #include <linux/pinctrl/pinconf.h>
0022 #include <linux/slab.h>
0023 
0024 #include "../core.h"
0025 #include "../pinctrl-utils.h"
0026 #include "pinctrl-tegra.h"
0027 
0028 static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
0029 {
0030     return readl(pmx->regs[bank] + reg);
0031 }
0032 
0033 static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
0034 {
0035     writel_relaxed(val, pmx->regs[bank] + reg);
0036     /* make sure pinmux register write completed */
0037     pmx_readl(pmx, bank, reg);
0038 }
0039 
0040 static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
0041 {
0042     struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
0043 
0044     return pmx->soc->ngroups;
0045 }
0046 
0047 static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
0048                         unsigned group)
0049 {
0050     struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
0051 
0052     return pmx->soc->groups[group].name;
0053 }
0054 
0055 static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
0056                     unsigned group,
0057                     const unsigned **pins,
0058                     unsigned *num_pins)
0059 {
0060     struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
0061 
0062     *pins = pmx->soc->groups[group].pins;
0063     *num_pins = pmx->soc->groups[group].npins;
0064 
0065     return 0;
0066 }
0067 
0068 #ifdef CONFIG_DEBUG_FS
0069 static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
0070                        struct seq_file *s,
0071                        unsigned offset)
0072 {
0073     seq_printf(s, " %s", dev_name(pctldev->dev));
0074 }
0075 #endif
0076 
0077 static const struct cfg_param {
0078     const char *property;
0079     enum tegra_pinconf_param param;
0080 } cfg_params[] = {
0081     {"nvidia,pull",         TEGRA_PINCONF_PARAM_PULL},
0082     {"nvidia,tristate",     TEGRA_PINCONF_PARAM_TRISTATE},
0083     {"nvidia,enable-input",     TEGRA_PINCONF_PARAM_ENABLE_INPUT},
0084     {"nvidia,open-drain",       TEGRA_PINCONF_PARAM_OPEN_DRAIN},
0085     {"nvidia,lock",         TEGRA_PINCONF_PARAM_LOCK},
0086     {"nvidia,io-reset",     TEGRA_PINCONF_PARAM_IORESET},
0087     {"nvidia,rcv-sel",      TEGRA_PINCONF_PARAM_RCV_SEL},
0088     {"nvidia,io-hv",        TEGRA_PINCONF_PARAM_RCV_SEL},
0089     {"nvidia,high-speed-mode",  TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
0090     {"nvidia,schmitt",      TEGRA_PINCONF_PARAM_SCHMITT},
0091     {"nvidia,low-power-mode",   TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
0092     {"nvidia,pull-down-strength",   TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
0093     {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
0094     {"nvidia,slew-rate-falling",    TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
0095     {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
0096     {"nvidia,drive-type",       TEGRA_PINCONF_PARAM_DRIVE_TYPE},
0097 };
0098 
0099 static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
0100                        struct device_node *np,
0101                        struct pinctrl_map **map,
0102                        unsigned *reserved_maps,
0103                        unsigned *num_maps)
0104 {
0105     struct device *dev = pctldev->dev;
0106     int ret, i;
0107     const char *function;
0108     u32 val;
0109     unsigned long config;
0110     unsigned long *configs = NULL;
0111     unsigned num_configs = 0;
0112     unsigned reserve;
0113     struct property *prop;
0114     const char *group;
0115 
0116     ret = of_property_read_string(np, "nvidia,function", &function);
0117     if (ret < 0) {
0118         /* EINVAL=missing, which is fine since it's optional */
0119         if (ret != -EINVAL)
0120             dev_err(dev,
0121                 "could not parse property nvidia,function\n");
0122         function = NULL;
0123     }
0124 
0125     for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
0126         ret = of_property_read_u32(np, cfg_params[i].property, &val);
0127         if (!ret) {
0128             config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
0129             ret = pinctrl_utils_add_config(pctldev, &configs,
0130                     &num_configs, config);
0131             if (ret < 0)
0132                 goto exit;
0133         /* EINVAL=missing, which is fine since it's optional */
0134         } else if (ret != -EINVAL) {
0135             dev_err(dev, "could not parse property %s\n",
0136                 cfg_params[i].property);
0137         }
0138     }
0139 
0140     reserve = 0;
0141     if (function != NULL)
0142         reserve++;
0143     if (num_configs)
0144         reserve++;
0145     ret = of_property_count_strings(np, "nvidia,pins");
0146     if (ret < 0) {
0147         dev_err(dev, "could not parse property nvidia,pins\n");
0148         goto exit;
0149     }
0150     reserve *= ret;
0151 
0152     ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
0153                     num_maps, reserve);
0154     if (ret < 0)
0155         goto exit;
0156 
0157     of_property_for_each_string(np, "nvidia,pins", prop, group) {
0158         if (function) {
0159             ret = pinctrl_utils_add_map_mux(pctldev, map,
0160                     reserved_maps, num_maps, group,
0161                     function);
0162             if (ret < 0)
0163                 goto exit;
0164         }
0165 
0166         if (num_configs) {
0167             ret = pinctrl_utils_add_map_configs(pctldev, map,
0168                     reserved_maps, num_maps, group,
0169                     configs, num_configs,
0170                     PIN_MAP_TYPE_CONFIGS_GROUP);
0171             if (ret < 0)
0172                 goto exit;
0173         }
0174     }
0175 
0176     ret = 0;
0177 
0178 exit:
0179     kfree(configs);
0180     return ret;
0181 }
0182 
0183 static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
0184                     struct device_node *np_config,
0185                     struct pinctrl_map **map,
0186                     unsigned *num_maps)
0187 {
0188     unsigned reserved_maps;
0189     struct device_node *np;
0190     int ret;
0191 
0192     reserved_maps = 0;
0193     *map = NULL;
0194     *num_maps = 0;
0195 
0196     for_each_child_of_node(np_config, np) {
0197         ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
0198                               &reserved_maps, num_maps);
0199         if (ret < 0) {
0200             pinctrl_utils_free_map(pctldev, *map,
0201                 *num_maps);
0202             of_node_put(np);
0203             return ret;
0204         }
0205     }
0206 
0207     return 0;
0208 }
0209 
0210 static const struct pinctrl_ops tegra_pinctrl_ops = {
0211     .get_groups_count = tegra_pinctrl_get_groups_count,
0212     .get_group_name = tegra_pinctrl_get_group_name,
0213     .get_group_pins = tegra_pinctrl_get_group_pins,
0214 #ifdef CONFIG_DEBUG_FS
0215     .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
0216 #endif
0217     .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
0218     .dt_free_map = pinctrl_utils_free_map,
0219 };
0220 
0221 static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
0222 {
0223     struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
0224 
0225     return pmx->soc->nfunctions;
0226 }
0227 
0228 static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
0229                            unsigned function)
0230 {
0231     struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
0232 
0233     return pmx->soc->functions[function].name;
0234 }
0235 
0236 static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
0237                      unsigned function,
0238                      const char * const **groups,
0239                      unsigned * const num_groups)
0240 {
0241     struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
0242 
0243     *groups = pmx->soc->functions[function].groups;
0244     *num_groups = pmx->soc->functions[function].ngroups;
0245 
0246     return 0;
0247 }
0248 
0249 static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
0250                  unsigned function,
0251                  unsigned group)
0252 {
0253     struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
0254     const struct tegra_pingroup *g;
0255     int i;
0256     u32 val;
0257 
0258     g = &pmx->soc->groups[group];
0259 
0260     if (WARN_ON(g->mux_reg < 0))
0261         return -EINVAL;
0262 
0263     for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
0264         if (g->funcs[i] == function)
0265             break;
0266     }
0267     if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
0268         return -EINVAL;
0269 
0270     val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
0271     val &= ~(0x3 << g->mux_bit);
0272     val |= i << g->mux_bit;
0273     pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
0274 
0275     return 0;
0276 }
0277 
0278 static const struct tegra_pingroup *tegra_pinctrl_get_group(struct pinctrl_dev *pctldev,
0279                     unsigned int offset)
0280 {
0281     struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
0282     unsigned int group, num_pins, j;
0283     const unsigned int *pins;
0284     int ret;
0285 
0286     for (group = 0; group < pmx->soc->ngroups; ++group) {
0287         ret = tegra_pinctrl_get_group_pins(pctldev, group, &pins, &num_pins);
0288         if (ret < 0)
0289             continue;
0290         for (j = 0; j < num_pins; j++) {
0291             if (offset == pins[j])
0292                 return &pmx->soc->groups[group];
0293         }
0294     }
0295 
0296     dev_err(pctldev->dev, "Pingroup not found for pin %u\n", offset);
0297     return NULL;
0298 }
0299 
0300 static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
0301                          struct pinctrl_gpio_range *range,
0302                          unsigned int offset)
0303 {
0304     struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
0305     const struct tegra_pingroup *group;
0306     u32 value;
0307 
0308     if (!pmx->soc->sfsel_in_mux)
0309         return 0;
0310 
0311     group = tegra_pinctrl_get_group(pctldev, offset);
0312 
0313     if (!group)
0314         return -EINVAL;
0315 
0316     if (group->mux_reg < 0 || group->sfsel_bit < 0)
0317         return -EINVAL;
0318 
0319     value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
0320     value &= ~BIT(group->sfsel_bit);
0321     pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
0322 
0323     return 0;
0324 }
0325 
0326 static void tegra_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev,
0327                         struct pinctrl_gpio_range *range,
0328                         unsigned int offset)
0329 {
0330     struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
0331     const struct tegra_pingroup *group;
0332     u32 value;
0333 
0334     if (!pmx->soc->sfsel_in_mux)
0335         return;
0336 
0337     group = tegra_pinctrl_get_group(pctldev, offset);
0338 
0339     if (!group)
0340         return;
0341 
0342     if (group->mux_reg < 0 || group->sfsel_bit < 0)
0343         return;
0344 
0345     value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
0346     value |= BIT(group->sfsel_bit);
0347     pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
0348 }
0349 
0350 static const struct pinmux_ops tegra_pinmux_ops = {
0351     .get_functions_count = tegra_pinctrl_get_funcs_count,
0352     .get_function_name = tegra_pinctrl_get_func_name,
0353     .get_function_groups = tegra_pinctrl_get_func_groups,
0354     .set_mux = tegra_pinctrl_set_mux,
0355     .gpio_request_enable = tegra_pinctrl_gpio_request_enable,
0356     .gpio_disable_free = tegra_pinctrl_gpio_disable_free,
0357 };
0358 
0359 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
0360                  const struct tegra_pingroup *g,
0361                  enum tegra_pinconf_param param,
0362                  bool report_err,
0363                  s8 *bank, s32 *reg, s8 *bit, s8 *width)
0364 {
0365     switch (param) {
0366     case TEGRA_PINCONF_PARAM_PULL:
0367         *bank = g->pupd_bank;
0368         *reg = g->pupd_reg;
0369         *bit = g->pupd_bit;
0370         *width = 2;
0371         break;
0372     case TEGRA_PINCONF_PARAM_TRISTATE:
0373         *bank = g->tri_bank;
0374         *reg = g->tri_reg;
0375         *bit = g->tri_bit;
0376         *width = 1;
0377         break;
0378     case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
0379         *bank = g->mux_bank;
0380         *reg = g->mux_reg;
0381         *bit = g->einput_bit;
0382         *width = 1;
0383         break;
0384     case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
0385         *bank = g->mux_bank;
0386         *reg = g->mux_reg;
0387         *bit = g->odrain_bit;
0388         *width = 1;
0389         break;
0390     case TEGRA_PINCONF_PARAM_LOCK:
0391         *bank = g->mux_bank;
0392         *reg = g->mux_reg;
0393         *bit = g->lock_bit;
0394         *width = 1;
0395         break;
0396     case TEGRA_PINCONF_PARAM_IORESET:
0397         *bank = g->mux_bank;
0398         *reg = g->mux_reg;
0399         *bit = g->ioreset_bit;
0400         *width = 1;
0401         break;
0402     case TEGRA_PINCONF_PARAM_RCV_SEL:
0403         *bank = g->mux_bank;
0404         *reg = g->mux_reg;
0405         *bit = g->rcv_sel_bit;
0406         *width = 1;
0407         break;
0408     case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
0409         if (pmx->soc->hsm_in_mux) {
0410             *bank = g->mux_bank;
0411             *reg = g->mux_reg;
0412         } else {
0413             *bank = g->drv_bank;
0414             *reg = g->drv_reg;
0415         }
0416         *bit = g->hsm_bit;
0417         *width = 1;
0418         break;
0419     case TEGRA_PINCONF_PARAM_SCHMITT:
0420         if (pmx->soc->schmitt_in_mux) {
0421             *bank = g->mux_bank;
0422             *reg = g->mux_reg;
0423         } else {
0424             *bank = g->drv_bank;
0425             *reg = g->drv_reg;
0426         }
0427         *bit = g->schmitt_bit;
0428         *width = 1;
0429         break;
0430     case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
0431         *bank = g->drv_bank;
0432         *reg = g->drv_reg;
0433         *bit = g->lpmd_bit;
0434         *width = 2;
0435         break;
0436     case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
0437         *bank = g->drv_bank;
0438         *reg = g->drv_reg;
0439         *bit = g->drvdn_bit;
0440         *width = g->drvdn_width;
0441         break;
0442     case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
0443         *bank = g->drv_bank;
0444         *reg = g->drv_reg;
0445         *bit = g->drvup_bit;
0446         *width = g->drvup_width;
0447         break;
0448     case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
0449         *bank = g->drv_bank;
0450         *reg = g->drv_reg;
0451         *bit = g->slwf_bit;
0452         *width = g->slwf_width;
0453         break;
0454     case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
0455         *bank = g->drv_bank;
0456         *reg = g->drv_reg;
0457         *bit = g->slwr_bit;
0458         *width = g->slwr_width;
0459         break;
0460     case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
0461         if (pmx->soc->drvtype_in_mux) {
0462             *bank = g->mux_bank;
0463             *reg = g->mux_reg;
0464         } else {
0465             *bank = g->drv_bank;
0466             *reg = g->drv_reg;
0467         }
0468         *bit = g->drvtype_bit;
0469         *width = 2;
0470         break;
0471     default:
0472         dev_err(pmx->dev, "Invalid config param %04x\n", param);
0473         return -ENOTSUPP;
0474     }
0475 
0476     if (*reg < 0 || *bit < 0)  {
0477         if (report_err) {
0478             const char *prop = "unknown";
0479             int i;
0480 
0481             for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
0482                 if (cfg_params[i].param == param) {
0483                     prop = cfg_params[i].property;
0484                     break;
0485                 }
0486             }
0487 
0488             dev_err(pmx->dev,
0489                 "Config param %04x (%s) not supported on group %s\n",
0490                 param, prop, g->name);
0491         }
0492         return -ENOTSUPP;
0493     }
0494 
0495     return 0;
0496 }
0497 
0498 static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
0499                  unsigned pin, unsigned long *config)
0500 {
0501     dev_err(pctldev->dev, "pin_config_get op not supported\n");
0502     return -ENOTSUPP;
0503 }
0504 
0505 static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
0506                  unsigned pin, unsigned long *configs,
0507                  unsigned num_configs)
0508 {
0509     dev_err(pctldev->dev, "pin_config_set op not supported\n");
0510     return -ENOTSUPP;
0511 }
0512 
0513 static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
0514                    unsigned group, unsigned long *config)
0515 {
0516     struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
0517     enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
0518     u16 arg;
0519     const struct tegra_pingroup *g;
0520     int ret;
0521     s8 bank, bit, width;
0522     s32 reg;
0523     u32 val, mask;
0524 
0525     g = &pmx->soc->groups[group];
0526 
0527     ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
0528                 &width);
0529     if (ret < 0)
0530         return ret;
0531 
0532     val = pmx_readl(pmx, bank, reg);
0533     mask = (1 << width) - 1;
0534     arg = (val >> bit) & mask;
0535 
0536     *config = TEGRA_PINCONF_PACK(param, arg);
0537 
0538     return 0;
0539 }
0540 
0541 static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
0542                    unsigned group, unsigned long *configs,
0543                    unsigned num_configs)
0544 {
0545     struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
0546     enum tegra_pinconf_param param;
0547     u16 arg;
0548     const struct tegra_pingroup *g;
0549     int ret, i;
0550     s8 bank, bit, width;
0551     s32 reg;
0552     u32 val, mask;
0553 
0554     g = &pmx->soc->groups[group];
0555 
0556     for (i = 0; i < num_configs; i++) {
0557         param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
0558         arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
0559 
0560         ret = tegra_pinconf_reg(pmx, g, param, true, &bank, &reg, &bit,
0561                     &width);
0562         if (ret < 0)
0563             return ret;
0564 
0565         val = pmx_readl(pmx, bank, reg);
0566 
0567         /* LOCK can't be cleared */
0568         if (param == TEGRA_PINCONF_PARAM_LOCK) {
0569             if ((val & BIT(bit)) && !arg) {
0570                 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
0571                 return -EINVAL;
0572             }
0573         }
0574 
0575         /* Special-case Boolean values; allow any non-zero as true */
0576         if (width == 1)
0577             arg = !!arg;
0578 
0579         /* Range-check user-supplied value */
0580         mask = (1 << width) - 1;
0581         if (arg & ~mask) {
0582             dev_err(pctldev->dev,
0583                 "config %lx: %x too big for %d bit register\n",
0584                 configs[i], arg, width);
0585             return -EINVAL;
0586         }
0587 
0588         /* Update register */
0589         val &= ~(mask << bit);
0590         val |= arg << bit;
0591         pmx_writel(pmx, val, bank, reg);
0592     } /* for each config */
0593 
0594     return 0;
0595 }
0596 
0597 #ifdef CONFIG_DEBUG_FS
0598 static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
0599                    struct seq_file *s, unsigned offset)
0600 {
0601 }
0602 
0603 static const char *strip_prefix(const char *s)
0604 {
0605     const char *comma = strchr(s, ',');
0606     if (!comma)
0607         return s;
0608 
0609     return comma + 1;
0610 }
0611 
0612 static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
0613                      struct seq_file *s, unsigned group)
0614 {
0615     struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
0616     const struct tegra_pingroup *g;
0617     int i, ret;
0618     s8 bank, bit, width;
0619     s32 reg;
0620     u32 val;
0621 
0622     g = &pmx->soc->groups[group];
0623 
0624     for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
0625         ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
0626                     &bank, &reg, &bit, &width);
0627         if (ret < 0)
0628             continue;
0629 
0630         val = pmx_readl(pmx, bank, reg);
0631         val >>= bit;
0632         val &= (1 << width) - 1;
0633 
0634         seq_printf(s, "\n\t%s=%u",
0635                strip_prefix(cfg_params[i].property), val);
0636     }
0637 }
0638 
0639 static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
0640                       struct seq_file *s,
0641                       unsigned long config)
0642 {
0643     enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
0644     u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
0645     const char *pname = "unknown";
0646     int i;
0647 
0648     for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
0649         if (cfg_params[i].param == param) {
0650             pname = cfg_params[i].property;
0651             break;
0652         }
0653     }
0654 
0655     seq_printf(s, "%s=%d", strip_prefix(pname), arg);
0656 }
0657 #endif
0658 
0659 static const struct pinconf_ops tegra_pinconf_ops = {
0660     .pin_config_get = tegra_pinconf_get,
0661     .pin_config_set = tegra_pinconf_set,
0662     .pin_config_group_get = tegra_pinconf_group_get,
0663     .pin_config_group_set = tegra_pinconf_group_set,
0664 #ifdef CONFIG_DEBUG_FS
0665     .pin_config_dbg_show = tegra_pinconf_dbg_show,
0666     .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
0667     .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
0668 #endif
0669 };
0670 
0671 static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
0672     .name = "Tegra GPIOs",
0673     .id = 0,
0674     .base = 0,
0675 };
0676 
0677 static struct pinctrl_desc tegra_pinctrl_desc = {
0678     .pctlops = &tegra_pinctrl_ops,
0679     .pmxops = &tegra_pinmux_ops,
0680     .confops = &tegra_pinconf_ops,
0681     .owner = THIS_MODULE,
0682 };
0683 
0684 static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
0685 {
0686     int i = 0;
0687     const struct tegra_pingroup *g;
0688     u32 val;
0689 
0690     for (i = 0; i < pmx->soc->ngroups; ++i) {
0691         g = &pmx->soc->groups[i];
0692         if (g->parked_bitmask > 0) {
0693             unsigned int bank, reg;
0694 
0695             if (g->mux_reg != -1) {
0696                 bank = g->mux_bank;
0697                 reg = g->mux_reg;
0698             } else {
0699                 bank = g->drv_bank;
0700                 reg = g->drv_reg;
0701             }
0702 
0703             val = pmx_readl(pmx, bank, reg);
0704             val &= ~g->parked_bitmask;
0705             pmx_writel(pmx, val, bank, reg);
0706         }
0707     }
0708 }
0709 
0710 static size_t tegra_pinctrl_get_bank_size(struct device *dev,
0711                       unsigned int bank_id)
0712 {
0713     struct platform_device *pdev = to_platform_device(dev);
0714     struct resource *res;
0715 
0716     res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id);
0717 
0718     return resource_size(res) / 4;
0719 }
0720 
0721 static int tegra_pinctrl_suspend(struct device *dev)
0722 {
0723     struct tegra_pmx *pmx = dev_get_drvdata(dev);
0724     u32 *backup_regs = pmx->backup_regs;
0725     u32 __iomem *regs;
0726     size_t bank_size;
0727     unsigned int i, k;
0728 
0729     for (i = 0; i < pmx->nbanks; i++) {
0730         bank_size = tegra_pinctrl_get_bank_size(dev, i);
0731         regs = pmx->regs[i];
0732         for (k = 0; k < bank_size; k++)
0733             *backup_regs++ = readl_relaxed(regs++);
0734     }
0735 
0736     return pinctrl_force_sleep(pmx->pctl);
0737 }
0738 
0739 static int tegra_pinctrl_resume(struct device *dev)
0740 {
0741     struct tegra_pmx *pmx = dev_get_drvdata(dev);
0742     u32 *backup_regs = pmx->backup_regs;
0743     u32 __iomem *regs;
0744     size_t bank_size;
0745     unsigned int i, k;
0746 
0747     for (i = 0; i < pmx->nbanks; i++) {
0748         bank_size = tegra_pinctrl_get_bank_size(dev, i);
0749         regs = pmx->regs[i];
0750         for (k = 0; k < bank_size; k++)
0751             writel_relaxed(*backup_regs++, regs++);
0752     }
0753 
0754     /* flush all the prior writes */
0755     readl_relaxed(pmx->regs[0]);
0756     /* wait for pinctrl register read to complete */
0757     rmb();
0758     return 0;
0759 }
0760 
0761 const struct dev_pm_ops tegra_pinctrl_pm = {
0762     .suspend_noirq = &tegra_pinctrl_suspend,
0763     .resume_noirq = &tegra_pinctrl_resume
0764 };
0765 
0766 static bool tegra_pinctrl_gpio_node_has_range(struct tegra_pmx *pmx)
0767 {
0768     struct device_node *np;
0769     bool has_prop = false;
0770 
0771     np = of_find_compatible_node(NULL, NULL, pmx->soc->gpio_compatible);
0772     if (!np)
0773         return has_prop;
0774 
0775     has_prop = of_find_property(np, "gpio-ranges", NULL);
0776 
0777     of_node_put(np);
0778 
0779     return has_prop;
0780 }
0781 
0782 int tegra_pinctrl_probe(struct platform_device *pdev,
0783             const struct tegra_pinctrl_soc_data *soc_data)
0784 {
0785     struct tegra_pmx *pmx;
0786     struct resource *res;
0787     int i;
0788     const char **group_pins;
0789     int fn, gn, gfn;
0790     unsigned long backup_regs_size = 0;
0791 
0792     pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
0793     if (!pmx)
0794         return -ENOMEM;
0795 
0796     pmx->dev = &pdev->dev;
0797     pmx->soc = soc_data;
0798 
0799     /*
0800      * Each mux group will appear in 4 functions' list of groups.
0801      * This over-allocates slightly, since not all groups are mux groups.
0802      */
0803     pmx->group_pins = devm_kcalloc(&pdev->dev,
0804         soc_data->ngroups * 4, sizeof(*pmx->group_pins),
0805         GFP_KERNEL);
0806     if (!pmx->group_pins)
0807         return -ENOMEM;
0808 
0809     group_pins = pmx->group_pins;
0810     for (fn = 0; fn < soc_data->nfunctions; fn++) {
0811         struct tegra_function *func = &soc_data->functions[fn];
0812 
0813         func->groups = group_pins;
0814 
0815         for (gn = 0; gn < soc_data->ngroups; gn++) {
0816             const struct tegra_pingroup *g = &soc_data->groups[gn];
0817 
0818             if (g->mux_reg == -1)
0819                 continue;
0820 
0821             for (gfn = 0; gfn < 4; gfn++)
0822                 if (g->funcs[gfn] == fn)
0823                     break;
0824             if (gfn == 4)
0825                 continue;
0826 
0827             BUG_ON(group_pins - pmx->group_pins >=
0828                 soc_data->ngroups * 4);
0829             *group_pins++ = g->name;
0830             func->ngroups++;
0831         }
0832     }
0833 
0834     tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
0835     tegra_pinctrl_desc.name = dev_name(&pdev->dev);
0836     tegra_pinctrl_desc.pins = pmx->soc->pins;
0837     tegra_pinctrl_desc.npins = pmx->soc->npins;
0838 
0839     for (i = 0; ; i++) {
0840         res = platform_get_resource(pdev, IORESOURCE_MEM, i);
0841         if (!res)
0842             break;
0843         backup_regs_size += resource_size(res);
0844     }
0845     pmx->nbanks = i;
0846 
0847     pmx->regs = devm_kcalloc(&pdev->dev, pmx->nbanks, sizeof(*pmx->regs),
0848                  GFP_KERNEL);
0849     if (!pmx->regs)
0850         return -ENOMEM;
0851 
0852     pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size,
0853                     GFP_KERNEL);
0854     if (!pmx->backup_regs)
0855         return -ENOMEM;
0856 
0857     for (i = 0; i < pmx->nbanks; i++) {
0858         pmx->regs[i] = devm_platform_ioremap_resource(pdev, i);
0859         if (IS_ERR(pmx->regs[i]))
0860             return PTR_ERR(pmx->regs[i]);
0861     }
0862 
0863     pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
0864     if (IS_ERR(pmx->pctl)) {
0865         dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
0866         return PTR_ERR(pmx->pctl);
0867     }
0868 
0869     tegra_pinctrl_clear_parked_bits(pmx);
0870 
0871     if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx))
0872         pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
0873 
0874     platform_set_drvdata(pdev, pmx);
0875 
0876     dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
0877 
0878     return 0;
0879 }
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