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0001 /*
0002  * Allwinner A1X SoCs pinctrl driver.
0003  *
0004  * Copyright (C) 2012 Maxime Ripard
0005  *
0006  * Maxime Ripard <maxime.ripard@free-electrons.com>
0007  *
0008  * This file is licensed under the terms of the GNU General Public
0009  * License version 2.  This program is licensed "as is" without any
0010  * warranty of any kind, whether express or implied.
0011  */
0012 
0013 #include <linux/io.h>
0014 #include <linux/clk.h>
0015 #include <linux/gpio/driver.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/irqdomain.h>
0018 #include <linux/irqchip/chained_irq.h>
0019 #include <linux/export.h>
0020 #include <linux/of.h>
0021 #include <linux/of_clk.h>
0022 #include <linux/of_address.h>
0023 #include <linux/of_device.h>
0024 #include <linux/of_irq.h>
0025 #include <linux/pinctrl/consumer.h>
0026 #include <linux/pinctrl/machine.h>
0027 #include <linux/pinctrl/pinctrl.h>
0028 #include <linux/pinctrl/pinconf-generic.h>
0029 #include <linux/pinctrl/pinmux.h>
0030 #include <linux/regulator/consumer.h>
0031 #include <linux/platform_device.h>
0032 #include <linux/slab.h>
0033 
0034 #include <dt-bindings/pinctrl/sun4i-a10.h>
0035 
0036 #include "../core.h"
0037 #include "pinctrl-sunxi.h"
0038 
0039 /*
0040  * These lock classes tell lockdep that GPIO IRQs are in a different
0041  * category than their parents, so it won't report false recursion.
0042  */
0043 static struct lock_class_key sunxi_pinctrl_irq_lock_class;
0044 static struct lock_class_key sunxi_pinctrl_irq_request_class;
0045 
0046 static struct irq_chip sunxi_pinctrl_edge_irq_chip;
0047 static struct irq_chip sunxi_pinctrl_level_irq_chip;
0048 
0049 /*
0050  * The sunXi PIO registers are organized as a series of banks, with registers
0051  * for each bank in the following order:
0052  *  - Mux config
0053  *  - Data value
0054  *  - Drive level
0055  *  - Pull direction
0056  *
0057  * Multiple consecutive registers are used for fields wider than one bit.
0058  *
0059  * The following functions calculate the register and the bit offset to access.
0060  * They take a pin number which is relative to the start of the current device.
0061  */
0062 static void sunxi_mux_reg(const struct sunxi_pinctrl *pctl,
0063               u32 pin, u32 *reg, u32 *shift, u32 *mask)
0064 {
0065     u32 bank   = pin / PINS_PER_BANK;
0066     u32 offset = pin % PINS_PER_BANK * MUX_FIELD_WIDTH;
0067 
0068     *reg   = bank * pctl->bank_mem_size + MUX_REGS_OFFSET +
0069          offset / BITS_PER_TYPE(u32) * sizeof(u32);
0070     *shift = offset % BITS_PER_TYPE(u32);
0071     *mask  = (BIT(MUX_FIELD_WIDTH) - 1) << *shift;
0072 }
0073 
0074 static void sunxi_data_reg(const struct sunxi_pinctrl *pctl,
0075                u32 pin, u32 *reg, u32 *shift, u32 *mask)
0076 {
0077     u32 bank   = pin / PINS_PER_BANK;
0078     u32 offset = pin % PINS_PER_BANK * DATA_FIELD_WIDTH;
0079 
0080     *reg   = bank * pctl->bank_mem_size + DATA_REGS_OFFSET +
0081          offset / BITS_PER_TYPE(u32) * sizeof(u32);
0082     *shift = offset % BITS_PER_TYPE(u32);
0083     *mask  = (BIT(DATA_FIELD_WIDTH) - 1) << *shift;
0084 }
0085 
0086 static void sunxi_dlevel_reg(const struct sunxi_pinctrl *pctl,
0087                  u32 pin, u32 *reg, u32 *shift, u32 *mask)
0088 {
0089     u32 bank   = pin / PINS_PER_BANK;
0090     u32 offset = pin % PINS_PER_BANK * pctl->dlevel_field_width;
0091 
0092     *reg   = bank * pctl->bank_mem_size + DLEVEL_REGS_OFFSET +
0093          offset / BITS_PER_TYPE(u32) * sizeof(u32);
0094     *shift = offset % BITS_PER_TYPE(u32);
0095     *mask  = (BIT(pctl->dlevel_field_width) - 1) << *shift;
0096 }
0097 
0098 static void sunxi_pull_reg(const struct sunxi_pinctrl *pctl,
0099                u32 pin, u32 *reg, u32 *shift, u32 *mask)
0100 {
0101     u32 bank   = pin / PINS_PER_BANK;
0102     u32 offset = pin % PINS_PER_BANK * PULL_FIELD_WIDTH;
0103 
0104     *reg   = bank * pctl->bank_mem_size + pctl->pull_regs_offset +
0105          offset / BITS_PER_TYPE(u32) * sizeof(u32);
0106     *shift = offset % BITS_PER_TYPE(u32);
0107     *mask  = (BIT(PULL_FIELD_WIDTH) - 1) << *shift;
0108 }
0109 
0110 static struct sunxi_pinctrl_group *
0111 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group)
0112 {
0113     int i;
0114 
0115     for (i = 0; i < pctl->ngroups; i++) {
0116         struct sunxi_pinctrl_group *grp = pctl->groups + i;
0117 
0118         if (!strcmp(grp->name, group))
0119             return grp;
0120     }
0121 
0122     return NULL;
0123 }
0124 
0125 static struct sunxi_pinctrl_function *
0126 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl,
0127                     const char *name)
0128 {
0129     struct sunxi_pinctrl_function *func = pctl->functions;
0130     int i;
0131 
0132     for (i = 0; i < pctl->nfunctions; i++) {
0133         if (!func[i].name)
0134             break;
0135 
0136         if (!strcmp(func[i].name, name))
0137             return func + i;
0138     }
0139 
0140     return NULL;
0141 }
0142 
0143 static struct sunxi_desc_function *
0144 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl,
0145                      const char *pin_name,
0146                      const char *func_name)
0147 {
0148     int i;
0149 
0150     for (i = 0; i < pctl->desc->npins; i++) {
0151         const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
0152 
0153         if (!strcmp(pin->pin.name, pin_name)) {
0154             struct sunxi_desc_function *func = pin->functions;
0155 
0156             while (func->name) {
0157                 if (!strcmp(func->name, func_name) &&
0158                     (!func->variant ||
0159                     func->variant & pctl->variant))
0160                     return func;
0161 
0162                 func++;
0163             }
0164         }
0165     }
0166 
0167     return NULL;
0168 }
0169 
0170 static struct sunxi_desc_function *
0171 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl,
0172                     const u16 pin_num,
0173                     const char *func_name)
0174 {
0175     int i;
0176 
0177     for (i = 0; i < pctl->desc->npins; i++) {
0178         const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
0179 
0180         if (pin->pin.number == pin_num) {
0181             struct sunxi_desc_function *func = pin->functions;
0182 
0183             while (func->name) {
0184                 if (!strcmp(func->name, func_name))
0185                     return func;
0186 
0187                 func++;
0188             }
0189         }
0190     }
0191 
0192     return NULL;
0193 }
0194 
0195 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
0196 {
0197     struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0198 
0199     return pctl->ngroups;
0200 }
0201 
0202 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev,
0203                           unsigned group)
0204 {
0205     struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0206 
0207     return pctl->groups[group].name;
0208 }
0209 
0210 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
0211                       unsigned group,
0212                       const unsigned **pins,
0213                       unsigned *num_pins)
0214 {
0215     struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0216 
0217     *pins = (unsigned *)&pctl->groups[group].pin;
0218     *num_pins = 1;
0219 
0220     return 0;
0221 }
0222 
0223 static bool sunxi_pctrl_has_bias_prop(struct device_node *node)
0224 {
0225     return of_find_property(node, "bias-pull-up", NULL) ||
0226         of_find_property(node, "bias-pull-down", NULL) ||
0227         of_find_property(node, "bias-disable", NULL) ||
0228         of_find_property(node, "allwinner,pull", NULL);
0229 }
0230 
0231 static bool sunxi_pctrl_has_drive_prop(struct device_node *node)
0232 {
0233     return of_find_property(node, "drive-strength", NULL) ||
0234         of_find_property(node, "allwinner,drive", NULL);
0235 }
0236 
0237 static int sunxi_pctrl_parse_bias_prop(struct device_node *node)
0238 {
0239     u32 val;
0240 
0241     /* Try the new style binding */
0242     if (of_find_property(node, "bias-pull-up", NULL))
0243         return PIN_CONFIG_BIAS_PULL_UP;
0244 
0245     if (of_find_property(node, "bias-pull-down", NULL))
0246         return PIN_CONFIG_BIAS_PULL_DOWN;
0247 
0248     if (of_find_property(node, "bias-disable", NULL))
0249         return PIN_CONFIG_BIAS_DISABLE;
0250 
0251     /* And fall back to the old binding */
0252     if (of_property_read_u32(node, "allwinner,pull", &val))
0253         return -EINVAL;
0254 
0255     switch (val) {
0256     case SUN4I_PINCTRL_NO_PULL:
0257         return PIN_CONFIG_BIAS_DISABLE;
0258     case SUN4I_PINCTRL_PULL_UP:
0259         return PIN_CONFIG_BIAS_PULL_UP;
0260     case SUN4I_PINCTRL_PULL_DOWN:
0261         return PIN_CONFIG_BIAS_PULL_DOWN;
0262     }
0263 
0264     return -EINVAL;
0265 }
0266 
0267 static int sunxi_pctrl_parse_drive_prop(struct device_node *node)
0268 {
0269     u32 val;
0270 
0271     /* Try the new style binding */
0272     if (!of_property_read_u32(node, "drive-strength", &val)) {
0273         /* We can't go below 10mA ... */
0274         if (val < 10)
0275             return -EINVAL;
0276 
0277         /* ... and only up to 40 mA ... */
0278         if (val > 40)
0279             val = 40;
0280 
0281         /* by steps of 10 mA */
0282         return rounddown(val, 10);
0283     }
0284 
0285     /* And then fall back to the old binding */
0286     if (of_property_read_u32(node, "allwinner,drive", &val))
0287         return -EINVAL;
0288 
0289     return (val + 1) * 10;
0290 }
0291 
0292 static const char *sunxi_pctrl_parse_function_prop(struct device_node *node)
0293 {
0294     const char *function;
0295     int ret;
0296 
0297     /* Try the generic binding */
0298     ret = of_property_read_string(node, "function", &function);
0299     if (!ret)
0300         return function;
0301 
0302     /* And fall back to our legacy one */
0303     ret = of_property_read_string(node, "allwinner,function", &function);
0304     if (!ret)
0305         return function;
0306 
0307     return NULL;
0308 }
0309 
0310 static const char *sunxi_pctrl_find_pins_prop(struct device_node *node,
0311                           int *npins)
0312 {
0313     int count;
0314 
0315     /* Try the generic binding */
0316     count = of_property_count_strings(node, "pins");
0317     if (count > 0) {
0318         *npins = count;
0319         return "pins";
0320     }
0321 
0322     /* And fall back to our legacy one */
0323     count = of_property_count_strings(node, "allwinner,pins");
0324     if (count > 0) {
0325         *npins = count;
0326         return "allwinner,pins";
0327     }
0328 
0329     return NULL;
0330 }
0331 
0332 static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node,
0333                            unsigned int *len)
0334 {
0335     unsigned long *pinconfig;
0336     unsigned int configlen = 0, idx = 0;
0337     int ret;
0338 
0339     if (sunxi_pctrl_has_drive_prop(node))
0340         configlen++;
0341     if (sunxi_pctrl_has_bias_prop(node))
0342         configlen++;
0343 
0344     /*
0345      * If we don't have any configuration, bail out
0346      */
0347     if (!configlen)
0348         return NULL;
0349 
0350     pinconfig = kcalloc(configlen, sizeof(*pinconfig), GFP_KERNEL);
0351     if (!pinconfig)
0352         return ERR_PTR(-ENOMEM);
0353 
0354     if (sunxi_pctrl_has_drive_prop(node)) {
0355         int drive = sunxi_pctrl_parse_drive_prop(node);
0356         if (drive < 0) {
0357             ret = drive;
0358             goto err_free;
0359         }
0360 
0361         pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH,
0362                               drive);
0363     }
0364 
0365     if (sunxi_pctrl_has_bias_prop(node)) {
0366         int pull = sunxi_pctrl_parse_bias_prop(node);
0367         int arg = 0;
0368         if (pull < 0) {
0369             ret = pull;
0370             goto err_free;
0371         }
0372 
0373         if (pull != PIN_CONFIG_BIAS_DISABLE)
0374             arg = 1; /* hardware uses weak pull resistors */
0375 
0376         pinconfig[idx++] = pinconf_to_config_packed(pull, arg);
0377     }
0378 
0379 
0380     *len = configlen;
0381     return pinconfig;
0382 
0383 err_free:
0384     kfree(pinconfig);
0385     return ERR_PTR(ret);
0386 }
0387 
0388 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
0389                       struct device_node *node,
0390                       struct pinctrl_map **map,
0391                       unsigned *num_maps)
0392 {
0393     struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0394     unsigned long *pinconfig;
0395     struct property *prop;
0396     const char *function, *pin_prop;
0397     const char *group;
0398     int ret, npins, nmaps, configlen = 0, i = 0;
0399 
0400     *map = NULL;
0401     *num_maps = 0;
0402 
0403     function = sunxi_pctrl_parse_function_prop(node);
0404     if (!function) {
0405         dev_err(pctl->dev, "missing function property in node %pOFn\n",
0406             node);
0407         return -EINVAL;
0408     }
0409 
0410     pin_prop = sunxi_pctrl_find_pins_prop(node, &npins);
0411     if (!pin_prop) {
0412         dev_err(pctl->dev, "missing pins property in node %pOFn\n",
0413             node);
0414         return -EINVAL;
0415     }
0416 
0417     /*
0418      * We have two maps for each pin: one for the function, one
0419      * for the configuration (bias, strength, etc).
0420      *
0421      * We might be slightly overshooting, since we might not have
0422      * any configuration.
0423      */
0424     nmaps = npins * 2;
0425     *map = kmalloc_array(nmaps, sizeof(struct pinctrl_map), GFP_KERNEL);
0426     if (!*map)
0427         return -ENOMEM;
0428 
0429     pinconfig = sunxi_pctrl_build_pin_config(node, &configlen);
0430     if (IS_ERR(pinconfig)) {
0431         ret = PTR_ERR(pinconfig);
0432         goto err_free_map;
0433     }
0434 
0435     of_property_for_each_string(node, pin_prop, prop, group) {
0436         struct sunxi_pinctrl_group *grp =
0437             sunxi_pinctrl_find_group_by_name(pctl, group);
0438 
0439         if (!grp) {
0440             dev_err(pctl->dev, "unknown pin %s", group);
0441             continue;
0442         }
0443 
0444         if (!sunxi_pinctrl_desc_find_function_by_name(pctl,
0445                                   grp->name,
0446                                   function)) {
0447             dev_err(pctl->dev, "unsupported function %s on pin %s",
0448                 function, group);
0449             continue;
0450         }
0451 
0452         (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
0453         (*map)[i].data.mux.group = group;
0454         (*map)[i].data.mux.function = function;
0455 
0456         i++;
0457 
0458         if (pinconfig) {
0459             (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP;
0460             (*map)[i].data.configs.group_or_pin = group;
0461             (*map)[i].data.configs.configs = pinconfig;
0462             (*map)[i].data.configs.num_configs = configlen;
0463             i++;
0464         }
0465     }
0466 
0467     *num_maps = i;
0468 
0469     /*
0470      * We know have the number of maps we need, we can resize our
0471      * map array
0472      */
0473     *map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL);
0474     if (!*map)
0475         return -ENOMEM;
0476 
0477     return 0;
0478 
0479 err_free_map:
0480     kfree(*map);
0481     *map = NULL;
0482     return ret;
0483 }
0484 
0485 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
0486                     struct pinctrl_map *map,
0487                     unsigned num_maps)
0488 {
0489     int i;
0490 
0491     /* pin config is never in the first map */
0492     for (i = 1; i < num_maps; i++) {
0493         if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP)
0494             continue;
0495 
0496         /*
0497          * All the maps share the same pin config,
0498          * free only the first one we find.
0499          */
0500         kfree(map[i].data.configs.configs);
0501         break;
0502     }
0503 
0504     kfree(map);
0505 }
0506 
0507 static const struct pinctrl_ops sunxi_pctrl_ops = {
0508     .dt_node_to_map     = sunxi_pctrl_dt_node_to_map,
0509     .dt_free_map        = sunxi_pctrl_dt_free_map,
0510     .get_groups_count   = sunxi_pctrl_get_groups_count,
0511     .get_group_name     = sunxi_pctrl_get_group_name,
0512     .get_group_pins     = sunxi_pctrl_get_group_pins,
0513 };
0514 
0515 static int sunxi_pconf_reg(const struct sunxi_pinctrl *pctl,
0516                u32 pin, enum pin_config_param param,
0517                u32 *reg, u32 *shift, u32 *mask)
0518 {
0519     switch (param) {
0520     case PIN_CONFIG_DRIVE_STRENGTH:
0521         sunxi_dlevel_reg(pctl, pin, reg, shift, mask);
0522         break;
0523 
0524     case PIN_CONFIG_BIAS_PULL_UP:
0525     case PIN_CONFIG_BIAS_PULL_DOWN:
0526     case PIN_CONFIG_BIAS_DISABLE:
0527         sunxi_pull_reg(pctl, pin, reg, shift, mask);
0528         break;
0529 
0530     default:
0531         return -ENOTSUPP;
0532     }
0533 
0534     return 0;
0535 }
0536 
0537 static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
0538                unsigned long *config)
0539 {
0540     struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0541     enum pin_config_param param = pinconf_to_config_param(*config);
0542     u32 reg, shift, mask, val;
0543     u16 arg;
0544     int ret;
0545 
0546     pin -= pctl->desc->pin_base;
0547 
0548     ret = sunxi_pconf_reg(pctl, pin, param, &reg, &shift, &mask);
0549     if (ret < 0)
0550         return ret;
0551 
0552     val = (readl(pctl->membase + reg) & mask) >> shift;
0553 
0554     switch (pinconf_to_config_param(*config)) {
0555     case PIN_CONFIG_DRIVE_STRENGTH:
0556         arg = (val + 1) * 10;
0557         break;
0558 
0559     case PIN_CONFIG_BIAS_PULL_UP:
0560         if (val != SUN4I_PINCTRL_PULL_UP)
0561             return -EINVAL;
0562         arg = 1; /* hardware is weak pull-up */
0563         break;
0564 
0565     case PIN_CONFIG_BIAS_PULL_DOWN:
0566         if (val != SUN4I_PINCTRL_PULL_DOWN)
0567             return -EINVAL;
0568         arg = 1; /* hardware is weak pull-down */
0569         break;
0570 
0571     case PIN_CONFIG_BIAS_DISABLE:
0572         if (val != SUN4I_PINCTRL_NO_PULL)
0573             return -EINVAL;
0574         arg = 0;
0575         break;
0576 
0577     default:
0578         /* sunxi_pconf_reg should catch anything unsupported */
0579         WARN_ON(1);
0580         return -ENOTSUPP;
0581     }
0582 
0583     *config = pinconf_to_config_packed(param, arg);
0584 
0585     return 0;
0586 }
0587 
0588 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev,
0589                  unsigned group,
0590                  unsigned long *config)
0591 {
0592     struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0593     struct sunxi_pinctrl_group *g = &pctl->groups[group];
0594 
0595     /* We only support 1 pin per group. Chain it to the pin callback */
0596     return sunxi_pconf_get(pctldev, g->pin, config);
0597 }
0598 
0599 static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
0600                unsigned long *configs, unsigned num_configs)
0601 {
0602     struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0603     int i;
0604 
0605     pin -= pctl->desc->pin_base;
0606 
0607     for (i = 0; i < num_configs; i++) {
0608         u32 arg, reg, shift, mask, val;
0609         enum pin_config_param param;
0610         unsigned long flags;
0611         int ret;
0612 
0613         param = pinconf_to_config_param(configs[i]);
0614         arg = pinconf_to_config_argument(configs[i]);
0615 
0616         ret = sunxi_pconf_reg(pctl, pin, param, &reg, &shift, &mask);
0617         if (ret < 0)
0618             return ret;
0619 
0620         switch (param) {
0621         case PIN_CONFIG_DRIVE_STRENGTH:
0622             if (arg < 10 || arg > 40)
0623                 return -EINVAL;
0624             /*
0625              * We convert from mA to what the register expects:
0626              *   0: 10mA
0627              *   1: 20mA
0628              *   2: 30mA
0629              *   3: 40mA
0630              */
0631             val = arg / 10 - 1;
0632             break;
0633         case PIN_CONFIG_BIAS_DISABLE:
0634             val = 0;
0635             break;
0636         case PIN_CONFIG_BIAS_PULL_UP:
0637             if (arg == 0)
0638                 return -EINVAL;
0639             val = 1;
0640             break;
0641         case PIN_CONFIG_BIAS_PULL_DOWN:
0642             if (arg == 0)
0643                 return -EINVAL;
0644             val = 2;
0645             break;
0646         default:
0647             /* sunxi_pconf_reg should catch anything unsupported */
0648             WARN_ON(1);
0649             return -ENOTSUPP;
0650         }
0651 
0652         raw_spin_lock_irqsave(&pctl->lock, flags);
0653         writel((readl(pctl->membase + reg) & ~mask) | val << shift,
0654                pctl->membase + reg);
0655         raw_spin_unlock_irqrestore(&pctl->lock, flags);
0656     } /* for each config */
0657 
0658     return 0;
0659 }
0660 
0661 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
0662                  unsigned long *configs, unsigned num_configs)
0663 {
0664     struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0665     struct sunxi_pinctrl_group *g = &pctl->groups[group];
0666 
0667     /* We only support 1 pin per group. Chain it to the pin callback */
0668     return sunxi_pconf_set(pctldev, g->pin, configs, num_configs);
0669 }
0670 
0671 static const struct pinconf_ops sunxi_pconf_ops = {
0672     .is_generic     = true,
0673     .pin_config_get     = sunxi_pconf_get,
0674     .pin_config_set     = sunxi_pconf_set,
0675     .pin_config_group_get   = sunxi_pconf_group_get,
0676     .pin_config_group_set   = sunxi_pconf_group_set,
0677 };
0678 
0679 static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
0680                      unsigned pin,
0681                      struct regulator *supply)
0682 {
0683     unsigned short bank;
0684     unsigned long flags;
0685     u32 val, reg;
0686     int uV;
0687 
0688     if (!pctl->desc->io_bias_cfg_variant)
0689         return 0;
0690 
0691     uV = regulator_get_voltage(supply);
0692     if (uV < 0)
0693         return uV;
0694 
0695     /* Might be dummy regulator with no voltage set */
0696     if (uV == 0)
0697         return 0;
0698 
0699     pin -= pctl->desc->pin_base;
0700     bank = pin / PINS_PER_BANK;
0701 
0702     switch (pctl->desc->io_bias_cfg_variant) {
0703     case BIAS_VOLTAGE_GRP_CONFIG:
0704         /*
0705          * Configured value must be equal or greater to actual
0706          * voltage.
0707          */
0708         if (uV <= 1800000)
0709             val = 0x0; /* 1.8V */
0710         else if (uV <= 2500000)
0711             val = 0x6; /* 2.5V */
0712         else if (uV <= 2800000)
0713             val = 0x9; /* 2.8V */
0714         else if (uV <= 3000000)
0715             val = 0xA; /* 3.0V */
0716         else
0717             val = 0xD; /* 3.3V */
0718 
0719         reg = readl(pctl->membase + sunxi_grp_config_reg(pin));
0720         reg &= ~IO_BIAS_MASK;
0721         writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));
0722         return 0;
0723     case BIAS_VOLTAGE_PIO_POW_MODE_CTL:
0724         val = uV > 1800000 && uV <= 2500000 ? BIT(bank) : 0;
0725 
0726         raw_spin_lock_irqsave(&pctl->lock, flags);
0727         reg = readl(pctl->membase + PIO_POW_MOD_CTL_REG);
0728         reg &= ~BIT(bank);
0729         writel(reg | val, pctl->membase + PIO_POW_MOD_CTL_REG);
0730         raw_spin_unlock_irqrestore(&pctl->lock, flags);
0731 
0732         fallthrough;
0733     case BIAS_VOLTAGE_PIO_POW_MODE_SEL:
0734         val = uV <= 1800000 ? 1 : 0;
0735 
0736         raw_spin_lock_irqsave(&pctl->lock, flags);
0737         reg = readl(pctl->membase + PIO_POW_MOD_SEL_REG);
0738         reg &= ~(1 << bank);
0739         writel(reg | val << bank, pctl->membase + PIO_POW_MOD_SEL_REG);
0740         raw_spin_unlock_irqrestore(&pctl->lock, flags);
0741         return 0;
0742     default:
0743         return -EINVAL;
0744     }
0745 }
0746 
0747 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
0748 {
0749     struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0750 
0751     return pctl->nfunctions;
0752 }
0753 
0754 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev,
0755                        unsigned function)
0756 {
0757     struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0758 
0759     return pctl->functions[function].name;
0760 }
0761 
0762 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev,
0763                      unsigned function,
0764                      const char * const **groups,
0765                      unsigned * const num_groups)
0766 {
0767     struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0768 
0769     *groups = pctl->functions[function].groups;
0770     *num_groups = pctl->functions[function].ngroups;
0771 
0772     return 0;
0773 }
0774 
0775 static void sunxi_pmx_set(struct pinctrl_dev *pctldev,
0776                  unsigned pin,
0777                  u8 config)
0778 {
0779     struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0780     u32 reg, shift, mask;
0781     unsigned long flags;
0782 
0783     pin -= pctl->desc->pin_base;
0784     sunxi_mux_reg(pctl, pin, &reg, &shift, &mask);
0785 
0786     raw_spin_lock_irqsave(&pctl->lock, flags);
0787 
0788     writel((readl(pctl->membase + reg) & ~mask) | config << shift,
0789            pctl->membase + reg);
0790 
0791     raw_spin_unlock_irqrestore(&pctl->lock, flags);
0792 }
0793 
0794 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev,
0795                  unsigned function,
0796                  unsigned group)
0797 {
0798     struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0799     struct sunxi_pinctrl_group *g = pctl->groups + group;
0800     struct sunxi_pinctrl_function *func = pctl->functions + function;
0801     struct sunxi_desc_function *desc =
0802         sunxi_pinctrl_desc_find_function_by_name(pctl,
0803                              g->name,
0804                              func->name);
0805 
0806     if (!desc)
0807         return -EINVAL;
0808 
0809     sunxi_pmx_set(pctldev, g->pin, desc->muxval);
0810 
0811     return 0;
0812 }
0813 
0814 static int
0815 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
0816             struct pinctrl_gpio_range *range,
0817             unsigned offset,
0818             bool input)
0819 {
0820     struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0821     struct sunxi_desc_function *desc;
0822     const char *func;
0823 
0824     if (input)
0825         func = "gpio_in";
0826     else
0827         func = "gpio_out";
0828 
0829     desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func);
0830     if (!desc)
0831         return -EINVAL;
0832 
0833     sunxi_pmx_set(pctldev, offset, desc->muxval);
0834 
0835     return 0;
0836 }
0837 
0838 static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset)
0839 {
0840     struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0841     unsigned short bank = offset / PINS_PER_BANK;
0842     unsigned short bank_offset = bank - pctl->desc->pin_base /
0843                         PINS_PER_BANK;
0844     struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
0845     struct regulator *reg = s_reg->regulator;
0846     char supply[16];
0847     int ret;
0848 
0849     if (reg) {
0850         refcount_inc(&s_reg->refcount);
0851         return 0;
0852     }
0853 
0854     snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank);
0855     reg = regulator_get(pctl->dev, supply);
0856     if (IS_ERR(reg))
0857         return dev_err_probe(pctl->dev, PTR_ERR(reg),
0858                      "Couldn't get bank P%c regulator\n",
0859                      'A' + bank);
0860 
0861     ret = regulator_enable(reg);
0862     if (ret) {
0863         dev_err(pctl->dev,
0864             "Couldn't enable bank P%c regulator\n", 'A' + bank);
0865         goto out;
0866     }
0867 
0868     sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg);
0869 
0870     s_reg->regulator = reg;
0871     refcount_set(&s_reg->refcount, 1);
0872 
0873     return 0;
0874 
0875 out:
0876     regulator_put(s_reg->regulator);
0877 
0878     return ret;
0879 }
0880 
0881 static int sunxi_pmx_free(struct pinctrl_dev *pctldev, unsigned offset)
0882 {
0883     struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0884     unsigned short bank = offset / PINS_PER_BANK;
0885     unsigned short bank_offset = bank - pctl->desc->pin_base /
0886                         PINS_PER_BANK;
0887     struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset];
0888 
0889     if (!refcount_dec_and_test(&s_reg->refcount))
0890         return 0;
0891 
0892     regulator_disable(s_reg->regulator);
0893     regulator_put(s_reg->regulator);
0894     s_reg->regulator = NULL;
0895 
0896     return 0;
0897 }
0898 
0899 static const struct pinmux_ops sunxi_pmx_ops = {
0900     .get_functions_count    = sunxi_pmx_get_funcs_cnt,
0901     .get_function_name  = sunxi_pmx_get_func_name,
0902     .get_function_groups    = sunxi_pmx_get_func_groups,
0903     .set_mux        = sunxi_pmx_set_mux,
0904     .gpio_set_direction = sunxi_pmx_gpio_set_direction,
0905     .request        = sunxi_pmx_request,
0906     .free           = sunxi_pmx_free,
0907     .strict         = true,
0908 };
0909 
0910 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip,
0911                     unsigned offset)
0912 {
0913     struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
0914 
0915     return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL,
0916                         chip->base + offset, true);
0917 }
0918 
0919 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
0920 {
0921     struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
0922     bool set_mux = pctl->desc->irq_read_needs_mux &&
0923         gpiochip_line_is_irq(chip, offset);
0924     u32 pin = offset + chip->base;
0925     u32 reg, shift, mask, val;
0926 
0927     sunxi_data_reg(pctl, offset, &reg, &shift, &mask);
0928 
0929     if (set_mux)
0930         sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT);
0931 
0932     val = (readl(pctl->membase + reg) & mask) >> shift;
0933 
0934     if (set_mux)
0935         sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ);
0936 
0937     return val;
0938 }
0939 
0940 static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
0941                 unsigned offset, int value)
0942 {
0943     struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
0944     u32 reg, shift, mask, val;
0945     unsigned long flags;
0946 
0947     sunxi_data_reg(pctl, offset, &reg, &shift, &mask);
0948 
0949     raw_spin_lock_irqsave(&pctl->lock, flags);
0950 
0951     val = readl(pctl->membase + reg);
0952 
0953     if (value)
0954         val |= mask;
0955     else
0956         val &= ~mask;
0957 
0958     writel(val, pctl->membase + reg);
0959 
0960     raw_spin_unlock_irqrestore(&pctl->lock, flags);
0961 }
0962 
0963 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
0964                     unsigned offset, int value)
0965 {
0966     struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
0967 
0968     sunxi_pinctrl_gpio_set(chip, offset, value);
0969     return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL,
0970                         chip->base + offset, false);
0971 }
0972 
0973 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
0974                 const struct of_phandle_args *gpiospec,
0975                 u32 *flags)
0976 {
0977     int pin, base;
0978 
0979     base = PINS_PER_BANK * gpiospec->args[0];
0980     pin = base + gpiospec->args[1];
0981 
0982     if (pin > gc->ngpio)
0983         return -EINVAL;
0984 
0985     if (flags)
0986         *flags = gpiospec->args[2];
0987 
0988     return pin;
0989 }
0990 
0991 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
0992 {
0993     struct sunxi_pinctrl *pctl = gpiochip_get_data(chip);
0994     struct sunxi_desc_function *desc;
0995     unsigned pinnum = pctl->desc->pin_base + offset;
0996     unsigned irqnum;
0997 
0998     if (offset >= chip->ngpio)
0999         return -ENXIO;
1000 
1001     desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq");
1002     if (!desc)
1003         return -EINVAL;
1004 
1005     irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum;
1006 
1007     dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n",
1008         chip->label, offset + chip->base, irqnum);
1009 
1010     return irq_find_mapping(pctl->domain, irqnum);
1011 }
1012 
1013 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d)
1014 {
1015     struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1016     struct sunxi_desc_function *func;
1017     int ret;
1018 
1019     func = sunxi_pinctrl_desc_find_function_by_pin(pctl,
1020                     pctl->irq_array[d->hwirq], "irq");
1021     if (!func)
1022         return -EINVAL;
1023 
1024     ret = gpiochip_lock_as_irq(pctl->chip,
1025             pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
1026     if (ret) {
1027         dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
1028             irqd_to_hwirq(d));
1029         return ret;
1030     }
1031 
1032     /* Change muxing to INT mode */
1033     sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval);
1034 
1035     return 0;
1036 }
1037 
1038 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d)
1039 {
1040     struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1041 
1042     gpiochip_unlock_as_irq(pctl->chip,
1043                   pctl->irq_array[d->hwirq] - pctl->desc->pin_base);
1044 }
1045 
1046 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type)
1047 {
1048     struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1049     u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq);
1050     u8 index = sunxi_irq_cfg_offset(d->hwirq);
1051     unsigned long flags;
1052     u32 regval;
1053     u8 mode;
1054 
1055     switch (type) {
1056     case IRQ_TYPE_EDGE_RISING:
1057         mode = IRQ_EDGE_RISING;
1058         break;
1059     case IRQ_TYPE_EDGE_FALLING:
1060         mode = IRQ_EDGE_FALLING;
1061         break;
1062     case IRQ_TYPE_EDGE_BOTH:
1063         mode = IRQ_EDGE_BOTH;
1064         break;
1065     case IRQ_TYPE_LEVEL_HIGH:
1066         mode = IRQ_LEVEL_HIGH;
1067         break;
1068     case IRQ_TYPE_LEVEL_LOW:
1069         mode = IRQ_LEVEL_LOW;
1070         break;
1071     default:
1072         return -EINVAL;
1073     }
1074 
1075     raw_spin_lock_irqsave(&pctl->lock, flags);
1076 
1077     if (type & IRQ_TYPE_LEVEL_MASK)
1078         irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip,
1079                          handle_fasteoi_irq, NULL);
1080     else
1081         irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip,
1082                          handle_edge_irq, NULL);
1083 
1084     regval = readl(pctl->membase + reg);
1085     regval &= ~(IRQ_CFG_IRQ_MASK << index);
1086     writel(regval | (mode << index), pctl->membase + reg);
1087 
1088     raw_spin_unlock_irqrestore(&pctl->lock, flags);
1089 
1090     return 0;
1091 }
1092 
1093 static void sunxi_pinctrl_irq_ack(struct irq_data *d)
1094 {
1095     struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1096     u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq);
1097     u8 status_idx = sunxi_irq_status_offset(d->hwirq);
1098 
1099     /* Clear the IRQ */
1100     writel(1 << status_idx, pctl->membase + status_reg);
1101 }
1102 
1103 static void sunxi_pinctrl_irq_mask(struct irq_data *d)
1104 {
1105     struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1106     u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1107     u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1108     unsigned long flags;
1109     u32 val;
1110 
1111     raw_spin_lock_irqsave(&pctl->lock, flags);
1112 
1113     /* Mask the IRQ */
1114     val = readl(pctl->membase + reg);
1115     writel(val & ~(1 << idx), pctl->membase + reg);
1116 
1117     raw_spin_unlock_irqrestore(&pctl->lock, flags);
1118 }
1119 
1120 static void sunxi_pinctrl_irq_unmask(struct irq_data *d)
1121 {
1122     struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1123     u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq);
1124     u8 idx = sunxi_irq_ctrl_offset(d->hwirq);
1125     unsigned long flags;
1126     u32 val;
1127 
1128     raw_spin_lock_irqsave(&pctl->lock, flags);
1129 
1130     /* Unmask the IRQ */
1131     val = readl(pctl->membase + reg);
1132     writel(val | (1 << idx), pctl->membase + reg);
1133 
1134     raw_spin_unlock_irqrestore(&pctl->lock, flags);
1135 }
1136 
1137 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d)
1138 {
1139     sunxi_pinctrl_irq_ack(d);
1140     sunxi_pinctrl_irq_unmask(d);
1141 }
1142 
1143 static int sunxi_pinctrl_irq_set_wake(struct irq_data *d, unsigned int on)
1144 {
1145     struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1146     u8 bank = d->hwirq / IRQ_PER_BANK;
1147 
1148     return irq_set_irq_wake(pctl->irq[bank], on);
1149 }
1150 
1151 static struct irq_chip sunxi_pinctrl_edge_irq_chip = {
1152     .name       = "sunxi_pio_edge",
1153     .irq_ack    = sunxi_pinctrl_irq_ack,
1154     .irq_mask   = sunxi_pinctrl_irq_mask,
1155     .irq_unmask = sunxi_pinctrl_irq_unmask,
1156     .irq_request_resources = sunxi_pinctrl_irq_request_resources,
1157     .irq_release_resources = sunxi_pinctrl_irq_release_resources,
1158     .irq_set_type   = sunxi_pinctrl_irq_set_type,
1159     .irq_set_wake   = sunxi_pinctrl_irq_set_wake,
1160     .flags      = IRQCHIP_MASK_ON_SUSPEND,
1161 };
1162 
1163 static struct irq_chip sunxi_pinctrl_level_irq_chip = {
1164     .name       = "sunxi_pio_level",
1165     .irq_eoi    = sunxi_pinctrl_irq_ack,
1166     .irq_mask   = sunxi_pinctrl_irq_mask,
1167     .irq_unmask = sunxi_pinctrl_irq_unmask,
1168     /* Define irq_enable / disable to avoid spurious irqs for drivers
1169      * using these to suppress irqs while they clear the irq source */
1170     .irq_enable = sunxi_pinctrl_irq_ack_unmask,
1171     .irq_disable    = sunxi_pinctrl_irq_mask,
1172     .irq_request_resources = sunxi_pinctrl_irq_request_resources,
1173     .irq_release_resources = sunxi_pinctrl_irq_release_resources,
1174     .irq_set_type   = sunxi_pinctrl_irq_set_type,
1175     .irq_set_wake   = sunxi_pinctrl_irq_set_wake,
1176     .flags      = IRQCHIP_EOI_THREADED |
1177               IRQCHIP_MASK_ON_SUSPEND |
1178               IRQCHIP_EOI_IF_HANDLED,
1179 };
1180 
1181 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d,
1182                       struct device_node *node,
1183                       const u32 *intspec,
1184                       unsigned int intsize,
1185                       unsigned long *out_hwirq,
1186                       unsigned int *out_type)
1187 {
1188     struct sunxi_pinctrl *pctl = d->host_data;
1189     struct sunxi_desc_function *desc;
1190     int pin, base;
1191 
1192     if (intsize < 3)
1193         return -EINVAL;
1194 
1195     base = PINS_PER_BANK * intspec[0];
1196     pin = pctl->desc->pin_base + base + intspec[1];
1197 
1198     desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq");
1199     if (!desc)
1200         return -EINVAL;
1201 
1202     *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum;
1203     *out_type = intspec[2];
1204 
1205     return 0;
1206 }
1207 
1208 static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = {
1209     .xlate      = sunxi_pinctrl_irq_of_xlate,
1210 };
1211 
1212 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc)
1213 {
1214     unsigned int irq = irq_desc_get_irq(desc);
1215     struct irq_chip *chip = irq_desc_get_chip(desc);
1216     struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc);
1217     unsigned long bank, reg, val;
1218 
1219     for (bank = 0; bank < pctl->desc->irq_banks; bank++)
1220         if (irq == pctl->irq[bank])
1221             break;
1222 
1223     WARN_ON(bank == pctl->desc->irq_banks);
1224 
1225     chained_irq_enter(chip, desc);
1226 
1227     reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank);
1228     val = readl(pctl->membase + reg);
1229 
1230     if (val) {
1231         int irqoffset;
1232 
1233         for_each_set_bit(irqoffset, &val, IRQ_PER_BANK)
1234             generic_handle_domain_irq(pctl->domain,
1235                           bank * IRQ_PER_BANK + irqoffset);
1236     }
1237 
1238     chained_irq_exit(chip, desc);
1239 }
1240 
1241 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl,
1242                     const char *name)
1243 {
1244     struct sunxi_pinctrl_function *func = pctl->functions;
1245 
1246     while (func->name) {
1247         /* function already there */
1248         if (strcmp(func->name, name) == 0) {
1249             func->ngroups++;
1250             return -EEXIST;
1251         }
1252         func++;
1253     }
1254 
1255     func->name = name;
1256     func->ngroups = 1;
1257 
1258     pctl->nfunctions++;
1259 
1260     return 0;
1261 }
1262 
1263 static int sunxi_pinctrl_build_state(struct platform_device *pdev)
1264 {
1265     struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev);
1266     void *ptr;
1267     int i;
1268 
1269     /*
1270      * Allocate groups
1271      *
1272      * We assume that the number of groups is the number of pins
1273      * given in the data array.
1274 
1275      * This will not always be true, since some pins might not be
1276      * available in the current variant, but fortunately for us,
1277      * this means that the number of pins is the maximum group
1278      * number we will ever see.
1279      */
1280     pctl->groups = devm_kcalloc(&pdev->dev,
1281                     pctl->desc->npins, sizeof(*pctl->groups),
1282                     GFP_KERNEL);
1283     if (!pctl->groups)
1284         return -ENOMEM;
1285 
1286     for (i = 0; i < pctl->desc->npins; i++) {
1287         const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1288         struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups;
1289 
1290         if (pin->variant && !(pctl->variant & pin->variant))
1291             continue;
1292 
1293         group->name = pin->pin.name;
1294         group->pin = pin->pin.number;
1295 
1296         /* And now we count the actual number of pins / groups */
1297         pctl->ngroups++;
1298     }
1299 
1300     /*
1301      * Find an upper bound for the maximum number of functions: in
1302      * the worst case we have gpio_in, gpio_out, irq and up to seven
1303      * special functions per pin, plus one entry for the sentinel.
1304      * We'll reallocate that later anyway.
1305      */
1306     pctl->functions = kcalloc(7 * pctl->ngroups + 4,
1307                   sizeof(*pctl->functions),
1308                   GFP_KERNEL);
1309     if (!pctl->functions)
1310         return -ENOMEM;
1311 
1312     /* Count functions and their associated groups */
1313     for (i = 0; i < pctl->desc->npins; i++) {
1314         const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1315         struct sunxi_desc_function *func;
1316 
1317         if (pin->variant && !(pctl->variant & pin->variant))
1318             continue;
1319 
1320         for (func = pin->functions; func->name; func++) {
1321             if (func->variant && !(pctl->variant & func->variant))
1322                 continue;
1323 
1324             /* Create interrupt mapping while we're at it */
1325             if (!strcmp(func->name, "irq")) {
1326                 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK;
1327                 pctl->irq_array[irqnum] = pin->pin.number;
1328             }
1329 
1330             sunxi_pinctrl_add_function(pctl, func->name);
1331         }
1332     }
1333 
1334     /* And now allocated and fill the array for real */
1335     ptr = krealloc(pctl->functions,
1336                pctl->nfunctions * sizeof(*pctl->functions),
1337                GFP_KERNEL);
1338     if (!ptr) {
1339         kfree(pctl->functions);
1340         pctl->functions = NULL;
1341         return -ENOMEM;
1342     }
1343     pctl->functions = ptr;
1344 
1345     for (i = 0; i < pctl->desc->npins; i++) {
1346         const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1347         struct sunxi_desc_function *func;
1348 
1349         if (pin->variant && !(pctl->variant & pin->variant))
1350             continue;
1351 
1352         for (func = pin->functions; func->name; func++) {
1353             struct sunxi_pinctrl_function *func_item;
1354             const char **func_grp;
1355 
1356             if (func->variant && !(pctl->variant & func->variant))
1357                 continue;
1358 
1359             func_item = sunxi_pinctrl_find_function_by_name(pctl,
1360                                     func->name);
1361             if (!func_item) {
1362                 kfree(pctl->functions);
1363                 return -EINVAL;
1364             }
1365 
1366             if (!func_item->groups) {
1367                 func_item->groups =
1368                     devm_kcalloc(&pdev->dev,
1369                              func_item->ngroups,
1370                              sizeof(*func_item->groups),
1371                              GFP_KERNEL);
1372                 if (!func_item->groups) {
1373                     kfree(pctl->functions);
1374                     return -ENOMEM;
1375                 }
1376             }
1377 
1378             func_grp = func_item->groups;
1379             while (*func_grp)
1380                 func_grp++;
1381 
1382             *func_grp = pin->pin.name;
1383         }
1384     }
1385 
1386     return 0;
1387 }
1388 
1389 static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff)
1390 {
1391     unsigned long clock = clk_get_rate(clk);
1392     unsigned int best_diff, best_div;
1393     int i;
1394 
1395     best_diff = abs(freq - clock);
1396     best_div = 0;
1397 
1398     for (i = 1; i < 8; i++) {
1399         int cur_diff = abs(freq - (clock >> i));
1400 
1401         if (cur_diff < best_diff) {
1402             best_diff = cur_diff;
1403             best_div = i;
1404         }
1405     }
1406 
1407     *diff = best_diff;
1408     return best_div;
1409 }
1410 
1411 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl,
1412                     struct device_node *node)
1413 {
1414     unsigned int hosc_diff, losc_diff;
1415     unsigned int hosc_div, losc_div;
1416     struct clk *hosc, *losc;
1417     u8 div, src;
1418     int i, ret;
1419 
1420     /* Deal with old DTs that didn't have the oscillators */
1421     if (of_clk_get_parent_count(node) != 3)
1422         return 0;
1423 
1424     /* If we don't have any setup, bail out */
1425     if (!of_find_property(node, "input-debounce", NULL))
1426         return 0;
1427 
1428     losc = devm_clk_get(pctl->dev, "losc");
1429     if (IS_ERR(losc))
1430         return PTR_ERR(losc);
1431 
1432     hosc = devm_clk_get(pctl->dev, "hosc");
1433     if (IS_ERR(hosc))
1434         return PTR_ERR(hosc);
1435 
1436     for (i = 0; i < pctl->desc->irq_banks; i++) {
1437         unsigned long debounce_freq;
1438         u32 debounce;
1439 
1440         ret = of_property_read_u32_index(node, "input-debounce",
1441                          i, &debounce);
1442         if (ret)
1443             return ret;
1444 
1445         if (!debounce)
1446             continue;
1447 
1448         debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce);
1449         losc_div = sunxi_pinctrl_get_debounce_div(losc,
1450                               debounce_freq,
1451                               &losc_diff);
1452 
1453         hosc_div = sunxi_pinctrl_get_debounce_div(hosc,
1454                               debounce_freq,
1455                               &hosc_diff);
1456 
1457         if (hosc_diff < losc_diff) {
1458             div = hosc_div;
1459             src = 1;
1460         } else {
1461             div = losc_div;
1462             src = 0;
1463         }
1464 
1465         writel(src | div << 4,
1466                pctl->membase +
1467                sunxi_irq_debounce_reg_from_bank(pctl->desc, i));
1468     }
1469 
1470     return 0;
1471 }
1472 
1473 int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
1474                     const struct sunxi_pinctrl_desc *desc,
1475                     unsigned long variant)
1476 {
1477     struct device_node *node = pdev->dev.of_node;
1478     struct pinctrl_desc *pctrl_desc;
1479     struct pinctrl_pin_desc *pins;
1480     struct sunxi_pinctrl *pctl;
1481     struct pinmux_ops *pmxops;
1482     int i, ret, last_pin, pin_idx;
1483     struct clk *clk;
1484 
1485     pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1486     if (!pctl)
1487         return -ENOMEM;
1488     platform_set_drvdata(pdev, pctl);
1489 
1490     raw_spin_lock_init(&pctl->lock);
1491 
1492     pctl->membase = devm_platform_ioremap_resource(pdev, 0);
1493     if (IS_ERR(pctl->membase))
1494         return PTR_ERR(pctl->membase);
1495 
1496     pctl->dev = &pdev->dev;
1497     pctl->desc = desc;
1498     pctl->variant = variant;
1499     if (pctl->variant >= PINCTRL_SUN20I_D1) {
1500         pctl->bank_mem_size = D1_BANK_MEM_SIZE;
1501         pctl->pull_regs_offset = D1_PULL_REGS_OFFSET;
1502         pctl->dlevel_field_width = D1_DLEVEL_FIELD_WIDTH;
1503     } else {
1504         pctl->bank_mem_size = BANK_MEM_SIZE;
1505         pctl->pull_regs_offset = PULL_REGS_OFFSET;
1506         pctl->dlevel_field_width = DLEVEL_FIELD_WIDTH;
1507     }
1508 
1509     pctl->irq_array = devm_kcalloc(&pdev->dev,
1510                        IRQ_PER_BANK * pctl->desc->irq_banks,
1511                        sizeof(*pctl->irq_array),
1512                        GFP_KERNEL);
1513     if (!pctl->irq_array)
1514         return -ENOMEM;
1515 
1516     ret = sunxi_pinctrl_build_state(pdev);
1517     if (ret) {
1518         dev_err(&pdev->dev, "dt probe failed: %d\n", ret);
1519         return ret;
1520     }
1521 
1522     pins = devm_kcalloc(&pdev->dev,
1523                 pctl->desc->npins, sizeof(*pins),
1524                 GFP_KERNEL);
1525     if (!pins)
1526         return -ENOMEM;
1527 
1528     for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) {
1529         const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1530 
1531         if (pin->variant && !(pctl->variant & pin->variant))
1532             continue;
1533 
1534         pins[pin_idx++] = pin->pin;
1535     }
1536 
1537     pctrl_desc = devm_kzalloc(&pdev->dev,
1538                   sizeof(*pctrl_desc),
1539                   GFP_KERNEL);
1540     if (!pctrl_desc)
1541         return -ENOMEM;
1542 
1543     pctrl_desc->name = dev_name(&pdev->dev);
1544     pctrl_desc->owner = THIS_MODULE;
1545     pctrl_desc->pins = pins;
1546     pctrl_desc->npins = pctl->ngroups;
1547     pctrl_desc->confops = &sunxi_pconf_ops;
1548     pctrl_desc->pctlops = &sunxi_pctrl_ops;
1549 
1550     pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops),
1551                   GFP_KERNEL);
1552     if (!pmxops)
1553         return -ENOMEM;
1554 
1555     if (desc->disable_strict_mode)
1556         pmxops->strict = false;
1557 
1558     pctrl_desc->pmxops = pmxops;
1559 
1560     pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
1561     if (IS_ERR(pctl->pctl_dev)) {
1562         dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1563         return PTR_ERR(pctl->pctl_dev);
1564     }
1565 
1566     pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1567     if (!pctl->chip)
1568         return -ENOMEM;
1569 
1570     last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number;
1571     pctl->chip->owner = THIS_MODULE;
1572     pctl->chip->request = gpiochip_generic_request;
1573     pctl->chip->free = gpiochip_generic_free;
1574     pctl->chip->set_config = gpiochip_generic_config;
1575     pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input;
1576     pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output;
1577     pctl->chip->get = sunxi_pinctrl_gpio_get;
1578     pctl->chip->set = sunxi_pinctrl_gpio_set;
1579     pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate;
1580     pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq;
1581     pctl->chip->of_gpio_n_cells = 3;
1582     pctl->chip->can_sleep = false;
1583     pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) -
1584                 pctl->desc->pin_base;
1585     pctl->chip->label = dev_name(&pdev->dev);
1586     pctl->chip->parent = &pdev->dev;
1587     pctl->chip->base = pctl->desc->pin_base;
1588 
1589     ret = gpiochip_add_data(pctl->chip, pctl);
1590     if (ret)
1591         return ret;
1592 
1593     for (i = 0; i < pctl->desc->npins; i++) {
1594         const struct sunxi_desc_pin *pin = pctl->desc->pins + i;
1595 
1596         ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1597                          pin->pin.number - pctl->desc->pin_base,
1598                          pin->pin.number, 1);
1599         if (ret)
1600             goto gpiochip_error;
1601     }
1602 
1603     ret = of_clk_get_parent_count(node);
1604     clk = devm_clk_get(&pdev->dev, ret == 1 ? NULL : "apb");
1605     if (IS_ERR(clk)) {
1606         ret = PTR_ERR(clk);
1607         goto gpiochip_error;
1608     }
1609 
1610     ret = clk_prepare_enable(clk);
1611     if (ret)
1612         goto gpiochip_error;
1613 
1614     pctl->irq = devm_kcalloc(&pdev->dev,
1615                  pctl->desc->irq_banks,
1616                  sizeof(*pctl->irq),
1617                  GFP_KERNEL);
1618     if (!pctl->irq) {
1619         ret = -ENOMEM;
1620         goto clk_error;
1621     }
1622 
1623     for (i = 0; i < pctl->desc->irq_banks; i++) {
1624         pctl->irq[i] = platform_get_irq(pdev, i);
1625         if (pctl->irq[i] < 0) {
1626             ret = pctl->irq[i];
1627             goto clk_error;
1628         }
1629     }
1630 
1631     pctl->domain = irq_domain_add_linear(node,
1632                          pctl->desc->irq_banks * IRQ_PER_BANK,
1633                          &sunxi_pinctrl_irq_domain_ops,
1634                          pctl);
1635     if (!pctl->domain) {
1636         dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1637         ret = -ENOMEM;
1638         goto clk_error;
1639     }
1640 
1641     for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) {
1642         int irqno = irq_create_mapping(pctl->domain, i);
1643 
1644         irq_set_lockdep_class(irqno, &sunxi_pinctrl_irq_lock_class,
1645                       &sunxi_pinctrl_irq_request_class);
1646         irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip,
1647                      handle_edge_irq);
1648         irq_set_chip_data(irqno, pctl);
1649     }
1650 
1651     for (i = 0; i < pctl->desc->irq_banks; i++) {
1652         /* Mask and clear all IRQs before registering a handler */
1653         writel(0, pctl->membase +
1654               sunxi_irq_ctrl_reg_from_bank(pctl->desc, i));
1655         writel(0xffffffff,
1656                pctl->membase +
1657                sunxi_irq_status_reg_from_bank(pctl->desc, i));
1658 
1659         irq_set_chained_handler_and_data(pctl->irq[i],
1660                          sunxi_pinctrl_irq_handler,
1661                          pctl);
1662     }
1663 
1664     sunxi_pinctrl_setup_debounce(pctl, node);
1665 
1666     dev_info(&pdev->dev, "initialized sunXi PIO driver\n");
1667 
1668     return 0;
1669 
1670 clk_error:
1671     clk_disable_unprepare(clk);
1672 gpiochip_error:
1673     gpiochip_remove(pctl->chip);
1674     return ret;
1675 }
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