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OSCL-LXR
 
 

     

0001 /*
0002  * Allwinner A80 SoCs pinctrl driver.
0003  *
0004  * Copyright (C) 2014 Maxime Ripard
0005  *
0006  * Maxime Ripard <maxime.ripard@free-electrons.com>
0007  *
0008  * This file is licensed under the terms of the GNU General Public
0009  * License version 2.  This program is licensed "as is" without any
0010  * warranty of any kind, whether express or implied.
0011  */
0012 
0013 #include <linux/init.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/of.h>
0016 #include <linux/of_device.h>
0017 #include <linux/pinctrl/pinctrl.h>
0018 
0019 #include "pinctrl-sunxi.h"
0020 
0021 static const struct sunxi_desc_pin sun9i_a80_pins[] = {
0022     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
0023           SUNXI_FUNCTION(0x0, "gpio_in"),
0024           SUNXI_FUNCTION(0x1, "gpio_out"),
0025           SUNXI_FUNCTION(0x2, "gmac"),      /* RXD3 */
0026           SUNXI_FUNCTION(0x4, "uart1"),     /* TX */
0027           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PA_EINT0 */
0028     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
0029           SUNXI_FUNCTION(0x0, "gpio_in"),
0030           SUNXI_FUNCTION(0x1, "gpio_out"),
0031           SUNXI_FUNCTION(0x2, "gmac"),      /* RXD2 */
0032           SUNXI_FUNCTION(0x4, "uart1"),     /* RX */
0033           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PA_EINT1 */
0034     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
0035           SUNXI_FUNCTION(0x0, "gpio_in"),
0036           SUNXI_FUNCTION(0x1, "gpio_out"),
0037           SUNXI_FUNCTION(0x2, "gmac"),      /* RXD1 */
0038           SUNXI_FUNCTION(0x4, "uart1"),     /* RTS */
0039           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PA_EINT2 */
0040     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
0041           SUNXI_FUNCTION(0x0, "gpio_in"),
0042           SUNXI_FUNCTION(0x1, "gpio_out"),
0043           SUNXI_FUNCTION(0x2, "gmac"),      /* RXD0 */
0044           SUNXI_FUNCTION(0x4, "uart1"),     /* CTS */
0045           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PA_EINT3 */
0046     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
0047           SUNXI_FUNCTION(0x0, "gpio_in"),
0048           SUNXI_FUNCTION(0x1, "gpio_out"),
0049           SUNXI_FUNCTION(0x2, "gmac"),      /* RXCK */
0050           SUNXI_FUNCTION(0x4, "uart1"),     /* DTR */
0051           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PA_EINT4 */
0052     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
0053           SUNXI_FUNCTION(0x0, "gpio_in"),
0054           SUNXI_FUNCTION(0x1, "gpio_out"),
0055           SUNXI_FUNCTION(0x2, "gmac"),      /* RXCTL */
0056           SUNXI_FUNCTION(0x4, "uart1"),     /* DSR */
0057           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),  /* PA_EINT5 */
0058     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
0059           SUNXI_FUNCTION(0x0, "gpio_in"),
0060           SUNXI_FUNCTION(0x1, "gpio_out"),
0061           SUNXI_FUNCTION(0x2, "gmac"),      /* RXERR */
0062           SUNXI_FUNCTION(0x4, "uart1"),     /* DCD */
0063           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),  /* PA_EINT6 */
0064     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
0065           SUNXI_FUNCTION(0x0, "gpio_in"),
0066           SUNXI_FUNCTION(0x1, "gpio_out"),
0067           SUNXI_FUNCTION(0x2, "gmac"),      /* TXD3 */
0068           SUNXI_FUNCTION(0x4, "uart1"),     /* RING */
0069           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),  /* PA_EINT7 */
0070     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
0071           SUNXI_FUNCTION(0x0, "gpio_in"),
0072           SUNXI_FUNCTION(0x1, "gpio_out"),
0073           SUNXI_FUNCTION(0x2, "gmac"),      /* TXD2 */
0074           SUNXI_FUNCTION(0x4, "eclk"),      /* IN0 */
0075           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),  /* PA_EINT8 */
0076     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
0077           SUNXI_FUNCTION(0x0, "gpio_in"),
0078           SUNXI_FUNCTION(0x1, "gpio_out"),
0079           SUNXI_FUNCTION(0x2, "gmac"),      /* TXEN */
0080           SUNXI_FUNCTION(0x4, "eclk"),      /* IN1 */
0081           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),  /* PA_EINT9 */
0082     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
0083           SUNXI_FUNCTION(0x0, "gpio_in"),
0084           SUNXI_FUNCTION(0x1, "gpio_out"),
0085           SUNXI_FUNCTION(0x2, "gmac"),      /* TXD0 */
0086           SUNXI_FUNCTION(0x4, "clk_out_a"),
0087           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
0088     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
0089           SUNXI_FUNCTION(0x0, "gpio_in"),
0090           SUNXI_FUNCTION(0x1, "gpio_out"),
0091           SUNXI_FUNCTION(0x2, "gmac"),      /* MII-CRS */
0092           SUNXI_FUNCTION(0x4, "clk_out_b"),
0093           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
0094     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
0095           SUNXI_FUNCTION(0x0, "gpio_in"),
0096           SUNXI_FUNCTION(0x1, "gpio_out"),
0097           SUNXI_FUNCTION(0x2, "gmac"),      /* TXCK */
0098           SUNXI_FUNCTION(0x4, "pwm3"),      /* PWM_P */
0099           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
0100     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
0101           SUNXI_FUNCTION(0x0, "gpio_in"),
0102           SUNXI_FUNCTION(0x1, "gpio_out"),
0103           SUNXI_FUNCTION(0x2, "gmac"),      /* RGMII-TXCK / GMII-TXEN */
0104           SUNXI_FUNCTION(0x4, "pwm3"),      /* PWM_N */
0105           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
0106     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
0107           SUNXI_FUNCTION(0x0, "gpio_in"),
0108           SUNXI_FUNCTION(0x1, "gpio_out"),
0109           SUNXI_FUNCTION(0x2, "gmac"),      /* MII-TXERR */
0110           SUNXI_FUNCTION(0x4, "spi1"),      /* CS0 */
0111           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
0112     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
0113           SUNXI_FUNCTION(0x0, "gpio_in"),
0114           SUNXI_FUNCTION(0x1, "gpio_out"),
0115           SUNXI_FUNCTION(0x2, "gmac"),      /* RGMII-CLKIN / MII-COL */
0116           SUNXI_FUNCTION(0x4, "spi1"),      /* CLK */
0117           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
0118     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
0119           SUNXI_FUNCTION(0x0, "gpio_in"),
0120           SUNXI_FUNCTION(0x1, "gpio_out"),
0121           SUNXI_FUNCTION(0x2, "gmac"),      /* EMDC */
0122           SUNXI_FUNCTION(0x4, "spi1"),      /* MOSI */
0123           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
0124     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
0125           SUNXI_FUNCTION(0x0, "gpio_in"),
0126           SUNXI_FUNCTION(0x1, "gpio_out"),
0127           SUNXI_FUNCTION(0x2, "gmac"),      /* EMDIO */
0128           SUNXI_FUNCTION(0x4, "spi1"),      /* MISO */
0129           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
0130 
0131     /* Hole */
0132     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
0133           SUNXI_FUNCTION(0x0, "gpio_in"),
0134           SUNXI_FUNCTION(0x1, "gpio_out"),
0135           SUNXI_FUNCTION(0x3, "uart3"),     /* TX */
0136           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),  /* PB_EINT5 */
0137     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
0138           SUNXI_FUNCTION(0x0, "gpio_in"),
0139           SUNXI_FUNCTION(0x1, "gpio_out"),
0140           SUNXI_FUNCTION(0x3, "uart3"),     /* RX */
0141           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),  /* PB_EINT6 */
0142 
0143     /* Hole */
0144     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
0145           SUNXI_FUNCTION(0x0, "gpio_in"),
0146           SUNXI_FUNCTION(0x1, "gpio_out"),
0147           SUNXI_FUNCTION(0x3, "mcsi"),      /* MCLK */
0148           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), /* PB_EINT14 */
0149     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
0150           SUNXI_FUNCTION(0x0, "gpio_in"),
0151           SUNXI_FUNCTION(0x1, "gpio_out"),
0152           SUNXI_FUNCTION(0x3, "mcsi"),      /* SCK */
0153           SUNXI_FUNCTION(0x4, "i2c4"),      /* SCK */
0154           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), /* PB_EINT15 */
0155     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
0156           SUNXI_FUNCTION(0x0, "gpio_in"),
0157           SUNXI_FUNCTION(0x1, "gpio_out"),
0158           SUNXI_FUNCTION(0x3, "mcsi"),      /* SDA */
0159           SUNXI_FUNCTION(0x4, "i2c4"),      /* SDA */
0160           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), /* PB_EINT16 */
0161 
0162     /* Hole */
0163     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
0164           SUNXI_FUNCTION(0x0, "gpio_in"),
0165           SUNXI_FUNCTION(0x1, "gpio_out"),
0166           SUNXI_FUNCTION(0x2, "nand0"),     /* WE */
0167           SUNXI_FUNCTION(0x3, "spi0")),     /* MOSI */
0168     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
0169           SUNXI_FUNCTION(0x0, "gpio_in"),
0170           SUNXI_FUNCTION(0x1, "gpio_out"),
0171           SUNXI_FUNCTION(0x2, "nand0"),     /* ALE */
0172           SUNXI_FUNCTION(0x3, "spi0")),     /* MISO */
0173     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
0174           SUNXI_FUNCTION(0x0, "gpio_in"),
0175           SUNXI_FUNCTION(0x1, "gpio_out"),
0176           SUNXI_FUNCTION(0x2, "nand0"),     /* CLE */
0177           SUNXI_FUNCTION(0x3, "spi0")),     /* CLK */
0178     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
0179           SUNXI_FUNCTION(0x0, "gpio_in"),
0180           SUNXI_FUNCTION(0x1, "gpio_out"),
0181           SUNXI_FUNCTION(0x2, "nand0")),    /* CE1 */
0182     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
0183           SUNXI_FUNCTION(0x0, "gpio_in"),
0184           SUNXI_FUNCTION(0x1, "gpio_out"),
0185           SUNXI_FUNCTION(0x2, "nand0")),    /* CE0 */
0186     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
0187           SUNXI_FUNCTION(0x0, "gpio_in"),
0188           SUNXI_FUNCTION(0x1, "gpio_out"),
0189           SUNXI_FUNCTION(0x2, "nand0")),    /* RE */
0190     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
0191           SUNXI_FUNCTION(0x0, "gpio_in"),
0192           SUNXI_FUNCTION(0x1, "gpio_out"),
0193           SUNXI_FUNCTION(0x2, "nand0"),     /* RB0 */
0194           SUNXI_FUNCTION(0x3, "mmc2")),     /* CMD */
0195     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
0196           SUNXI_FUNCTION(0x0, "gpio_in"),
0197           SUNXI_FUNCTION(0x1, "gpio_out"),
0198           SUNXI_FUNCTION(0x2, "nand0"),     /* RB1 */
0199           SUNXI_FUNCTION(0x3, "mmc2")),     /* CLK */
0200     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
0201           SUNXI_FUNCTION(0x0, "gpio_in"),
0202           SUNXI_FUNCTION(0x1, "gpio_out"),
0203           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ0 */
0204           SUNXI_FUNCTION(0x3, "mmc2")),     /* D0 */
0205     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
0206           SUNXI_FUNCTION(0x0, "gpio_in"),
0207           SUNXI_FUNCTION(0x1, "gpio_out"),
0208           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ1 */
0209           SUNXI_FUNCTION(0x3, "mmc2")),     /* D1 */
0210     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
0211           SUNXI_FUNCTION(0x0, "gpio_in"),
0212           SUNXI_FUNCTION(0x1, "gpio_out"),
0213           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ2 */
0214           SUNXI_FUNCTION(0x3, "mmc2")),     /* D2 */
0215     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
0216           SUNXI_FUNCTION(0x0, "gpio_in"),
0217           SUNXI_FUNCTION(0x1, "gpio_out"),
0218           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ3 */
0219           SUNXI_FUNCTION(0x3, "mmc2")),     /* D3 */
0220     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
0221           SUNXI_FUNCTION(0x0, "gpio_in"),
0222           SUNXI_FUNCTION(0x1, "gpio_out"),
0223           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ4 */
0224           SUNXI_FUNCTION(0x3, "mmc2")),     /* D4 */
0225     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
0226           SUNXI_FUNCTION(0x0, "gpio_in"),
0227           SUNXI_FUNCTION(0x1, "gpio_out"),
0228           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ5 */
0229           SUNXI_FUNCTION(0x3, "mmc2")),     /* D5 */
0230     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
0231           SUNXI_FUNCTION(0x0, "gpio_in"),
0232           SUNXI_FUNCTION(0x1, "gpio_out"),
0233           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ6 */
0234           SUNXI_FUNCTION(0x3, "mmc2")),     /* D6 */
0235     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
0236           SUNXI_FUNCTION(0x0, "gpio_in"),
0237           SUNXI_FUNCTION(0x1, "gpio_out"),
0238           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ7 */
0239           SUNXI_FUNCTION(0x3, "mmc2")),     /* D7 */
0240     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
0241           SUNXI_FUNCTION(0x0, "gpio_in"),
0242           SUNXI_FUNCTION(0x1, "gpio_out"),
0243           SUNXI_FUNCTION(0x2, "nand0"),     /* DQS */
0244           SUNXI_FUNCTION(0x3, "mmc2")),     /* RST */
0245     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
0246           SUNXI_FUNCTION(0x0, "gpio_in"),
0247           SUNXI_FUNCTION(0x1, "gpio_out"),
0248           SUNXI_FUNCTION(0x2, "nand0"),     /* CE2 */
0249           SUNXI_FUNCTION(0x3, "nand0_b")),  /* RE */
0250     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
0251           SUNXI_FUNCTION(0x0, "gpio_in"),
0252           SUNXI_FUNCTION(0x1, "gpio_out"),
0253           SUNXI_FUNCTION(0x2, "nand0"),     /* CE3 */
0254           SUNXI_FUNCTION(0x3, "nand0_b")),  /* DQS */
0255     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 19),
0256           SUNXI_FUNCTION(0x0, "gpio_in"),
0257           SUNXI_FUNCTION(0x1, "gpio_out"),
0258           SUNXI_FUNCTION(0x3, "spi0")),     /* CS0 */
0259 
0260     /* Hole */
0261     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
0262           SUNXI_FUNCTION(0x0, "gpio_in"),
0263           SUNXI_FUNCTION(0x1, "gpio_out"),
0264           SUNXI_FUNCTION(0x2, "lcd0"),      /* D0 */
0265           SUNXI_FUNCTION(0x3, "lvds0")),    /* VP0 */
0266     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
0267           SUNXI_FUNCTION(0x0, "gpio_in"),
0268           SUNXI_FUNCTION(0x1, "gpio_out"),
0269           SUNXI_FUNCTION(0x2, "lcd0"),      /* D1 */
0270           SUNXI_FUNCTION(0x3, "lvds0")),    /* VN0 */
0271     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
0272           SUNXI_FUNCTION(0x0, "gpio_in"),
0273           SUNXI_FUNCTION(0x1, "gpio_out"),
0274           SUNXI_FUNCTION(0x2, "lcd0"),      /* D2 */
0275           SUNXI_FUNCTION(0x3, "lvds0")),    /* VP1 */
0276     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
0277           SUNXI_FUNCTION(0x0, "gpio_in"),
0278           SUNXI_FUNCTION(0x1, "gpio_out"),
0279           SUNXI_FUNCTION(0x2, "lcd0"),      /* D3 */
0280           SUNXI_FUNCTION(0x3, "lvds0")),    /* VN1 */
0281     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
0282           SUNXI_FUNCTION(0x0, "gpio_in"),
0283           SUNXI_FUNCTION(0x1, "gpio_out"),
0284           SUNXI_FUNCTION(0x2, "lcd0"),      /* D4 */
0285           SUNXI_FUNCTION(0x3, "lvds0")),    /* VP2 */
0286     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
0287           SUNXI_FUNCTION(0x0, "gpio_in"),
0288           SUNXI_FUNCTION(0x1, "gpio_out"),
0289           SUNXI_FUNCTION(0x2, "lcd0"),      /* D5 */
0290           SUNXI_FUNCTION(0x3, "lvds0")),    /* VN2 */
0291     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
0292           SUNXI_FUNCTION(0x0, "gpio_in"),
0293           SUNXI_FUNCTION(0x1, "gpio_out"),
0294           SUNXI_FUNCTION(0x2, "lcd0"),      /* D6 */
0295           SUNXI_FUNCTION(0x3, "lvds0")),    /* VPC */
0296     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
0297           SUNXI_FUNCTION(0x0, "gpio_in"),
0298           SUNXI_FUNCTION(0x1, "gpio_out"),
0299           SUNXI_FUNCTION(0x2, "lcd0"),      /* D7 */
0300           SUNXI_FUNCTION(0x3, "lvds0")),    /* VNC */
0301     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
0302           SUNXI_FUNCTION(0x0, "gpio_in"),
0303           SUNXI_FUNCTION(0x1, "gpio_out"),
0304           SUNXI_FUNCTION(0x2, "lcd0"),      /* D8 */
0305           SUNXI_FUNCTION(0x3, "lvds0")),    /* VP3 */
0306     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
0307           SUNXI_FUNCTION(0x0, "gpio_in"),
0308           SUNXI_FUNCTION(0x1, "gpio_out"),
0309           SUNXI_FUNCTION(0x2, "lcd0"),      /* D9 */
0310           SUNXI_FUNCTION(0x3, "lvds0")),    /* VN3 */
0311     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
0312           SUNXI_FUNCTION(0x0, "gpio_in"),
0313           SUNXI_FUNCTION(0x1, "gpio_out"),
0314           SUNXI_FUNCTION(0x2, "lcd0"),      /* D10 */
0315           SUNXI_FUNCTION(0x3, "lvds1")),    /* VP0 */
0316     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
0317           SUNXI_FUNCTION(0x0, "gpio_in"),
0318           SUNXI_FUNCTION(0x1, "gpio_out"),
0319           SUNXI_FUNCTION(0x2, "lcd0"),      /* D11 */
0320           SUNXI_FUNCTION(0x3, "lvds1")),    /* VN0 */
0321     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
0322           SUNXI_FUNCTION(0x0, "gpio_in"),
0323           SUNXI_FUNCTION(0x1, "gpio_out"),
0324           SUNXI_FUNCTION(0x2, "lcd0"),      /* D12 */
0325           SUNXI_FUNCTION(0x3, "lvds1")),    /* VP1 */
0326     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
0327           SUNXI_FUNCTION(0x0, "gpio_in"),
0328           SUNXI_FUNCTION(0x1, "gpio_out"),
0329           SUNXI_FUNCTION(0x2, "lcd0"),      /* D13 */
0330           SUNXI_FUNCTION(0x3, "lvds1")),    /* VN1 */
0331     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
0332           SUNXI_FUNCTION(0x0, "gpio_in"),
0333           SUNXI_FUNCTION(0x1, "gpio_out"),
0334           SUNXI_FUNCTION(0x2, "lcd0"),      /* D14 */
0335           SUNXI_FUNCTION(0x3, "lvds1")),    /* VP2 */
0336     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
0337           SUNXI_FUNCTION(0x0, "gpio_in"),
0338           SUNXI_FUNCTION(0x1, "gpio_out"),
0339           SUNXI_FUNCTION(0x2, "lcd0"),      /* D15 */
0340           SUNXI_FUNCTION(0x3, "lvds1")),    /* VN2 */
0341     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
0342           SUNXI_FUNCTION(0x0, "gpio_in"),
0343           SUNXI_FUNCTION(0x1, "gpio_out"),
0344           SUNXI_FUNCTION(0x2, "lcd0"),      /* D16 */
0345           SUNXI_FUNCTION(0x3, "lvds1")),    /* VPC */
0346     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
0347           SUNXI_FUNCTION(0x0, "gpio_in"),
0348           SUNXI_FUNCTION(0x1, "gpio_out"),
0349           SUNXI_FUNCTION(0x2, "lcd0"),      /* D17 */
0350           SUNXI_FUNCTION(0x3, "lvds1")),    /* VNC */
0351     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
0352           SUNXI_FUNCTION(0x0, "gpio_in"),
0353           SUNXI_FUNCTION(0x1, "gpio_out"),
0354           SUNXI_FUNCTION(0x2, "lcd0"),      /* D18 */
0355           SUNXI_FUNCTION(0x3, "lvds1")),    /* VP3 */
0356     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
0357           SUNXI_FUNCTION(0x0, "gpio_in"),
0358           SUNXI_FUNCTION(0x1, "gpio_out"),
0359           SUNXI_FUNCTION(0x2, "lcd0"),      /* D19 */
0360           SUNXI_FUNCTION(0x3, "lvds1")),    /* VN3 */
0361     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
0362           SUNXI_FUNCTION(0x0, "gpio_in"),
0363           SUNXI_FUNCTION(0x1, "gpio_out"),
0364           SUNXI_FUNCTION(0x2, "lcd0")),     /* D20 */
0365     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
0366           SUNXI_FUNCTION(0x0, "gpio_in"),
0367           SUNXI_FUNCTION(0x1, "gpio_out"),
0368           SUNXI_FUNCTION(0x2, "lcd0")),     /* D21 */
0369     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
0370           SUNXI_FUNCTION(0x0, "gpio_in"),
0371           SUNXI_FUNCTION(0x1, "gpio_out"),
0372           SUNXI_FUNCTION(0x2, "lcd0")),     /* D22 */
0373     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
0374           SUNXI_FUNCTION(0x0, "gpio_in"),
0375           SUNXI_FUNCTION(0x1, "gpio_out"),
0376           SUNXI_FUNCTION(0x2, "lcd0")),     /* D23 */
0377     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
0378           SUNXI_FUNCTION(0x0, "gpio_in"),
0379           SUNXI_FUNCTION(0x1, "gpio_out"),
0380           SUNXI_FUNCTION(0x2, "lcd0")),     /* CLK */
0381     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
0382           SUNXI_FUNCTION(0x0, "gpio_in"),
0383           SUNXI_FUNCTION(0x1, "gpio_out"),
0384           SUNXI_FUNCTION(0x2, "lcd0")),     /* DE */
0385     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
0386           SUNXI_FUNCTION(0x0, "gpio_in"),
0387           SUNXI_FUNCTION(0x1, "gpio_out"),
0388           SUNXI_FUNCTION(0x2, "lcd0")),     /* HSYNC */
0389     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
0390           SUNXI_FUNCTION(0x0, "gpio_in"),
0391           SUNXI_FUNCTION(0x1, "gpio_out"),
0392           SUNXI_FUNCTION(0x2, "lcd0")),     /* VSYNC */
0393 
0394     /* Hole */
0395     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
0396           SUNXI_FUNCTION(0x0, "gpio_in"),
0397           SUNXI_FUNCTION(0x1, "gpio_out"),
0398           SUNXI_FUNCTION(0x2, "csi"),       /* PCLK */
0399           SUNXI_FUNCTION(0x3, "ts"),        /* CLK */
0400           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),  /* PE_EINT0 */
0401     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
0402           SUNXI_FUNCTION(0x0, "gpio_in"),
0403           SUNXI_FUNCTION(0x1, "gpio_out"),
0404           SUNXI_FUNCTION(0x2, "csi"),       /* MCLK */
0405           SUNXI_FUNCTION(0x3, "ts"),        /* ERR */
0406           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),  /* PE_EINT1 */
0407     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
0408           SUNXI_FUNCTION(0x0, "gpio_in"),
0409           SUNXI_FUNCTION(0x1, "gpio_out"),
0410           SUNXI_FUNCTION(0x2, "csi"),       /* HSYNC */
0411           SUNXI_FUNCTION(0x3, "ts"),        /* SYNC */
0412           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),  /* PE_EINT2 */
0413     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
0414           SUNXI_FUNCTION(0x0, "gpio_in"),
0415           SUNXI_FUNCTION(0x1, "gpio_out"),
0416           SUNXI_FUNCTION(0x2, "csi"),       /* VSYNC */
0417           SUNXI_FUNCTION(0x3, "ts"),        /* DVLD */
0418           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),  /* PE_EINT3 */
0419     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
0420           SUNXI_FUNCTION(0x0, "gpio_in"),
0421           SUNXI_FUNCTION(0x1, "gpio_out"),
0422           SUNXI_FUNCTION(0x2, "csi"),       /* D0 */
0423           SUNXI_FUNCTION(0x3, "spi2"),      /* CS0 */
0424           SUNXI_FUNCTION(0x4, "uart5"),     /* TX */
0425           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),  /* PE_EINT4 */
0426     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
0427           SUNXI_FUNCTION(0x0, "gpio_in"),
0428           SUNXI_FUNCTION(0x1, "gpio_out"),
0429           SUNXI_FUNCTION(0x2, "csi"),       /* D1 */
0430           SUNXI_FUNCTION(0x3, "spi2"),      /* CLK */
0431           SUNXI_FUNCTION(0x4, "uart5"),     /* RX */
0432           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),  /* PE_EINT5 */
0433     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
0434           SUNXI_FUNCTION(0x0, "gpio_in"),
0435           SUNXI_FUNCTION(0x1, "gpio_out"),
0436           SUNXI_FUNCTION(0x2, "csi"),       /* D2 */
0437           SUNXI_FUNCTION(0x3, "spi2"),      /* MOSI */
0438           SUNXI_FUNCTION(0x4, "uart5"),     /* RTS */
0439           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),  /* PE_EINT6 */
0440     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
0441           SUNXI_FUNCTION(0x0, "gpio_in"),
0442           SUNXI_FUNCTION(0x1, "gpio_out"),
0443           SUNXI_FUNCTION(0x2, "csi"),       /* D3 */
0444           SUNXI_FUNCTION(0x3, "spi2"),      /* MISO */
0445           SUNXI_FUNCTION(0x4, "uart5"),     /* CTS */
0446           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),  /* PE_EINT7 */
0447     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
0448           SUNXI_FUNCTION(0x0, "gpio_in"),
0449           SUNXI_FUNCTION(0x1, "gpio_out"),
0450           SUNXI_FUNCTION(0x2, "csi"),       /* D4 */
0451           SUNXI_FUNCTION(0x3, "ts"),        /* D0 */
0452           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),  /* PE_EINT8 */
0453     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
0454           SUNXI_FUNCTION(0x0, "gpio_in"),
0455           SUNXI_FUNCTION(0x1, "gpio_out"),
0456           SUNXI_FUNCTION(0x2, "csi"),       /* D5 */
0457           SUNXI_FUNCTION(0x3, "ts"),        /* D1 */
0458           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),  /* PE_EINT9 */
0459     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
0460           SUNXI_FUNCTION(0x0, "gpio_in"),
0461           SUNXI_FUNCTION(0x1, "gpio_out"),
0462           SUNXI_FUNCTION(0x2, "csi"),       /* D6 */
0463           SUNXI_FUNCTION(0x3, "ts"),        /* D2 */
0464           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PE_EINT10 */
0465     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
0466           SUNXI_FUNCTION(0x0, "gpio_in"),
0467           SUNXI_FUNCTION(0x1, "gpio_out"),
0468           SUNXI_FUNCTION(0x2, "csi"),       /* D7 */
0469           SUNXI_FUNCTION(0x3, "ts"),        /* D3 */
0470           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PE_EINT11 */
0471     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
0472           SUNXI_FUNCTION(0x0, "gpio_in"),
0473           SUNXI_FUNCTION(0x1, "gpio_out"),
0474           SUNXI_FUNCTION(0x2, "csi"),       /* D8 */
0475           SUNXI_FUNCTION(0x3, "ts"),        /* D4 */
0476           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PE_EINT12 */
0477     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
0478           SUNXI_FUNCTION(0x0, "gpio_in"),
0479           SUNXI_FUNCTION(0x1, "gpio_out"),
0480           SUNXI_FUNCTION(0x2, "csi"),       /* D9 */
0481           SUNXI_FUNCTION(0x3, "ts"),        /* D5 */
0482           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PE_EINT13 */
0483     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
0484           SUNXI_FUNCTION(0x0, "gpio_in"),
0485           SUNXI_FUNCTION(0x1, "gpio_out"),
0486           SUNXI_FUNCTION(0x2, "csi"),       /* D10 */
0487           SUNXI_FUNCTION(0x3, "ts"),        /* D6 */
0488           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PE_EINT14 */
0489     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
0490           SUNXI_FUNCTION(0x0, "gpio_in"),
0491           SUNXI_FUNCTION(0x1, "gpio_out"),
0492           SUNXI_FUNCTION(0x2, "csi"),       /* D11 */
0493           SUNXI_FUNCTION(0x3, "ts"),        /* D7 */
0494           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), /* PE_EINT15 */
0495     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
0496           SUNXI_FUNCTION(0x0, "gpio_in"),
0497           SUNXI_FUNCTION(0x1, "gpio_out"),
0498           SUNXI_FUNCTION(0x2, "csi"),       /* SCK */
0499           SUNXI_FUNCTION(0x3, "i2c4"),      /* SCK */
0500           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), /* PE_EINT16 */
0501     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
0502           SUNXI_FUNCTION(0x0, "gpio_in"),
0503           SUNXI_FUNCTION(0x1, "gpio_out"),
0504           SUNXI_FUNCTION(0x2, "csi"),       /* SDA */
0505           SUNXI_FUNCTION(0x3, "i2c4"),      /* SDA */
0506           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)), /* PE_EINT17 */
0507 
0508     /* Hole */
0509     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
0510           SUNXI_FUNCTION(0x0, "gpio_in"),
0511           SUNXI_FUNCTION(0x1, "gpio_out"),
0512           SUNXI_FUNCTION(0x2, "mmc0")),     /* D1 */
0513     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
0514           SUNXI_FUNCTION(0x0, "gpio_in"),
0515           SUNXI_FUNCTION(0x1, "gpio_out"),
0516           SUNXI_FUNCTION(0x2, "mmc0")),     /* D0 */
0517     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
0518           SUNXI_FUNCTION(0x0, "gpio_in"),
0519           SUNXI_FUNCTION(0x1, "gpio_out"),
0520           SUNXI_FUNCTION(0x2, "mmc0"),      /* CLK */
0521           SUNXI_FUNCTION(0x4, "uart0")),    /* TX */
0522     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
0523           SUNXI_FUNCTION(0x0, "gpio_in"),
0524           SUNXI_FUNCTION(0x1, "gpio_out"),
0525           SUNXI_FUNCTION(0x2, "mmc0")),     /* CMD */
0526     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
0527           SUNXI_FUNCTION(0x0, "gpio_in"),
0528           SUNXI_FUNCTION(0x1, "gpio_out"),
0529           SUNXI_FUNCTION(0x2, "mmc0"),      /* D3 */
0530           SUNXI_FUNCTION(0x4, "uart0")),    /* RX */
0531     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
0532           SUNXI_FUNCTION(0x0, "gpio_in"),
0533           SUNXI_FUNCTION(0x1, "gpio_out"),
0534           SUNXI_FUNCTION(0x2, "mmc0")),     /* D2 */
0535 
0536     /* Hole */
0537     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
0538           SUNXI_FUNCTION(0x0, "gpio_in"),
0539           SUNXI_FUNCTION(0x1, "gpio_out"),
0540           SUNXI_FUNCTION(0x2, "mmc1"),      /* CLK */
0541           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)),  /* PG_EINT0 */
0542     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
0543           SUNXI_FUNCTION(0x0, "gpio_in"),
0544           SUNXI_FUNCTION(0x1, "gpio_out"),
0545           SUNXI_FUNCTION(0x2, "mmc1"),      /* CMD */
0546           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)),  /* PG_EINT1 */
0547     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
0548           SUNXI_FUNCTION(0x0, "gpio_in"),
0549           SUNXI_FUNCTION(0x1, "gpio_out"),
0550           SUNXI_FUNCTION(0x2, "mmc1"),      /* D0 */
0551           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)),  /* PG_EINT2 */
0552     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
0553           SUNXI_FUNCTION(0x0, "gpio_in"),
0554           SUNXI_FUNCTION(0x1, "gpio_out"),
0555           SUNXI_FUNCTION(0x2, "mmc1"),      /* D1 */
0556           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)),  /* PG_EINT3 */
0557     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
0558           SUNXI_FUNCTION(0x0, "gpio_in"),
0559           SUNXI_FUNCTION(0x1, "gpio_out"),
0560           SUNXI_FUNCTION(0x2, "mmc1"),      /* D2 */
0561           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)),  /* PG_EINT4 */
0562     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
0563           SUNXI_FUNCTION(0x0, "gpio_in"),
0564           SUNXI_FUNCTION(0x1, "gpio_out"),
0565           SUNXI_FUNCTION(0x2, "mmc1"),      /* D3 */
0566           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)),  /* PG_EINT5 */
0567     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
0568           SUNXI_FUNCTION(0x0, "gpio_in"),
0569           SUNXI_FUNCTION(0x1, "gpio_out"),
0570           SUNXI_FUNCTION(0x2, "uart2"),     /* TX */
0571           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)),  /* PG_EINT6 */
0572     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
0573           SUNXI_FUNCTION(0x0, "gpio_in"),
0574           SUNXI_FUNCTION(0x1, "gpio_out"),
0575           SUNXI_FUNCTION(0x2, "uart2"),     /* RX */
0576           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)),  /* PG_EINT7 */
0577     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
0578           SUNXI_FUNCTION(0x0, "gpio_in"),
0579           SUNXI_FUNCTION(0x1, "gpio_out"),
0580           SUNXI_FUNCTION(0x2, "uart2"),     /* RTS */
0581           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)),  /* PG_EINT8 */
0582     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
0583           SUNXI_FUNCTION(0x0, "gpio_in"),
0584           SUNXI_FUNCTION(0x1, "gpio_out"),
0585           SUNXI_FUNCTION(0x2, "uart2"),     /* CTS */
0586           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)),  /* PG_EINT9 */
0587     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
0588           SUNXI_FUNCTION(0x0, "gpio_in"),
0589           SUNXI_FUNCTION(0x1, "gpio_out"),
0590           SUNXI_FUNCTION(0x2, "i2c3"),      /* SCK */
0591           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PG_EINT10 */
0592     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
0593           SUNXI_FUNCTION(0x0, "gpio_in"),
0594           SUNXI_FUNCTION(0x1, "gpio_out"),
0595           SUNXI_FUNCTION(0x2, "i2c3"),      /* SDA */
0596           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 11)), /* PG_EINT11 */
0597     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
0598           SUNXI_FUNCTION(0x0, "gpio_in"),
0599           SUNXI_FUNCTION(0x1, "gpio_out"),
0600           SUNXI_FUNCTION(0x2, "uart4"),     /* TX */
0601           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 12)), /* PG_EINT12 */
0602     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
0603           SUNXI_FUNCTION(0x0, "gpio_in"),
0604           SUNXI_FUNCTION(0x1, "gpio_out"),
0605           SUNXI_FUNCTION(0x2, "uart4"),     /* RX */
0606           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 13)), /* PG_EINT13 */
0607     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
0608           SUNXI_FUNCTION(0x0, "gpio_in"),
0609           SUNXI_FUNCTION(0x1, "gpio_out"),
0610           SUNXI_FUNCTION(0x2, "uart4"),     /* RTS */
0611           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 14)), /* PG_EINT14 */
0612     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
0613           SUNXI_FUNCTION(0x0, "gpio_in"),
0614           SUNXI_FUNCTION(0x1, "gpio_out"),
0615           SUNXI_FUNCTION(0x2, "uart4"),     /* CTS */
0616           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 15)), /* PG_EINT15 */
0617 
0618     /* Hole */
0619     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
0620           SUNXI_FUNCTION(0x0, "gpio_in"),
0621           SUNXI_FUNCTION(0x1, "gpio_out"),
0622           SUNXI_FUNCTION(0x2, "i2c0")),     /* SCK */
0623     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
0624           SUNXI_FUNCTION(0x0, "gpio_in"),
0625           SUNXI_FUNCTION(0x1, "gpio_out"),
0626           SUNXI_FUNCTION(0x2, "i2c0")),     /* SDA */
0627     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
0628           SUNXI_FUNCTION(0x0, "gpio_in"),
0629           SUNXI_FUNCTION(0x1, "gpio_out"),
0630           SUNXI_FUNCTION(0x2, "i2c1")),     /* SCK */
0631     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
0632           SUNXI_FUNCTION(0x0, "gpio_in"),
0633           SUNXI_FUNCTION(0x1, "gpio_out"),
0634           SUNXI_FUNCTION(0x2, "i2c1")),     /* SDA */
0635     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
0636           SUNXI_FUNCTION(0x0, "gpio_in"),
0637           SUNXI_FUNCTION(0x1, "gpio_out"),
0638           SUNXI_FUNCTION(0x2, "i2c2")),     /* SCK */
0639     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
0640           SUNXI_FUNCTION(0x0, "gpio_in"),
0641           SUNXI_FUNCTION(0x1, "gpio_out"),
0642           SUNXI_FUNCTION(0x2, "i2c2")),     /* SDA */
0643     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
0644           SUNXI_FUNCTION(0x0, "gpio_in"),
0645           SUNXI_FUNCTION(0x1, "gpio_out"),
0646           SUNXI_FUNCTION(0x2, "pwm0")),
0647 
0648     /* Hole */
0649     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
0650           SUNXI_FUNCTION(0x0, "gpio_in"),
0651           SUNXI_FUNCTION(0x1, "gpio_out"),
0652           SUNXI_FUNCTION(0x3, "pwm1"),      /* Positive */
0653           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 8)),  /* PH_EINT8 */
0654     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
0655           SUNXI_FUNCTION(0x0, "gpio_in"),
0656           SUNXI_FUNCTION(0x1, "gpio_out"),
0657           SUNXI_FUNCTION(0x3, "pwm1"),      /* Negative */
0658           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 9)),  /* PH_EINT9 */
0659     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
0660           SUNXI_FUNCTION(0x0, "gpio_in"),
0661           SUNXI_FUNCTION(0x1, "gpio_out"),
0662           SUNXI_FUNCTION(0x3, "pwm2"),      /* Positive */
0663           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 10)), /* PH_EINT10 */
0664     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
0665           SUNXI_FUNCTION(0x0, "gpio_in"),
0666           SUNXI_FUNCTION(0x1, "gpio_out"),
0667           SUNXI_FUNCTION(0x3, "pwm2"),      /* Negative */
0668           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 11)), /* PH_EINT12 */
0669     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
0670           SUNXI_FUNCTION(0x0, "gpio_in"),
0671           SUNXI_FUNCTION(0x1, "gpio_out"),
0672           SUNXI_FUNCTION(0x2, "uart0"),     /* TX */
0673           SUNXI_FUNCTION(0x3, "spi3"),      /* CS2 */
0674           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 12)), /* PH_EINT12 */
0675     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
0676           SUNXI_FUNCTION(0x0, "gpio_in"),
0677           SUNXI_FUNCTION(0x1, "gpio_out"),
0678           SUNXI_FUNCTION(0x2, "uart0"),     /* RX */
0679           SUNXI_FUNCTION(0x3, "spi3"),      /* CS2 */
0680           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 13)), /* PH_EINT13 */
0681     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
0682           SUNXI_FUNCTION(0x0, "gpio_in"),
0683           SUNXI_FUNCTION(0x1, "gpio_out"),
0684           SUNXI_FUNCTION(0x2, "spi3"),      /* CLK */
0685           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 14)), /* PH_EINT14 */
0686     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
0687           SUNXI_FUNCTION(0x0, "gpio_in"),
0688           SUNXI_FUNCTION(0x1, "gpio_out"),
0689           SUNXI_FUNCTION(0x2, "spi3"),      /* MOSI */
0690           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 15)), /* PH_EINT15 */
0691     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
0692           SUNXI_FUNCTION(0x0, "gpio_in"),
0693           SUNXI_FUNCTION(0x1, "gpio_out"),
0694           SUNXI_FUNCTION(0x2, "spi3"),      /* MISO */
0695           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 16)), /* PH_EINT16 */
0696     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
0697           SUNXI_FUNCTION(0x0, "gpio_in"),
0698           SUNXI_FUNCTION(0x1, "gpio_out"),
0699           SUNXI_FUNCTION(0x2, "spi3"),      /* CS0 */
0700           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 17)), /* PH_EINT17 */
0701     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
0702           SUNXI_FUNCTION(0x0, "gpio_in"),
0703           SUNXI_FUNCTION(0x1, "gpio_out"),
0704           SUNXI_FUNCTION(0x2, "spi3"),      /* CS1 */
0705           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 18)), /* PH_EINT18 */
0706     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
0707           SUNXI_FUNCTION(0x0, "gpio_in"),
0708           SUNXI_FUNCTION(0x1, "gpio_out"),
0709           SUNXI_FUNCTION(0x2, "hdmi")),     /* SCL */
0710     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 20),
0711           SUNXI_FUNCTION(0x0, "gpio_in"),
0712           SUNXI_FUNCTION(0x1, "gpio_out"),
0713           SUNXI_FUNCTION(0x2, "hdmi")),     /* SDA */
0714     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 21),
0715           SUNXI_FUNCTION(0x0, "gpio_in"),
0716           SUNXI_FUNCTION(0x1, "gpio_out"),
0717           SUNXI_FUNCTION(0x2, "hdmi")),     /* CEC */
0718 };
0719 
0720 static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = {
0721     .pins = sun9i_a80_pins,
0722     .npins = ARRAY_SIZE(sun9i_a80_pins),
0723     .irq_banks = 5,
0724     .disable_strict_mode = true,
0725     .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG,
0726 };
0727 
0728 static int sun9i_a80_pinctrl_probe(struct platform_device *pdev)
0729 {
0730     return sunxi_pinctrl_init(pdev,
0731                   &sun9i_a80_pinctrl_data);
0732 }
0733 
0734 static const struct of_device_id sun9i_a80_pinctrl_match[] = {
0735     { .compatible = "allwinner,sun9i-a80-pinctrl", },
0736     {}
0737 };
0738 
0739 static struct platform_driver sun9i_a80_pinctrl_driver = {
0740     .probe  = sun9i_a80_pinctrl_probe,
0741     .driver = {
0742         .name       = "sun9i-a80-pinctrl",
0743         .of_match_table = sun9i_a80_pinctrl_match,
0744     },
0745 };
0746 builtin_platform_driver(sun9i_a80_pinctrl_driver);
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