pinctrl/sunxi/pinctrl-sun9i-a80-r.c

0001 /*
0002  * Allwinner A80 SoCs special pins pinctrl driver.
0003  *
0004  * Copyright (C) 2014 Maxime Ripard
0005  * Maxime Ripard <maxime.ripard@free-electrons.com>
0006  *
0007  * This file is licensed under the terms of the GNU General Public
0008  * License version 2.  This program is licensed "as is" without any
0009  * warranty of any kind, whether express or implied.
0010  */
0011
0012 #include <linux/init.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/of.h>
0015 #include <linux/of_device.h>
0016 #include <linux/pinctrl/pinctrl.h>
0017
0018 #include "pinctrl-sunxi.h"
0019
0020 static const struct sunxi_desc_pin sun9i_a80_r_pins[] = {
0021     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
0022           SUNXI_FUNCTION(0x0, "gpio_in"),
0023           SUNXI_FUNCTION(0x1, "gpio_out"),
0024           SUNXI_FUNCTION(0x3, "s_uart"),    /* TX */
0025           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PL_EINT0 */
0026     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
0027           SUNXI_FUNCTION(0x0, "gpio_in"),
0028           SUNXI_FUNCTION(0x1, "gpio_out"),
0029           SUNXI_FUNCTION(0x3, "s_uart"),    /* RX */
0030           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PL_EINT1 */
0031     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
0032           SUNXI_FUNCTION(0x0, "gpio_in"),
0033           SUNXI_FUNCTION(0x1, "gpio_out"),
0034           SUNXI_FUNCTION(0x3, "s_jtag"),    /* TMS */
0035           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PL_EINT2 */
0036     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
0037           SUNXI_FUNCTION(0x0, "gpio_in"),
0038           SUNXI_FUNCTION(0x1, "gpio_out"),
0039           SUNXI_FUNCTION(0x3, "s_jtag"),    /* TCK */
0040           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PL_EINT3 */
0041     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
0042           SUNXI_FUNCTION(0x0, "gpio_in"),
0043           SUNXI_FUNCTION(0x1, "gpio_out"),
0044           SUNXI_FUNCTION(0x3, "s_jtag"),    /* TDO */
0045           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PL_EINT4 */
0046     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
0047           SUNXI_FUNCTION(0x0, "gpio_in"),
0048           SUNXI_FUNCTION(0x1, "gpio_out"),
0049           SUNXI_FUNCTION(0x3, "s_jtag"),    /* TDI */
0050           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),  /* PL_EINT5 */
0051     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
0052           SUNXI_FUNCTION(0x0, "gpio_in"),
0053           SUNXI_FUNCTION(0x1, "gpio_out"),
0054           SUNXI_FUNCTION(0x3, "s_cir_rx"),
0055           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),  /* PL_EINT6 */
0056     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
0057           SUNXI_FUNCTION(0x0, "gpio_in"),
0058           SUNXI_FUNCTION(0x1, "gpio_out"),
0059           SUNXI_FUNCTION(0x3, "1wire"),
0060           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),  /* PL_EINT7 */
0061     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
0062           SUNXI_FUNCTION(0x0, "gpio_in"),
0063           SUNXI_FUNCTION(0x1, "gpio_out"),
0064           SUNXI_FUNCTION(0x2, "s_ps2"),     /* SCK1 */
0065           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),  /* PL_EINT8 */
0066     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
0067           SUNXI_FUNCTION(0x0, "gpio_in"),
0068           SUNXI_FUNCTION(0x1, "gpio_out"),
0069           SUNXI_FUNCTION(0x2, "s_ps2"),     /* SDA1 */
0070           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),  /* PL_EINT9 */
0071
0072     /* Hole */
0073     SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
0074           SUNXI_FUNCTION(0x0, "gpio_in"),
0075           SUNXI_FUNCTION(0x1, "gpio_out"),
0076           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),  /* PM_EINT0 */
0077     SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
0078           SUNXI_FUNCTION(0x0, "gpio_in"),
0079           SUNXI_FUNCTION(0x1, "gpio_out"),
0080           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),  /* PM_EINT1 */
0081     SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
0082           SUNXI_FUNCTION(0x0, "gpio_in"),
0083           SUNXI_FUNCTION(0x1, "gpio_out"),
0084           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),  /* PM_EINT2 */
0085     SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
0086           SUNXI_FUNCTION(0x0, "gpio_in"),
0087           SUNXI_FUNCTION(0x1, "gpio_out"),
0088           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),  /* PM_EINT3 */
0089     SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
0090           SUNXI_FUNCTION(0x0, "gpio_in"),
0091           SUNXI_FUNCTION(0x1, "gpio_out"),
0092           SUNXI_FUNCTION(0x3, "s_i2s1"),    /* LRCKR */
0093           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),  /* PM_EINT4 */
0094
0095     /* Hole */
0096     SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 8),
0097           SUNXI_FUNCTION(0x0, "gpio_in"),
0098           SUNXI_FUNCTION(0x1, "gpio_out"),
0099           SUNXI_FUNCTION(0x3, "s_i2c1"),    /* SCK */
0100           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),  /* PM_EINT8 */
0101     SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 9),
0102           SUNXI_FUNCTION(0x0, "gpio_in"),
0103           SUNXI_FUNCTION(0x1, "gpio_out"),
0104           SUNXI_FUNCTION(0x3, "s_i2c1"),    /* SDA */
0105           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),  /* PM_EINT9 */
0106     SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 10),
0107           SUNXI_FUNCTION(0x0, "gpio_in"),
0108           SUNXI_FUNCTION(0x1, "gpio_out"),
0109           SUNXI_FUNCTION(0x2, "s_i2s0"),    /* MCLK */
0110           SUNXI_FUNCTION(0x3, "s_i2s1")),   /* MCLK */
0111     SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 11),
0112           SUNXI_FUNCTION(0x0, "gpio_in"),
0113           SUNXI_FUNCTION(0x1, "gpio_out"),
0114           SUNXI_FUNCTION(0x2, "s_i2s0"),    /* BCLK */
0115           SUNXI_FUNCTION(0x3, "s_i2s1")),   /* BCLK */
0116     SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 12),
0117           SUNXI_FUNCTION(0x0, "gpio_in"),
0118           SUNXI_FUNCTION(0x1, "gpio_out"),
0119           SUNXI_FUNCTION(0x2, "s_i2s0"),    /* LRCK */
0120           SUNXI_FUNCTION(0x3, "s_i2s1")),   /* LRCK */
0121     SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 13),
0122           SUNXI_FUNCTION(0x0, "gpio_in"),
0123           SUNXI_FUNCTION(0x1, "gpio_out"),
0124           SUNXI_FUNCTION(0x2, "s_i2s0"),    /* DIN */
0125           SUNXI_FUNCTION(0x3, "s_i2s1")),   /* DIN */
0126     SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 14),
0127           SUNXI_FUNCTION(0x0, "gpio_in"),
0128           SUNXI_FUNCTION(0x1, "gpio_out"),
0129           SUNXI_FUNCTION(0x2, "s_i2s0"),    /* DOUT */
0130           SUNXI_FUNCTION(0x3, "s_i2s1")),   /* DOUT */
0131     SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 15),
0132           SUNXI_FUNCTION(0x0, "gpio_in"),
0133           SUNXI_FUNCTION(0x1, "gpio_out"),
0134           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), /* PM_EINT15 */
0135
0136     /* Hole */
0137     SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 0),
0138           SUNXI_FUNCTION(0x0, "gpio_in"),
0139           SUNXI_FUNCTION(0x1, "gpio_out"),
0140           SUNXI_FUNCTION(0x2, "s_i2c0"),    /* SCK */
0141           SUNXI_FUNCTION(0x3, "s_rsb")),    /* SCK */
0142     SUNXI_PIN(SUNXI_PINCTRL_PIN(N, 1),
0143           SUNXI_FUNCTION(0x0, "gpio_in"),
0144           SUNXI_FUNCTION(0x1, "gpio_out"),
0145           SUNXI_FUNCTION(0x2, "s_i2c0"),    /* SDA */
0146           SUNXI_FUNCTION(0x3, "s_rsb")),    /* SDA */
0147 };
0148
0149 static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = {
0150     .pins = sun9i_a80_r_pins,
0151     .npins = ARRAY_SIZE(sun9i_a80_r_pins),
0152     .pin_base = PL_BASE,
0153     .irq_banks = 2,
0154     .disable_strict_mode = true,
0155     .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG,
0156 };
0157
0158 static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev)
0159 {
0160     return sunxi_pinctrl_init(pdev,
0161                   &sun9i_a80_r_pinctrl_data);
0162 }
0163
0164 static const struct of_device_id sun9i_a80_r_pinctrl_match[] = {
0165     { .compatible = "allwinner,sun9i-a80-r-pinctrl", },
0166     {}
0167 };
0168
0169 static struct platform_driver sun9i_a80_r_pinctrl_driver = {
0170     .probe  = sun9i_a80_r_pinctrl_probe,
0171     .driver = {
0172         .name       = "sun9i-a80-r-pinctrl",
0173         .owner      = THIS_MODULE,
0174         .of_match_table = sun9i_a80_r_pinctrl_match,
0175     },
0176 };
0177 builtin_platform_driver(sun9i_a80_r_pinctrl_driver);