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OSCL-LXR
 
 

     

0001 /*
0002  * Allwinner a83t SoCs pinctrl driver.
0003  *
0004  * Copyright (C) 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
0005  *
0006  * Based on pinctrl-sun8i-a23.c, which is:
0007  * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
0008  * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
0009  *
0010  * This file is licensed under the terms of the GNU General Public
0011  * License version 2.  This program is licensed "as is" without any
0012  * warranty of any kind, whether express or implied.
0013  */
0014 
0015 #include <linux/init.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/of.h>
0018 #include <linux/of_device.h>
0019 #include <linux/pinctrl/pinctrl.h>
0020 
0021 #include "pinctrl-sunxi.h"
0022 
0023 static const struct sunxi_desc_pin sun8i_a83t_pins[] = {
0024     /* Hole */
0025     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
0026           SUNXI_FUNCTION(0x0, "gpio_in"),
0027           SUNXI_FUNCTION(0x1, "gpio_out"),
0028           SUNXI_FUNCTION(0x2, "uart2"),     /* TX */
0029           SUNXI_FUNCTION(0x3, "jtag"),      /* MS0 */
0030           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PB_EINT0 */
0031     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
0032           SUNXI_FUNCTION(0x0, "gpio_in"),
0033           SUNXI_FUNCTION(0x1, "gpio_out"),
0034           SUNXI_FUNCTION(0x2, "uart2"),     /* RX */
0035           SUNXI_FUNCTION(0x3, "jtag"),      /* CK0 */
0036           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PB_EINT1 */
0037     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
0038           SUNXI_FUNCTION(0x0, "gpio_in"),
0039           SUNXI_FUNCTION(0x1, "gpio_out"),
0040           SUNXI_FUNCTION(0x2, "uart2"),     /* RTS */
0041           SUNXI_FUNCTION(0x3, "jtag"),      /* DO0 */
0042           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PB_EINT2 */
0043     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
0044           SUNXI_FUNCTION(0x0, "gpio_in"),
0045           SUNXI_FUNCTION(0x1, "gpio_out"),
0046           SUNXI_FUNCTION(0x2, "uart2"),     /* CTS */
0047           SUNXI_FUNCTION(0x3, "jtag"),      /* DI0 */
0048           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PB_EINT3 */
0049     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
0050           SUNXI_FUNCTION(0x0, "gpio_in"),
0051           SUNXI_FUNCTION(0x1, "gpio_out"),
0052           SUNXI_FUNCTION(0x2, "i2s0"),      /* LRCK */
0053           SUNXI_FUNCTION(0x3, "tdm"),       /* LRCK */
0054           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PB_EINT4 */
0055     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
0056           SUNXI_FUNCTION(0x0, "gpio_in"),
0057           SUNXI_FUNCTION(0x1, "gpio_out"),
0058           SUNXI_FUNCTION(0x2, "i2s0"),      /* BCLK */
0059           SUNXI_FUNCTION(0x3, "tdm"),       /* BCLK */
0060           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),  /* PB_EINT5 */
0061     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
0062           SUNXI_FUNCTION(0x0, "gpio_in"),
0063           SUNXI_FUNCTION(0x1, "gpio_out"),
0064           SUNXI_FUNCTION(0x2, "i2s0"),      /* DOUT */
0065           SUNXI_FUNCTION(0x3, "tdm"),       /* DOUT */
0066           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),  /* PB_EINT6 */
0067     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
0068           SUNXI_FUNCTION(0x0, "gpio_in"),
0069           SUNXI_FUNCTION(0x1, "gpio_out"),
0070           SUNXI_FUNCTION(0x2, "i2s0"),      /* DIN */
0071           SUNXI_FUNCTION(0x3, "tdm"),       /* DIN */
0072           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),  /* PB_EINT7 */
0073     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
0074           SUNXI_FUNCTION(0x0, "gpio_in"),
0075           SUNXI_FUNCTION(0x1, "gpio_out"),
0076           SUNXI_FUNCTION(0x2, "i2s0"),      /* MCLK */
0077           SUNXI_FUNCTION(0x3, "tdm"),       /* MCLK */
0078           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),  /* PB_EINT8 */
0079     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
0080           SUNXI_FUNCTION(0x0, "gpio_in"),
0081           SUNXI_FUNCTION(0x1, "gpio_out"),
0082           SUNXI_FUNCTION(0x2, "uart0"),     /* TX */
0083           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),  /* PB_EINT9 */
0084     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
0085           SUNXI_FUNCTION(0x0, "gpio_in"),
0086           SUNXI_FUNCTION(0x1, "gpio_out"),
0087           SUNXI_FUNCTION(0x2, "uart0"),     /* RX */
0088           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PB_EINT10 */
0089     /* Hole */
0090     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
0091           SUNXI_FUNCTION(0x0, "gpio_in"),
0092           SUNXI_FUNCTION(0x1, "gpio_out"),
0093           SUNXI_FUNCTION(0x2, "nand0"),     /* WE */
0094           SUNXI_FUNCTION(0x3, "spi0")),     /* MOSI */
0095     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
0096           SUNXI_FUNCTION(0x0, "gpio_in"),
0097           SUNXI_FUNCTION(0x1, "gpio_out"),
0098           SUNXI_FUNCTION(0x2, "nand0"),     /* ALE */
0099           SUNXI_FUNCTION(0x3, "spi0")),     /* MISO */
0100     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
0101           SUNXI_FUNCTION(0x0, "gpio_in"),
0102           SUNXI_FUNCTION(0x1, "gpio_out"),
0103           SUNXI_FUNCTION(0x2, "nand0"),     /* CLE */
0104           SUNXI_FUNCTION(0x3, "spi0")),     /* CLK */
0105     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
0106           SUNXI_FUNCTION(0x0, "gpio_in"),
0107           SUNXI_FUNCTION(0x1, "gpio_out"),
0108           SUNXI_FUNCTION(0x2, "nand0"),     /* CE1 */
0109           SUNXI_FUNCTION(0x3, "spi0")),     /* CS */
0110     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
0111           SUNXI_FUNCTION(0x0, "gpio_in"),
0112           SUNXI_FUNCTION(0x1, "gpio_out"),
0113           SUNXI_FUNCTION(0x2, "nand0")),    /* CE0 */
0114     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
0115           SUNXI_FUNCTION(0x0, "gpio_in"),
0116           SUNXI_FUNCTION(0x1, "gpio_out"),
0117           SUNXI_FUNCTION(0x2, "nand0"),     /* RE */
0118           SUNXI_FUNCTION(0x3, "mmc2")),     /* CLK */
0119     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
0120           SUNXI_FUNCTION(0x0, "gpio_in"),
0121           SUNXI_FUNCTION(0x1, "gpio_out"),
0122           SUNXI_FUNCTION(0x2, "nand0"),     /* RB0 */
0123           SUNXI_FUNCTION(0x3, "mmc2")),     /* CMD */
0124     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
0125           SUNXI_FUNCTION(0x0, "gpio_in"),
0126           SUNXI_FUNCTION(0x1, "gpio_out"),
0127           SUNXI_FUNCTION(0x2, "nand0")),    /* RB1 */
0128     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
0129           SUNXI_FUNCTION(0x0, "gpio_in"),
0130           SUNXI_FUNCTION(0x1, "gpio_out"),
0131           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ0 */
0132           SUNXI_FUNCTION(0x3, "mmc2")),     /* D0 */
0133     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
0134           SUNXI_FUNCTION(0x0, "gpio_in"),
0135           SUNXI_FUNCTION(0x1, "gpio_out"),
0136           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ1 */
0137           SUNXI_FUNCTION(0x3, "mmc2")),     /* D1 */
0138     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
0139           SUNXI_FUNCTION(0x0, "gpio_in"),
0140           SUNXI_FUNCTION(0x1, "gpio_out"),
0141           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ2 */
0142           SUNXI_FUNCTION(0x3, "mmc2")),     /* D2 */
0143     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
0144           SUNXI_FUNCTION(0x0, "gpio_in"),
0145           SUNXI_FUNCTION(0x1, "gpio_out"),
0146           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ3 */
0147           SUNXI_FUNCTION(0x3, "mmc2")),     /* D3 */
0148     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
0149           SUNXI_FUNCTION(0x0, "gpio_in"),
0150           SUNXI_FUNCTION(0x1, "gpio_out"),
0151           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ4 */
0152           SUNXI_FUNCTION(0x3, "mmc2")),     /* D4 */
0153     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
0154           SUNXI_FUNCTION(0x0, "gpio_in"),
0155           SUNXI_FUNCTION(0x1, "gpio_out"),
0156           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ5 */
0157           SUNXI_FUNCTION(0x3, "mmc2")),     /* D5 */
0158     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
0159           SUNXI_FUNCTION(0x0, "gpio_in"),
0160           SUNXI_FUNCTION(0x1, "gpio_out"),
0161           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ6 */
0162           SUNXI_FUNCTION(0x3, "mmc2")),     /* D6 */
0163     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
0164           SUNXI_FUNCTION(0x0, "gpio_in"),
0165           SUNXI_FUNCTION(0x1, "gpio_out"),
0166           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ7 */
0167           SUNXI_FUNCTION(0x3, "mmc2")),     /* D7 */
0168     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
0169           SUNXI_FUNCTION(0x0, "gpio_in"),
0170           SUNXI_FUNCTION(0x1, "gpio_out"),
0171           SUNXI_FUNCTION(0x2, "nand0"),     /* DQS */
0172           SUNXI_FUNCTION(0x3, "mmc2")),     /* RST */
0173     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 17),
0174           SUNXI_FUNCTION(0x0, "gpio_in"),
0175           SUNXI_FUNCTION(0x1, "gpio_out"),
0176           SUNXI_FUNCTION(0x2, "nand0")),    /* CE2 */
0177     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 18),
0178           SUNXI_FUNCTION(0x0, "gpio_in"),
0179           SUNXI_FUNCTION(0x1, "gpio_out"),
0180           SUNXI_FUNCTION(0x2, "nand0")),    /* CE3 */
0181     /* Hole */
0182     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
0183           SUNXI_FUNCTION(0x0, "gpio_in"),
0184           SUNXI_FUNCTION(0x1, "gpio_out"),
0185           SUNXI_FUNCTION(0x2, "lcd0"),      /* D2 */
0186           SUNXI_FUNCTION(0x4, "gmac")),     /* RGMII / MII RXD3 */
0187     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
0188           SUNXI_FUNCTION(0x0, "gpio_in"),
0189           SUNXI_FUNCTION(0x1, "gpio_out"),
0190           SUNXI_FUNCTION(0x2, "lcd0"),      /* D3 */
0191           SUNXI_FUNCTION(0x4, "gmac")),     /* RGMII / MII RXD2 */
0192     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
0193           SUNXI_FUNCTION(0x0, "gpio_in"),
0194           SUNXI_FUNCTION(0x1, "gpio_out"),
0195           SUNXI_FUNCTION(0x2, "lcd0"),      /* D4 */
0196           SUNXI_FUNCTION(0x4, "gmac")),     /* RGMII / MII RXD1 */
0197     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
0198           SUNXI_FUNCTION(0x0, "gpio_in"),
0199           SUNXI_FUNCTION(0x1, "gpio_out"),
0200           SUNXI_FUNCTION(0x2, "lcd0"),      /* D5 */
0201           SUNXI_FUNCTION(0x4, "gmac")),     /* RGMII / MII RXD0 */
0202     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
0203           SUNXI_FUNCTION(0x0, "gpio_in"),
0204           SUNXI_FUNCTION(0x1, "gpio_out"),
0205           SUNXI_FUNCTION(0x2, "lcd0"),      /* D6 */
0206           SUNXI_FUNCTION(0x4, "gmac")),     /* RGMII / MII RXCK */
0207     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
0208           SUNXI_FUNCTION(0x0, "gpio_in"),
0209           SUNXI_FUNCTION(0x1, "gpio_out"),
0210           SUNXI_FUNCTION(0x2, "lcd0"),      /* D7 */
0211           SUNXI_FUNCTION(0x4, "gmac")),     /* RGMII / MII RXDV */
0212     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
0213           SUNXI_FUNCTION(0x0, "gpio_in"),
0214           SUNXI_FUNCTION(0x1, "gpio_out"),
0215           SUNXI_FUNCTION(0x2, "lcd0"),      /* D10 */
0216           SUNXI_FUNCTION(0x4, "gmac")),     /* RGMII / MII RXERR */
0217     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
0218           SUNXI_FUNCTION(0x0, "gpio_in"),
0219           SUNXI_FUNCTION(0x1, "gpio_out"),
0220           SUNXI_FUNCTION(0x2, "lcd0"),      /* D11 */
0221           SUNXI_FUNCTION(0x4, "gmac")),     /* RGMII / MII TXD3 */
0222     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
0223           SUNXI_FUNCTION(0x0, "gpio_in"),
0224           SUNXI_FUNCTION(0x1, "gpio_out"),
0225           SUNXI_FUNCTION(0x2, "lcd0"),      /* D12 */
0226           SUNXI_FUNCTION(0x4, "gmac")),     /* RGMII / MII TXD2 */
0227     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
0228           SUNXI_FUNCTION(0x0, "gpio_in"),
0229           SUNXI_FUNCTION(0x1, "gpio_out"),
0230           SUNXI_FUNCTION(0x2, "lcd0"),      /* D13 */
0231           SUNXI_FUNCTION(0x4, "gmac")),     /* RGMII / MII TXD1 */
0232     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
0233           SUNXI_FUNCTION(0x0, "gpio_in"),
0234           SUNXI_FUNCTION(0x1, "gpio_out"),
0235           SUNXI_FUNCTION(0x2, "lcd0"),      /* D14 */
0236           SUNXI_FUNCTION(0x4, "gmac")),     /* RGMII / MII TXD0 */
0237     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
0238           SUNXI_FUNCTION(0x0, "gpio_in"),
0239           SUNXI_FUNCTION(0x1, "gpio_out"),
0240           SUNXI_FUNCTION(0x2, "lcd0"),      /* D15 */
0241           SUNXI_FUNCTION(0x4, "gmac")), /* RGMII-NULL / MII-CRS */
0242     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
0243           SUNXI_FUNCTION(0x0, "gpio_in"),
0244           SUNXI_FUNCTION(0x1, "gpio_out"),
0245           SUNXI_FUNCTION(0x2, "lcd0"),      /* D18 */
0246           SUNXI_FUNCTION(0x3, "lvds0"),     /* VP0 */
0247           SUNXI_FUNCTION(0x4, "gmac")),     /* GTXCK / ETXCK */
0248     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
0249           SUNXI_FUNCTION(0x0, "gpio_in"),
0250           SUNXI_FUNCTION(0x1, "gpio_out"),
0251           SUNXI_FUNCTION(0x2, "lcd0"),      /* D19 */
0252           SUNXI_FUNCTION(0x3, "lvds0"),     /* VN0 */
0253           SUNXI_FUNCTION(0x4, "gmac")),     /* GTXCTL / ETXEL */
0254     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
0255           SUNXI_FUNCTION(0x0, "gpio_in"),
0256           SUNXI_FUNCTION(0x1, "gpio_out"),
0257           SUNXI_FUNCTION(0x2, "lcd0"),      /* D20 */
0258           SUNXI_FUNCTION(0x3, "lvds0"),     /* VP1 */
0259           SUNXI_FUNCTION(0x4, "gmac")),     /* GNULL / ETXERR */
0260     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
0261           SUNXI_FUNCTION(0x0, "gpio_in"),
0262           SUNXI_FUNCTION(0x1, "gpio_out"),
0263           SUNXI_FUNCTION(0x2, "lcd0"),      /* D21 */
0264           SUNXI_FUNCTION(0x3, "lvds0"),     /* VN1 */
0265           SUNXI_FUNCTION(0x4, "gmac")),     /* GCLKIN / ECOL */
0266     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
0267           SUNXI_FUNCTION(0x0, "gpio_in"),
0268           SUNXI_FUNCTION(0x1, "gpio_out"),
0269           SUNXI_FUNCTION(0x2, "lcd0"),      /* D22 */
0270           SUNXI_FUNCTION(0x3, "lvds0"),     /* VP2 */
0271           SUNXI_FUNCTION(0x4, "gmac")),     /* GMDC */
0272     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
0273           SUNXI_FUNCTION(0x0, "gpio_in"),
0274           SUNXI_FUNCTION(0x1, "gpio_out"),
0275           SUNXI_FUNCTION(0x2, "lcd0"),      /* D23 */
0276           SUNXI_FUNCTION(0x3, "lvds0"),     /* VN2 */
0277           SUNXI_FUNCTION(0x4, "gmac")),     /* GMDIO */
0278     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
0279           SUNXI_FUNCTION(0x0, "gpio_in"),
0280           SUNXI_FUNCTION(0x1, "gpio_out"),
0281           SUNXI_FUNCTION(0x2, "lcd0"),      /* CLK */
0282           SUNXI_FUNCTION(0x3, "lvds0")),    /* VPC */
0283     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
0284           SUNXI_FUNCTION(0x0, "gpio_in"),
0285           SUNXI_FUNCTION(0x1, "gpio_out"),
0286           SUNXI_FUNCTION(0x2, "lcd0"),      /* DE */
0287           SUNXI_FUNCTION(0x3, "lvds0")),    /* VNC */
0288     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
0289           SUNXI_FUNCTION(0x0, "gpio_in"),
0290           SUNXI_FUNCTION(0x1, "gpio_out"),
0291           SUNXI_FUNCTION(0x2, "lcd0"),      /* HSYNC */
0292           SUNXI_FUNCTION(0x3, "lvds0")),    /* VP3 */
0293     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 27),
0294           SUNXI_FUNCTION(0x0, "gpio_in"),
0295           SUNXI_FUNCTION(0x1, "gpio_out"),
0296           SUNXI_FUNCTION(0x2, "lcd0"),      /* VSYNC */
0297           SUNXI_FUNCTION(0x3, "lvds0")),    /* VN3 */
0298     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 28),
0299           SUNXI_FUNCTION(0x0, "gpio_in"),
0300           SUNXI_FUNCTION(0x1, "gpio_out"),
0301           SUNXI_FUNCTION(0x2, "pwm")),      /* PWM */
0302     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 29),
0303           SUNXI_FUNCTION(0x0, "gpio_in"),
0304           SUNXI_FUNCTION(0x1, "gpio_out")),
0305     /* Hole */
0306     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
0307           SUNXI_FUNCTION(0x0, "gpio_in"),
0308           SUNXI_FUNCTION(0x1, "gpio_out"),
0309           SUNXI_FUNCTION(0x2, "csi"),       /* PCLK */
0310           SUNXI_FUNCTION(0x4, "ccir")),     /* CLK */
0311     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
0312           SUNXI_FUNCTION(0x0, "gpio_in"),
0313           SUNXI_FUNCTION(0x1, "gpio_out"),
0314           SUNXI_FUNCTION(0x2, "csi"),       /* MCLK */
0315           SUNXI_FUNCTION(0x4, "ccir")),     /* DE */
0316     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
0317           SUNXI_FUNCTION(0x0, "gpio_in"),
0318           SUNXI_FUNCTION(0x1, "gpio_out"),
0319           SUNXI_FUNCTION(0x2, "csi"),       /* HSYNC */
0320           SUNXI_FUNCTION(0x4, "ccir")),     /* HSYNC */
0321     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
0322           SUNXI_FUNCTION(0x0, "gpio_in"),
0323           SUNXI_FUNCTION(0x1, "gpio_out"),
0324           SUNXI_FUNCTION(0x2, "csi"),       /* VSYNC */
0325           SUNXI_FUNCTION(0x4, "ccir")),     /* VSYNC */
0326     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
0327           SUNXI_FUNCTION(0x0, "gpio_in"),
0328           SUNXI_FUNCTION(0x1, "gpio_out"),
0329           SUNXI_FUNCTION(0x2, "csi")),      /* D0 */
0330     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
0331           SUNXI_FUNCTION(0x0, "gpio_in"),
0332           SUNXI_FUNCTION(0x1, "gpio_out"),
0333           SUNXI_FUNCTION(0x2, "csi")),      /* D1 */
0334     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
0335           SUNXI_FUNCTION(0x0, "gpio_in"),
0336           SUNXI_FUNCTION(0x1, "gpio_out"),
0337           SUNXI_FUNCTION(0x2, "csi"),       /* D2 */
0338           SUNXI_FUNCTION(0x4, "ccir")),     /* D0 */
0339     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
0340           SUNXI_FUNCTION(0x0, "gpio_in"),
0341           SUNXI_FUNCTION(0x1, "gpio_out"),
0342           SUNXI_FUNCTION(0x2, "csi"),       /* D3 */
0343           SUNXI_FUNCTION(0x4, "ccir")),     /* D1 */
0344     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
0345           SUNXI_FUNCTION(0x0, "gpio_in"),
0346           SUNXI_FUNCTION(0x1, "gpio_out"),
0347           SUNXI_FUNCTION(0x2, "csi"),       /* D4 */
0348           SUNXI_FUNCTION(0x4, "ccir")),     /* D2 */
0349     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
0350           SUNXI_FUNCTION(0x0, "gpio_in"),
0351           SUNXI_FUNCTION(0x1, "gpio_out"),
0352           SUNXI_FUNCTION(0x2, "csi"),       /* D5 */
0353           SUNXI_FUNCTION(0x4, "ccir")),     /* D3 */
0354     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
0355           SUNXI_FUNCTION(0x0, "gpio_in"),
0356           SUNXI_FUNCTION(0x1, "gpio_out"),
0357           SUNXI_FUNCTION(0x2, "csi"),       /* D6 */
0358           SUNXI_FUNCTION(0x3, "uart4"),     /* TX */
0359           SUNXI_FUNCTION(0x4, "ccir")),     /* D4 */
0360     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
0361           SUNXI_FUNCTION(0x0, "gpio_in"),
0362           SUNXI_FUNCTION(0x1, "gpio_out"),
0363           SUNXI_FUNCTION(0x2, "csi"),       /* D7 */
0364           SUNXI_FUNCTION(0x3, "uart4"),     /* RX */
0365           SUNXI_FUNCTION(0x4, "ccir")),     /* D5 */
0366     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
0367           SUNXI_FUNCTION(0x0, "gpio_in"),
0368           SUNXI_FUNCTION(0x1, "gpio_out"),
0369           SUNXI_FUNCTION(0x2, "csi"),       /* D8 */
0370           SUNXI_FUNCTION(0x3, "uart4"),     /* RTS */
0371           SUNXI_FUNCTION(0x4, "ccir")),     /* D6 */
0372     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
0373           SUNXI_FUNCTION(0x0, "gpio_in"),
0374           SUNXI_FUNCTION(0x1, "gpio_out"),
0375           SUNXI_FUNCTION(0x2, "csi"),       /* D9 */
0376           SUNXI_FUNCTION(0x3, "uart4"),     /* CTS */
0377           SUNXI_FUNCTION(0x4, "ccir")),     /* D7 */
0378     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
0379           SUNXI_FUNCTION(0x0, "gpio_in"),
0380           SUNXI_FUNCTION(0x1, "gpio_out"),
0381           SUNXI_FUNCTION(0x2, "csi"),       /* SCK */
0382           SUNXI_FUNCTION(0x3, "i2c2")),     /* SCK */
0383     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
0384           SUNXI_FUNCTION(0x0, "gpio_in"),
0385           SUNXI_FUNCTION(0x1, "gpio_out"),
0386           SUNXI_FUNCTION(0x2, "csi"),       /* SDA */
0387           SUNXI_FUNCTION(0x3, "i2c2")),     /* SDA */
0388     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
0389           SUNXI_FUNCTION(0x0, "gpio_in"),
0390           SUNXI_FUNCTION(0x1, "gpio_out")),
0391     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
0392           SUNXI_FUNCTION(0x0, "gpio_in"),
0393           SUNXI_FUNCTION(0x1, "gpio_out")),
0394     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 18),
0395           SUNXI_FUNCTION(0x0, "gpio_in"),
0396           SUNXI_FUNCTION(0x1, "gpio_out"),
0397           SUNXI_FUNCTION(0x3, "spdif")),    /* DOUT */
0398     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 19),
0399           SUNXI_FUNCTION(0x0, "gpio_in"),
0400           SUNXI_FUNCTION(0x1, "gpio_out")),
0401     /* Hole */
0402     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
0403           SUNXI_FUNCTION(0x0, "gpio_in"),
0404           SUNXI_FUNCTION(0x1, "gpio_out"),
0405           SUNXI_FUNCTION(0x2, "mmc0"),      /* D1 */
0406           SUNXI_FUNCTION(0x3, "jtag")),     /* MS1 */
0407     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
0408           SUNXI_FUNCTION(0x0, "gpio_in"),
0409           SUNXI_FUNCTION(0x1, "gpio_out"),
0410           SUNXI_FUNCTION(0x2, "mmc0"),      /* D0 */
0411           SUNXI_FUNCTION(0x3, "jtag")),     /* DI1 */
0412     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
0413           SUNXI_FUNCTION(0x0, "gpio_in"),
0414           SUNXI_FUNCTION(0x1, "gpio_out"),
0415           SUNXI_FUNCTION(0x2, "mmc0"),      /* CLK */
0416           SUNXI_FUNCTION(0x3, "uart0")),    /* TX */
0417     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
0418           SUNXI_FUNCTION(0x0, "gpio_in"),
0419           SUNXI_FUNCTION(0x1, "gpio_out"),
0420           SUNXI_FUNCTION(0x2, "mmc0"),      /* CMD */
0421           SUNXI_FUNCTION(0x3, "jtag")),     /* DO1 */
0422     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
0423           SUNXI_FUNCTION(0x0, "gpio_in"),
0424           SUNXI_FUNCTION(0x1, "gpio_out"),
0425           SUNXI_FUNCTION(0x2, "mmc0"),      /* D3 */
0426           SUNXI_FUNCTION(0x3, "uart0")),    /* RX */
0427     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
0428           SUNXI_FUNCTION(0x0, "gpio_in"),
0429           SUNXI_FUNCTION(0x1, "gpio_out"),
0430           SUNXI_FUNCTION(0x2, "mmc0"),      /* D2 */
0431           SUNXI_FUNCTION(0x3, "jtag")),     /* CK1 */
0432     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
0433           SUNXI_FUNCTION(0x0, "gpio_in"),
0434           SUNXI_FUNCTION(0x1, "gpio_out")),
0435     /* Hole */
0436     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
0437           SUNXI_FUNCTION(0x0, "gpio_in"),
0438           SUNXI_FUNCTION(0x1, "gpio_out"),
0439           SUNXI_FUNCTION(0x2, "mmc1"),      /* CLK */
0440           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),  /* PG_EINT0 */
0441     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
0442           SUNXI_FUNCTION(0x0, "gpio_in"),
0443           SUNXI_FUNCTION(0x1, "gpio_out"),
0444           SUNXI_FUNCTION(0x2, "mmc1"),      /* CMD */
0445           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),  /* PG_EINT1 */
0446     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
0447           SUNXI_FUNCTION(0x0, "gpio_in"),
0448           SUNXI_FUNCTION(0x1, "gpio_out"),
0449           SUNXI_FUNCTION(0x2, "mmc1"),      /* D0 */
0450           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),  /* PG_EINT2 */
0451     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
0452           SUNXI_FUNCTION(0x0, "gpio_in"),
0453           SUNXI_FUNCTION(0x1, "gpio_out"),
0454           SUNXI_FUNCTION(0x2, "mmc1"),      /* D1 */
0455           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),  /* PG_EINT3 */
0456     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
0457           SUNXI_FUNCTION(0x0, "gpio_in"),
0458           SUNXI_FUNCTION(0x1, "gpio_out"),
0459           SUNXI_FUNCTION(0x2, "mmc1"),      /* D2 */
0460           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),  /* PG_EINT4 */
0461     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
0462           SUNXI_FUNCTION(0x0, "gpio_in"),
0463           SUNXI_FUNCTION(0x1, "gpio_out"),
0464           SUNXI_FUNCTION(0x2, "mmc1"),      /* D3 */
0465           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),  /* PG_EINT5 */
0466     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
0467           SUNXI_FUNCTION(0x0, "gpio_in"),
0468           SUNXI_FUNCTION(0x1, "gpio_out"),
0469           SUNXI_FUNCTION(0x2, "uart1"),     /* TX */
0470           SUNXI_FUNCTION(0x3, "spi1"),      /* CS */
0471           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),  /* PG_EINT6 */
0472     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
0473           SUNXI_FUNCTION(0x0, "gpio_in"),
0474           SUNXI_FUNCTION(0x1, "gpio_out"),
0475           SUNXI_FUNCTION(0x2, "uart1"),     /* RX */
0476           SUNXI_FUNCTION(0x3, "spi1"),      /* CLK */
0477           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),  /* PG_EINT7 */
0478     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
0479           SUNXI_FUNCTION(0x0, "gpio_in"),
0480           SUNXI_FUNCTION(0x1, "gpio_out"),
0481           SUNXI_FUNCTION(0x2, "uart1"),     /* RTS */
0482           SUNXI_FUNCTION(0x3, "spi1"),      /* MOSI */
0483           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),  /* PG_EINT8 */
0484     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
0485           SUNXI_FUNCTION(0x0, "gpio_in"),
0486           SUNXI_FUNCTION(0x1, "gpio_out"),
0487           SUNXI_FUNCTION(0x2, "uart1"),     /* CTS */
0488           SUNXI_FUNCTION(0x3, "spi1"),      /* MISO */
0489           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),  /* PG_EINT9 */
0490     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
0491           SUNXI_FUNCTION(0x0, "gpio_in"),
0492           SUNXI_FUNCTION(0x1, "gpio_out"),
0493           SUNXI_FUNCTION(0x2, "i2s1"),      /* BCLK */
0494           SUNXI_FUNCTION(0x3, "uart3"),     /* TX */
0495           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */
0496     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
0497           SUNXI_FUNCTION(0x0, "gpio_in"),
0498           SUNXI_FUNCTION(0x1, "gpio_out"),
0499           SUNXI_FUNCTION(0x2, "i2s1"),      /* LRCK */
0500           SUNXI_FUNCTION(0x3, "uart3"),     /* RX */
0501           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */
0502     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
0503           SUNXI_FUNCTION(0x0, "gpio_in"),
0504           SUNXI_FUNCTION(0x1, "gpio_out"),
0505           SUNXI_FUNCTION(0x2, "i2s1"),      /* DOUT */
0506           SUNXI_FUNCTION(0x3, "uart3"),     /* RTS */
0507           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */
0508     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
0509           SUNXI_FUNCTION(0x0, "gpio_in"),
0510           SUNXI_FUNCTION(0x1, "gpio_out"),
0511           SUNXI_FUNCTION(0x2, "i2s1"),      /* DIN */
0512           SUNXI_FUNCTION(0x3, "uart3"),     /* CTS */
0513           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */
0514     /* Hole */
0515     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
0516           SUNXI_FUNCTION(0x0, "gpio_in"),
0517           SUNXI_FUNCTION(0x1, "gpio_out"),
0518           SUNXI_FUNCTION(0x2, "i2c0"),      /* SCK */
0519           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),  /* PH_EINT0 */
0520     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
0521           SUNXI_FUNCTION(0x0, "gpio_in"),
0522           SUNXI_FUNCTION(0x1, "gpio_out"),
0523           SUNXI_FUNCTION(0x2, "i2c0"),      /* SDA */
0524           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),  /* PH_EINT1 */
0525     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
0526           SUNXI_FUNCTION(0x0, "gpio_in"),
0527           SUNXI_FUNCTION(0x1, "gpio_out"),
0528           SUNXI_FUNCTION(0x2, "i2c1"),      /* SCK */
0529           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),  /* PH_EINT2 */
0530     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
0531           SUNXI_FUNCTION(0x0, "gpio_in"),
0532           SUNXI_FUNCTION(0x1, "gpio_out"),
0533           SUNXI_FUNCTION(0x2, "i2c1"),      /* SDA */
0534           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),  /* PH_EINT3 */
0535     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
0536           SUNXI_FUNCTION(0x0, "gpio_in"),
0537           SUNXI_FUNCTION(0x1, "gpio_out"),
0538           SUNXI_FUNCTION(0x2, "i2c2"),      /* SCK */
0539           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),  /* PH_EINT4 */
0540     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
0541           SUNXI_FUNCTION(0x0, "gpio_in"),
0542           SUNXI_FUNCTION(0x1, "gpio_out"),
0543           SUNXI_FUNCTION(0x2, "i2c2"),      /* SDA */
0544           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),  /* PH_EINT5 */
0545     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
0546           SUNXI_FUNCTION(0x0, "gpio_in"),
0547           SUNXI_FUNCTION(0x1, "gpio_out"),
0548           SUNXI_FUNCTION(0x2, "hdmi"),      /* HSCL */
0549           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),  /* PH_EINT6 */
0550     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
0551           SUNXI_FUNCTION(0x0, "gpio_in"),
0552           SUNXI_FUNCTION(0x1, "gpio_out"),
0553           SUNXI_FUNCTION(0x2, "hdmi"),      /* HSDA */
0554           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),  /* PH_EINT7 */
0555     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
0556           SUNXI_FUNCTION(0x0, "gpio_in"),
0557           SUNXI_FUNCTION(0x1, "gpio_out"),
0558           SUNXI_FUNCTION(0x2, "hdmi"),      /* HCEC */
0559           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),  /* PH_EINT8 */
0560     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
0561           SUNXI_FUNCTION(0x0, "gpio_in"),
0562           SUNXI_FUNCTION(0x1, "gpio_out"),
0563           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),  /* PH_EINT9 */
0564     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
0565           SUNXI_FUNCTION(0x0, "gpio_in"),
0566           SUNXI_FUNCTION(0x1, "gpio_out"),
0567           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PH_EINT10 */
0568     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
0569           SUNXI_FUNCTION(0x0, "gpio_in"),
0570           SUNXI_FUNCTION(0x1, "gpio_out"),
0571           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PH_EINT11 */
0572 };
0573 
0574 static const struct sunxi_pinctrl_desc sun8i_a83t_pinctrl_data = {
0575     .pins = sun8i_a83t_pins,
0576     .npins = ARRAY_SIZE(sun8i_a83t_pins),
0577     .irq_banks = 3,
0578 };
0579 
0580 static int sun8i_a83t_pinctrl_probe(struct platform_device *pdev)
0581 {
0582     return sunxi_pinctrl_init(pdev,
0583                   &sun8i_a83t_pinctrl_data);
0584 }
0585 
0586 static const struct of_device_id sun8i_a83t_pinctrl_match[] = {
0587     { .compatible = "allwinner,sun8i-a83t-pinctrl", },
0588     {}
0589 };
0590 
0591 static struct platform_driver sun8i_a83t_pinctrl_driver = {
0592     .probe  = sun8i_a83t_pinctrl_probe,
0593     .driver = {
0594         .name       = "sun8i-a83t-pinctrl",
0595         .of_match_table = sun8i_a83t_pinctrl_match,
0596     },
0597 };
0598 builtin_platform_driver(sun8i_a83t_pinctrl_driver);
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