Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Allwinner H616 SoC pinctrl driver.
0004  *
0005  * Copyright (C) 2020 Arm Ltd.
0006  * based on the H6 pinctrl driver
0007  *   Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
0008  */
0009 
0010 #include <linux/module.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/of.h>
0013 #include <linux/of_device.h>
0014 #include <linux/pinctrl/pinctrl.h>
0015 
0016 #include "pinctrl-sunxi.h"
0017 
0018 static const struct sunxi_desc_pin h616_pins[] = {
0019     /* Internal connection to the AC200 part */
0020     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
0021           SUNXI_FUNCTION(0x2, "emac1")),    /* ERXD1 */
0022     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
0023           SUNXI_FUNCTION(0x2, "emac1")),    /* ERXD0 */
0024     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
0025           SUNXI_FUNCTION(0x2, "emac1")),    /* ECRS_DV */
0026     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
0027           SUNXI_FUNCTION(0x2, "emac1")),    /* ERXERR */
0028     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
0029           SUNXI_FUNCTION(0x2, "emac1")),    /* ETXD1 */
0030     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
0031           SUNXI_FUNCTION(0x2, "emac1")),    /* ETXD0 */
0032     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
0033           SUNXI_FUNCTION(0x2, "emac1")),    /* ETXCK */
0034     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
0035           SUNXI_FUNCTION(0x2, "emac1")),    /* ETXEN */
0036     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
0037           SUNXI_FUNCTION(0x2, "emac1")),    /* EMDC */
0038     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
0039           SUNXI_FUNCTION(0x2, "emac1")),    /* EMDIO */
0040     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
0041           SUNXI_FUNCTION(0x2, "i2c3")),     /* SCK */
0042     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
0043           SUNXI_FUNCTION(0x2, "i2c3")),     /* SDA */
0044     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
0045           SUNXI_FUNCTION(0x2, "pwm5")),
0046     /* Hole */
0047     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
0048           SUNXI_FUNCTION(0x0, "gpio_in"),
0049           SUNXI_FUNCTION(0x1, "gpio_out"),
0050           SUNXI_FUNCTION(0x2, "nand0"),     /* WE */
0051           SUNXI_FUNCTION(0x3, "mmc2"),      /* DS */
0052           SUNXI_FUNCTION(0x4, "spi0"),      /* CLK */
0053           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),  /* PC_EINT0 */
0054     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
0055           SUNXI_FUNCTION(0x0, "gpio_in"),
0056           SUNXI_FUNCTION(0x1, "gpio_out"),
0057           SUNXI_FUNCTION(0x2, "nand0"),     /* ALE */
0058           SUNXI_FUNCTION(0x3, "mmc2"),      /* RST */
0059           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),  /* PC_EINT1 */
0060     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
0061           SUNXI_FUNCTION(0x0, "gpio_in"),
0062           SUNXI_FUNCTION(0x1, "gpio_out"),
0063           SUNXI_FUNCTION(0x2, "nand0"),     /* CLE */
0064           SUNXI_FUNCTION(0x4, "spi0"),      /* MOSI */
0065           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),  /* PC_EINT2 */
0066     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
0067           SUNXI_FUNCTION(0x0, "gpio_in"),
0068           SUNXI_FUNCTION(0x1, "gpio_out"),
0069           SUNXI_FUNCTION(0x2, "nand0"),     /* CE1 */
0070           SUNXI_FUNCTION(0x4, "spi0"),      /* CS0 */
0071           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),  /* PC_EINT3 */
0072     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
0073           SUNXI_FUNCTION(0x0, "gpio_in"),
0074           SUNXI_FUNCTION(0x1, "gpio_out"),
0075           SUNXI_FUNCTION(0x2, "nand0"),     /* CE0 */
0076           SUNXI_FUNCTION(0x4, "spi0"),      /* MISO */
0077           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),  /* PC_EINT4 */
0078     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
0079           SUNXI_FUNCTION(0x0, "gpio_in"),
0080           SUNXI_FUNCTION(0x1, "gpio_out"),
0081           SUNXI_FUNCTION(0x2, "nand0"),     /* RE */
0082           SUNXI_FUNCTION(0x3, "mmc2"),      /* CLK */
0083           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),  /* PC_EINT5 */
0084     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
0085           SUNXI_FUNCTION(0x0, "gpio_in"),
0086           SUNXI_FUNCTION(0x1, "gpio_out"),
0087           SUNXI_FUNCTION(0x2, "nand0"),     /* RB0 */
0088           SUNXI_FUNCTION(0x3, "mmc2"),      /* CMD */
0089           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),  /* PC_EINT6 */
0090     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
0091           SUNXI_FUNCTION(0x0, "gpio_in"),
0092           SUNXI_FUNCTION(0x1, "gpio_out"),
0093           SUNXI_FUNCTION(0x2, "nand0"),     /* RB1 */
0094           SUNXI_FUNCTION(0x4, "spi0"),      /* CS1 */
0095           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),  /* PC_EINT7 */
0096     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
0097           SUNXI_FUNCTION(0x0, "gpio_in"),
0098           SUNXI_FUNCTION(0x1, "gpio_out"),
0099           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ7 */
0100           SUNXI_FUNCTION(0x3, "mmc2"),      /* D3 */
0101           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),  /* PC_EINT8 */
0102     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
0103           SUNXI_FUNCTION(0x0, "gpio_in"),
0104           SUNXI_FUNCTION(0x1, "gpio_out"),
0105           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ6 */
0106           SUNXI_FUNCTION(0x3, "mmc2"),      /* D4 */
0107           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),  /* PC_EINT9 */
0108     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
0109           SUNXI_FUNCTION(0x0, "gpio_in"),
0110           SUNXI_FUNCTION(0x1, "gpio_out"),
0111           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ5 */
0112           SUNXI_FUNCTION(0x3, "mmc2"),      /* D0 */
0113           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PC_EINT10 */
0114     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
0115           SUNXI_FUNCTION(0x0, "gpio_in"),
0116           SUNXI_FUNCTION(0x1, "gpio_out"),
0117           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ4 */
0118           SUNXI_FUNCTION(0x3, "mmc2"),      /* D5 */
0119           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PC_EINT11 */
0120     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
0121           SUNXI_FUNCTION(0x0, "gpio_in"),
0122           SUNXI_FUNCTION(0x1, "gpio_out"),
0123           SUNXI_FUNCTION(0x2, "nand0"),     /* DQS */
0124           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PC_EINT12 */
0125     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
0126           SUNXI_FUNCTION(0x0, "gpio_in"),
0127           SUNXI_FUNCTION(0x1, "gpio_out"),
0128           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ3 */
0129           SUNXI_FUNCTION(0x3, "mmc2"),      /* D1 */
0130           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PC_EINT13 */
0131     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
0132           SUNXI_FUNCTION(0x0, "gpio_in"),
0133           SUNXI_FUNCTION(0x1, "gpio_out"),
0134           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ2 */
0135           SUNXI_FUNCTION(0x3, "mmc2"),      /* D6 */
0136           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), /* PC_EINT14 */
0137     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
0138           SUNXI_FUNCTION(0x0, "gpio_in"),
0139           SUNXI_FUNCTION(0x1, "gpio_out"),
0140           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ1 */
0141           SUNXI_FUNCTION(0x3, "mmc2"),      /* D2 */
0142           SUNXI_FUNCTION(0x4, "spi0"),      /* WP */
0143           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), /* PC_EINT15 */
0144     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
0145           SUNXI_FUNCTION(0x0, "gpio_in"),
0146           SUNXI_FUNCTION(0x1, "gpio_out"),
0147           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ0 */
0148           SUNXI_FUNCTION(0x3, "mmc2"),      /* D7 */
0149           SUNXI_FUNCTION(0x4, "spi0"),      /* HOLD */
0150           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), /* PC_EINT16 */
0151     /* Hole */
0152     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
0153           SUNXI_FUNCTION(0x0, "gpio_in"),
0154           SUNXI_FUNCTION(0x1, "gpio_out"),
0155           SUNXI_FUNCTION(0x2, "mmc0"),      /* D1 */
0156           SUNXI_FUNCTION(0x3, "jtag"),      /* MS */
0157           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 0)),  /* PF_EINT0 */
0158     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
0159           SUNXI_FUNCTION(0x0, "gpio_in"),
0160           SUNXI_FUNCTION(0x1, "gpio_out"),
0161           SUNXI_FUNCTION(0x2, "mmc0"),      /* D0 */
0162           SUNXI_FUNCTION(0x3, "jtag"),      /* DI */
0163           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 1)),  /* PF_EINT1 */
0164     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
0165           SUNXI_FUNCTION(0x0, "gpio_in"),
0166           SUNXI_FUNCTION(0x1, "gpio_out"),
0167           SUNXI_FUNCTION(0x2, "mmc0"),      /* CLK */
0168           SUNXI_FUNCTION(0x3, "uart0"),     /* TX */
0169           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 2)),  /* PF_EINT2 */
0170     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
0171           SUNXI_FUNCTION(0x0, "gpio_in"),
0172           SUNXI_FUNCTION(0x1, "gpio_out"),
0173           SUNXI_FUNCTION(0x2, "mmc0"),      /* CMD */
0174           SUNXI_FUNCTION(0x3, "jtag"),      /* DO */
0175           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 3)),  /* PF_EINT3 */
0176     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
0177           SUNXI_FUNCTION(0x0, "gpio_in"),
0178           SUNXI_FUNCTION(0x1, "gpio_out"),
0179           SUNXI_FUNCTION(0x2, "mmc0"),      /* D3 */
0180           SUNXI_FUNCTION(0x3, "uart0"),     /* RX */
0181           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4)),  /* PF_EINT4 */
0182     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
0183           SUNXI_FUNCTION(0x0, "gpio_in"),
0184           SUNXI_FUNCTION(0x1, "gpio_out"),
0185           SUNXI_FUNCTION(0x2, "mmc0"),      /* D2 */
0186           SUNXI_FUNCTION(0x3, "jtag"),      /* CK */
0187           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 5)),  /* PF_EINT5 */
0188     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
0189           SUNXI_FUNCTION(0x0, "gpio_in"),
0190           SUNXI_FUNCTION(0x1, "gpio_out"),
0191           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 6)),  /* PF_EINT6 */
0192     /* Hole */
0193     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
0194           SUNXI_FUNCTION(0x0, "gpio_in"),
0195           SUNXI_FUNCTION(0x1, "gpio_out"),
0196           SUNXI_FUNCTION(0x2, "mmc1"),      /* CLK */
0197           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 0)),  /* PG_EINT0 */
0198     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
0199           SUNXI_FUNCTION(0x0, "gpio_in"),
0200           SUNXI_FUNCTION(0x1, "gpio_out"),
0201           SUNXI_FUNCTION(0x2, "mmc1"),      /* CMD */
0202           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 1)),  /* PG_EINT1 */
0203     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
0204           SUNXI_FUNCTION(0x0, "gpio_in"),
0205           SUNXI_FUNCTION(0x1, "gpio_out"),
0206           SUNXI_FUNCTION(0x2, "mmc1"),      /* D0 */
0207           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 2)),  /* PG_EINT2 */
0208     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
0209           SUNXI_FUNCTION(0x0, "gpio_in"),
0210           SUNXI_FUNCTION(0x1, "gpio_out"),
0211           SUNXI_FUNCTION(0x2, "mmc1"),      /* D1 */
0212           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3)),  /* PG_EINT3 */
0213     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
0214           SUNXI_FUNCTION(0x0, "gpio_in"),
0215           SUNXI_FUNCTION(0x1, "gpio_out"),
0216           SUNXI_FUNCTION(0x2, "mmc1"),      /* D2 */
0217           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4)),  /* PG_EINT4 */
0218     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
0219           SUNXI_FUNCTION(0x0, "gpio_in"),
0220           SUNXI_FUNCTION(0x1, "gpio_out"),
0221           SUNXI_FUNCTION(0x2, "mmc1"),      /* D3 */
0222           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5)),  /* PG_EINT5 */
0223     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
0224           SUNXI_FUNCTION(0x0, "gpio_in"),
0225           SUNXI_FUNCTION(0x1, "gpio_out"),
0226           SUNXI_FUNCTION(0x2, "uart1"),     /* TX */
0227           SUNXI_FUNCTION(0x4, "jtag"),      /* MS */
0228           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 6)),  /* PG_EINT6 */
0229     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
0230           SUNXI_FUNCTION(0x0, "gpio_in"),
0231           SUNXI_FUNCTION(0x1, "gpio_out"),
0232           SUNXI_FUNCTION(0x2, "uart1"),     /* RX */
0233           SUNXI_FUNCTION(0x4, "jtag"),      /* CK */
0234           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 7)),  /* PG_EINT7 */
0235     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
0236           SUNXI_FUNCTION(0x0, "gpio_in"),
0237           SUNXI_FUNCTION(0x1, "gpio_out"),
0238           SUNXI_FUNCTION(0x2, "uart1"),     /* RTS */
0239           SUNXI_FUNCTION(0x3, "clock"),     /* PLL_LOCK_DEBUG */
0240           SUNXI_FUNCTION(0x4, "jtag"),      /* DO */
0241           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 8)),  /* PG_EINT8 */
0242     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
0243           SUNXI_FUNCTION(0x0, "gpio_in"),
0244           SUNXI_FUNCTION(0x1, "gpio_out"),
0245           SUNXI_FUNCTION(0x2, "uart1"),     /* CTS */
0246           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 9)),  /* PG_EINT9 */
0247     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
0248           SUNXI_FUNCTION(0x0, "gpio_in"),
0249           SUNXI_FUNCTION(0x1, "gpio_out"),
0250           SUNXI_FUNCTION(0x2, "i2s2"),  /* MCLK */
0251           SUNXI_FUNCTION(0x3, "clock"),     /* X32KFOUT */
0252           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 10)), /* PG_EINT10 */
0253     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
0254           SUNXI_FUNCTION(0x0, "gpio_in"),
0255           SUNXI_FUNCTION(0x1, "gpio_out"),
0256           SUNXI_FUNCTION(0x2, "i2s2"),  /* BCLK */
0257           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 11)), /* PG_EINT11 */
0258     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
0259           SUNXI_FUNCTION(0x0, "gpio_in"),
0260           SUNXI_FUNCTION(0x1, "gpio_out"),
0261           SUNXI_FUNCTION(0x2, "i2s2"),  /* SYNC */
0262           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 12)), /* PG_EINT12 */
0263     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
0264           SUNXI_FUNCTION(0x0, "gpio_in"),
0265           SUNXI_FUNCTION(0x1, "gpio_out"),
0266           SUNXI_FUNCTION(0x2, "i2s2"),  /* DOUT */
0267           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 13)), /* PG_EINT13 */
0268     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
0269           SUNXI_FUNCTION(0x0, "gpio_in"),
0270           SUNXI_FUNCTION(0x1, "gpio_out"),
0271           SUNXI_FUNCTION(0x2, "i2s2"),  /* DIN */
0272           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 14)), /* PG_EINT14 */
0273     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 15),
0274           SUNXI_FUNCTION(0x0, "gpio_in"),
0275           SUNXI_FUNCTION(0x1, "gpio_out"),
0276           SUNXI_FUNCTION(0x2, "uart2"),     /* TX */
0277           SUNXI_FUNCTION(0x5, "i2c4"),      /* SCK */
0278           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 15)), /* PG_EINT15 */
0279     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 16),
0280           SUNXI_FUNCTION(0x0, "gpio_in"),
0281           SUNXI_FUNCTION(0x1, "gpio_out"),
0282           SUNXI_FUNCTION(0x2, "uart2"),     /* RX */
0283           SUNXI_FUNCTION(0x5, "i2c4"),      /* SDA */
0284           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 16)), /* PG_EINT16 */
0285     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 17),
0286           SUNXI_FUNCTION(0x0, "gpio_in"),
0287           SUNXI_FUNCTION(0x1, "gpio_out"),
0288           SUNXI_FUNCTION(0x2, "uart2"),     /* RTS */
0289           SUNXI_FUNCTION(0x5, "i2c3"),      /* SCK */
0290           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 17)), /* PG_EINT17 */
0291     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 18),
0292           SUNXI_FUNCTION(0x0, "gpio_in"),
0293           SUNXI_FUNCTION(0x1, "gpio_out"),
0294           SUNXI_FUNCTION(0x2, "uart2"),     /* CTS */
0295           SUNXI_FUNCTION(0x5, "i2c3"),      /* SDA */
0296           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 18)), /* PG_EINT18 */
0297     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 19),
0298           SUNXI_FUNCTION(0x0, "gpio_in"),
0299           SUNXI_FUNCTION(0x1, "gpio_out"),
0300           SUNXI_FUNCTION(0x4, "pwm1"),
0301           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 19)), /* PG_EINT19 */
0302     /* Hole */
0303     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
0304           SUNXI_FUNCTION(0x0, "gpio_in"),
0305           SUNXI_FUNCTION(0x1, "gpio_out"),
0306           SUNXI_FUNCTION(0x2, "uart0"),     /* TX */
0307           SUNXI_FUNCTION(0x4, "pwm3"),
0308           SUNXI_FUNCTION(0x5, "i2c1"),      /* SCK */
0309           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),  /* PH_EINT0 */
0310     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
0311           SUNXI_FUNCTION(0x0, "gpio_in"),
0312           SUNXI_FUNCTION(0x1, "gpio_out"),
0313           SUNXI_FUNCTION(0x2, "uart0"),     /* RX */
0314           SUNXI_FUNCTION(0x4, "pwm4"),
0315           SUNXI_FUNCTION(0x5, "i2c1"),      /* SDA */
0316           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),  /* PH_EINT1 */
0317     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
0318           SUNXI_FUNCTION(0x0, "gpio_in"),
0319           SUNXI_FUNCTION(0x1, "gpio_out"),
0320           SUNXI_FUNCTION(0x2, "uart5"),     /* TX */
0321           SUNXI_FUNCTION(0x3, "spdif"),     /* MCLK */
0322           SUNXI_FUNCTION(0x4, "pwm2"),
0323           SUNXI_FUNCTION(0x5, "i2c2"),      /* SCK */
0324           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),  /* PH_EINT2 */
0325     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
0326           SUNXI_FUNCTION(0x0, "gpio_in"),
0327           SUNXI_FUNCTION(0x1, "gpio_out"),
0328           SUNXI_FUNCTION(0x2, "uart5"),     /* RX */
0329           SUNXI_FUNCTION(0x4, "pwm1"),
0330           SUNXI_FUNCTION(0x5, "i2c2"),      /* SDA */
0331           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),  /* PH_EINT3 */
0332     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
0333           SUNXI_FUNCTION(0x0, "gpio_in"),
0334           SUNXI_FUNCTION(0x1, "gpio_out"),
0335           SUNXI_FUNCTION(0x3, "spdif"),     /* OUT */
0336           SUNXI_FUNCTION(0x5, "i2c3"),      /* SCK */
0337           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),  /* PH_EINT4 */
0338     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
0339           SUNXI_FUNCTION(0x0, "gpio_in"),
0340           SUNXI_FUNCTION(0x1, "gpio_out"),
0341           SUNXI_FUNCTION(0x2, "uart2"),     /* TX */
0342           SUNXI_FUNCTION(0x3, "i2s3"),  /* MCLK */
0343           SUNXI_FUNCTION(0x4, "spi1"),      /* CS0 */
0344           SUNXI_FUNCTION(0x5, "i2c3"),      /* SDA */
0345           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),  /* PH_EINT5 */
0346     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
0347           SUNXI_FUNCTION(0x0, "gpio_in"),
0348           SUNXI_FUNCTION(0x1, "gpio_out"),
0349           SUNXI_FUNCTION(0x2, "uart2"),     /* RX */
0350           SUNXI_FUNCTION(0x3, "i2s3"),  /* BCLK */
0351           SUNXI_FUNCTION(0x4, "spi1"),      /* CLK */
0352           SUNXI_FUNCTION(0x5, "i2c4"),      /* SCK */
0353           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),  /* PH_EINT6 */
0354     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
0355           SUNXI_FUNCTION(0x0, "gpio_in"),
0356           SUNXI_FUNCTION(0x1, "gpio_out"),
0357           SUNXI_FUNCTION(0x2, "uart2"),     /* RTS */
0358           SUNXI_FUNCTION(0x3, "i2s3"),  /* SYNC */
0359           SUNXI_FUNCTION(0x4, "spi1"),      /* MOSI */
0360           SUNXI_FUNCTION(0x5, "i2c4"),      /* SDA */
0361           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),  /* PH_EINT7 */
0362     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
0363           SUNXI_FUNCTION(0x0, "gpio_in"),
0364           SUNXI_FUNCTION(0x1, "gpio_out"),
0365           SUNXI_FUNCTION(0x2, "uart2"),     /* CTS */
0366           SUNXI_FUNCTION(0x3, "i2s3_dout0"),    /* DO0 */
0367           SUNXI_FUNCTION(0x4, "spi1"),      /* MISO */
0368           SUNXI_FUNCTION(0x5, "i2s3_din1"), /* DI1 */
0369           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 8)),  /* PH_EINT8 */
0370     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
0371           SUNXI_FUNCTION(0x0, "gpio_in"),
0372           SUNXI_FUNCTION(0x1, "gpio_out"),
0373           SUNXI_FUNCTION(0x3, "i2s3_din0"), /* DI0 */
0374           SUNXI_FUNCTION(0x4, "spi1"),      /* CS1 */
0375           SUNXI_FUNCTION(0x5, "i2s3_dout1"),    /* DO1 */
0376           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),  /* PH_EINT9 */
0377     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
0378           SUNXI_FUNCTION(0x0, "gpio_in"),
0379           SUNXI_FUNCTION(0x1, "gpio_out"),
0380           SUNXI_FUNCTION(0x3, "ir_rx"),
0381           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)), /* PH_EINT10 */
0382     /* Hole */
0383     SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 0),
0384           SUNXI_FUNCTION(0x0, "gpio_in"),
0385           SUNXI_FUNCTION(0x1, "gpio_out"),
0386           SUNXI_FUNCTION(0x2, "emac0"),     /* ERXD3 */
0387           SUNXI_FUNCTION(0x3, "dmic"),      /* CLK */
0388           SUNXI_FUNCTION(0x4, "i2s0"),  /* MCLK */
0389           SUNXI_FUNCTION(0x5, "hdmi"),      /* HSCL */
0390           SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 0)),  /* PI_EINT0 */
0391     SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 1),
0392           SUNXI_FUNCTION(0x0, "gpio_in"),
0393           SUNXI_FUNCTION(0x1, "gpio_out"),
0394           SUNXI_FUNCTION(0x2, "emac0"),     /* ERXD2 */
0395           SUNXI_FUNCTION(0x3, "dmic"),      /* DATA0 */
0396           SUNXI_FUNCTION(0x4, "i2s0"),  /* BCLK */
0397           SUNXI_FUNCTION(0x5, "hdmi"),      /* HSDA */
0398           SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 1)),  /* PI_EINT1 */
0399     SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 2),
0400           SUNXI_FUNCTION(0x0, "gpio_in"),
0401           SUNXI_FUNCTION(0x1, "gpio_out"),
0402           SUNXI_FUNCTION(0x2, "emac0"),     /* ERXD1 */
0403           SUNXI_FUNCTION(0x3, "dmic"),      /* DATA1 */
0404           SUNXI_FUNCTION(0x4, "i2s0"),  /* SYNC */
0405           SUNXI_FUNCTION(0x5, "hdmi"),      /* HCEC */
0406           SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 2)),  /* PI_EINT2 */
0407     SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 3),
0408           SUNXI_FUNCTION(0x0, "gpio_in"),
0409           SUNXI_FUNCTION(0x1, "gpio_out"),
0410           SUNXI_FUNCTION(0x2, "emac0"),     /* ERXD0 */
0411           SUNXI_FUNCTION(0x3, "dmic"),      /* DATA2 */
0412           SUNXI_FUNCTION(0x4, "i2s0_dout0"),    /* DO0 */
0413           SUNXI_FUNCTION(0x5, "i2s0_din1"), /* DI1 */
0414           SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 3)),  /* PI_EINT3 */
0415     SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 4),
0416           SUNXI_FUNCTION(0x0, "gpio_in"),
0417           SUNXI_FUNCTION(0x1, "gpio_out"),
0418           SUNXI_FUNCTION(0x2, "emac0"),     /* ERXCK */
0419           SUNXI_FUNCTION(0x3, "dmic"),      /* DATA3 */
0420           SUNXI_FUNCTION(0x4, "i2s0_din0"), /* DI0 */
0421           SUNXI_FUNCTION(0x5, "i2s0_dout1"),    /* DO1 */
0422           SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 4)),  /* PI_EINT4 */
0423     SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 5),
0424           SUNXI_FUNCTION(0x0, "gpio_in"),
0425           SUNXI_FUNCTION(0x1, "gpio_out"),
0426           SUNXI_FUNCTION(0x2, "emac0"),     /* ERXCTL */
0427           SUNXI_FUNCTION(0x3, "uart2"),     /* TX */
0428           SUNXI_FUNCTION(0x4, "ts0"),       /* CLK */
0429           SUNXI_FUNCTION(0x5, "i2c0"),      /* SCK */
0430           SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 5)),  /* PI_EINT5 */
0431     SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 6),
0432           SUNXI_FUNCTION(0x0, "gpio_in"),
0433           SUNXI_FUNCTION(0x1, "gpio_out"),
0434           SUNXI_FUNCTION(0x2, "emac0"),     /* ENULL */
0435           SUNXI_FUNCTION(0x3, "uart2"),     /* RX */
0436           SUNXI_FUNCTION(0x4, "ts0"),       /* ERR */
0437           SUNXI_FUNCTION(0x5, "i2c0"),      /* SDA */
0438           SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 6)),  /* PI_EINT6 */
0439     SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 7),
0440           SUNXI_FUNCTION(0x0, "gpio_in"),
0441           SUNXI_FUNCTION(0x1, "gpio_out"),
0442           SUNXI_FUNCTION(0x2, "emac0"),     /* ETXD3 */
0443           SUNXI_FUNCTION(0x3, "uart2"),     /* RTS */
0444           SUNXI_FUNCTION(0x4, "ts0"),       /* SYNC */
0445           SUNXI_FUNCTION(0x5, "i2c1"),      /* SCK */
0446           SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 7)),  /* PI_EINT7 */
0447     SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 8),
0448           SUNXI_FUNCTION(0x0, "gpio_in"),
0449           SUNXI_FUNCTION(0x1, "gpio_out"),
0450           SUNXI_FUNCTION(0x2, "emac0"),     /* ETXD2 */
0451           SUNXI_FUNCTION(0x3, "uart2"),     /* CTS */
0452           SUNXI_FUNCTION(0x4, "ts0"),       /* DVLD */
0453           SUNXI_FUNCTION(0x5, "i2c1"),      /* SDA */
0454           SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 8)),  /* PI_EINT8 */
0455     SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 9),
0456           SUNXI_FUNCTION(0x0, "gpio_in"),
0457           SUNXI_FUNCTION(0x1, "gpio_out"),
0458           SUNXI_FUNCTION(0x2, "emac0"),     /* ETXD1 */
0459           SUNXI_FUNCTION(0x3, "uart3"),     /* TX */
0460           SUNXI_FUNCTION(0x4, "ts0"),       /* D0 */
0461           SUNXI_FUNCTION(0x5, "i2c2"),      /* SCK */
0462           SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 9)),  /* PI_EINT9 */
0463     SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 10),
0464           SUNXI_FUNCTION(0x0, "gpio_in"),
0465           SUNXI_FUNCTION(0x1, "gpio_out"),
0466           SUNXI_FUNCTION(0x2, "emac0"),     /* ETXD0 */
0467           SUNXI_FUNCTION(0x3, "uart3"),     /* RX */
0468           SUNXI_FUNCTION(0x4, "ts0"),       /* D1 */
0469           SUNXI_FUNCTION(0x5, "i2c2"),      /* SDA */
0470           SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 10)), /* PI_EINT10 */
0471     SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 11),
0472           SUNXI_FUNCTION(0x0, "gpio_in"),
0473           SUNXI_FUNCTION(0x1, "gpio_out"),
0474           SUNXI_FUNCTION(0x2, "emac0"),     /* ETXCK */
0475           SUNXI_FUNCTION(0x3, "uart3"),     /* RTS */
0476           SUNXI_FUNCTION(0x4, "ts0"),       /* D2 */
0477           SUNXI_FUNCTION(0x5, "pwm1"),
0478           SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 11)), /* PI_EINT11 */
0479     SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 12),
0480           SUNXI_FUNCTION(0x0, "gpio_in"),
0481           SUNXI_FUNCTION(0x1, "gpio_out"),
0482           SUNXI_FUNCTION(0x2, "emac0"),     /* ETXCTL */
0483           SUNXI_FUNCTION(0x3, "uart3"),     /* CTS */
0484           SUNXI_FUNCTION(0x4, "ts0"),       /* D3 */
0485           SUNXI_FUNCTION(0x5, "pwm2"),
0486           SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 12)), /* PI_EINT12 */
0487     SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 13),
0488           SUNXI_FUNCTION(0x0, "gpio_in"),
0489           SUNXI_FUNCTION(0x1, "gpio_out"),
0490           SUNXI_FUNCTION(0x2, "emac0"),     /* ECLKIN */
0491           SUNXI_FUNCTION(0x3, "uart4"),     /* TX */
0492           SUNXI_FUNCTION(0x4, "ts0"),       /* D4 */
0493           SUNXI_FUNCTION(0x5, "pwm3"),
0494           SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 13)), /* PI_EINT13 */
0495     SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 14),
0496           SUNXI_FUNCTION(0x0, "gpio_in"),
0497           SUNXI_FUNCTION(0x1, "gpio_out"),
0498           SUNXI_FUNCTION(0x2, "emac0"),     /* MDC */
0499           SUNXI_FUNCTION(0x3, "uart4"),     /* RX */
0500           SUNXI_FUNCTION(0x4, "ts0"),       /* D5 */
0501           SUNXI_FUNCTION(0x5, "pwm4"),
0502           SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 14)), /* PI_EINT14 */
0503     SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 15),
0504           SUNXI_FUNCTION(0x0, "gpio_in"),
0505           SUNXI_FUNCTION(0x1, "gpio_out"),
0506           SUNXI_FUNCTION(0x2, "emac0"),     /* MDIO */
0507           SUNXI_FUNCTION(0x3, "uart4"),     /* RTS */
0508           SUNXI_FUNCTION(0x4, "ts0"),       /* D6 */
0509           SUNXI_FUNCTION(0x5, "clock"),     /* CLK_FANOUT0 */
0510           SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 15)), /* PI_EINT15 */
0511     SUNXI_PIN(SUNXI_PINCTRL_PIN(I, 16),
0512           SUNXI_FUNCTION(0x0, "gpio_in"),
0513           SUNXI_FUNCTION(0x1, "gpio_out"),
0514           SUNXI_FUNCTION(0x2, "emac0"),     /* EPHY_CLK */
0515           SUNXI_FUNCTION(0x3, "uart4"),     /* CTS */
0516           SUNXI_FUNCTION(0x4, "ts0"),       /* D7 */
0517           SUNXI_FUNCTION(0x5, "clock"),     /* CLK_FANOUT1 */
0518           SUNXI_FUNCTION_IRQ_BANK(0x6, 7, 16)), /* PI_EINT16 */
0519 };
0520 static const unsigned int h616_irq_bank_map[] = { 0, 2, 3, 4, 5, 6, 7, 8 };
0521 
0522 static const struct sunxi_pinctrl_desc h616_pinctrl_data = {
0523     .pins = h616_pins,
0524     .npins = ARRAY_SIZE(h616_pins),
0525     .irq_banks = ARRAY_SIZE(h616_irq_bank_map),
0526     .irq_bank_map = h616_irq_bank_map,
0527     .irq_read_needs_mux = true,
0528     .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
0529 };
0530 
0531 static int h616_pinctrl_probe(struct platform_device *pdev)
0532 {
0533     return sunxi_pinctrl_init(pdev, &h616_pinctrl_data);
0534 }
0535 
0536 static const struct of_device_id h616_pinctrl_match[] = {
0537     { .compatible = "allwinner,sun50i-h616-pinctrl", },
0538     {}
0539 };
0540 
0541 static struct platform_driver h616_pinctrl_driver = {
0542     .probe  = h616_pinctrl_probe,
0543     .driver = {
0544         .name       = "sun50i-h616-pinctrl",
0545         .of_match_table = h616_pinctrl_match,
0546     },
0547 };
0548 builtin_platform_driver(h616_pinctrl_driver);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!