Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Allwinner H6 SoC pinctrl driver.
0004  *
0005  * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
0006  */
0007 
0008 #include <linux/module.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/of.h>
0011 #include <linux/of_device.h>
0012 #include <linux/pinctrl/pinctrl.h>
0013 
0014 #include "pinctrl-sunxi.h"
0015 
0016 static const struct sunxi_desc_pin h6_pins[] = {
0017     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
0018           SUNXI_FUNCTION(0x2, "emac")),     /* ERXD1 */
0019     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
0020           SUNXI_FUNCTION(0x2, "emac")),     /* ERXD0 */
0021     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
0022           SUNXI_FUNCTION(0x2, "emac")),     /* ECRS_DV */
0023     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
0024           SUNXI_FUNCTION(0x2, "emac")),     /* ERXERR */
0025     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
0026           SUNXI_FUNCTION(0x2, "emac")),     /* ETXD1 */
0027     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
0028           SUNXI_FUNCTION(0x2, "emac")),     /* ETXD0 */
0029     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
0030           SUNXI_FUNCTION(0x2, "emac")),     /* ETXCK */
0031     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
0032           SUNXI_FUNCTION(0x2, "emac")),     /* ETXEN */
0033     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
0034           SUNXI_FUNCTION(0x2, "emac")),     /* EMDC */
0035     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
0036           SUNXI_FUNCTION(0x2, "emac")),     /* EMDIO */
0037     /* Hole */
0038     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
0039           SUNXI_FUNCTION(0x2, "ccir"),      /* CLK */
0040           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
0041     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
0042           SUNXI_FUNCTION(0x2, "ccir"),      /* DE */
0043           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
0044     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
0045           SUNXI_FUNCTION(0x2, "ccir"),      /* HSYNC */
0046           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
0047     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
0048           SUNXI_FUNCTION(0x2, "ccir"),      /* VSYNC */
0049           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
0050     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
0051           SUNXI_FUNCTION(0x2, "ccir"),      /* DO0 */
0052           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
0053     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
0054           SUNXI_FUNCTION(0x2, "ccir"),      /* DO1 */
0055           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
0056     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
0057           SUNXI_FUNCTION(0x2, "ccir"),      /* DO2 */
0058           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
0059     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
0060           SUNXI_FUNCTION(0x2, "ccir"),      /* DO3 */
0061           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
0062     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
0063           SUNXI_FUNCTION(0x2, "ccir"),      /* DO4 */
0064           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
0065     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
0066           SUNXI_FUNCTION(0x2, "ccir"),      /* DO5 */
0067           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
0068     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
0069           SUNXI_FUNCTION(0x2, "ccir"),      /* DO6 */
0070           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
0071     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 11),
0072           SUNXI_FUNCTION(0x2, "ccir"),      /* DO7 */
0073           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)),
0074     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 12),
0075           SUNXI_FUNCTION(0x2, "i2s3"),      /* SYNC */
0076           SUNXI_FUNCTION(0x4, "h_i2s3"),    /* SYNC */
0077           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)),
0078     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 13),
0079           SUNXI_FUNCTION(0x2, "i2s3"),      /* CLK */
0080           SUNXI_FUNCTION(0x4, "h_i2s3"),    /* CLK */
0081           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)),
0082     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 14),
0083           SUNXI_FUNCTION(0x2, "i2s3"),      /* DOUT */
0084           SUNXI_FUNCTION(0x4, "h_i2s3"),    /* DOUT */
0085           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)),
0086     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 15),
0087           SUNXI_FUNCTION(0x2, "i2s3"),      /* DIN */
0088           SUNXI_FUNCTION(0x4, "h_i2s3"),    /* DIN */
0089           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)),
0090     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 16),
0091           SUNXI_FUNCTION(0x2, "i2s3"),      /* MCLK */
0092           SUNXI_FUNCTION(0x4, "h_i2s3"),    /* MCLK */
0093           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)),
0094     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 17),
0095           SUNXI_FUNCTION(0x2, "i2c3"),      /* SCK */
0096           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)),
0097     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 18),
0098           SUNXI_FUNCTION(0x2, "i2c3"),      /* SDA */
0099           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)),
0100     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 19),
0101           SUNXI_FUNCTION(0x2, "pwm1"),
0102           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)),
0103     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 20),
0104           SUNXI_FUNCTION(0x0, "gpio_in"),
0105           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)),
0106     /* Hole */
0107     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
0108           SUNXI_FUNCTION(0x0, "gpio_in"),
0109           SUNXI_FUNCTION(0x1, "gpio_out"),
0110           SUNXI_FUNCTION(0x2, "nand0"),     /* WE */
0111           SUNXI_FUNCTION(0x4, "spi0")),     /* CLK */
0112     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
0113           SUNXI_FUNCTION(0x0, "gpio_in"),
0114           SUNXI_FUNCTION(0x1, "gpio_out"),
0115           SUNXI_FUNCTION(0x2, "nand0"),     /* ALE */
0116           SUNXI_FUNCTION(0x3, "mmc2")),     /* DS */
0117     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
0118           SUNXI_FUNCTION(0x0, "gpio_in"),
0119           SUNXI_FUNCTION(0x1, "gpio_out"),
0120           SUNXI_FUNCTION(0x2, "nand0"),     /* CLE */
0121           SUNXI_FUNCTION(0x4, "spi0")),     /* MOSI */
0122     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
0123           SUNXI_FUNCTION(0x0, "gpio_in"),
0124           SUNXI_FUNCTION(0x1, "gpio_out"),
0125           SUNXI_FUNCTION(0x2, "nand0"),     /* CE0 */
0126           SUNXI_FUNCTION(0x4, "spi0")),     /* MISO */
0127     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
0128           SUNXI_FUNCTION(0x0, "gpio_in"),
0129           SUNXI_FUNCTION(0x1, "gpio_out"),
0130           SUNXI_FUNCTION(0x2, "nand0"),     /* RE */
0131           SUNXI_FUNCTION(0x3, "mmc2")),     /* CLK */
0132     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
0133           SUNXI_FUNCTION(0x0, "gpio_in"),
0134           SUNXI_FUNCTION(0x1, "gpio_out"),
0135           SUNXI_FUNCTION(0x2, "nand0"),     /* RB0 */
0136           SUNXI_FUNCTION(0x3, "mmc2"),      /* CMD */
0137           SUNXI_FUNCTION(0x4, "spi0")),     /* CS */
0138     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
0139           SUNXI_FUNCTION(0x0, "gpio_in"),
0140           SUNXI_FUNCTION(0x1, "gpio_out"),
0141           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ0 */
0142           SUNXI_FUNCTION(0x3, "mmc2"),      /* D0 */
0143           SUNXI_FUNCTION(0x4, "spi0")),     /* HOLD */
0144     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
0145           SUNXI_FUNCTION(0x0, "gpio_in"),
0146           SUNXI_FUNCTION(0x1, "gpio_out"),
0147           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ1 */
0148           SUNXI_FUNCTION(0x3, "mmc2"),      /* D1 */
0149           SUNXI_FUNCTION(0x4, "spi0")),     /* WP */
0150     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
0151           SUNXI_FUNCTION(0x0, "gpio_in"),
0152           SUNXI_FUNCTION(0x1, "gpio_out"),
0153           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ2 */
0154           SUNXI_FUNCTION(0x3, "mmc2")),     /* D2 */
0155     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
0156           SUNXI_FUNCTION(0x0, "gpio_in"),
0157           SUNXI_FUNCTION(0x1, "gpio_out"),
0158           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ3 */
0159           SUNXI_FUNCTION(0x3, "mmc2")),     /* D3 */
0160     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
0161           SUNXI_FUNCTION(0x0, "gpio_in"),
0162           SUNXI_FUNCTION(0x1, "gpio_out"),
0163           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ4 */
0164           SUNXI_FUNCTION(0x3, "mmc2")),     /* D4 */
0165     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
0166           SUNXI_FUNCTION(0x0, "gpio_in"),
0167           SUNXI_FUNCTION(0x1, "gpio_out"),
0168           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ5 */
0169           SUNXI_FUNCTION(0x3, "mmc2")),     /* D5 */
0170     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
0171           SUNXI_FUNCTION(0x0, "gpio_in"),
0172           SUNXI_FUNCTION(0x1, "gpio_out"),
0173           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ6 */
0174           SUNXI_FUNCTION(0x3, "mmc2")),     /* D6 */
0175     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
0176           SUNXI_FUNCTION(0x0, "gpio_in"),
0177           SUNXI_FUNCTION(0x1, "gpio_out"),
0178           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ7 */
0179           SUNXI_FUNCTION(0x3, "mmc2")),     /* D7 */
0180     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
0181           SUNXI_FUNCTION(0x0, "gpio_in"),
0182           SUNXI_FUNCTION(0x1, "gpio_out"),
0183           SUNXI_FUNCTION(0x2, "nand0"),     /* DQS */
0184           SUNXI_FUNCTION(0x3, "mmc2")),     /* RST */
0185     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
0186           SUNXI_FUNCTION(0x0, "gpio_in"),
0187           SUNXI_FUNCTION(0x1, "gpio_out"),
0188           SUNXI_FUNCTION(0x2, "nand0")),    /* CE1 */
0189     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
0190           SUNXI_FUNCTION(0x0, "gpio_in"),
0191           SUNXI_FUNCTION(0x1, "gpio_out"),
0192           SUNXI_FUNCTION(0x2, "nand0")),    /* RB1 */
0193     /* Hole */
0194     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
0195           SUNXI_FUNCTION(0x0, "gpio_in"),
0196           SUNXI_FUNCTION(0x1, "gpio_out"),
0197           SUNXI_FUNCTION(0x2, "lcd0"),      /* D2 */
0198           SUNXI_FUNCTION(0x3, "ts0"),       /* CLK */
0199           SUNXI_FUNCTION(0x4, "csi"),       /* PCLK */
0200           SUNXI_FUNCTION(0x5, "emac")),     /* ERXD3 */
0201     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
0202           SUNXI_FUNCTION(0x0, "gpio_in"),
0203           SUNXI_FUNCTION(0x1, "gpio_out"),
0204           SUNXI_FUNCTION(0x2, "lcd0"),      /* D3 */
0205           SUNXI_FUNCTION(0x3, "ts0"),       /* ERR */
0206           SUNXI_FUNCTION(0x4, "csi"),       /* MCLK */
0207           SUNXI_FUNCTION(0x5, "emac")),     /* ERXD2 */
0208     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
0209           SUNXI_FUNCTION(0x0, "gpio_in"),
0210           SUNXI_FUNCTION(0x1, "gpio_out"),
0211           SUNXI_FUNCTION(0x2, "lcd0"),      /* D4 */
0212           SUNXI_FUNCTION(0x3, "ts0"),       /* SYNC */
0213           SUNXI_FUNCTION(0x4, "csi"),       /* HSYNC */
0214           SUNXI_FUNCTION(0x5, "emac")),     /* ERXD1 */
0215     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
0216           SUNXI_FUNCTION(0x0, "gpio_in"),
0217           SUNXI_FUNCTION(0x1, "gpio_out"),
0218           SUNXI_FUNCTION(0x2, "lcd0"),      /* D5 */
0219           SUNXI_FUNCTION(0x3, "ts0"),       /* DVLD */
0220           SUNXI_FUNCTION(0x4, "csi"),       /* VSYNC */
0221           SUNXI_FUNCTION(0x5, "emac")),     /* ERXD0 */
0222     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
0223           SUNXI_FUNCTION(0x0, "gpio_in"),
0224           SUNXI_FUNCTION(0x1, "gpio_out"),
0225           SUNXI_FUNCTION(0x2, "lcd0"),      /* D6 */
0226           SUNXI_FUNCTION(0x3, "ts0"),       /* D0 */
0227           SUNXI_FUNCTION(0x4, "csi"),       /* D0 */
0228           SUNXI_FUNCTION(0x5, "emac")),     /* ERXCK */
0229     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
0230           SUNXI_FUNCTION(0x0, "gpio_in"),
0231           SUNXI_FUNCTION(0x1, "gpio_out"),
0232           SUNXI_FUNCTION(0x2, "lcd0"),      /* D7 */
0233           SUNXI_FUNCTION(0x3, "ts0"),       /* D1 */
0234           SUNXI_FUNCTION(0x4, "csi"),       /* D1 */
0235           SUNXI_FUNCTION(0x5, "emac")),     /* ERXCTL */
0236     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
0237           SUNXI_FUNCTION(0x0, "gpio_in"),
0238           SUNXI_FUNCTION(0x1, "gpio_out"),
0239           SUNXI_FUNCTION(0x2, "lcd0"),      /* D10 */
0240           SUNXI_FUNCTION(0x3, "ts0"),       /* D2 */
0241           SUNXI_FUNCTION(0x4, "csi"),       /* D2 */
0242           SUNXI_FUNCTION(0x5, "emac")),     /* ENULL */
0243     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
0244           SUNXI_FUNCTION(0x0, "gpio_in"),
0245           SUNXI_FUNCTION(0x1, "gpio_out"),
0246           SUNXI_FUNCTION(0x2, "lcd0"),      /* D11 */
0247           SUNXI_FUNCTION(0x3, "ts0"),       /* D3 */
0248           SUNXI_FUNCTION(0x4, "csi"),       /* D3 */
0249           SUNXI_FUNCTION(0x5, "emac")),     /* ETXD3 */
0250     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
0251           SUNXI_FUNCTION(0x0, "gpio_in"),
0252           SUNXI_FUNCTION(0x1, "gpio_out"),
0253           SUNXI_FUNCTION(0x2, "lcd0"),      /* D12 */
0254           SUNXI_FUNCTION(0x3, "ts0"),       /* D4 */
0255           SUNXI_FUNCTION(0x4, "csi"),       /* D4 */
0256           SUNXI_FUNCTION(0x5, "emac")),     /* ETXD2 */
0257     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
0258           SUNXI_FUNCTION(0x0, "gpio_in"),
0259           SUNXI_FUNCTION(0x1, "gpio_out"),
0260           SUNXI_FUNCTION(0x2, "lcd0"),      /* D13 */
0261           SUNXI_FUNCTION(0x3, "ts0"),       /* D5 */
0262           SUNXI_FUNCTION(0x4, "csi"),       /* D5 */
0263           SUNXI_FUNCTION(0x5, "emac")),     /* ETXD1 */
0264     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
0265           SUNXI_FUNCTION(0x0, "gpio_in"),
0266           SUNXI_FUNCTION(0x1, "gpio_out"),
0267           SUNXI_FUNCTION(0x2, "lcd0"),      /* D14 */
0268           SUNXI_FUNCTION(0x3, "ts0"),       /* D6 */
0269           SUNXI_FUNCTION(0x4, "csi"),       /* D6 */
0270           SUNXI_FUNCTION(0x5, "emac")),     /* ETXD0 */
0271     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
0272           SUNXI_FUNCTION(0x0, "gpio_in"),
0273           SUNXI_FUNCTION(0x1, "gpio_out"),
0274           SUNXI_FUNCTION(0x2, "lcd0"),      /* D15 */
0275           SUNXI_FUNCTION(0x3, "ts0"),       /* D7 */
0276           SUNXI_FUNCTION(0x4, "csi"),       /* D7 */
0277           SUNXI_FUNCTION(0x5, "emac")),     /* ETXCK */
0278     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
0279           SUNXI_FUNCTION(0x0, "gpio_in"),
0280           SUNXI_FUNCTION(0x1, "gpio_out"),
0281           SUNXI_FUNCTION(0x2, "lcd0"),      /* D18 */
0282           SUNXI_FUNCTION(0x3, "ts1"),       /* CLK */
0283           SUNXI_FUNCTION(0x4, "csi"),       /* SCK */
0284           SUNXI_FUNCTION(0x5, "emac")),     /* ETXCTL */
0285     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
0286           SUNXI_FUNCTION(0x0, "gpio_in"),
0287           SUNXI_FUNCTION(0x1, "gpio_out"),
0288           SUNXI_FUNCTION(0x2, "lcd0"),      /* D19 */
0289           SUNXI_FUNCTION(0x3, "ts1"),       /* ERR */
0290           SUNXI_FUNCTION(0x4, "csi"),       /* SDA */
0291           SUNXI_FUNCTION(0x5, "emac")),     /* ECLKIN */
0292     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
0293           SUNXI_FUNCTION(0x0, "gpio_in"),
0294           SUNXI_FUNCTION(0x1, "gpio_out"),
0295           SUNXI_FUNCTION(0x2, "lcd0"),      /* D20 */
0296           SUNXI_FUNCTION(0x3, "ts1"),       /* SYNC */
0297           SUNXI_FUNCTION(0x4, "dmic"),      /* CLK */
0298           SUNXI_FUNCTION(0x5, "csi")),      /* D8 */
0299     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
0300           SUNXI_FUNCTION(0x0, "gpio_in"),
0301           SUNXI_FUNCTION(0x1, "gpio_out"),
0302           SUNXI_FUNCTION(0x2, "lcd0"),      /* D21 */
0303           SUNXI_FUNCTION(0x3, "ts1"),       /* DVLD */
0304           SUNXI_FUNCTION(0x4, "dmic"),      /* DATA0 */
0305           SUNXI_FUNCTION(0x5, "csi")),      /* D9 */
0306     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
0307           SUNXI_FUNCTION(0x0, "gpio_in"),
0308           SUNXI_FUNCTION(0x1, "gpio_out"),
0309           SUNXI_FUNCTION(0x2, "lcd0"),      /* D22 */
0310           SUNXI_FUNCTION(0x3, "ts1"),       /* D0 */
0311           SUNXI_FUNCTION(0x4, "dmic")),     /* DATA1 */
0312     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
0313           SUNXI_FUNCTION(0x0, "gpio_in"),
0314           SUNXI_FUNCTION(0x1, "gpio_out"),
0315           SUNXI_FUNCTION(0x2, "lcd0"),      /* D23 */
0316           SUNXI_FUNCTION(0x3, "ts2"),       /* CLK */
0317           SUNXI_FUNCTION(0x4, "dmic")),     /* DATA2 */
0318     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
0319           SUNXI_FUNCTION(0x0, "gpio_in"),
0320           SUNXI_FUNCTION(0x1, "gpio_out"),
0321           SUNXI_FUNCTION(0x2, "lcd0"),      /* CLK */
0322           SUNXI_FUNCTION(0x3, "ts2"),       /* ERR */
0323           SUNXI_FUNCTION(0x4, "dmic")),     /* DATA3 */
0324     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
0325           SUNXI_FUNCTION(0x0, "gpio_in"),
0326           SUNXI_FUNCTION(0x1, "gpio_out"),
0327           SUNXI_FUNCTION(0x2, "lcd0"),      /* DE */
0328           SUNXI_FUNCTION(0x3, "ts2"),       /* SYNC */
0329           SUNXI_FUNCTION(0x4, "uart2"),     /* TX */
0330           SUNXI_FUNCTION(0x5, "emac")),     /* EMDC */
0331     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
0332           SUNXI_FUNCTION(0x0, "gpio_in"),
0333           SUNXI_FUNCTION(0x1, "gpio_out"),
0334           SUNXI_FUNCTION(0x2, "lcd0"),      /* HSYNC */
0335           SUNXI_FUNCTION(0x3, "ts2"),       /* DVLD */
0336           SUNXI_FUNCTION(0x4, "uart2"),     /* RX */
0337           SUNXI_FUNCTION(0x5, "emac")),     /* EMDIO */
0338     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
0339           SUNXI_FUNCTION(0x0, "gpio_in"),
0340           SUNXI_FUNCTION(0x1, "gpio_out"),
0341           SUNXI_FUNCTION(0x2, "lcd0"),      /* VSYNC */
0342           SUNXI_FUNCTION(0x3, "ts2"),       /* D0 */
0343           SUNXI_FUNCTION(0x4, "uart2")),    /* RTS */
0344     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
0345           SUNXI_FUNCTION(0x0, "gpio_in"),
0346           SUNXI_FUNCTION(0x1, "gpio_out"),
0347           SUNXI_FUNCTION(0x2, "pwm"),       /* PWM0 */
0348           SUNXI_FUNCTION(0x3, "ts3"),       /* CLK */
0349           SUNXI_FUNCTION(0x4, "uart2")),    /* CTS */
0350     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
0351           SUNXI_FUNCTION(0x0, "gpio_in"),
0352           SUNXI_FUNCTION(0x1, "gpio_out"),
0353           SUNXI_FUNCTION(0x2, "i2c2"),      /* SCK */
0354           SUNXI_FUNCTION(0x3, "ts3"),       /* ERR */
0355           SUNXI_FUNCTION(0x4, "uart3"),     /* TX */
0356           SUNXI_FUNCTION(0x5, "jtag")),     /* MS */
0357     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
0358           SUNXI_FUNCTION(0x0, "gpio_in"),
0359           SUNXI_FUNCTION(0x1, "gpio_out"),
0360           SUNXI_FUNCTION(0x2, "i2c2"),      /* SDA */
0361           SUNXI_FUNCTION(0x3, "ts3"),       /* SYNC */
0362           SUNXI_FUNCTION(0x4, "uart3"),     /* RX */
0363           SUNXI_FUNCTION(0x5, "jtag")),     /* CK */
0364     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 25),
0365           SUNXI_FUNCTION(0x0, "gpio_in"),
0366           SUNXI_FUNCTION(0x1, "gpio_out"),
0367           SUNXI_FUNCTION(0x2, "i2c0"),      /* SCK */
0368           SUNXI_FUNCTION(0x3, "ts3"),       /* DVLD */
0369           SUNXI_FUNCTION(0x4, "uart3"),     /* RTS */
0370           SUNXI_FUNCTION(0x5, "jtag")),     /* DO */
0371     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 26),
0372           SUNXI_FUNCTION(0x0, "gpio_in"),
0373           SUNXI_FUNCTION(0x1, "gpio_out"),
0374           SUNXI_FUNCTION(0x2, "i2c0"),      /* SDA */
0375           SUNXI_FUNCTION(0x3, "ts3"),       /* D0 */
0376           SUNXI_FUNCTION(0x4, "uart3"),     /* CTS */
0377           SUNXI_FUNCTION(0x5, "jtag")),     /* DI */
0378     /* Hole */
0379     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
0380           SUNXI_FUNCTION(0x0, "gpio_in"),
0381           SUNXI_FUNCTION(0x1, "gpio_out"),
0382           SUNXI_FUNCTION(0x2, "mmc0"),      /* D1 */
0383           SUNXI_FUNCTION(0x3, "jtag"),      /* MS */
0384           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),  /* PF_EINT0 */
0385     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
0386           SUNXI_FUNCTION(0x0, "gpio_in"),
0387           SUNXI_FUNCTION(0x1, "gpio_out"),
0388           SUNXI_FUNCTION(0x2, "mmc0"),      /* D0 */
0389           SUNXI_FUNCTION(0x3, "jtag"),      /* DI */
0390           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),  /* PF_EINT1 */
0391     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
0392           SUNXI_FUNCTION(0x0, "gpio_in"),
0393           SUNXI_FUNCTION(0x1, "gpio_out"),
0394           SUNXI_FUNCTION(0x2, "mmc0"),      /* CLK */
0395           SUNXI_FUNCTION(0x3, "uart0"),     /* TX */
0396           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),  /* PF_EINT2 */
0397     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
0398           SUNXI_FUNCTION(0x0, "gpio_in"),
0399           SUNXI_FUNCTION(0x1, "gpio_out"),
0400           SUNXI_FUNCTION(0x2, "mmc0"),      /* CMD */
0401           SUNXI_FUNCTION(0x3, "jtag"),      /* DO */
0402           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),  /* PF_EINT3 */
0403     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
0404           SUNXI_FUNCTION(0x0, "gpio_in"),
0405           SUNXI_FUNCTION(0x1, "gpio_out"),
0406           SUNXI_FUNCTION(0x2, "mmc0"),      /* D3 */
0407           SUNXI_FUNCTION(0x3, "uart0"),     /* RX */
0408           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),  /* PF_EINT4 */
0409     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
0410           SUNXI_FUNCTION(0x0, "gpio_in"),
0411           SUNXI_FUNCTION(0x1, "gpio_out"),
0412           SUNXI_FUNCTION(0x2, "mmc0"),      /* D2 */
0413           SUNXI_FUNCTION(0x3, "jtag"),      /* CK */
0414           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),  /* PF_EINT5 */
0415     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
0416           SUNXI_FUNCTION(0x0, "gpio_in"),
0417           SUNXI_FUNCTION(0x1, "gpio_out"),
0418           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),  /* PF_EINT6 */
0419     /* Hole */
0420     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
0421           SUNXI_FUNCTION(0x0, "gpio_in"),
0422           SUNXI_FUNCTION(0x1, "gpio_out"),
0423           SUNXI_FUNCTION(0x2, "mmc1"),      /* CLK */
0424           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),  /* PG_EINT0 */
0425     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
0426           SUNXI_FUNCTION(0x0, "gpio_in"),
0427           SUNXI_FUNCTION(0x1, "gpio_out"),
0428           SUNXI_FUNCTION(0x2, "mmc1"),      /* CMD */
0429           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),  /* PG_EINT1 */
0430     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
0431           SUNXI_FUNCTION(0x0, "gpio_in"),
0432           SUNXI_FUNCTION(0x1, "gpio_out"),
0433           SUNXI_FUNCTION(0x2, "mmc1"),      /* D0 */
0434           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),  /* PG_EINT2 */
0435     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
0436           SUNXI_FUNCTION(0x0, "gpio_in"),
0437           SUNXI_FUNCTION(0x1, "gpio_out"),
0438           SUNXI_FUNCTION(0x2, "mmc1"),      /* D1 */
0439           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),  /* PG_EINT3 */
0440     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
0441           SUNXI_FUNCTION(0x0, "gpio_in"),
0442           SUNXI_FUNCTION(0x1, "gpio_out"),
0443           SUNXI_FUNCTION(0x2, "mmc1"),      /* D2 */
0444           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),  /* PG_EINT4 */
0445     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
0446           SUNXI_FUNCTION(0x0, "gpio_in"),
0447           SUNXI_FUNCTION(0x1, "gpio_out"),
0448           SUNXI_FUNCTION(0x2, "mmc1"),      /* D3 */
0449           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),  /* PG_EINT5 */
0450     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
0451           SUNXI_FUNCTION(0x0, "gpio_in"),
0452           SUNXI_FUNCTION(0x1, "gpio_out"),
0453           SUNXI_FUNCTION(0x2, "uart1"),     /* TX */
0454           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),  /* PG_EINT6 */
0455     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
0456           SUNXI_FUNCTION(0x0, "gpio_in"),
0457           SUNXI_FUNCTION(0x1, "gpio_out"),
0458           SUNXI_FUNCTION(0x2, "uart1"),     /* RX */
0459           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),  /* PG_EINT7 */
0460     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
0461           SUNXI_FUNCTION(0x0, "gpio_in"),
0462           SUNXI_FUNCTION(0x1, "gpio_out"),
0463           SUNXI_FUNCTION(0x2, "uart1"),     /* RTS */
0464           SUNXI_FUNCTION(0x4, "sim0"),      /* VPPEN */
0465           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),  /* PG_EINT8 */
0466     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
0467           SUNXI_FUNCTION(0x0, "gpio_in"),
0468           SUNXI_FUNCTION(0x1, "gpio_out"),
0469           SUNXI_FUNCTION(0x2, "uart1"),     /* CTS */
0470           SUNXI_FUNCTION(0x4, "sim0"),      /* VPPPP */
0471           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),  /* PG_EINT9 */
0472     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
0473           SUNXI_FUNCTION(0x0, "gpio_in"),
0474           SUNXI_FUNCTION(0x1, "gpio_out"),
0475           SUNXI_FUNCTION(0x2, "i2s2"),      /* SYNC */
0476           SUNXI_FUNCTION(0x3, "h_i2s2"),    /* SYNC */
0477           SUNXI_FUNCTION(0x4, "sim0"),      /* PWREN */
0478           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */
0479     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
0480           SUNXI_FUNCTION(0x0, "gpio_in"),
0481           SUNXI_FUNCTION(0x1, "gpio_out"),
0482           SUNXI_FUNCTION(0x2, "i2s2"),      /* CLK */
0483           SUNXI_FUNCTION(0x3, "h_i2s2"),    /* CLK */
0484           SUNXI_FUNCTION(0x4, "sim0"),      /* CLK */
0485           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */
0486     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
0487           SUNXI_FUNCTION(0x0, "gpio_in"),
0488           SUNXI_FUNCTION(0x1, "gpio_out"),
0489           SUNXI_FUNCTION(0x2, "i2s2"),      /* DOUT */
0490           SUNXI_FUNCTION(0x3, "h_i2s2"),    /* DOUT */
0491           SUNXI_FUNCTION(0x4, "sim0"),      /* DATA */
0492           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */
0493     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
0494           SUNXI_FUNCTION(0x0, "gpio_in"),
0495           SUNXI_FUNCTION(0x1, "gpio_out"),
0496           SUNXI_FUNCTION(0x2, "i2s2"),      /* DIN */
0497           SUNXI_FUNCTION(0x3, "h_i2s2"),    /* DIN */
0498           SUNXI_FUNCTION(0x4, "sim0"),      /* RST */
0499           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */
0500     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14),
0501           SUNXI_FUNCTION(0x0, "gpio_in"),
0502           SUNXI_FUNCTION(0x1, "gpio_out"),
0503           SUNXI_FUNCTION(0x2, "i2s2"),      /* MCLK */
0504           SUNXI_FUNCTION(0x3, "h_i2s2"),    /* MCLK */
0505           SUNXI_FUNCTION(0x4, "sim0"),      /* DET */
0506           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PG_EINT14 */
0507     /* Hole */
0508     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
0509           SUNXI_FUNCTION(0x0, "gpio_in"),
0510           SUNXI_FUNCTION(0x1, "gpio_out"),
0511           SUNXI_FUNCTION(0x2, "uart0"),     /* TX */
0512           SUNXI_FUNCTION(0x3, "i2s0"),      /* SYNC */
0513           SUNXI_FUNCTION(0x4, "h_i2s0"),    /* SYNC */
0514           SUNXI_FUNCTION(0x5, "sim1"),      /* VPPEN */
0515           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)),  /* PH_EINT0 */
0516     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
0517           SUNXI_FUNCTION(0x0, "gpio_in"),
0518           SUNXI_FUNCTION(0x1, "gpio_out"),
0519           SUNXI_FUNCTION(0x2, "uart0"),     /* RX */
0520           SUNXI_FUNCTION(0x3, "i2s0"),      /* CLK */
0521           SUNXI_FUNCTION(0x4, "h_i2s0"),    /* CLK */
0522           SUNXI_FUNCTION(0x5, "sim1"),      /* VPPPP */
0523           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)),  /* PH_EINT1 */
0524     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
0525           SUNXI_FUNCTION(0x0, "gpio_in"),
0526           SUNXI_FUNCTION(0x1, "gpio_out"),
0527           SUNXI_FUNCTION(0x2, "ir_tx"),
0528           SUNXI_FUNCTION(0x3, "i2s0"),      /* DOUT */
0529           SUNXI_FUNCTION(0x4, "h_i2s0"),    /* DOUT */
0530           SUNXI_FUNCTION(0x5, "sim1"),      /* PWREN */
0531           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)),  /* PH_EINT2 */
0532     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
0533           SUNXI_FUNCTION(0x0, "gpio_in"),
0534           SUNXI_FUNCTION(0x1, "gpio_out"),
0535           SUNXI_FUNCTION(0x2, "spi1"),      /* CS */
0536           SUNXI_FUNCTION(0x3, "i2s0"),      /* DIN */
0537           SUNXI_FUNCTION(0x4, "h_i2s0"),    /* DIN */
0538           SUNXI_FUNCTION(0x5, "sim1"),      /* CLK */
0539           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)),  /* PH_EINT3 */
0540     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
0541           SUNXI_FUNCTION(0x0, "gpio_in"),
0542           SUNXI_FUNCTION(0x1, "gpio_out"),
0543           SUNXI_FUNCTION(0x2, "spi1"),      /* CLK */
0544           SUNXI_FUNCTION(0x3, "i2s0"),      /* MCLK */
0545           SUNXI_FUNCTION(0x4, "h_i2s0"),    /* MCLK */
0546           SUNXI_FUNCTION(0x5, "sim1"),      /* DATA */
0547           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)),  /* PH_EINT4 */
0548     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
0549           SUNXI_FUNCTION(0x0, "gpio_in"),
0550           SUNXI_FUNCTION(0x1, "gpio_out"),
0551           SUNXI_FUNCTION(0x2, "spi1"),      /* MOSI */
0552           SUNXI_FUNCTION(0x3, "spdif"),     /* MCLK */
0553           SUNXI_FUNCTION(0x4, "i2c1"),      /* SCK */
0554           SUNXI_FUNCTION(0x5, "sim1"),      /* RST */
0555           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)),  /* PH_EINT5 */
0556     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
0557           SUNXI_FUNCTION(0x0, "gpio_in"),
0558           SUNXI_FUNCTION(0x1, "gpio_out"),
0559           SUNXI_FUNCTION(0x2, "spi1"),      /* MISO */
0560           SUNXI_FUNCTION(0x3, "spdif"),     /* IN */
0561           SUNXI_FUNCTION(0x4, "i2c1"),      /* SDA */
0562           SUNXI_FUNCTION(0x5, "sim1"),      /* DET */
0563           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)),  /* PH_EINT6 */
0564     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
0565           SUNXI_FUNCTION(0x0, "gpio_in"),
0566           SUNXI_FUNCTION(0x1, "gpio_out"),
0567           SUNXI_FUNCTION(0x3, "spdif"),     /* OUT */
0568           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)),  /* PH_EINT7 */
0569     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
0570           SUNXI_FUNCTION(0x0, "gpio_in"),
0571           SUNXI_FUNCTION(0x1, "gpio_out"),
0572           SUNXI_FUNCTION(0x2, "hdmi"),      /* HSCL */
0573           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)),  /* PH_EINT8 */
0574     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
0575           SUNXI_FUNCTION(0x0, "gpio_in"),
0576           SUNXI_FUNCTION(0x1, "gpio_out"),
0577           SUNXI_FUNCTION(0x2, "hdmi"),      /* HSDA */
0578           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)),  /* PH_EINT9 */
0579     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
0580           SUNXI_FUNCTION(0x0, "gpio_in"),
0581           SUNXI_FUNCTION(0x1, "gpio_out"),
0582           SUNXI_FUNCTION(0x2, "hdmi"),      /* HCEC */
0583           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 10)), /* PH_EINT10 */
0584 };
0585 
0586 static const unsigned int h6_irq_bank_map[] = { 1, 5, 6, 7 };
0587 
0588 static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
0589     .pins = h6_pins,
0590     .npins = ARRAY_SIZE(h6_pins),
0591     .irq_banks = 4,
0592     .irq_bank_map = h6_irq_bank_map,
0593     .irq_read_needs_mux = true,
0594     .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
0595 };
0596 
0597 static int h6_pinctrl_probe(struct platform_device *pdev)
0598 {
0599     return sunxi_pinctrl_init(pdev,
0600                   &h6_pinctrl_data);
0601 }
0602 
0603 static const struct of_device_id h6_pinctrl_match[] = {
0604     { .compatible = "allwinner,sun50i-h6-pinctrl", },
0605     {}
0606 };
0607 
0608 static struct platform_driver h6_pinctrl_driver = {
0609     .probe  = h6_pinctrl_probe,
0610     .driver = {
0611         .name       = "sun50i-h6-pinctrl",
0612         .of_match_table = h6_pinctrl_match,
0613     },
0614 };
0615 builtin_platform_driver(h6_pinctrl_driver);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!