pinctrl/sunxi/pinctrl-sun50i-h6-r.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Allwinner H6 R_PIO pin controller driver
0004  *
0005  * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
0006  *
0007  * Based on pinctrl-sun6i-a31-r.c, which is:
0008  *   Copyright (C) 2014 Boris Brezillon
0009  *   Boris Brezillon <boris.brezillon@free-electrons.com>
0010  *   Copyright (C) 2014 Maxime Ripard
0011  *   Maxime Ripard <maxime.ripard@free-electrons.com>
0012  */
0013
0014 #include <linux/init.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/of.h>
0017 #include <linux/of_device.h>
0018 #include <linux/pinctrl/pinctrl.h>
0019
0020 #include "pinctrl-sunxi.h"
0021
0022 static const struct sunxi_desc_pin sun50i_h6_r_pins[] = {
0023     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0),
0024           SUNXI_FUNCTION(0x0, "gpio_in"),
0025           SUNXI_FUNCTION(0x1, "gpio_out"),
0026           SUNXI_FUNCTION(0x2, "s_rsb"),     /* SCK */
0027           SUNXI_FUNCTION(0x3, "s_i2c"),     /* SCK */
0028           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PL_EINT0 */
0029     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1),
0030           SUNXI_FUNCTION(0x0, "gpio_in"),
0031           SUNXI_FUNCTION(0x1, "gpio_out"),
0032           SUNXI_FUNCTION(0x2, "s_rsb"),     /* SDA */
0033           SUNXI_FUNCTION(0x3, "s_i2c"),     /* SDA */
0034           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PL_EINT1 */
0035     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2),
0036           SUNXI_FUNCTION(0x0, "gpio_in"),
0037           SUNXI_FUNCTION(0x1, "gpio_out"),
0038           SUNXI_FUNCTION(0x2, "s_uart"),    /* TX */
0039           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PL_EINT2 */
0040     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3),
0041           SUNXI_FUNCTION(0x0, "gpio_in"),
0042           SUNXI_FUNCTION(0x1, "gpio_out"),
0043           SUNXI_FUNCTION(0x2, "s_uart"),    /* RX */
0044           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PL_EINT3 */
0045     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4),
0046           SUNXI_FUNCTION(0x0, "gpio_in"),
0047           SUNXI_FUNCTION(0x1, "gpio_out"),
0048           SUNXI_FUNCTION(0x2, "s_jtag"),    /* MS */
0049           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PL_EINT4 */
0050     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5),
0051           SUNXI_FUNCTION(0x0, "gpio_in"),
0052           SUNXI_FUNCTION(0x1, "gpio_out"),
0053           SUNXI_FUNCTION(0x2, "s_jtag"),    /* CK */
0054           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),  /* PL_EINT5 */
0055     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6),
0056           SUNXI_FUNCTION(0x0, "gpio_in"),
0057           SUNXI_FUNCTION(0x1, "gpio_out"),
0058           SUNXI_FUNCTION(0x2, "s_jtag"),    /* DO */
0059           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),  /* PL_EINT6 */
0060     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7),
0061           SUNXI_FUNCTION(0x0, "gpio_in"),
0062           SUNXI_FUNCTION(0x1, "gpio_out"),
0063           SUNXI_FUNCTION(0x2, "s_jtag"),    /* DI */
0064           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),  /* PL_EINT7 */
0065     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8),
0066           SUNXI_FUNCTION(0x0, "gpio_in"),
0067           SUNXI_FUNCTION(0x1, "gpio_out"),
0068           SUNXI_FUNCTION(0x2, "s_pwm"),
0069           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),  /* PL_EINT8 */
0070     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9),
0071           SUNXI_FUNCTION(0x0, "gpio_in"),
0072           SUNXI_FUNCTION(0x1, "gpio_out"),
0073           SUNXI_FUNCTION(0x2, "s_cir_rx"),
0074           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),  /* PL_EINT9 */
0075     SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10),
0076           SUNXI_FUNCTION(0x0, "gpio_in"),
0077           SUNXI_FUNCTION(0x1, "gpio_out"),
0078           SUNXI_FUNCTION(0x2, "s_w1"),
0079           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PL_EINT10 */
0080     /* Hole */
0081     SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 0),
0082           SUNXI_FUNCTION(0x0, "gpio_in"),
0083           SUNXI_FUNCTION(0x1, "gpio_out"),
0084           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),  /* PM_EINT0 */
0085     SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 1),
0086           SUNXI_FUNCTION(0x0, "gpio_in"),
0087           SUNXI_FUNCTION(0x1, "gpio_out"),
0088           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),  /* PM_EINT1 */
0089     SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 2),
0090           SUNXI_FUNCTION(0x0, "gpio_in"),
0091           SUNXI_FUNCTION(0x1, "gpio_out"),
0092           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2),   /* PM_EINT2 */
0093           SUNXI_FUNCTION(0x3, "1wire")),
0094     SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 3),
0095           SUNXI_FUNCTION(0x0, "gpio_in"),
0096           SUNXI_FUNCTION(0x1, "gpio_out"),
0097           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),  /* PM_EINT3 */
0098     SUNXI_PIN(SUNXI_PINCTRL_PIN(M, 4),
0099           SUNXI_FUNCTION(0x0, "gpio_in"),
0100           SUNXI_FUNCTION(0x1, "gpio_out"),
0101           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),  /* PM_EINT4 */
0102 };
0103
0104 static const struct sunxi_pinctrl_desc sun50i_h6_r_pinctrl_data = {
0105     .pins = sun50i_h6_r_pins,
0106     .npins = ARRAY_SIZE(sun50i_h6_r_pins),
0107     .pin_base = PL_BASE,
0108     .irq_banks = 2,
0109     .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
0110 };
0111
0112 static int sun50i_h6_r_pinctrl_probe(struct platform_device *pdev)
0113 {
0114     return sunxi_pinctrl_init(pdev,
0115                   &sun50i_h6_r_pinctrl_data);
0116 }
0117
0118 static const struct of_device_id sun50i_h6_r_pinctrl_match[] = {
0119     { .compatible = "allwinner,sun50i-h6-r-pinctrl", },
0120     {}
0121 };
0122
0123 static struct platform_driver sun50i_h6_r_pinctrl_driver = {
0124     .probe  = sun50i_h6_r_pinctrl_probe,
0125     .driver = {
0126         .name       = "sun50i-h6-r-pinctrl",
0127         .of_match_table = sun50i_h6_r_pinctrl_match,
0128     },
0129 };
0130 builtin_platform_driver(sun50i_h6_r_pinctrl_driver);