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OSCL-LXR
 
 

     

0001 /*
0002  * Allwinner H5 SoC pinctrl driver.
0003  *
0004  * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
0005  *
0006  * Based on pinctrl-sun8i-h3.c, which is:
0007  * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
0008  *
0009  * Based on pinctrl-sun8i-a23.c, which is:
0010  * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
0011  * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
0012  *
0013  * This file is licensed under the terms of the GNU General Public
0014  * License version 2.  This program is licensed "as is" without any
0015  * warranty of any kind, whether express or implied.
0016  */
0017 
0018 #include <linux/module.h>
0019 #include <linux/platform_device.h>
0020 #include <linux/of.h>
0021 #include <linux/of_device.h>
0022 #include <linux/pinctrl/pinctrl.h>
0023 
0024 #include "pinctrl-sunxi.h"
0025 
0026 static const struct sunxi_desc_pin sun50i_h5_pins[] = {
0027     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
0028           SUNXI_FUNCTION(0x0, "gpio_in"),
0029           SUNXI_FUNCTION(0x1, "gpio_out"),
0030           SUNXI_FUNCTION(0x2, "uart2"),     /* TX */
0031           SUNXI_FUNCTION(0x3, "jtag"),      /* MS */
0032           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PA_EINT0 */
0033     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
0034           SUNXI_FUNCTION(0x0, "gpio_in"),
0035           SUNXI_FUNCTION(0x1, "gpio_out"),
0036           SUNXI_FUNCTION(0x2, "uart2"),     /* RX */
0037           SUNXI_FUNCTION(0x3, "jtag"),      /* CK */
0038           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PA_EINT1 */
0039     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
0040           SUNXI_FUNCTION(0x0, "gpio_in"),
0041           SUNXI_FUNCTION(0x1, "gpio_out"),
0042           SUNXI_FUNCTION(0x2, "uart2"),     /* RTS */
0043           SUNXI_FUNCTION(0x3, "jtag"),      /* DO */
0044           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PA_EINT2 */
0045     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
0046           SUNXI_FUNCTION(0x0, "gpio_in"),
0047           SUNXI_FUNCTION(0x1, "gpio_out"),
0048           SUNXI_FUNCTION(0x2, "uart2"),     /* CTS */
0049           SUNXI_FUNCTION(0x3, "jtag"),      /* DI */
0050           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PA_EINT3 */
0051     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
0052           SUNXI_FUNCTION(0x0, "gpio_in"),
0053           SUNXI_FUNCTION(0x1, "gpio_out"),
0054           SUNXI_FUNCTION(0x2, "uart0"),     /* TX */
0055           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PA_EINT4 */
0056     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
0057           SUNXI_FUNCTION(0x0, "gpio_in"),
0058           SUNXI_FUNCTION(0x1, "gpio_out"),
0059           SUNXI_FUNCTION(0x2, "uart0"),     /* RX */
0060           SUNXI_FUNCTION(0x3, "pwm0"),
0061           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),  /* PA_EINT5 */
0062     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
0063           SUNXI_FUNCTION(0x0, "gpio_in"),
0064           SUNXI_FUNCTION(0x1, "gpio_out"),
0065           SUNXI_FUNCTION(0x2, "sim"),       /* PWREN */
0066           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),  /* PA_EINT6 */
0067     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
0068           SUNXI_FUNCTION(0x0, "gpio_in"),
0069           SUNXI_FUNCTION(0x1, "gpio_out"),
0070           SUNXI_FUNCTION(0x2, "sim"),       /* CLK */
0071           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),  /* PA_EINT7 */
0072     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
0073           SUNXI_FUNCTION(0x0, "gpio_in"),
0074           SUNXI_FUNCTION(0x1, "gpio_out"),
0075           SUNXI_FUNCTION(0x2, "sim"),       /* DATA */
0076           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),  /* PA_EINT8 */
0077     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
0078           SUNXI_FUNCTION(0x0, "gpio_in"),
0079           SUNXI_FUNCTION(0x1, "gpio_out"),
0080           SUNXI_FUNCTION(0x2, "sim"),       /* RST */
0081           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),  /* PA_EINT9 */
0082     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
0083           SUNXI_FUNCTION(0x0, "gpio_in"),
0084           SUNXI_FUNCTION(0x1, "gpio_out"),
0085           SUNXI_FUNCTION(0x2, "sim"),       /* DET */
0086           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
0087     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
0088           SUNXI_FUNCTION(0x0, "gpio_in"),
0089           SUNXI_FUNCTION(0x1, "gpio_out"),
0090           SUNXI_FUNCTION(0x2, "i2c0"),      /* SCK */
0091           SUNXI_FUNCTION(0x3, "di"),        /* TX */
0092           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
0093     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
0094           SUNXI_FUNCTION(0x0, "gpio_in"),
0095           SUNXI_FUNCTION(0x1, "gpio_out"),
0096           SUNXI_FUNCTION(0x2, "i2c0"),      /* SDA */
0097           SUNXI_FUNCTION(0x3, "di"),        /* RX */
0098           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
0099     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
0100           SUNXI_FUNCTION(0x0, "gpio_in"),
0101           SUNXI_FUNCTION(0x1, "gpio_out"),
0102           SUNXI_FUNCTION(0x2, "spi1"),      /* CS */
0103           SUNXI_FUNCTION(0x3, "uart3"),     /* TX */
0104           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
0105     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
0106           SUNXI_FUNCTION(0x0, "gpio_in"),
0107           SUNXI_FUNCTION(0x1, "gpio_out"),
0108           SUNXI_FUNCTION(0x2, "spi1"),      /* CLK */
0109           SUNXI_FUNCTION(0x3, "uart3"),     /* RX */
0110           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
0111     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
0112           SUNXI_FUNCTION(0x0, "gpio_in"),
0113           SUNXI_FUNCTION(0x1, "gpio_out"),
0114           SUNXI_FUNCTION(0x2, "spi1"),      /* MOSI */
0115           SUNXI_FUNCTION(0x3, "uart3"),     /* RTS */
0116           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
0117     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
0118           SUNXI_FUNCTION(0x0, "gpio_in"),
0119           SUNXI_FUNCTION(0x1, "gpio_out"),
0120           SUNXI_FUNCTION(0x2, "spi1"),      /* MISO */
0121           SUNXI_FUNCTION(0x3, "uart3"),     /* CTS */
0122           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
0123     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
0124           SUNXI_FUNCTION(0x0, "gpio_in"),
0125           SUNXI_FUNCTION(0x1, "gpio_out"),
0126           SUNXI_FUNCTION(0x2, "spdif"),     /* OUT */
0127           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
0128     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
0129           SUNXI_FUNCTION(0x0, "gpio_in"),
0130           SUNXI_FUNCTION(0x1, "gpio_out"),
0131           SUNXI_FUNCTION(0x2, "i2s0"),      /* SYNC */
0132           SUNXI_FUNCTION(0x3, "i2c1"),      /* SCK */
0133           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
0134     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
0135           SUNXI_FUNCTION(0x0, "gpio_in"),
0136           SUNXI_FUNCTION(0x1, "gpio_out"),
0137           SUNXI_FUNCTION(0x2, "i2s0"),      /* CLK */
0138           SUNXI_FUNCTION(0x3, "i2c1"),      /* SDA */
0139           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
0140     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
0141           SUNXI_FUNCTION(0x0, "gpio_in"),
0142           SUNXI_FUNCTION(0x1, "gpio_out"),
0143           SUNXI_FUNCTION(0x2, "i2s0"),      /* DOUT */
0144           SUNXI_FUNCTION(0x3, "sim"),       /* VPPEN */
0145           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
0146     SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
0147           SUNXI_FUNCTION(0x0, "gpio_in"),
0148           SUNXI_FUNCTION(0x1, "gpio_out"),
0149           SUNXI_FUNCTION(0x2, "i2s0"),      /* DIN */
0150           SUNXI_FUNCTION(0x3, "sim"),       /* VPPPP */
0151           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
0152     /* Hole */
0153     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
0154           SUNXI_FUNCTION(0x0, "gpio_in"),
0155           SUNXI_FUNCTION(0x1, "gpio_out"),
0156           SUNXI_FUNCTION(0x2, "nand0"),     /* WE */
0157           SUNXI_FUNCTION(0x3, "spi0")),     /* MOSI */
0158     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
0159           SUNXI_FUNCTION(0x0, "gpio_in"),
0160           SUNXI_FUNCTION(0x1, "gpio_out"),
0161           SUNXI_FUNCTION(0x2, "nand0"),     /* ALE */
0162           SUNXI_FUNCTION(0x3, "spi0"),      /* MISO */
0163           SUNXI_FUNCTION(0x4, "mmc2")),     /* DS */
0164     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
0165           SUNXI_FUNCTION(0x0, "gpio_in"),
0166           SUNXI_FUNCTION(0x1, "gpio_out"),
0167           SUNXI_FUNCTION(0x2, "nand0"),     /* CLE */
0168           SUNXI_FUNCTION(0x3, "spi0")),     /* CLK */
0169     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
0170           SUNXI_FUNCTION(0x0, "gpio_in"),
0171           SUNXI_FUNCTION(0x1, "gpio_out"),
0172           SUNXI_FUNCTION(0x2, "nand0"),     /* CE1 */
0173           SUNXI_FUNCTION(0x3, "spi0")),     /* CS */
0174     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
0175           SUNXI_FUNCTION(0x0, "gpio_in"),
0176           SUNXI_FUNCTION(0x1, "gpio_out"),
0177           SUNXI_FUNCTION(0x2, "nand0"),     /* CE0 */
0178           SUNXI_FUNCTION(0x4, "spi0")),     /* MISO */
0179     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
0180           SUNXI_FUNCTION(0x0, "gpio_in"),
0181           SUNXI_FUNCTION(0x1, "gpio_out"),
0182           SUNXI_FUNCTION(0x2, "nand0"),     /* RE */
0183           SUNXI_FUNCTION(0x3, "mmc2")),     /* CLK */
0184     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
0185           SUNXI_FUNCTION(0x0, "gpio_in"),
0186           SUNXI_FUNCTION(0x1, "gpio_out"),
0187           SUNXI_FUNCTION(0x2, "nand0"),     /* RB0 */
0188           SUNXI_FUNCTION(0x3, "mmc2")),     /* CMD */
0189     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
0190           SUNXI_FUNCTION(0x0, "gpio_in"),
0191           SUNXI_FUNCTION(0x1, "gpio_out"),
0192           SUNXI_FUNCTION(0x2, "nand0")),    /* RB1 */
0193     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
0194           SUNXI_FUNCTION(0x0, "gpio_in"),
0195           SUNXI_FUNCTION(0x1, "gpio_out"),
0196           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ0 */
0197           SUNXI_FUNCTION(0x3, "mmc2")),     /* D0 */
0198     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
0199           SUNXI_FUNCTION(0x0, "gpio_in"),
0200           SUNXI_FUNCTION(0x1, "gpio_out"),
0201           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ1 */
0202           SUNXI_FUNCTION(0x3, "mmc2")),     /* D1 */
0203     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
0204           SUNXI_FUNCTION(0x0, "gpio_in"),
0205           SUNXI_FUNCTION(0x1, "gpio_out"),
0206           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ2 */
0207           SUNXI_FUNCTION(0x3, "mmc2")),     /* D2 */
0208     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
0209           SUNXI_FUNCTION(0x0, "gpio_in"),
0210           SUNXI_FUNCTION(0x1, "gpio_out"),
0211           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ3 */
0212           SUNXI_FUNCTION(0x3, "mmc2")),     /* D3 */
0213     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
0214           SUNXI_FUNCTION(0x0, "gpio_in"),
0215           SUNXI_FUNCTION(0x1, "gpio_out"),
0216           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ4 */
0217           SUNXI_FUNCTION(0x3, "mmc2")),     /* D4 */
0218     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
0219           SUNXI_FUNCTION(0x0, "gpio_in"),
0220           SUNXI_FUNCTION(0x1, "gpio_out"),
0221           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ5 */
0222           SUNXI_FUNCTION(0x3, "mmc2")),     /* D5 */
0223     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
0224           SUNXI_FUNCTION(0x0, "gpio_in"),
0225           SUNXI_FUNCTION(0x1, "gpio_out"),
0226           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ6 */
0227           SUNXI_FUNCTION(0x3, "mmc2")),     /* D6 */
0228     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
0229           SUNXI_FUNCTION(0x0, "gpio_in"),
0230           SUNXI_FUNCTION(0x1, "gpio_out"),
0231           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ7 */
0232           SUNXI_FUNCTION(0x3, "mmc2")),     /* D7 */
0233     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
0234           SUNXI_FUNCTION(0x0, "gpio_in"),
0235           SUNXI_FUNCTION(0x1, "gpio_out"),
0236           SUNXI_FUNCTION(0x2, "nand0"),     /* DQS */
0237           SUNXI_FUNCTION(0x3, "mmc2")),     /* RST */
0238     /* Hole */
0239     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
0240           SUNXI_FUNCTION(0x0, "gpio_in"),
0241           SUNXI_FUNCTION(0x1, "gpio_out"),
0242           SUNXI_FUNCTION(0x2, "emac"),      /* RXD3 */
0243           SUNXI_FUNCTION(0x3, "di"),        /* TX */
0244           SUNXI_FUNCTION(0x4, "ts2")),      /* CLK */
0245     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
0246           SUNXI_FUNCTION(0x0, "gpio_in"),
0247           SUNXI_FUNCTION(0x1, "gpio_out"),
0248           SUNXI_FUNCTION(0x2, "emac"),      /* RXD2 */
0249           SUNXI_FUNCTION(0x3, "di"),        /* RX */
0250           SUNXI_FUNCTION(0x4, "ts2")),      /* ERR */
0251     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
0252           SUNXI_FUNCTION(0x0, "gpio_in"),
0253           SUNXI_FUNCTION(0x1, "gpio_out"),
0254           SUNXI_FUNCTION(0x2, "emac"),      /* RXD1 */
0255           SUNXI_FUNCTION(0x4, "ts2")),      /* SYNC */
0256     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
0257           SUNXI_FUNCTION(0x0, "gpio_in"),
0258           SUNXI_FUNCTION(0x1, "gpio_out"),
0259           SUNXI_FUNCTION(0x2, "emac"),      /* RXD0 */
0260           SUNXI_FUNCTION(0x4, "ts2")),      /* DVLD */
0261     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
0262           SUNXI_FUNCTION(0x0, "gpio_in"),
0263           SUNXI_FUNCTION(0x1, "gpio_out"),
0264           SUNXI_FUNCTION(0x2, "emac"),      /* RXCK */
0265           SUNXI_FUNCTION(0x4, "ts2")),      /* D0 */
0266     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
0267           SUNXI_FUNCTION(0x0, "gpio_in"),
0268           SUNXI_FUNCTION(0x1, "gpio_out"),
0269           SUNXI_FUNCTION(0x2, "emac"),      /* RXCTL/RXDV */
0270           SUNXI_FUNCTION(0x4, "ts2")),      /* D1 */
0271     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
0272           SUNXI_FUNCTION(0x0, "gpio_in"),
0273           SUNXI_FUNCTION(0x1, "gpio_out"),
0274           SUNXI_FUNCTION(0x2, "emac"),      /* RXERR */
0275           SUNXI_FUNCTION(0x4, "ts2")),      /* D2 */
0276     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
0277           SUNXI_FUNCTION(0x0, "gpio_in"),
0278           SUNXI_FUNCTION(0x1, "gpio_out"),
0279           SUNXI_FUNCTION(0x2, "emac"),      /* TXD3 */
0280           SUNXI_FUNCTION(0x4, "ts2"),       /* D3 */
0281           SUNXI_FUNCTION(0x5, "ts3")),      /* CLK */
0282     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
0283           SUNXI_FUNCTION(0x0, "gpio_in"),
0284           SUNXI_FUNCTION(0x1, "gpio_out"),
0285           SUNXI_FUNCTION(0x2, "emac"),      /* TXD2 */
0286           SUNXI_FUNCTION(0x4, "ts2"),       /* D4 */
0287           SUNXI_FUNCTION(0x5, "ts3")),      /* ERR */
0288     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
0289           SUNXI_FUNCTION(0x0, "gpio_in"),
0290           SUNXI_FUNCTION(0x1, "gpio_out"),
0291           SUNXI_FUNCTION(0x2, "emac"),      /* TXD1 */
0292           SUNXI_FUNCTION(0x4, "ts2"),       /* D5 */
0293           SUNXI_FUNCTION(0x5, "ts3")),      /* SYNC */
0294     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
0295           SUNXI_FUNCTION(0x0, "gpio_in"),
0296           SUNXI_FUNCTION(0x1, "gpio_out"),
0297           SUNXI_FUNCTION(0x2, "emac"),      /* TXD0 */
0298           SUNXI_FUNCTION(0x4, "ts2"),       /* D6 */
0299           SUNXI_FUNCTION(0x5, "ts3")),      /* DVLD */
0300     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
0301           SUNXI_FUNCTION(0x0, "gpio_in"),
0302           SUNXI_FUNCTION(0x1, "gpio_out"),
0303           SUNXI_FUNCTION(0x2, "emac"),      /* CRS */
0304           SUNXI_FUNCTION(0x4, "ts2"),       /* D7 */
0305           SUNXI_FUNCTION(0x5, "ts3")),      /* D0 */
0306     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
0307           SUNXI_FUNCTION(0x0, "gpio_in"),
0308           SUNXI_FUNCTION(0x1, "gpio_out"),
0309           SUNXI_FUNCTION(0x2, "emac"),      /* TXCK */
0310           SUNXI_FUNCTION(0x4, "sim")),      /* PWREN */
0311     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
0312           SUNXI_FUNCTION(0x0, "gpio_in"),
0313           SUNXI_FUNCTION(0x1, "gpio_out"),
0314           SUNXI_FUNCTION(0x2, "emac"),      /* TXCTL/TXEN */
0315           SUNXI_FUNCTION(0x4, "sim")),      /* CLK */
0316     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
0317           SUNXI_FUNCTION(0x0, "gpio_in"),
0318           SUNXI_FUNCTION(0x1, "gpio_out"),
0319           SUNXI_FUNCTION(0x2, "emac"),      /* TXERR */
0320           SUNXI_FUNCTION(0x4, "sim")),      /* DATA */
0321     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
0322           SUNXI_FUNCTION(0x0, "gpio_in"),
0323           SUNXI_FUNCTION(0x1, "gpio_out"),
0324           SUNXI_FUNCTION(0x2, "emac"),      /* CLKIN/COL */
0325           SUNXI_FUNCTION(0x4, "sim")),      /* RST */
0326     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
0327           SUNXI_FUNCTION(0x0, "gpio_in"),
0328           SUNXI_FUNCTION(0x1, "gpio_out"),
0329           SUNXI_FUNCTION(0x2, "emac"),      /* MDC */
0330           SUNXI_FUNCTION(0x4, "sim")),      /* DET */
0331     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
0332           SUNXI_FUNCTION(0x0, "gpio_in"),
0333           SUNXI_FUNCTION(0x1, "gpio_out"),
0334           SUNXI_FUNCTION(0x2, "emac")),     /* MDIO */
0335     /* Hole */
0336     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
0337           SUNXI_FUNCTION(0x0, "gpio_in"),
0338           SUNXI_FUNCTION(0x1, "gpio_out"),
0339           SUNXI_FUNCTION(0x2, "csi"),       /* PCLK */
0340           SUNXI_FUNCTION(0x3, "ts0")),      /* CLK */
0341     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
0342           SUNXI_FUNCTION(0x0, "gpio_in"),
0343           SUNXI_FUNCTION(0x1, "gpio_out"),
0344           SUNXI_FUNCTION(0x2, "csi"),       /* MCLK */
0345           SUNXI_FUNCTION(0x3, "ts0")),      /* ERR */
0346     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
0347           SUNXI_FUNCTION(0x0, "gpio_in"),
0348           SUNXI_FUNCTION(0x1, "gpio_out"),
0349           SUNXI_FUNCTION(0x2, "csi"),       /* HSYNC */
0350           SUNXI_FUNCTION(0x3, "ts0")),      /* SYNC */
0351     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
0352           SUNXI_FUNCTION(0x0, "gpio_in"),
0353           SUNXI_FUNCTION(0x1, "gpio_out"),
0354           SUNXI_FUNCTION(0x2, "csi"),       /* VSYNC */
0355           SUNXI_FUNCTION(0x3, "ts0")),      /* DVLD */
0356     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
0357           SUNXI_FUNCTION(0x0, "gpio_in"),
0358           SUNXI_FUNCTION(0x1, "gpio_out"),
0359           SUNXI_FUNCTION(0x2, "csi"),       /* D0 */
0360           SUNXI_FUNCTION(0x3, "ts0")),      /* D0 */
0361     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
0362           SUNXI_FUNCTION(0x0, "gpio_in"),
0363           SUNXI_FUNCTION(0x1, "gpio_out"),
0364           SUNXI_FUNCTION(0x2, "csi"),       /* D1 */
0365           SUNXI_FUNCTION(0x3, "ts0")),      /* D1 */
0366     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
0367           SUNXI_FUNCTION(0x0, "gpio_in"),
0368           SUNXI_FUNCTION(0x1, "gpio_out"),
0369           SUNXI_FUNCTION(0x2, "csi"),       /* D2 */
0370           SUNXI_FUNCTION(0x3, "ts0")),      /* D2 */
0371     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
0372           SUNXI_FUNCTION(0x0, "gpio_in"),
0373           SUNXI_FUNCTION(0x1, "gpio_out"),
0374           SUNXI_FUNCTION(0x2, "csi"),       /* D3 */
0375           SUNXI_FUNCTION(0x3, "ts0"),       /* D3 */
0376           SUNXI_FUNCTION(0x4, "ts1")),      /* CLK */
0377     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
0378           SUNXI_FUNCTION(0x0, "gpio_in"),
0379           SUNXI_FUNCTION(0x1, "gpio_out"),
0380           SUNXI_FUNCTION(0x2, "csi"),       /* D4 */
0381           SUNXI_FUNCTION(0x3, "ts0"),       /* D4 */
0382           SUNXI_FUNCTION(0x4, "ts1")),      /* ERR */
0383     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
0384           SUNXI_FUNCTION(0x0, "gpio_in"),
0385           SUNXI_FUNCTION(0x1, "gpio_out"),
0386           SUNXI_FUNCTION(0x2, "csi"),       /* D5 */
0387           SUNXI_FUNCTION(0x3, "ts0"),       /* D5 */
0388           SUNXI_FUNCTION(0x4, "ts1")),      /* SYNC */
0389     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
0390           SUNXI_FUNCTION(0x0, "gpio_in"),
0391           SUNXI_FUNCTION(0x1, "gpio_out"),
0392           SUNXI_FUNCTION(0x2, "csi"),       /* D6 */
0393           SUNXI_FUNCTION(0x3, "ts0"),       /* D6 */
0394           SUNXI_FUNCTION(0x4, "ts1")),      /* DVLD */
0395     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
0396           SUNXI_FUNCTION(0x0, "gpio_in"),
0397           SUNXI_FUNCTION(0x1, "gpio_out"),
0398           SUNXI_FUNCTION(0x2, "csi"),       /* D7 */
0399           SUNXI_FUNCTION(0x3, "ts"),        /* D7 */
0400           SUNXI_FUNCTION(0x4, "ts1")),      /* D0 */
0401     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
0402           SUNXI_FUNCTION(0x0, "gpio_in"),
0403           SUNXI_FUNCTION(0x1, "gpio_out"),
0404           SUNXI_FUNCTION(0x2, "csi"),       /* SCK */
0405           SUNXI_FUNCTION(0x3, "i2c2")),     /* SCK */
0406     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
0407           SUNXI_FUNCTION(0x0, "gpio_in"),
0408           SUNXI_FUNCTION(0x1, "gpio_out"),
0409           SUNXI_FUNCTION(0x2, "csi"),       /* SDA */
0410           SUNXI_FUNCTION(0x3, "i2c2")),     /* SDA */
0411     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
0412           SUNXI_FUNCTION(0x0, "gpio_in"),
0413           SUNXI_FUNCTION(0x1, "gpio_out"),
0414           SUNXI_FUNCTION(0x3, "sim")),      /* VPPEN */
0415     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
0416           SUNXI_FUNCTION(0x0, "gpio_in"),
0417           SUNXI_FUNCTION(0x1, "gpio_out"),
0418           SUNXI_FUNCTION(0x3, "sim")),      /* VPPPP */
0419     /* Hole */
0420     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
0421           SUNXI_FUNCTION(0x0, "gpio_in"),
0422           SUNXI_FUNCTION(0x1, "gpio_out"),
0423           SUNXI_FUNCTION(0x2, "mmc0"),      /* D1 */
0424           SUNXI_FUNCTION(0x3, "jtag"),      /* MS */
0425           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),  /* PF_EINT0 */
0426     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
0427           SUNXI_FUNCTION(0x0, "gpio_in"),
0428           SUNXI_FUNCTION(0x1, "gpio_out"),
0429           SUNXI_FUNCTION(0x2, "mmc0"),      /* D0 */
0430           SUNXI_FUNCTION(0x3, "jtag"),      /* DI */
0431           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),  /* PF_EINT1 */
0432     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
0433           SUNXI_FUNCTION(0x0, "gpio_in"),
0434           SUNXI_FUNCTION(0x1, "gpio_out"),
0435           SUNXI_FUNCTION(0x2, "mmc0"),      /* CLK */
0436           SUNXI_FUNCTION(0x3, "uart0"),     /* TX */
0437           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),  /* PF_EINT2 */
0438     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
0439           SUNXI_FUNCTION(0x0, "gpio_in"),
0440           SUNXI_FUNCTION(0x1, "gpio_out"),
0441           SUNXI_FUNCTION(0x2, "mmc0"),      /* CMD */
0442           SUNXI_FUNCTION(0x3, "jtag"),      /* DO */
0443           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),  /* PF_EINT3 */
0444     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
0445           SUNXI_FUNCTION(0x0, "gpio_in"),
0446           SUNXI_FUNCTION(0x1, "gpio_out"),
0447           SUNXI_FUNCTION(0x2, "mmc0"),      /* D3 */
0448           SUNXI_FUNCTION(0x3, "uart0"),     /* RX */
0449           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),  /* PF_EINT4 */
0450     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
0451           SUNXI_FUNCTION(0x0, "gpio_in"),
0452           SUNXI_FUNCTION(0x1, "gpio_out"),
0453           SUNXI_FUNCTION(0x2, "mmc0"),      /* D2 */
0454           SUNXI_FUNCTION(0x3, "jtag"),      /* CK */
0455           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),  /* PF_EINT5 */
0456     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
0457           SUNXI_FUNCTION(0x0, "gpio_in"),
0458           SUNXI_FUNCTION(0x1, "gpio_out"),
0459           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),  /* PF_EINT6 */
0460     /* Hole */
0461     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
0462           SUNXI_FUNCTION(0x0, "gpio_in"),
0463           SUNXI_FUNCTION(0x1, "gpio_out"),
0464           SUNXI_FUNCTION(0x2, "mmc1"),      /* CLK */
0465           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),  /* PG_EINT0 */
0466     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
0467           SUNXI_FUNCTION(0x0, "gpio_in"),
0468           SUNXI_FUNCTION(0x1, "gpio_out"),
0469           SUNXI_FUNCTION(0x2, "mmc1"),      /* CMD */
0470           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),  /* PG_EINT1 */
0471     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
0472           SUNXI_FUNCTION(0x0, "gpio_in"),
0473           SUNXI_FUNCTION(0x1, "gpio_out"),
0474           SUNXI_FUNCTION(0x2, "mmc1"),      /* D0 */
0475           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),  /* PG_EINT2 */
0476     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
0477           SUNXI_FUNCTION(0x0, "gpio_in"),
0478           SUNXI_FUNCTION(0x1, "gpio_out"),
0479           SUNXI_FUNCTION(0x2, "mmc1"),      /* D1 */
0480           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),  /* PG_EINT3 */
0481     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
0482           SUNXI_FUNCTION(0x0, "gpio_in"),
0483           SUNXI_FUNCTION(0x1, "gpio_out"),
0484           SUNXI_FUNCTION(0x2, "mmc1"),      /* D2 */
0485           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),  /* PG_EINT4 */
0486     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
0487           SUNXI_FUNCTION(0x0, "gpio_in"),
0488           SUNXI_FUNCTION(0x1, "gpio_out"),
0489           SUNXI_FUNCTION(0x2, "mmc1"),      /* D3 */
0490           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),  /* PG_EINT5 */
0491     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
0492           SUNXI_FUNCTION(0x0, "gpio_in"),
0493           SUNXI_FUNCTION(0x1, "gpio_out"),
0494           SUNXI_FUNCTION(0x2, "uart1"),     /* TX */
0495           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),  /* PG_EINT6 */
0496     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
0497           SUNXI_FUNCTION(0x0, "gpio_in"),
0498           SUNXI_FUNCTION(0x1, "gpio_out"),
0499           SUNXI_FUNCTION(0x2, "uart1"),     /* RX */
0500           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),  /* PG_EINT7 */
0501     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
0502           SUNXI_FUNCTION(0x0, "gpio_in"),
0503           SUNXI_FUNCTION(0x1, "gpio_out"),
0504           SUNXI_FUNCTION(0x2, "uart1"),     /* RTS */
0505           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),  /* PG_EINT8 */
0506     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
0507           SUNXI_FUNCTION(0x0, "gpio_in"),
0508           SUNXI_FUNCTION(0x1, "gpio_out"),
0509           SUNXI_FUNCTION(0x2, "uart1"),     /* CTS */
0510           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),  /* PG_EINT9 */
0511     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
0512           SUNXI_FUNCTION(0x0, "gpio_in"),
0513           SUNXI_FUNCTION(0x1, "gpio_out"),
0514           SUNXI_FUNCTION(0x2, "i2s1"),      /* SYNC */
0515           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */
0516     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
0517           SUNXI_FUNCTION(0x0, "gpio_in"),
0518           SUNXI_FUNCTION(0x1, "gpio_out"),
0519           SUNXI_FUNCTION(0x2, "i2s1"),      /* CLK */
0520           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */
0521     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
0522           SUNXI_FUNCTION(0x0, "gpio_in"),
0523           SUNXI_FUNCTION(0x1, "gpio_out"),
0524           SUNXI_FUNCTION(0x2, "i2s1"),      /* DOUT */
0525           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */
0526     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
0527           SUNXI_FUNCTION(0x0, "gpio_in"),
0528           SUNXI_FUNCTION(0x1, "gpio_out"),
0529           SUNXI_FUNCTION(0x2, "i2s1"),      /* DIN */
0530           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */
0531 };
0532 
0533 static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data_broken = {
0534     .pins = sun50i_h5_pins,
0535     .npins = ARRAY_SIZE(sun50i_h5_pins),
0536     .irq_banks = 2,
0537     .irq_read_needs_mux = true,
0538     .disable_strict_mode = true,
0539 };
0540 
0541 static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = {
0542     .pins = sun50i_h5_pins,
0543     .npins = ARRAY_SIZE(sun50i_h5_pins),
0544     .irq_banks = 3,
0545     .irq_read_needs_mux = true,
0546     .disable_strict_mode = true,
0547 };
0548 
0549 static int sun50i_h5_pinctrl_probe(struct platform_device *pdev)
0550 {
0551     int ret;
0552 
0553     ret = platform_irq_count(pdev);
0554     if (ret < 0) {
0555         if (ret != -EPROBE_DEFER)
0556             dev_err(&pdev->dev, "Couldn't determine irq count: %pe\n",
0557                 ERR_PTR(ret));
0558         return ret;
0559     }
0560 
0561     switch (ret) {
0562     case 2:
0563         dev_warn(&pdev->dev,
0564              "Your device tree's pinctrl node is broken, which has no IRQ of PG bank routed.\n");
0565         dev_warn(&pdev->dev,
0566              "Please update the device tree, otherwise PG bank IRQ won't work.\n");
0567         return sunxi_pinctrl_init(pdev,
0568                       &sun50i_h5_pinctrl_data_broken);
0569     case 3:
0570         return sunxi_pinctrl_init(pdev,
0571                       &sun50i_h5_pinctrl_data);
0572     default:
0573         return -EINVAL;
0574     }
0575 }
0576 
0577 static const struct of_device_id sun50i_h5_pinctrl_match[] = {
0578     { .compatible = "allwinner,sun50i-h5-pinctrl", },
0579     {}
0580 };
0581 
0582 static struct platform_driver sun50i_h5_pinctrl_driver = {
0583     .probe  = sun50i_h5_pinctrl_probe,
0584     .driver = {
0585         .name       = "sun50i-h5-pinctrl",
0586         .of_match_table = sun50i_h5_pinctrl_match,
0587     },
0588 };
0589 builtin_platform_driver(sun50i_h5_pinctrl_driver);
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