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OSCL-LXR
 
 

     

0001 /*
0002  * Allwinner A64 SoCs pinctrl driver.
0003  *
0004  * Copyright (C) 2016 - ARM Ltd.
0005  * Author: Andre Przywara <andre.przywara@arm.com>
0006  *
0007  * Based on pinctrl-sun7i-a20.c, which is:
0008  * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
0009  *
0010  * This file is licensed under the terms of the GNU General Public
0011  * License version 2.  This program is licensed "as is" without any
0012  * warranty of any kind, whether express or implied.
0013  */
0014 
0015 #include <linux/module.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/of.h>
0018 #include <linux/of_device.h>
0019 #include <linux/pinctrl/pinctrl.h>
0020 
0021 #include "pinctrl-sunxi.h"
0022 
0023 static const struct sunxi_desc_pin a64_pins[] = {
0024     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
0025           SUNXI_FUNCTION(0x0, "gpio_in"),
0026           SUNXI_FUNCTION(0x1, "gpio_out"),
0027           SUNXI_FUNCTION(0x2, "uart2"),     /* TX */
0028           SUNXI_FUNCTION(0x4, "jtag"),      /* MS0 */
0029           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* EINT0 */
0030     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
0031           SUNXI_FUNCTION(0x0, "gpio_in"),
0032           SUNXI_FUNCTION(0x1, "gpio_out"),
0033           SUNXI_FUNCTION(0x2, "uart2"),     /* RX */
0034           SUNXI_FUNCTION(0x4, "jtag"),      /* CK0 */
0035           SUNXI_FUNCTION(0x5, "sim"),       /* VCCEN */
0036           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),      /* EINT1 */
0037     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
0038           SUNXI_FUNCTION(0x0, "gpio_in"),
0039           SUNXI_FUNCTION(0x1, "gpio_out"),
0040           SUNXI_FUNCTION(0x2, "uart2"),     /* RTS */
0041           SUNXI_FUNCTION(0x4, "jtag"),      /* DO0 */
0042           SUNXI_FUNCTION(0x5, "sim"),       /* VPPEN */
0043           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),      /* EINT2 */
0044     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
0045           SUNXI_FUNCTION(0x0, "gpio_in"),
0046           SUNXI_FUNCTION(0x1, "gpio_out"),
0047           SUNXI_FUNCTION(0x2, "uart2"),     /* CTS */
0048           SUNXI_FUNCTION(0x3, "i2s0"),      /* MCLK */
0049           SUNXI_FUNCTION(0x4, "jtag"),      /* DI0 */
0050           SUNXI_FUNCTION(0x5, "sim"),       /* VPPPP */
0051           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),      /* EINT3 */
0052     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
0053           SUNXI_FUNCTION(0x0, "gpio_in"),
0054           SUNXI_FUNCTION(0x1, "gpio_out"),
0055           SUNXI_FUNCTION(0x2, "aif2"),      /* SYNC */
0056           SUNXI_FUNCTION(0x3, "i2s0"),      /* SYNC */
0057           SUNXI_FUNCTION(0x5, "sim"),       /* CLK */
0058           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),      /* EINT4 */
0059     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
0060           SUNXI_FUNCTION(0x0, "gpio_in"),
0061           SUNXI_FUNCTION(0x1, "gpio_out"),
0062           SUNXI_FUNCTION(0x2, "aif2"),      /* BCLK */
0063           SUNXI_FUNCTION(0x3, "i2s0"),      /* BCLK */
0064           SUNXI_FUNCTION(0x5, "sim"),       /* DATA */
0065           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),      /* EINT5 */
0066     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
0067           SUNXI_FUNCTION(0x0, "gpio_in"),
0068           SUNXI_FUNCTION(0x1, "gpio_out"),
0069           SUNXI_FUNCTION(0x2, "aif2"),      /* DOUT */
0070           SUNXI_FUNCTION(0x3, "i2s0"),      /* DOUT */
0071           SUNXI_FUNCTION(0x5, "sim"),       /* RST */
0072           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),      /* EINT6 */
0073     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
0074           SUNXI_FUNCTION(0x0, "gpio_in"),
0075           SUNXI_FUNCTION(0x1, "gpio_out"),
0076           SUNXI_FUNCTION(0x2, "aif2"),      /* DIN */
0077           SUNXI_FUNCTION(0x3, "i2s0"),      /* DIN */
0078           SUNXI_FUNCTION(0x5, "sim"),       /* DET */
0079           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),      /* EINT7 */
0080     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
0081           SUNXI_FUNCTION(0x0, "gpio_in"),
0082           SUNXI_FUNCTION(0x1, "gpio_out"),
0083           SUNXI_FUNCTION(0x4, "uart0"),     /* TX */
0084           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),      /* EINT8 */
0085     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
0086           SUNXI_FUNCTION(0x0, "gpio_in"),
0087           SUNXI_FUNCTION(0x1, "gpio_out"),
0088           SUNXI_FUNCTION(0x4, "uart0"),     /* RX */
0089           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),      /* EINT9 */
0090     /* Hole */
0091     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
0092           SUNXI_FUNCTION(0x0, "gpio_in"),
0093           SUNXI_FUNCTION(0x1, "gpio_out"),
0094           SUNXI_FUNCTION(0x2, "nand0"),     /* NWE */
0095           SUNXI_FUNCTION(0x4, "spi0")),     /* MOSI */
0096     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
0097           SUNXI_FUNCTION(0x0, "gpio_in"),
0098           SUNXI_FUNCTION(0x1, "gpio_out"),
0099           SUNXI_FUNCTION(0x2, "nand0"),     /* NALE */
0100           SUNXI_FUNCTION(0x3, "mmc2"),      /* DS */
0101           SUNXI_FUNCTION(0x4, "spi0")),     /* MISO */
0102     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
0103           SUNXI_FUNCTION(0x0, "gpio_in"),
0104           SUNXI_FUNCTION(0x1, "gpio_out"),
0105           SUNXI_FUNCTION(0x2, "nand0"),     /* NCLE */
0106           SUNXI_FUNCTION(0x4, "spi0")),     /* SCK */
0107     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
0108           SUNXI_FUNCTION(0x0, "gpio_in"),
0109           SUNXI_FUNCTION(0x1, "gpio_out"),
0110           SUNXI_FUNCTION(0x2, "nand0"),     /* NCE1 */
0111           SUNXI_FUNCTION(0x4, "spi0")),     /* CS */
0112     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
0113           SUNXI_FUNCTION(0x0, "gpio_in"),
0114           SUNXI_FUNCTION(0x1, "gpio_out"),
0115           SUNXI_FUNCTION(0x2, "nand0")),    /* NCE0 */
0116     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
0117           SUNXI_FUNCTION(0x0, "gpio_in"),
0118           SUNXI_FUNCTION(0x1, "gpio_out"),
0119           SUNXI_FUNCTION(0x2, "nand0"),     /* NRE# */
0120           SUNXI_FUNCTION(0x3, "mmc2")),     /* CLK */
0121     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
0122           SUNXI_FUNCTION(0x0, "gpio_in"),
0123           SUNXI_FUNCTION(0x1, "gpio_out"),
0124           SUNXI_FUNCTION(0x2, "nand0"),     /* NRB0 */
0125           SUNXI_FUNCTION(0x3, "mmc2")),     /* CMD */
0126     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
0127           SUNXI_FUNCTION(0x0, "gpio_in"),
0128           SUNXI_FUNCTION(0x1, "gpio_out"),
0129           SUNXI_FUNCTION(0x2, "nand0")),    /* NRB1 */
0130     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
0131           SUNXI_FUNCTION(0x0, "gpio_in"),
0132           SUNXI_FUNCTION(0x1, "gpio_out"),
0133           SUNXI_FUNCTION(0x2, "nand0"),     /* NDQ0 */
0134           SUNXI_FUNCTION(0x3, "mmc2")),     /* D0 */
0135     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
0136           SUNXI_FUNCTION(0x0, "gpio_in"),
0137           SUNXI_FUNCTION(0x1, "gpio_out"),
0138           SUNXI_FUNCTION(0x2, "nand0"),     /* NDQ1 */
0139           SUNXI_FUNCTION(0x3, "mmc2")),     /* D1 */
0140     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
0141           SUNXI_FUNCTION(0x0, "gpio_in"),
0142           SUNXI_FUNCTION(0x1, "gpio_out"),
0143           SUNXI_FUNCTION(0x2, "nand0"),     /* NDQ2 */
0144           SUNXI_FUNCTION(0x3, "mmc2")),     /* D2 */
0145     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
0146           SUNXI_FUNCTION(0x0, "gpio_in"),
0147           SUNXI_FUNCTION(0x1, "gpio_out"),
0148           SUNXI_FUNCTION(0x2, "nand0"),     /* NDQ3 */
0149           SUNXI_FUNCTION(0x3, "mmc2")),     /* D3 */
0150     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
0151           SUNXI_FUNCTION(0x0, "gpio_in"),
0152           SUNXI_FUNCTION(0x1, "gpio_out"),
0153           SUNXI_FUNCTION(0x2, "nand0"),     /* NDQ4 */
0154           SUNXI_FUNCTION(0x3, "mmc2")),     /* D4 */
0155     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
0156           SUNXI_FUNCTION(0x0, "gpio_in"),
0157           SUNXI_FUNCTION(0x1, "gpio_out"),
0158           SUNXI_FUNCTION(0x2, "nand0"),     /* NDQ5 */
0159           SUNXI_FUNCTION(0x3, "mmc2")),     /* D5 */
0160     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
0161           SUNXI_FUNCTION(0x0, "gpio_in"),
0162           SUNXI_FUNCTION(0x1, "gpio_out"),
0163           SUNXI_FUNCTION(0x2, "nand0"),     /* NDQ6 */
0164           SUNXI_FUNCTION(0x3, "mmc2")),     /* D6 */
0165     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
0166           SUNXI_FUNCTION(0x0, "gpio_in"),
0167           SUNXI_FUNCTION(0x1, "gpio_out"),
0168           SUNXI_FUNCTION(0x2, "nand0"),     /* NDQ7 */
0169           SUNXI_FUNCTION(0x3, "mmc2")),     /* D7 */
0170     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
0171           SUNXI_FUNCTION(0x0, "gpio_in"),
0172           SUNXI_FUNCTION(0x1, "gpio_out"),
0173           SUNXI_FUNCTION(0x2, "nand0"),     /* NDQS */
0174           SUNXI_FUNCTION(0x3, "mmc2")),     /* RST */
0175     /* Hole */
0176     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
0177           SUNXI_FUNCTION(0x0, "gpio_in"),
0178           SUNXI_FUNCTION(0x1, "gpio_out"),
0179           SUNXI_FUNCTION(0x2, "lcd0"),      /* D2 */
0180           SUNXI_FUNCTION(0x3, "uart3"),     /* TX */
0181           SUNXI_FUNCTION(0x4, "spi1"),      /* CS */
0182           SUNXI_FUNCTION(0x5, "ccir")),     /* CLK */
0183     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
0184           SUNXI_FUNCTION(0x0, "gpio_in"),
0185           SUNXI_FUNCTION(0x1, "gpio_out"),
0186           SUNXI_FUNCTION(0x2, "lcd0"),      /* D3 */
0187           SUNXI_FUNCTION(0x3, "uart3"),     /* RX */
0188           SUNXI_FUNCTION(0x4, "spi1"),      /* CLK */
0189           SUNXI_FUNCTION(0x5, "ccir")),     /* DE */
0190     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
0191           SUNXI_FUNCTION(0x0, "gpio_in"),
0192           SUNXI_FUNCTION(0x1, "gpio_out"),
0193           SUNXI_FUNCTION(0x2, "lcd0"),      /* D4 */
0194           SUNXI_FUNCTION(0x3, "uart4"),     /* TX */
0195           SUNXI_FUNCTION(0x4, "spi1"),      /* MOSI */
0196           SUNXI_FUNCTION(0x5, "ccir")),     /* HSYNC */
0197     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
0198           SUNXI_FUNCTION(0x0, "gpio_in"),
0199           SUNXI_FUNCTION(0x1, "gpio_out"),
0200           SUNXI_FUNCTION(0x2, "lcd0"),      /* D5 */
0201           SUNXI_FUNCTION(0x3, "uart4"),     /* RX */
0202           SUNXI_FUNCTION(0x4, "spi1"),      /* MISO */
0203           SUNXI_FUNCTION(0x5, "ccir")),     /* VSYNC */
0204     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
0205           SUNXI_FUNCTION(0x0, "gpio_in"),
0206           SUNXI_FUNCTION(0x1, "gpio_out"),
0207           SUNXI_FUNCTION(0x2, "lcd0"),      /* D6 */
0208           SUNXI_FUNCTION(0x3, "uart4"),     /* RTS */
0209           SUNXI_FUNCTION(0x5, "ccir")),     /* D0 */
0210     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
0211           SUNXI_FUNCTION(0x0, "gpio_in"),
0212           SUNXI_FUNCTION(0x1, "gpio_out"),
0213           SUNXI_FUNCTION(0x2, "lcd0"),      /* D7 */
0214           SUNXI_FUNCTION(0x3, "uart4"),     /* CTS */
0215           SUNXI_FUNCTION(0x5, "ccir")),     /* D1 */
0216     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
0217           SUNXI_FUNCTION(0x0, "gpio_in"),
0218           SUNXI_FUNCTION(0x1, "gpio_out"),
0219           SUNXI_FUNCTION(0x2, "lcd0"),      /* D10 */
0220           SUNXI_FUNCTION(0x5, "ccir")),     /* D2 */
0221     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
0222           SUNXI_FUNCTION(0x0, "gpio_in"),
0223           SUNXI_FUNCTION(0x1, "gpio_out"),
0224           SUNXI_FUNCTION(0x2, "lcd0"),      /* D11 */
0225           SUNXI_FUNCTION(0x5, "ccir")),     /* D3 */
0226     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
0227           SUNXI_FUNCTION(0x0, "gpio_in"),
0228           SUNXI_FUNCTION(0x1, "gpio_out"),
0229           SUNXI_FUNCTION(0x2, "lcd0"),      /* D12 */
0230           SUNXI_FUNCTION(0x4, "emac"),      /* ERXD3 */
0231           SUNXI_FUNCTION(0x5, "ccir")),     /* D4 */
0232     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
0233           SUNXI_FUNCTION(0x0, "gpio_in"),
0234           SUNXI_FUNCTION(0x1, "gpio_out"),
0235           SUNXI_FUNCTION(0x2, "lcd0"),      /* D13 */
0236           SUNXI_FUNCTION(0x4, "emac"),      /* ERXD2 */
0237           SUNXI_FUNCTION(0x5, "ccir")),     /* D5 */
0238     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
0239           SUNXI_FUNCTION(0x0, "gpio_in"),
0240           SUNXI_FUNCTION(0x1, "gpio_out"),
0241           SUNXI_FUNCTION(0x2, "lcd0"),      /* D14 */
0242           SUNXI_FUNCTION(0x4, "emac")),     /* ERXD1 */
0243     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
0244           SUNXI_FUNCTION(0x0, "gpio_in"),
0245           SUNXI_FUNCTION(0x1, "gpio_out"),
0246           SUNXI_FUNCTION(0x2, "lcd0"),      /* D15 */
0247           SUNXI_FUNCTION(0x4, "emac")),     /* ERXD0 */
0248     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
0249           SUNXI_FUNCTION(0x0, "gpio_in"),
0250           SUNXI_FUNCTION(0x1, "gpio_out"),
0251           SUNXI_FUNCTION(0x2, "lcd0"),      /* D18 */
0252           SUNXI_FUNCTION(0x3, "lvds0"),     /* VP0 */
0253           SUNXI_FUNCTION(0x4, "emac")),     /* ERXCK */
0254     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
0255           SUNXI_FUNCTION(0x0, "gpio_in"),
0256           SUNXI_FUNCTION(0x1, "gpio_out"),
0257           SUNXI_FUNCTION(0x2, "lcd0"),      /* D19 */
0258           SUNXI_FUNCTION(0x3, "lvds0"),     /* VN0 */
0259           SUNXI_FUNCTION(0x4, "emac")),     /* ERXCTL */
0260     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
0261           SUNXI_FUNCTION(0x0, "gpio_in"),
0262           SUNXI_FUNCTION(0x1, "gpio_out"),
0263           SUNXI_FUNCTION(0x2, "lcd0"),      /* D20 */
0264           SUNXI_FUNCTION(0x3, "lvds0"),     /* VP1 */
0265           SUNXI_FUNCTION(0x4, "emac")),     /* ENULL */
0266     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
0267           SUNXI_FUNCTION(0x0, "gpio_in"),
0268           SUNXI_FUNCTION(0x1, "gpio_out"),
0269           SUNXI_FUNCTION(0x2, "lcd0"),      /* D21 */
0270           SUNXI_FUNCTION(0x3, "lvds0"),     /* VN1 */
0271           SUNXI_FUNCTION(0x4, "emac"),      /* ETXD3 */
0272           SUNXI_FUNCTION(0x5, "ccir")),     /* D6 */
0273     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
0274           SUNXI_FUNCTION(0x0, "gpio_in"),
0275           SUNXI_FUNCTION(0x1, "gpio_out"),
0276           SUNXI_FUNCTION(0x2, "lcd0"),      /* D22 */
0277           SUNXI_FUNCTION(0x3, "lvds0"),     /* VP2 */
0278           SUNXI_FUNCTION(0x4, "emac"),      /* ETXD2 */
0279           SUNXI_FUNCTION(0x5, "ccir")),     /* D7 */
0280     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
0281           SUNXI_FUNCTION(0x0, "gpio_in"),
0282           SUNXI_FUNCTION(0x1, "gpio_out"),
0283           SUNXI_FUNCTION(0x2, "lcd0"),      /* D23 */
0284           SUNXI_FUNCTION(0x3, "lvds0"),     /* VN2 */
0285           SUNXI_FUNCTION(0x4, "emac")),     /* ETXD1 */
0286     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
0287           SUNXI_FUNCTION(0x0, "gpio_in"),
0288           SUNXI_FUNCTION(0x1, "gpio_out"),
0289           SUNXI_FUNCTION(0x2, "lcd0"),      /* CLK */
0290           SUNXI_FUNCTION(0x3, "lvds0"),     /* VPC */
0291           SUNXI_FUNCTION(0x4, "emac")),     /* ETXD0 */
0292     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
0293           SUNXI_FUNCTION(0x0, "gpio_in"),
0294           SUNXI_FUNCTION(0x1, "gpio_out"),
0295           SUNXI_FUNCTION(0x2, "lcd0"),      /* DE */
0296           SUNXI_FUNCTION(0x3, "lvds0"),     /* VNC */
0297           SUNXI_FUNCTION(0x4, "emac")),     /* ETXCK */
0298     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
0299           SUNXI_FUNCTION(0x0, "gpio_in"),
0300           SUNXI_FUNCTION(0x1, "gpio_out"),
0301           SUNXI_FUNCTION(0x2, "lcd0"),      /* HSYNC */
0302           SUNXI_FUNCTION(0x3, "lvds0"),     /* VP3 */
0303           SUNXI_FUNCTION(0x4, "emac")),     /* ETXCTL */
0304     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
0305           SUNXI_FUNCTION(0x0, "gpio_in"),
0306           SUNXI_FUNCTION(0x1, "gpio_out"),
0307           SUNXI_FUNCTION(0x2, "lcd0"),      /* VSYNC */
0308           SUNXI_FUNCTION(0x3, "lvds0"),     /* VN3 */
0309           SUNXI_FUNCTION(0x4, "emac")),     /* ECLKIN */
0310     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
0311           SUNXI_FUNCTION(0x0, "gpio_in"),
0312           SUNXI_FUNCTION(0x1, "gpio_out"),
0313           SUNXI_FUNCTION(0x2, "pwm"),       /* PWM0 */
0314           SUNXI_FUNCTION(0x4, "emac")),     /* EMDC */
0315     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
0316           SUNXI_FUNCTION(0x0, "gpio_in"),
0317           SUNXI_FUNCTION(0x1, "gpio_out"),
0318           SUNXI_FUNCTION(0x4, "emac")),     /* EMDIO */
0319     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 24),
0320           SUNXI_FUNCTION(0x0, "gpio_in"),
0321           SUNXI_FUNCTION(0x1, "gpio_out")),
0322     /* Hole */
0323     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
0324           SUNXI_FUNCTION(0x0, "gpio_in"),
0325           SUNXI_FUNCTION(0x1, "gpio_out"),
0326           SUNXI_FUNCTION(0x2, "csi"),       /* PCK */
0327           SUNXI_FUNCTION(0x4, "ts")),       /* CLK */
0328     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
0329           SUNXI_FUNCTION(0x0, "gpio_in"),
0330           SUNXI_FUNCTION(0x1, "gpio_out"),
0331           SUNXI_FUNCTION(0x2, "csi"),       /* CK */
0332           SUNXI_FUNCTION(0x4, "ts")),       /* ERR */
0333     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
0334           SUNXI_FUNCTION(0x0, "gpio_in"),
0335           SUNXI_FUNCTION(0x1, "gpio_out"),
0336           SUNXI_FUNCTION(0x2, "csi"),       /* HSYNC */
0337           SUNXI_FUNCTION(0x4, "ts")),       /* SYNC */
0338     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
0339           SUNXI_FUNCTION(0x0, "gpio_in"),
0340           SUNXI_FUNCTION(0x1, "gpio_out"),
0341           SUNXI_FUNCTION(0x2, "csi"),       /* VSYNC */
0342           SUNXI_FUNCTION(0x4, "ts")),       /* DVLD */
0343     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
0344           SUNXI_FUNCTION(0x0, "gpio_in"),
0345           SUNXI_FUNCTION(0x1, "gpio_out"),
0346           SUNXI_FUNCTION(0x2, "csi"),       /* D0 */
0347           SUNXI_FUNCTION(0x4, "ts")),       /* D0 */
0348     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
0349           SUNXI_FUNCTION(0x0, "gpio_in"),
0350           SUNXI_FUNCTION(0x1, "gpio_out"),
0351           SUNXI_FUNCTION(0x2, "csi"),       /* D1 */
0352           SUNXI_FUNCTION(0x4, "ts")),       /* D1 */
0353     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
0354           SUNXI_FUNCTION(0x0, "gpio_in"),
0355           SUNXI_FUNCTION(0x1, "gpio_out"),
0356           SUNXI_FUNCTION(0x2, "csi"),       /* D2 */
0357           SUNXI_FUNCTION(0x4, "ts")),       /* D2 */
0358     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
0359           SUNXI_FUNCTION(0x0, "gpio_in"),
0360           SUNXI_FUNCTION(0x1, "gpio_out"),
0361           SUNXI_FUNCTION(0x2, "csi"),       /* D3 */
0362           SUNXI_FUNCTION(0x4, "ts")),       /* D3 */
0363     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
0364           SUNXI_FUNCTION(0x0, "gpio_in"),
0365           SUNXI_FUNCTION(0x1, "gpio_out"),
0366           SUNXI_FUNCTION(0x2, "csi"),       /* D4 */
0367           SUNXI_FUNCTION(0x4, "ts")),       /* D4 */
0368     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
0369           SUNXI_FUNCTION(0x0, "gpio_in"),
0370           SUNXI_FUNCTION(0x1, "gpio_out"),
0371           SUNXI_FUNCTION(0x2, "csi"),       /* D5 */
0372           SUNXI_FUNCTION(0x4, "ts")),       /* D5 */
0373     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
0374           SUNXI_FUNCTION(0x0, "gpio_in"),
0375           SUNXI_FUNCTION(0x1, "gpio_out"),
0376           SUNXI_FUNCTION(0x2, "csi"),       /* D6 */
0377           SUNXI_FUNCTION(0x4, "ts")),       /* D6 */
0378     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
0379           SUNXI_FUNCTION(0x0, "gpio_in"),
0380           SUNXI_FUNCTION(0x1, "gpio_out"),
0381           SUNXI_FUNCTION(0x2, "csi"),       /* D7 */
0382           SUNXI_FUNCTION(0x4, "ts")),       /* D7 */
0383     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
0384           SUNXI_FUNCTION(0x0, "gpio_in"),
0385           SUNXI_FUNCTION(0x1, "gpio_out"),
0386           SUNXI_FUNCTION(0x2, "csi")),      /* SCK */
0387     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
0388           SUNXI_FUNCTION(0x0, "gpio_in"),
0389           SUNXI_FUNCTION(0x1, "gpio_out"),
0390           SUNXI_FUNCTION(0x2, "csi")),      /* SDA */
0391     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
0392           SUNXI_FUNCTION(0x0, "gpio_in"),
0393           SUNXI_FUNCTION(0x1, "gpio_out"),
0394           SUNXI_FUNCTION(0x2, "pll"),       /* LOCK_DBG */
0395           SUNXI_FUNCTION(0x3, "i2c2")),     /* SCK */
0396     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
0397           SUNXI_FUNCTION(0x0, "gpio_in"),
0398           SUNXI_FUNCTION(0x1, "gpio_out"),
0399           SUNXI_FUNCTION(0x3, "i2c2")),     /* SDA */
0400     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 16),
0401           SUNXI_FUNCTION(0x0, "gpio_in"),
0402           SUNXI_FUNCTION(0x1, "gpio_out")),
0403     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 17),
0404           SUNXI_FUNCTION(0x0, "gpio_in"),
0405           SUNXI_FUNCTION(0x1, "gpio_out")),
0406     /* Hole */
0407     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
0408           SUNXI_FUNCTION(0x0, "gpio_in"),
0409           SUNXI_FUNCTION(0x1, "gpio_out"),
0410           SUNXI_FUNCTION(0x2, "mmc0"),      /* D1 */
0411           SUNXI_FUNCTION(0x3, "jtag")),     /* MSI */
0412     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
0413           SUNXI_FUNCTION(0x0, "gpio_in"),
0414           SUNXI_FUNCTION(0x1, "gpio_out"),
0415           SUNXI_FUNCTION(0x2, "mmc0"),      /* D0 */
0416           SUNXI_FUNCTION(0x3, "jtag")),     /* DI1 */
0417     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
0418           SUNXI_FUNCTION(0x0, "gpio_in"),
0419           SUNXI_FUNCTION(0x1, "gpio_out"),
0420           SUNXI_FUNCTION(0x2, "mmc0"),      /* CLK */
0421           SUNXI_FUNCTION(0x3, "uart0")),    /* TX */
0422     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
0423           SUNXI_FUNCTION(0x0, "gpio_in"),
0424           SUNXI_FUNCTION(0x1, "gpio_out"),
0425           SUNXI_FUNCTION(0x2, "mmc0"),      /* CMD */
0426           SUNXI_FUNCTION(0x3, "jtag")),     /* DO1 */
0427     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
0428           SUNXI_FUNCTION(0x0, "gpio_in"),
0429           SUNXI_FUNCTION(0x1, "gpio_out"),
0430           SUNXI_FUNCTION(0x2, "mmc0"),      /* D3 */
0431           SUNXI_FUNCTION(0x3, "uart0")),    /* RX */
0432     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
0433           SUNXI_FUNCTION(0x0, "gpio_in"),
0434           SUNXI_FUNCTION(0x1, "gpio_out"),
0435           SUNXI_FUNCTION(0x2, "mmc0"),      /* D2 */
0436           SUNXI_FUNCTION(0x3, "jtag")),     /* CK1 */
0437     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
0438           SUNXI_FUNCTION(0x0, "gpio_in"),
0439           SUNXI_FUNCTION(0x1, "gpio_out")),
0440     /* Hole */
0441     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
0442           SUNXI_FUNCTION(0x0, "gpio_in"),
0443           SUNXI_FUNCTION(0x1, "gpio_out"),
0444           SUNXI_FUNCTION(0x2, "mmc1"),      /* CLK */
0445           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),  /* EINT0 */
0446     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
0447           SUNXI_FUNCTION(0x0, "gpio_in"),
0448           SUNXI_FUNCTION(0x1, "gpio_out"),
0449           SUNXI_FUNCTION(0x2, "mmc1"),      /* CMD */
0450           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),  /* EINT1 */
0451     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
0452           SUNXI_FUNCTION(0x0, "gpio_in"),
0453           SUNXI_FUNCTION(0x1, "gpio_out"),
0454           SUNXI_FUNCTION(0x2, "mmc1"),      /* D0 */
0455           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),  /* EINT2 */
0456     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
0457           SUNXI_FUNCTION(0x0, "gpio_in"),
0458           SUNXI_FUNCTION(0x1, "gpio_out"),
0459           SUNXI_FUNCTION(0x2, "mmc1"),      /* D1 */
0460           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),  /* EINT3 */
0461     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
0462           SUNXI_FUNCTION(0x0, "gpio_in"),
0463           SUNXI_FUNCTION(0x1, "gpio_out"),
0464           SUNXI_FUNCTION(0x2, "mmc1"),      /* D2 */
0465           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),  /* EINT4 */
0466     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
0467           SUNXI_FUNCTION(0x0, "gpio_in"),
0468           SUNXI_FUNCTION(0x1, "gpio_out"),
0469           SUNXI_FUNCTION(0x2, "mmc1"),      /* D3 */
0470           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),  /* EINT5 */
0471     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
0472           SUNXI_FUNCTION(0x0, "gpio_in"),
0473           SUNXI_FUNCTION(0x1, "gpio_out"),
0474           SUNXI_FUNCTION(0x2, "uart1"),     /* TX */
0475           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),  /* EINT6 */
0476     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
0477           SUNXI_FUNCTION(0x0, "gpio_in"),
0478           SUNXI_FUNCTION(0x1, "gpio_out"),
0479           SUNXI_FUNCTION(0x2, "uart1"),     /* RX */
0480           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),  /* EINT7 */
0481     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
0482           SUNXI_FUNCTION(0x0, "gpio_in"),
0483           SUNXI_FUNCTION(0x1, "gpio_out"),
0484           SUNXI_FUNCTION(0x2, "uart1"),     /* RTS */
0485           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),  /* EINT8 */
0486     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
0487           SUNXI_FUNCTION(0x0, "gpio_in"),
0488           SUNXI_FUNCTION(0x1, "gpio_out"),
0489           SUNXI_FUNCTION(0x2, "uart1"),     /* CTS */
0490           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),  /* EINT9 */
0491     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
0492           SUNXI_FUNCTION(0x0, "gpio_in"),
0493           SUNXI_FUNCTION(0x1, "gpio_out"),
0494           SUNXI_FUNCTION(0x2, "aif3"),      /* SYNC */
0495           SUNXI_FUNCTION(0x3, "i2s1"),      /* SYNC */
0496           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* EINT10 */
0497     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
0498           SUNXI_FUNCTION(0x0, "gpio_in"),
0499           SUNXI_FUNCTION(0x1, "gpio_out"),
0500           SUNXI_FUNCTION(0x2, "aif3"),      /* BCLK */
0501           SUNXI_FUNCTION(0x3, "i2s1"),      /* BCLK */
0502           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* EINT11 */
0503     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
0504           SUNXI_FUNCTION(0x0, "gpio_in"),
0505           SUNXI_FUNCTION(0x1, "gpio_out"),
0506           SUNXI_FUNCTION(0x2, "aif3"),      /* DOUT */
0507           SUNXI_FUNCTION(0x3, "i2s1"),      /* DOUT */
0508           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* EINT12 */
0509     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
0510           SUNXI_FUNCTION(0x0, "gpio_in"),
0511           SUNXI_FUNCTION(0x1, "gpio_out"),
0512           SUNXI_FUNCTION(0x2, "aif3"),      /* DIN */
0513           SUNXI_FUNCTION(0x3, "i2s1"),      /* DIN */
0514           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* EINT13 */
0515     /* Hole */
0516     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
0517           SUNXI_FUNCTION(0x0, "gpio_in"),
0518           SUNXI_FUNCTION(0x1, "gpio_out"),
0519           SUNXI_FUNCTION(0x2, "i2c0"),      /* SCK */
0520           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),  /* EINT0 */
0521     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
0522           SUNXI_FUNCTION(0x0, "gpio_in"),
0523           SUNXI_FUNCTION(0x1, "gpio_out"),
0524           SUNXI_FUNCTION(0x2, "i2c0"),      /* SDA */
0525           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),  /* EINT1 */
0526     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
0527           SUNXI_FUNCTION(0x0, "gpio_in"),
0528           SUNXI_FUNCTION(0x1, "gpio_out"),
0529           SUNXI_FUNCTION(0x2, "i2c1"),      /* SCK */
0530           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),  /* EINT2 */
0531     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
0532           SUNXI_FUNCTION(0x0, "gpio_in"),
0533           SUNXI_FUNCTION(0x1, "gpio_out"),
0534           SUNXI_FUNCTION(0x2, "i2c1"),      /* SDA */
0535           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),  /* EINT3 */
0536     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
0537           SUNXI_FUNCTION(0x0, "gpio_in"),
0538           SUNXI_FUNCTION(0x1, "gpio_out"),
0539           SUNXI_FUNCTION(0x2, "uart3"),     /* TX */
0540           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),  /* EINT4 */
0541     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
0542           SUNXI_FUNCTION(0x0, "gpio_in"),
0543           SUNXI_FUNCTION(0x1, "gpio_out"),
0544           SUNXI_FUNCTION(0x2, "uart3"),     /* RX */
0545           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),  /* EINT5 */
0546     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
0547           SUNXI_FUNCTION(0x0, "gpio_in"),
0548           SUNXI_FUNCTION(0x1, "gpio_out"),
0549           SUNXI_FUNCTION(0x2, "uart3"),     /* RTS */
0550           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),  /* EINT6 */
0551     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
0552           SUNXI_FUNCTION(0x0, "gpio_in"),
0553           SUNXI_FUNCTION(0x1, "gpio_out"),
0554           SUNXI_FUNCTION(0x2, "uart3"),     /* CTS */
0555           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),  /* EINT7 */
0556     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
0557           SUNXI_FUNCTION(0x0, "gpio_in"),
0558           SUNXI_FUNCTION(0x1, "gpio_out"),
0559           SUNXI_FUNCTION(0x2, "spdif"),     /* OUT */
0560           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),  /* EINT8 */
0561     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
0562           SUNXI_FUNCTION(0x0, "gpio_in"),
0563           SUNXI_FUNCTION(0x1, "gpio_out"),
0564           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),  /* EINT9 */
0565     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
0566           SUNXI_FUNCTION(0x0, "gpio_in"),
0567           SUNXI_FUNCTION(0x1, "gpio_out"),
0568           SUNXI_FUNCTION(0x2, "mic"),       /* CLK */
0569           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* EINT10 */
0570     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
0571           SUNXI_FUNCTION(0x0, "gpio_in"),
0572           SUNXI_FUNCTION(0x1, "gpio_out"),
0573           SUNXI_FUNCTION(0x2, "mic"),       /* DATA */
0574           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* EINT11 */
0575 };
0576 
0577 static const struct sunxi_pinctrl_desc a64_pinctrl_data = {
0578     .pins = a64_pins,
0579     .npins = ARRAY_SIZE(a64_pins),
0580     .irq_banks = 3,
0581 };
0582 
0583 static int a64_pinctrl_probe(struct platform_device *pdev)
0584 {
0585     return sunxi_pinctrl_init(pdev,
0586                   &a64_pinctrl_data);
0587 }
0588 
0589 static const struct of_device_id a64_pinctrl_match[] = {
0590     { .compatible = "allwinner,sun50i-a64-pinctrl", },
0591     {}
0592 };
0593 
0594 static struct platform_driver a64_pinctrl_driver = {
0595     .probe  = a64_pinctrl_probe,
0596     .driver = {
0597         .name       = "sun50i-a64-pinctrl",
0598         .of_match_table = a64_pinctrl_match,
0599     },
0600 };
0601 builtin_platform_driver(a64_pinctrl_driver);
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