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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
0004  *
0005  * Based on:
0006  * huangshuosheng <huangshuosheng@allwinnertech.com>
0007  */
0008 
0009 #include <linux/module.h>
0010 #include <linux/of.h>
0011 #include <linux/of_device.h>
0012 #include <linux/pinctrl/pinctrl.h>
0013 #include <linux/platform_device.h>
0014 
0015 #include "pinctrl-sunxi.h"
0016 
0017 static const struct sunxi_desc_pin a100_pins[] = {
0018     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
0019           SUNXI_FUNCTION(0x0, "gpio_in"),
0020           SUNXI_FUNCTION(0x1, "gpio_out"),
0021           SUNXI_FUNCTION(0x2, "uart2"),     /* TX */
0022           SUNXI_FUNCTION(0x3, "spi2"),      /* CS */
0023           SUNXI_FUNCTION(0x4, "jtag"),      /* MS */
0024           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),
0025     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1),
0026           SUNXI_FUNCTION(0x0, "gpio_in"),
0027           SUNXI_FUNCTION(0x1, "gpio_out"),
0028           SUNXI_FUNCTION(0x2, "uart2"),     /* RX */
0029           SUNXI_FUNCTION(0x3, "spi2"),      /* CLK */
0030           SUNXI_FUNCTION(0x4, "jtag"),      /* CK */
0031           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),
0032     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2),
0033           SUNXI_FUNCTION(0x0, "gpio_in"),
0034           SUNXI_FUNCTION(0x1, "gpio_out"),
0035           SUNXI_FUNCTION(0x2, "uart2"),     /* RTS */
0036           SUNXI_FUNCTION(0x3, "spi2"),      /* MOSI */
0037           SUNXI_FUNCTION(0x4, "jtag"),      /* DO */
0038           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),
0039     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3),
0040           SUNXI_FUNCTION(0x0, "gpio_in"),
0041           SUNXI_FUNCTION(0x1, "gpio_out"),
0042           SUNXI_FUNCTION(0x2, "uart2"),     /* CTS */
0043           SUNXI_FUNCTION(0x3, "spi2"),      /* MISO */
0044           SUNXI_FUNCTION(0x4, "jtag"),      /* DI */
0045           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),
0046     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4),
0047           SUNXI_FUNCTION(0x0, "gpio_in"),
0048           SUNXI_FUNCTION(0x1, "gpio_out"),
0049           SUNXI_FUNCTION(0x2, "i2c1"),      /* SCK */
0050           SUNXI_FUNCTION(0x3, "i2s0"),      /* MCLK */
0051           SUNXI_FUNCTION(0x4, "jtag_gpu"),  /* MS_GPU */
0052           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),
0053     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5),
0054           SUNXI_FUNCTION(0x0, "gpio_in"),
0055           SUNXI_FUNCTION(0x1, "gpio_out"),
0056           SUNXI_FUNCTION(0x2, "i2c1"),      /* SDA */
0057           SUNXI_FUNCTION(0x3, "i2s0"),      /* BCLK */
0058           SUNXI_FUNCTION(0x4, "jtag_gpu"),  /* CK_GPU */
0059           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),
0060     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6),
0061           SUNXI_FUNCTION(0x0, "gpio_in"),
0062           SUNXI_FUNCTION(0x1, "gpio_out"),
0063           SUNXI_FUNCTION(0x3, "i2s0"),      /* LRCK */
0064           SUNXI_FUNCTION(0x4, "jtag_gpu"),  /* DO_GPU */
0065           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),
0066     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7),
0067           SUNXI_FUNCTION(0x0, "gpio_in"),
0068           SUNXI_FUNCTION(0x1, "gpio_out"),
0069           SUNXI_FUNCTION(0x2, "spdif"),     /* DIN */
0070           SUNXI_FUNCTION(0x3, "i2s0_dout0"),    /* DOUT0 */
0071           SUNXI_FUNCTION(0x4, "i2s0_din1"), /* DIN1 */
0072           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),
0073     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8),
0074           SUNXI_FUNCTION(0x0, "gpio_in"),
0075           SUNXI_FUNCTION(0x1, "gpio_out"),
0076           SUNXI_FUNCTION(0x2, "spdif"),     /* DOUT */
0077           SUNXI_FUNCTION(0x3, "i2s0_din0"), /* DIN0 */
0078           SUNXI_FUNCTION(0x4, "i2s0_dout1"),    /* DOUT1 */
0079           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),
0080     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9),
0081           SUNXI_FUNCTION(0x0, "gpio_in"),
0082           SUNXI_FUNCTION(0x1, "gpio_out"),
0083           SUNXI_FUNCTION(0x2, "uart0"),     /* TX */
0084           SUNXI_FUNCTION(0x3, "i2c0"),      /* SCK */
0085           SUNXI_FUNCTION(0x4, "jtag_gpu"),  /* DI_GPU */
0086           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),
0087     SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10),
0088           SUNXI_FUNCTION(0x0, "gpio_in"),
0089           SUNXI_FUNCTION(0x1, "gpio_out"),
0090           SUNXI_FUNCTION(0x2, "uart0"),     /* RX */
0091           SUNXI_FUNCTION(0x3, "i2c0"),      /* SDA */
0092           SUNXI_FUNCTION(0x4, "pwm1"),
0093           SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)),
0094     /* HOLE */
0095     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
0096           SUNXI_FUNCTION(0x0, "gpio_in"),
0097           SUNXI_FUNCTION(0x1, "gpio_out"),
0098           SUNXI_FUNCTION(0x2, "nand0"),     /* WE */
0099           SUNXI_FUNCTION(0x3, "mmc2"),      /* DS */
0100           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)),
0101     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
0102           SUNXI_FUNCTION(0x0, "gpio_in"),
0103           SUNXI_FUNCTION(0x1, "gpio_out"),
0104           SUNXI_FUNCTION(0x2, "nand0"),     /* ALE */
0105           SUNXI_FUNCTION(0x3, "mmc2"),      /* RST */
0106           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)),
0107     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
0108           SUNXI_FUNCTION(0x0, "gpio_in"),
0109           SUNXI_FUNCTION(0x1, "gpio_out"),
0110           SUNXI_FUNCTION(0x2, "nand0"),     /* CLE */
0111           SUNXI_FUNCTION(0x4, "spi0"),      /* MOSI */
0112           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)),
0113     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
0114           SUNXI_FUNCTION(0x0, "gpio_in"),
0115           SUNXI_FUNCTION(0x1, "gpio_out"),
0116           SUNXI_FUNCTION(0x2, "nand0"),     /* CE1 */
0117           SUNXI_FUNCTION(0x4, "spi0"),      /* CS0 */
0118           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)),
0119     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
0120           SUNXI_FUNCTION(0x0, "gpio_in"),
0121           SUNXI_FUNCTION(0x1, "gpio_out"),
0122           SUNXI_FUNCTION(0x2, "nand0"),     /* CE0 */
0123           SUNXI_FUNCTION(0x4, "spi0"),      /* MISO */
0124           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)),
0125     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
0126           SUNXI_FUNCTION(0x0, "gpio_in"),
0127           SUNXI_FUNCTION(0x1, "gpio_out"),
0128           SUNXI_FUNCTION(0x2, "nand0"),     /* RE */
0129           SUNXI_FUNCTION(0x3, "mmc2"),      /* CLK */
0130           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)),
0131     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
0132           SUNXI_FUNCTION(0x0, "gpio_in"),
0133           SUNXI_FUNCTION(0x1, "gpio_out"),
0134           SUNXI_FUNCTION(0x2, "nand0"),     /* RB0 */
0135           SUNXI_FUNCTION(0x3, "mmc2"),      /* CMD */
0136           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)),
0137     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
0138           SUNXI_FUNCTION(0x0, "gpio_in"),
0139           SUNXI_FUNCTION(0x1, "gpio_out"),
0140           SUNXI_FUNCTION(0x2, "nand0"),     /* RB1 */
0141           SUNXI_FUNCTION(0x4, "spi0"),      /* CS1 */
0142           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)),
0143     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
0144           SUNXI_FUNCTION(0x0, "gpio_in"),
0145           SUNXI_FUNCTION(0x1, "gpio_out"),
0146           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ7 */
0147           SUNXI_FUNCTION(0x3, "mmc2"),      /* D3 */
0148           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)),
0149     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
0150           SUNXI_FUNCTION(0x0, "gpio_in"),
0151           SUNXI_FUNCTION(0x1, "gpio_out"),
0152           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ6 */
0153           SUNXI_FUNCTION(0x3, "mmc2"),      /* D4 */
0154           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)),
0155     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
0156           SUNXI_FUNCTION(0x0, "gpio_in"),
0157           SUNXI_FUNCTION(0x1, "gpio_out"),
0158           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ5 */
0159           SUNXI_FUNCTION(0x3, "mmc2"),      /* D0 */
0160           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)),
0161     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
0162           SUNXI_FUNCTION(0x0, "gpio_in"),
0163           SUNXI_FUNCTION(0x1, "gpio_out"),
0164           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ4 */
0165           SUNXI_FUNCTION(0x3, "mmc2"),      /* D5 */
0166           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)),
0167     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
0168           SUNXI_FUNCTION(0x0, "gpio_in"),
0169           SUNXI_FUNCTION(0x1, "gpio_out"),
0170           SUNXI_FUNCTION(0x2, "nand0"),     /* DQS */
0171           SUNXI_FUNCTION(0x4, "spi0"),      /* CLK */
0172           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)),
0173     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
0174           SUNXI_FUNCTION(0x0, "gpio_in"),
0175           SUNXI_FUNCTION(0x1, "gpio_out"),
0176           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ3 */
0177           SUNXI_FUNCTION(0x3, "mmc2"),      /* D1 */
0178           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)),
0179     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
0180           SUNXI_FUNCTION(0x0, "gpio_in"),
0181           SUNXI_FUNCTION(0x1, "gpio_out"),
0182           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ2 */
0183           SUNXI_FUNCTION(0x3, "mmc2"),      /* D6 */
0184           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)),
0185     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
0186           SUNXI_FUNCTION(0x0, "gpio_in"),
0187           SUNXI_FUNCTION(0x1, "gpio_out"),
0188           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ1 */
0189           SUNXI_FUNCTION(0x3, "mmc2"),      /* D2 */
0190           SUNXI_FUNCTION(0x4, "spi0"),      /* WP */
0191           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)),
0192     SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
0193           SUNXI_FUNCTION(0x0, "gpio_in"),
0194           SUNXI_FUNCTION(0x1, "gpio_out"),
0195           SUNXI_FUNCTION(0x2, "nand0"),     /* DQ0 */
0196           SUNXI_FUNCTION(0x3, "mmc2"),      /* D7 */
0197           SUNXI_FUNCTION(0x4, "spi0"),      /* HOLD */
0198           SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)),
0199     /* HOLE */
0200     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
0201           SUNXI_FUNCTION(0x0, "gpio_in"),
0202           SUNXI_FUNCTION(0x1, "gpio_out"),
0203           SUNXI_FUNCTION(0x2, "lcd0"),      /* D2 */
0204           SUNXI_FUNCTION(0x3, "lvds0"),     /* D0P */
0205           SUNXI_FUNCTION(0x4, "dsi0"),      /* DP0 */
0206           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)),
0207     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
0208           SUNXI_FUNCTION(0x0, "gpio_in"),
0209           SUNXI_FUNCTION(0x1, "gpio_out"),
0210           SUNXI_FUNCTION(0x2, "lcd0"),      /* D3 */
0211           SUNXI_FUNCTION(0x3, "lvds0"),     /* D0N */
0212           SUNXI_FUNCTION(0x4, "dsi0"),      /* DM0 */
0213           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)),
0214     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
0215           SUNXI_FUNCTION(0x0, "gpio_in"),
0216           SUNXI_FUNCTION(0x1, "gpio_out"),
0217           SUNXI_FUNCTION(0x2, "lcd0"),      /* D4 */
0218           SUNXI_FUNCTION(0x3, "lvds0"),     /* D1P */
0219           SUNXI_FUNCTION(0x4, "dsi0"),      /* DP1 */
0220           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)),
0221     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
0222           SUNXI_FUNCTION(0x0, "gpio_in"),
0223           SUNXI_FUNCTION(0x1, "gpio_out"),
0224           SUNXI_FUNCTION(0x2, "lcd0"),      /* D5 */
0225           SUNXI_FUNCTION(0x3, "lvds0"),     /* D1N */
0226           SUNXI_FUNCTION(0x4, "dsi0"),      /* DM1 */
0227           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)),
0228     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
0229           SUNXI_FUNCTION(0x0, "gpio_in"),
0230           SUNXI_FUNCTION(0x1, "gpio_out"),
0231           SUNXI_FUNCTION(0x2, "lcd0"),      /* D6 */
0232           SUNXI_FUNCTION(0x3, "lvds0"),     /* D2P */
0233           SUNXI_FUNCTION(0x4, "dsi0"),      /* CKP */
0234           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)),
0235     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
0236           SUNXI_FUNCTION(0x0, "gpio_in"),
0237           SUNXI_FUNCTION(0x1, "gpio_out"),
0238           SUNXI_FUNCTION(0x2, "lcd0"),      /* D7 */
0239           SUNXI_FUNCTION(0x3, "lvds0"),     /* D2N */
0240           SUNXI_FUNCTION(0x4, "dsi0"),      /* CKM */
0241           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)),
0242     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
0243           SUNXI_FUNCTION(0x0, "gpio_in"),
0244           SUNXI_FUNCTION(0x1, "gpio_out"),
0245           SUNXI_FUNCTION(0x2, "lcd0"),      /* D10 */
0246           SUNXI_FUNCTION(0x3, "lvds0"),     /* CKP */
0247           SUNXI_FUNCTION(0x4, "dsi0"),      /* DP2 */
0248           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)),
0249     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
0250           SUNXI_FUNCTION(0x0, "gpio_in"),
0251           SUNXI_FUNCTION(0x1, "gpio_out"),
0252           SUNXI_FUNCTION(0x2, "lcd0"),      /* D11 */
0253           SUNXI_FUNCTION(0x3, "lvds0"),     /* CKN */
0254           SUNXI_FUNCTION(0x4, "dsi0"),      /* DM2 */
0255           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)),
0256     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
0257           SUNXI_FUNCTION(0x0, "gpio_in"),
0258           SUNXI_FUNCTION(0x1, "gpio_out"),
0259           SUNXI_FUNCTION(0x2, "lcd0"),      /* D12 */
0260           SUNXI_FUNCTION(0x4, "dsi0"),      /* DP3 */
0261           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)),
0262     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
0263           SUNXI_FUNCTION(0x0, "gpio_in"),
0264           SUNXI_FUNCTION(0x1, "gpio_out"),
0265           SUNXI_FUNCTION(0x2, "lcd0"),      /* D13 */
0266           SUNXI_FUNCTION(0x4, "dsi0"),      /* DM3 */
0267           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)),
0268     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
0269           SUNXI_FUNCTION(0x0, "gpio_in"),
0270           SUNXI_FUNCTION(0x1, "gpio_out"),
0271           SUNXI_FUNCTION(0x2, "lcd0"),      /* D14 */
0272           SUNXI_FUNCTION(0x4, "spi1"),      /* CS */
0273           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)),
0274     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
0275           SUNXI_FUNCTION(0x0, "gpio_in"),
0276           SUNXI_FUNCTION(0x1, "gpio_out"),
0277           SUNXI_FUNCTION(0x2, "lcd0"),      /* D15 */
0278           SUNXI_FUNCTION(0x4, "spi1"),      /* CLK */
0279           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)),
0280     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
0281           SUNXI_FUNCTION(0x0, "gpio_in"),
0282           SUNXI_FUNCTION(0x1, "gpio_out"),
0283           SUNXI_FUNCTION(0x2, "lcd0"),      /* D18 */
0284           SUNXI_FUNCTION(0x4, "spi1"),      /* MOSI */
0285           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)),
0286     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
0287           SUNXI_FUNCTION(0x0, "gpio_in"),
0288           SUNXI_FUNCTION(0x1, "gpio_out"),
0289           SUNXI_FUNCTION(0x2, "lcd0"),      /* D19 */
0290           SUNXI_FUNCTION(0x4, "spi1"),      /* MISO */
0291           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)),
0292     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
0293           SUNXI_FUNCTION(0x0, "gpio_in"),
0294           SUNXI_FUNCTION(0x1, "gpio_out"),
0295           SUNXI_FUNCTION(0x2, "lcd0"),      /* D20 */
0296           SUNXI_FUNCTION(0x4, "uart3"),     /* TX */
0297           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)),
0298     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
0299           SUNXI_FUNCTION(0x0, "gpio_in"),
0300           SUNXI_FUNCTION(0x1, "gpio_out"),
0301           SUNXI_FUNCTION(0x2, "lcd0"),      /* D21 */
0302           SUNXI_FUNCTION(0x4, "uart3"),     /* RX */
0303           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)),
0304     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
0305           SUNXI_FUNCTION(0x0, "gpio_in"),
0306           SUNXI_FUNCTION(0x1, "gpio_out"),
0307           SUNXI_FUNCTION(0x2, "lcd0"),      /* D22 */
0308           SUNXI_FUNCTION(0x4, "uart3"),     /* RTS */
0309           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)),
0310     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
0311           SUNXI_FUNCTION(0x0, "gpio_in"),
0312           SUNXI_FUNCTION(0x1, "gpio_out"),
0313           SUNXI_FUNCTION(0x2, "lcd0"),      /* D23 */
0314           SUNXI_FUNCTION(0x4, "uart3"),     /* CTS */
0315           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)),
0316     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18),
0317           SUNXI_FUNCTION(0x0, "gpio_in"),
0318           SUNXI_FUNCTION(0x1, "gpio_out"),
0319           SUNXI_FUNCTION(0x2, "lcd0"),      /* CLK */
0320           SUNXI_FUNCTION(0x4, "uart4"),     /* TX */
0321           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)),
0322     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19),
0323           SUNXI_FUNCTION(0x0, "gpio_in"),
0324           SUNXI_FUNCTION(0x1, "gpio_out"),
0325           SUNXI_FUNCTION(0x2, "lcd0"),      /* DE */
0326           SUNXI_FUNCTION(0x4, "uart4"),     /* RX */
0327           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)),
0328     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20),
0329           SUNXI_FUNCTION(0x0, "gpio_in"),
0330           SUNXI_FUNCTION(0x1, "gpio_out"),
0331           SUNXI_FUNCTION(0x2, "lcd0"),      /* HSYNC */
0332           SUNXI_FUNCTION(0x3, "pwm2"),
0333           SUNXI_FUNCTION(0x4, "uart4"),     /* RTS */
0334           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 20)),
0335     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21),
0336           SUNXI_FUNCTION(0x0, "gpio_in"),
0337           SUNXI_FUNCTION(0x1, "gpio_out"),
0338           SUNXI_FUNCTION(0x2, "lcd0"),      /* VSYNC */
0339           SUNXI_FUNCTION(0x3, "pwm3"),
0340           SUNXI_FUNCTION(0x4, "uart4"),     /* CTS */
0341           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 21)),
0342     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22),
0343           SUNXI_FUNCTION(0x0, "gpio_in"),
0344           SUNXI_FUNCTION(0x1, "gpio_out"),
0345           SUNXI_FUNCTION(0x2, "pwm1"),
0346           SUNXI_FUNCTION(0x4, "i2c0"),      /* SCK */
0347           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 22)),
0348     SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23),
0349           SUNXI_FUNCTION(0x0, "gpio_in"),
0350           SUNXI_FUNCTION(0x1, "gpio_out"),
0351           SUNXI_FUNCTION(0x2, "pwm0"),
0352           SUNXI_FUNCTION(0x4, "i2c0"),      /* SDA */
0353           SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 23)),
0354     /* HOLE */
0355     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
0356           SUNXI_FUNCTION(0x0, "gpio_in"),
0357           SUNXI_FUNCTION(0x1, "gpio_out"),
0358           SUNXI_FUNCTION(0x2, "csi"),       /* MCLK */
0359           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)),
0360     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
0361           SUNXI_FUNCTION(0x0, "gpio_in"),
0362           SUNXI_FUNCTION(0x1, "gpio_out"),
0363           SUNXI_FUNCTION(0x2, "i2c2"),      /* SCK */
0364           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)),
0365     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
0366           SUNXI_FUNCTION(0x0, "gpio_in"),
0367           SUNXI_FUNCTION(0x1, "gpio_out"),
0368           SUNXI_FUNCTION(0x2, "i2c2"),      /* SDA */
0369           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)),
0370     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
0371           SUNXI_FUNCTION(0x0, "gpio_in"),
0372           SUNXI_FUNCTION(0x1, "gpio_out"),
0373           SUNXI_FUNCTION(0x2, "i2c3"),      /* SCK */
0374           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)),
0375     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
0376           SUNXI_FUNCTION(0x0, "gpio_in"),
0377           SUNXI_FUNCTION(0x1, "gpio_out"),
0378           SUNXI_FUNCTION(0x2, "i2c3"),      /* SDA */
0379           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)),
0380     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
0381           SUNXI_FUNCTION(0x0, "gpio_in"),
0382           SUNXI_FUNCTION(0x1, "gpio_out"),
0383           SUNXI_FUNCTION(0x2, "csi"),       /* MCLK */
0384           SUNXI_FUNCTION(0x3, "pll"),       /* LOCK_DBG */
0385           SUNXI_FUNCTION(0x4, "i2s2"),      /* MCLK */
0386           SUNXI_FUNCTION(0x5, "ledc"),      /* LEDC */
0387           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)),
0388     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
0389           SUNXI_FUNCTION(0x0, "gpio_in"),
0390           SUNXI_FUNCTION(0x1, "gpio_out"),
0391           SUNXI_FUNCTION(0x3, "bist0"),     /* RESULT0 */
0392           SUNXI_FUNCTION(0x4, "i2s2"),      /* BCLK */
0393           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)),
0394     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
0395           SUNXI_FUNCTION(0x0, "gpio_in"),
0396           SUNXI_FUNCTION(0x1, "gpio_out"),
0397           SUNXI_FUNCTION(0x2, "csi"),       /* SM_VS */
0398           SUNXI_FUNCTION(0x3, "bist0"),     /* RESULT1 */
0399           SUNXI_FUNCTION(0x4, "i2s2"),      /* LRCK */
0400           SUNXI_FUNCTION(0x5, "tcon0"),     /* TRIG */
0401           SUNXI_FUNCTION_IRQ_BANK(0x6, 3,   7)),
0402     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
0403           SUNXI_FUNCTION(0x0, "gpio_in"),
0404           SUNXI_FUNCTION(0x1, "gpio_out"),
0405           SUNXI_FUNCTION(0x3, "bist0"),     /* RESULT2 */
0406           SUNXI_FUNCTION(0x4, "i2s2"),      /* DOUT0 */
0407           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)),
0408     SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
0409           SUNXI_FUNCTION(0x0, "gpio_in"),
0410           SUNXI_FUNCTION(0x1, "gpio_out"),
0411           SUNXI_FUNCTION(0x3, "bist0"),     /* RESULT3 */
0412           SUNXI_FUNCTION(0x4, "i2s2"),      /* DIN0 */
0413           SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)),
0414     /* HOLE */
0415     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
0416           SUNXI_FUNCTION(0x0, "gpio_in"),
0417           SUNXI_FUNCTION(0x1, "gpio_out"),
0418           SUNXI_FUNCTION(0x2, "mmc0"),      /* D1 */
0419           SUNXI_FUNCTION(0x3, "jtag"),      /* MS1 */
0420           SUNXI_FUNCTION(0x4, "jtag_gpu"),  /* MS_GPU */
0421           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 0)),
0422     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
0423           SUNXI_FUNCTION(0x0, "gpio_in"),
0424           SUNXI_FUNCTION(0x1, "gpio_out"),
0425           SUNXI_FUNCTION(0x2, "mmc0"),      /* D0 */
0426           SUNXI_FUNCTION(0x3, "jtag"),      /* DI1 */
0427           SUNXI_FUNCTION(0x4, "jtag_gpu"),  /* DI_GPU */
0428           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 1)),
0429     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
0430           SUNXI_FUNCTION(0x0, "gpio_in"),
0431           SUNXI_FUNCTION(0x1, "gpio_out"),
0432           SUNXI_FUNCTION(0x2, "mmc0"),      /* CLK */
0433           SUNXI_FUNCTION(0x3, "uart0"),     /* TX */
0434           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 2)),
0435     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
0436           SUNXI_FUNCTION(0x0, "gpio_in"),
0437           SUNXI_FUNCTION(0x1, "gpio_out"),
0438           SUNXI_FUNCTION(0x2, "mmc0"),      /* CMD */
0439           SUNXI_FUNCTION(0x3, "jtag"),      /* DO */
0440           SUNXI_FUNCTION(0x4, "jtag_gpu"),  /* DO_GPU */
0441           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 3)),
0442     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
0443           SUNXI_FUNCTION(0x0, "gpio_in"),
0444           SUNXI_FUNCTION(0x1, "gpio_out"),
0445           SUNXI_FUNCTION(0x2, "mmc0"),      /* D3 */
0446           SUNXI_FUNCTION(0x3, "uart0"),     /* RX */
0447           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4)),
0448     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
0449           SUNXI_FUNCTION(0x0, "gpio_in"),
0450           SUNXI_FUNCTION(0x1, "gpio_out"),
0451           SUNXI_FUNCTION(0x2, "mmc0"),      /* D2 */
0452           SUNXI_FUNCTION(0x3, "jtag"),      /* CK */
0453           SUNXI_FUNCTION(0x4, "jtag_gpu"),  /* CK_GPU */
0454           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 5)),
0455     SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
0456           SUNXI_FUNCTION(0x0, "gpio_in"),
0457           SUNXI_FUNCTION(0x1, "gpio_out"),
0458           SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 6)),
0459     /* HOLE */
0460     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
0461           SUNXI_FUNCTION(0x0, "gpio_in"),
0462           SUNXI_FUNCTION(0x1, "gpio_out"),
0463           SUNXI_FUNCTION(0x2, "mmc1"),      /* CLK */
0464           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 0)),
0465     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
0466           SUNXI_FUNCTION(0x0, "gpio_in"),
0467           SUNXI_FUNCTION(0x1, "gpio_out"),
0468           SUNXI_FUNCTION(0x2, "mmc1"),      /* CMD */
0469           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 1)),
0470     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
0471           SUNXI_FUNCTION(0x0, "gpio_in"),
0472           SUNXI_FUNCTION(0x1, "gpio_out"),
0473           SUNXI_FUNCTION(0x2, "mmc1"),      /* D0 */
0474           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 2)),
0475     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
0476           SUNXI_FUNCTION(0x0, "gpio_in"),
0477           SUNXI_FUNCTION(0x1, "gpio_out"),
0478           SUNXI_FUNCTION(0x2, "mmc1"),      /* D1 */
0479           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3)),
0480     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
0481           SUNXI_FUNCTION(0x0, "gpio_in"),
0482           SUNXI_FUNCTION(0x1, "gpio_out"),
0483           SUNXI_FUNCTION(0x2, "mmc1"),      /* D2 */
0484           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4)),
0485     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
0486           SUNXI_FUNCTION(0x0, "gpio_in"),
0487           SUNXI_FUNCTION(0x1, "gpio_out"),
0488           SUNXI_FUNCTION(0x2, "mmc1"),      /* D3 */
0489           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5)),
0490     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
0491           SUNXI_FUNCTION(0x0, "gpio_in"),
0492           SUNXI_FUNCTION(0x1, "gpio_out"),
0493           SUNXI_FUNCTION(0x2, "uart1"),     /* TX */
0494           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 6)),
0495     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
0496           SUNXI_FUNCTION(0x0, "gpio_in"),
0497           SUNXI_FUNCTION(0x1, "gpio_out"),
0498           SUNXI_FUNCTION(0x2, "uart1"),     /* RX */
0499           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 7)),
0500     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
0501           SUNXI_FUNCTION(0x0, "gpio_in"),
0502           SUNXI_FUNCTION(0x1, "gpio_out"),
0503           SUNXI_FUNCTION(0x2, "uart1"),     /* RTS */
0504           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 8)),
0505     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
0506           SUNXI_FUNCTION(0x0, "gpio_in"),
0507           SUNXI_FUNCTION(0x1, "gpio_out"),
0508           SUNXI_FUNCTION(0x2, "uart1"),     /* CTS */
0509           SUNXI_FUNCTION(0x3, "i2s1"),      /* MCLK */
0510           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 9)),
0511     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
0512           SUNXI_FUNCTION(0x0, "gpio_in"),
0513           SUNXI_FUNCTION(0x1, "gpio_out"),
0514           SUNXI_FUNCTION(0x3, "i2s1"),      /* BCLK */
0515           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 10)),
0516     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
0517           SUNXI_FUNCTION(0x0, "gpio_in"),
0518           SUNXI_FUNCTION(0x1, "gpio_out"),
0519           SUNXI_FUNCTION(0x3, "i2s1"),      /* LRCK */
0520           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 11)),
0521     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
0522           SUNXI_FUNCTION(0x0, "gpio_in"),
0523           SUNXI_FUNCTION(0x1, "gpio_out"),
0524           SUNXI_FUNCTION(0x3, "i2s1_dout0"),    /* DOUT0 */
0525           SUNXI_FUNCTION(0x4, "i2s1_din1"), /* DIN1 */
0526           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 12)),
0527     SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
0528           SUNXI_FUNCTION(0x0, "gpio_in"),
0529           SUNXI_FUNCTION(0x1, "gpio_out"),
0530           SUNXI_FUNCTION(0x3, "i2s1_din0"), /* DIN0 */
0531           SUNXI_FUNCTION(0x4, "i2s1_dout1"),    /* DOUT1 */
0532           SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 13)),
0533     /* HOLE */
0534     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0),
0535           SUNXI_FUNCTION(0x0, "gpio_in"),
0536           SUNXI_FUNCTION(0x1, "gpio_out"),
0537           SUNXI_FUNCTION(0x2, "i2c0"),      /* SCK */
0538           SUNXI_FUNCTION(0x5, "emac0"),     /* RXD1 */
0539           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)),
0540     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1),
0541           SUNXI_FUNCTION(0x0, "gpio_in"),
0542           SUNXI_FUNCTION(0x1, "gpio_out"),
0543           SUNXI_FUNCTION(0x2, "i2c0"),      /* SDA */
0544           SUNXI_FUNCTION(0x5, "emac0"),     /* RXD0 */
0545           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)),
0546     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2),
0547           SUNXI_FUNCTION(0x0, "gpio_in"),
0548           SUNXI_FUNCTION(0x1, "gpio_out"),
0549           SUNXI_FUNCTION(0x2, "i2c1"),      /* SCK */
0550           SUNXI_FUNCTION(0x5, "emac0"),     /* RXCTL */
0551           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)),
0552     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3),
0553           SUNXI_FUNCTION(0x0, "gpio_in"),
0554           SUNXI_FUNCTION(0x1, "gpio_out"),
0555           SUNXI_FUNCTION(0x2, "i2c1"),      /* SDA */
0556           SUNXI_FUNCTION(0x3, "cir0"),      /* OUT */
0557           SUNXI_FUNCTION(0x5, "emac0"),     /* CLKIN */
0558           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)),
0559     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4),
0560           SUNXI_FUNCTION(0x0, "gpio_in"),
0561           SUNXI_FUNCTION(0x1, "gpio_out"),
0562           SUNXI_FUNCTION(0x2, "uart3"),     /* TX */
0563           SUNXI_FUNCTION(0x3, "spi1"),      /* CS */
0564           SUNXI_FUNCTION(0x5, "emac0"),     /* TXD1 */
0565           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)),
0566     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5),
0567           SUNXI_FUNCTION(0x0, "gpio_in"),
0568           SUNXI_FUNCTION(0x1, "gpio_out"),
0569           SUNXI_FUNCTION(0x2, "uart3"),     /* RX */
0570           SUNXI_FUNCTION(0x3, "spi1"),      /* CLK */
0571           SUNXI_FUNCTION(0x4, "ledc"),
0572           SUNXI_FUNCTION(0x5, "emac0"),     /* TXD0 */
0573           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)),
0574     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6),
0575           SUNXI_FUNCTION(0x0, "gpio_in"),
0576           SUNXI_FUNCTION(0x1, "gpio_out"),
0577           SUNXI_FUNCTION(0x2, "uart3"),     /* RTS */
0578           SUNXI_FUNCTION(0x3, "spi1"),      /* MOSI */
0579           SUNXI_FUNCTION(0x5, "emac0"),     /* TXCK */
0580           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)),
0581     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7),
0582           SUNXI_FUNCTION(0x0, "gpio_in"),
0583           SUNXI_FUNCTION(0x1, "gpio_out"),
0584           SUNXI_FUNCTION(0x2, "uart3"),     /* CTS */
0585           SUNXI_FUNCTION(0x3, "spi1"),      /* MISO */
0586           SUNXI_FUNCTION(0x4, "spdif"),     /* OUT */
0587           SUNXI_FUNCTION(0x5, "emac0"),     /* TXCTL */
0588           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)),
0589     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8),
0590           SUNXI_FUNCTION(0x0, "gpio_in"),
0591           SUNXI_FUNCTION(0x1, "gpio_out"),
0592           SUNXI_FUNCTION(0x2, "dmic"),      /* CLK */
0593           SUNXI_FUNCTION(0x3, "spi2"),      /* CS */
0594           SUNXI_FUNCTION(0x4, "i2s2"),      /* MCLK */
0595           SUNXI_FUNCTION(0x5, "i2s2_din2"), /* DIN2 */
0596           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 8)),
0597     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9),
0598           SUNXI_FUNCTION(0x0, "gpio_in"),
0599           SUNXI_FUNCTION(0x1, "gpio_out"),
0600           SUNXI_FUNCTION(0x2, "dmic"),      /* DATA0 */
0601           SUNXI_FUNCTION(0x3, "spi2"),      /* CLK */
0602           SUNXI_FUNCTION(0x4, "i2s2"),      /* BCLK */
0603           SUNXI_FUNCTION(0x5, "emac0"),     /* MDC */
0604           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)),
0605     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10),
0606           SUNXI_FUNCTION(0x0, "gpio_in"),
0607           SUNXI_FUNCTION(0x1, "gpio_out"),
0608           SUNXI_FUNCTION(0x2, "dmic"),      /* DATA1 */
0609           SUNXI_FUNCTION(0x3, "spi2"),      /* MOSI */
0610           SUNXI_FUNCTION(0x4, "i2s2"),      /* LRCK */
0611           SUNXI_FUNCTION(0x5, "emac0"),     /* MDIO */
0612           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)),
0613     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11),
0614           SUNXI_FUNCTION(0x0, "gpio_in"),
0615           SUNXI_FUNCTION(0x1, "gpio_out"),
0616           SUNXI_FUNCTION(0x2, "dmic"),      /* DATA2 */
0617           SUNXI_FUNCTION(0x3, "spi2"),      /* MISO */
0618           SUNXI_FUNCTION(0x4, "i2s2_dout0"),    /* DOUT0 */
0619           SUNXI_FUNCTION(0x5, "i2s2_din1"), /* DIN1 */
0620           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 11)),
0621     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12),
0622           SUNXI_FUNCTION(0x0, "gpio_in"),
0623           SUNXI_FUNCTION(0x1, "gpio_out"),
0624           SUNXI_FUNCTION(0x2, "dmic"),      /* DATA3 */
0625           SUNXI_FUNCTION(0x3, "i2c3"),      /* SCK */
0626           SUNXI_FUNCTION(0x4, "i2s2_din0"), /* DIN0 */
0627           SUNXI_FUNCTION(0x5, "i2s2_dout1"),    /* DOUT1 */
0628           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 12)),
0629     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13),
0630           SUNXI_FUNCTION(0x0, "gpio_in"),
0631           SUNXI_FUNCTION(0x1, "gpio_out"),
0632           SUNXI_FUNCTION(0x3, "i2c3"),      /* SCK */
0633           SUNXI_FUNCTION(0x4, "i2s3"),      /* MCLK */
0634           SUNXI_FUNCTION(0x5, "emac0"),     /* EPHY */
0635           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)),
0636     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14),
0637           SUNXI_FUNCTION(0x0, "gpio_in"),
0638           SUNXI_FUNCTION(0x1, "gpio_out"),
0639           SUNXI_FUNCTION(0x4, "i2s3"),      /* BCLK */
0640           SUNXI_FUNCTION(0x5, "emac0"),     /* RXD3 */
0641           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)),
0642     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15),
0643           SUNXI_FUNCTION(0x0, "gpio_in"),
0644           SUNXI_FUNCTION(0x1, "gpio_out"),
0645           SUNXI_FUNCTION(0x4, "i2s3"),      /* LRCK */
0646           SUNXI_FUNCTION(0x5, "emac0"),     /* RXD2 */
0647           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)),
0648     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16),
0649           SUNXI_FUNCTION(0x0, "gpio_in"),
0650           SUNXI_FUNCTION(0x1, "gpio_out"),
0651           SUNXI_FUNCTION(0x3, "i2s3_dout0"),    /* DOUT0 */
0652           SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */
0653           SUNXI_FUNCTION(0x5, "emac0"),     /* RXCK */
0654           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)),
0655     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17),
0656           SUNXI_FUNCTION(0x0, "gpio_in"),
0657           SUNXI_FUNCTION(0x1, "gpio_out"),
0658           SUNXI_FUNCTION(0x3, "i2s3_dout1"),    /* DOUT1 */
0659           SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */
0660           SUNXI_FUNCTION(0x5, "emac0"),     /* TXD3 */
0661           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)),
0662     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18),
0663           SUNXI_FUNCTION(0x0, "gpio_in"),
0664           SUNXI_FUNCTION(0x1, "gpio_out"),
0665           SUNXI_FUNCTION(0x2, "cir0"),      /* OUT */
0666           SUNXI_FUNCTION(0x3, "i2s3_dout2"),    /* DOUT2 */
0667           SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */
0668           SUNXI_FUNCTION(0x5, "emac0"),     /* TXD2 */
0669           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)),
0670     SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19),
0671           SUNXI_FUNCTION(0x0, "gpio_in"),
0672           SUNXI_FUNCTION(0x1, "gpio_out"),
0673           SUNXI_FUNCTION(0x2, "cir0"),      /* IN */
0674           SUNXI_FUNCTION(0x3, "i2s3_dout3"),    /* DOUT3 */
0675           SUNXI_FUNCTION(0x4, "i2s3_din3"), /* DIN3 */
0676           SUNXI_FUNCTION(0x5, "ledc"),
0677           SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 19)),
0678 };
0679 
0680 static const unsigned int a100_irq_bank_map[] = { 1, 2, 3, 4, 5, 6, 7};
0681 
0682 static const struct sunxi_pinctrl_desc a100_pinctrl_data = {
0683     .pins = a100_pins,
0684     .npins = ARRAY_SIZE(a100_pins),
0685     .irq_banks = 7,
0686     .irq_bank_map = a100_irq_bank_map,
0687     .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_CTL,
0688 };
0689 
0690 static int a100_pinctrl_probe(struct platform_device *pdev)
0691 {
0692     return sunxi_pinctrl_init(pdev, &a100_pinctrl_data);
0693 }
0694 
0695 static const struct of_device_id a100_pinctrl_match[] = {
0696     { .compatible = "allwinner,sun50i-a100-pinctrl", },
0697     {}
0698 };
0699 MODULE_DEVICE_TABLE(of, a100_pinctrl_match);
0700 
0701 static struct platform_driver a100_pinctrl_driver = {
0702     .probe  = a100_pinctrl_probe,
0703     .driver = {
0704         .name       = "sun50i-a100-pinctrl",
0705         .of_match_table = a100_pinctrl_match,
0706     },
0707 };
0708 module_platform_driver(a100_pinctrl_driver);
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