pinctrl/sunplus/sppctl_sp7021.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * SP7021 Pin Controller Driver.
0004  * Copyright (C) Sunplus Tech / Tibbo Tech.
0005  */
0006
0007 #include <linux/gpio/driver.h>
0008 #include <linux/kernel.h>
0009 #include <linux/pinctrl/pinctrl.h>
0010
0011 #include "sppctl.h"
0012
0013 #define D_PIS(x, y) "P" __stringify(x) "_0" __stringify(y)
0014 #define D(x, y)     ((x) * 8 + (y))
0015 #define P(x, y)     PINCTRL_PIN(D(x, y), D_PIS(x, y))
0016
0017 const char * const sppctl_gpio_list_s[] = {
0018     D_PIS(0, 0),  D_PIS(0, 1),  D_PIS(0, 2),  D_PIS(0, 3),
0019     D_PIS(0, 4),  D_PIS(0, 5),  D_PIS(0, 6),  D_PIS(0, 7),
0020     D_PIS(1, 0),  D_PIS(1, 1),  D_PIS(1, 2),  D_PIS(1, 3),
0021     D_PIS(1, 4),  D_PIS(1, 5),  D_PIS(1, 6),  D_PIS(1, 7),
0022     D_PIS(2, 0),  D_PIS(2, 1),  D_PIS(2, 2),  D_PIS(2, 3),
0023     D_PIS(2, 4),  D_PIS(2, 5),  D_PIS(2, 6),  D_PIS(2, 7),
0024     D_PIS(3, 0),  D_PIS(3, 1),  D_PIS(3, 2),  D_PIS(3, 3),
0025     D_PIS(3, 4),  D_PIS(3, 5),  D_PIS(3, 6),  D_PIS(3, 7),
0026     D_PIS(4, 0),  D_PIS(4, 1),  D_PIS(4, 2),  D_PIS(4, 3),
0027     D_PIS(4, 4),  D_PIS(4, 5),  D_PIS(4, 6),  D_PIS(4, 7),
0028     D_PIS(5, 0),  D_PIS(5, 1),  D_PIS(5, 2),  D_PIS(5, 3),
0029     D_PIS(5, 4),  D_PIS(5, 5),  D_PIS(5, 6),  D_PIS(5, 7),
0030     D_PIS(6, 0),  D_PIS(6, 1),  D_PIS(6, 2),  D_PIS(6, 3),
0031     D_PIS(6, 4),  D_PIS(6, 5),  D_PIS(6, 6),  D_PIS(6, 7),
0032     D_PIS(7, 0),  D_PIS(7, 1),  D_PIS(7, 2),  D_PIS(7, 3),
0033     D_PIS(7, 4),  D_PIS(7, 5),  D_PIS(7, 6),  D_PIS(7, 7),
0034     D_PIS(8, 0),  D_PIS(8, 1),  D_PIS(8, 2),  D_PIS(8, 3),
0035     D_PIS(8, 4),  D_PIS(8, 5),  D_PIS(8, 6),  D_PIS(8, 7),
0036     D_PIS(9, 0),  D_PIS(9, 1),  D_PIS(9, 2),  D_PIS(9, 3),
0037     D_PIS(9, 4),  D_PIS(9, 5),  D_PIS(9, 6),  D_PIS(9, 7),
0038     D_PIS(10, 0), D_PIS(10, 1), D_PIS(10, 2), D_PIS(10, 3),
0039     D_PIS(10, 4), D_PIS(10, 5), D_PIS(10, 6), D_PIS(10, 7),
0040     D_PIS(11, 0), D_PIS(11, 1), D_PIS(11, 2), D_PIS(11, 3),
0041     D_PIS(11, 4), D_PIS(11, 5), D_PIS(11, 6), D_PIS(11, 7),
0042     D_PIS(12, 0), D_PIS(12, 1), D_PIS(12, 2),
0043 };
0044
0045 const size_t sppctl_gpio_list_sz = ARRAY_SIZE(sppctl_gpio_list_s);
0046
0047 const unsigned int sppctl_pins_gpio[] = {
0048     D(0, 0), D(0, 1), D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7),
0049     D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7),
0050     D(2, 0), D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7),
0051     D(3, 0), D(3, 1), D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7),
0052     D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7),
0053     D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7),
0054     D(6, 0), D(6, 1), D(6, 2), D(6, 3), D(6, 4), D(6, 5), D(6, 6), D(6, 7),
0055     D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7),
0056     D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), D(8, 7),
0057     D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), D(9, 6), D(9, 7),
0058     D(10, 0), D(10, 1), D(10, 2), D(10, 3), D(10, 4), D(10, 5), D(10, 6), D(10, 7),
0059     D(11, 0), D(11, 1), D(11, 2), D(11, 3), D(11, 4), D(11, 5), D(11, 6), D(11, 7),
0060     D(12, 0), D(12, 1), D(12, 2),
0061 };
0062
0063 const struct pinctrl_pin_desc sppctl_pins_all[] = {
0064     /* gpio and iop only */
0065     P(0, 0), P(0, 1), P(0, 2), P(0, 3), P(0, 4), P(0, 5), P(0, 6), P(0, 7),
0066     /* gpio, iop, muxable */
0067     P(1, 0), P(1, 1), P(1, 2), P(1, 3), P(1, 4), P(1, 5), P(1, 6), P(1, 7),
0068     P(2, 0), P(2, 1), P(2, 2), P(2, 3), P(2, 4), P(2, 5), P(2, 6), P(2, 7),
0069     P(3, 0), P(3, 1), P(3, 2), P(3, 3), P(3, 4), P(3, 5), P(3, 6), P(3, 7),
0070     P(4, 0), P(4, 1), P(4, 2), P(4, 3), P(4, 4), P(4, 5), P(4, 6), P(4, 7),
0071     P(5, 0), P(5, 1), P(5, 2), P(5, 3), P(5, 4), P(5, 5), P(5, 6), P(5, 7),
0072     P(6, 0), P(6, 1), P(6, 2), P(6, 3), P(6, 4), P(6, 5), P(6, 6), P(6, 7),
0073     P(7, 0), P(7, 1), P(7, 2), P(7, 3), P(7, 4), P(7, 5), P(7, 6), P(7, 7),
0074     P(8, 0), P(8, 1), P(8, 2), P(8, 3), P(8, 4), P(8, 5), P(8, 6), P(8, 7),
0075     /* gpio and iop only */
0076     P(9, 0),  P(9, 1),  P(9, 2),  P(9, 3),  P(9, 4),  P(9, 5),  P(9, 6),  P(9, 7),
0077     P(10, 0), P(10, 1), P(10, 2), P(10, 3), P(10, 4), P(10, 5), P(10, 6), P(10, 7),
0078     P(11, 0), P(11, 1), P(11, 2), P(11, 3), P(11, 4), P(11, 5), P(11, 6), P(11, 7),
0079     P(12, 0), P(12, 1), P(12, 2),
0080 };
0081
0082 const size_t sppctl_pins_all_sz = ARRAY_SIZE(sppctl_pins_all);
0083
0084 const char * const sppctl_pmux_list_s[] = {
0085     D_PIS(0, 0),
0086     D_PIS(1, 0), D_PIS(1, 1), D_PIS(1, 2), D_PIS(1, 3),
0087     D_PIS(1, 4), D_PIS(1, 5), D_PIS(1, 6), D_PIS(1, 7),
0088     D_PIS(2, 0), D_PIS(2, 1), D_PIS(2, 2), D_PIS(2, 3),
0089     D_PIS(2, 4), D_PIS(2, 5), D_PIS(2, 6), D_PIS(2, 7),
0090     D_PIS(3, 0), D_PIS(3, 1), D_PIS(3, 2), D_PIS(3, 3),
0091     D_PIS(3, 4), D_PIS(3, 5), D_PIS(3, 6), D_PIS(3, 7),
0092     D_PIS(4, 0), D_PIS(4, 1), D_PIS(4, 2), D_PIS(4, 3),
0093     D_PIS(4, 4), D_PIS(4, 5), D_PIS(4, 6), D_PIS(4, 7),
0094     D_PIS(5, 0), D_PIS(5, 1), D_PIS(5, 2), D_PIS(5, 3),
0095     D_PIS(5, 4), D_PIS(5, 5), D_PIS(5, 6), D_PIS(5, 7),
0096     D_PIS(6, 0), D_PIS(6, 1), D_PIS(6, 2), D_PIS(6, 3),
0097     D_PIS(6, 4), D_PIS(6, 5), D_PIS(6, 6), D_PIS(6, 7),
0098     D_PIS(7, 0), D_PIS(7, 1), D_PIS(7, 2), D_PIS(7, 3),
0099     D_PIS(7, 4), D_PIS(7, 5), D_PIS(7, 6), D_PIS(7, 7),
0100     D_PIS(8, 0), D_PIS(8, 1), D_PIS(8, 2), D_PIS(8, 3),
0101     D_PIS(8, 4), D_PIS(8, 5), D_PIS(8, 6), D_PIS(8, 7),
0102 };
0103
0104 const size_t sppctl_pmux_list_sz = ARRAY_SIZE(sppctl_pmux_list_s);
0105
0106 static const unsigned int pins_spif1[] = {
0107     D(10, 3), D(10, 4), D(10, 6), D(10, 7),
0108 };
0109
0110 static const unsigned int pins_spif2[] = {
0111     D(9, 4), D(9, 6), D(9, 7), D(10, 1),
0112 };
0113
0114 static const struct sppctl_grp sp7021grps_spif[] = {
0115     EGRP("SPI_FLASH1", 1, pins_spif1),
0116     EGRP("SPI_FLASH2", 2, pins_spif2),
0117 };
0118
0119 static const unsigned int pins_spi41[] = {
0120     D(10, 2), D(10, 5),
0121 };
0122
0123 static const unsigned int pins_spi42[] = {
0124     D(9, 5), D(9, 8),
0125 };
0126
0127 static const struct sppctl_grp sp7021grps_spi4[] = {
0128     EGRP("SPI_FLASH_4BIT1", 1, pins_spi41),
0129     EGRP("SPI_FLASH_4BIT2", 2, pins_spi42),
0130 };
0131
0132 static const unsigned int pins_snan[] = {
0133     D(9, 4), D(9, 5), D(9, 6), D(9, 7), D(10, 0), D(10, 1),
0134 };
0135
0136 static const struct sppctl_grp sp7021grps_snan[] = {
0137     EGRP("SPI_NAND", 1, pins_snan),
0138 };
0139
0140 static const unsigned int pins_emmc[] = {
0141     D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5),
0142     D(9, 6), D(9, 7), D(10, 0), D(10, 1),
0143 };
0144
0145 static const struct sppctl_grp sp7021grps_emmc[] = {
0146     EGRP("CARD0_EMMC", 1, pins_emmc),
0147 };
0148
0149 static const unsigned int pins_sdsd[] = {
0150     D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6),
0151 };
0152
0153 static const struct sppctl_grp sp7021grps_sdsd[] = {
0154     EGRP("SD_CARD", 1, pins_sdsd),
0155 };
0156
0157 static const unsigned int pins_uar0[] = {
0158     D(11, 0), D(11, 1),
0159 };
0160
0161 static const struct sppctl_grp sp7021grps_uar0[] = {
0162     EGRP("UA0", 1, pins_uar0),
0163 };
0164
0165 static const unsigned int pins_adbg1[] = {
0166     D(10, 2), D(10, 3),
0167 };
0168
0169 static const unsigned int pins_adbg2[] = {
0170     D(7, 1), D(7, 2),
0171 };
0172
0173 static const struct sppctl_grp sp7021grps_adbg[] = {
0174     EGRP("ACHIP_DEBUG1", 1, pins_adbg1),
0175     EGRP("ACHIP_DEBUG2", 2, pins_adbg2),
0176 };
0177
0178 static const unsigned int pins_aua2axi1[] = {
0179     D(2, 0), D(2, 1), D(2, 2),
0180 };
0181
0182 static const unsigned int pins_aua2axi2[] = {
0183     D(1, 0), D(1, 1), D(1, 2),
0184 };
0185
0186 static const struct sppctl_grp sp7021grps_au2x[] = {
0187     EGRP("ACHIP_UA2AXI1", 1, pins_aua2axi1),
0188     EGRP("ACHIP_UA2AXI2", 2, pins_aua2axi2),
0189 };
0190
0191 static const unsigned int pins_fpga[] = {
0192     D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7),
0193     D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5),
0194     D(1, 6), D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3),
0195     D(2, 4), D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1),
0196     D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7),
0197     D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5),
0198     D(4, 6), D(4, 7), D(5, 0), D(5, 1), D(5, 2),
0199 };
0200
0201 static const struct sppctl_grp sp7021grps_fpga[] = {
0202     EGRP("FPGA_IFX", 1, pins_fpga),
0203 };
0204
0205 static const unsigned int pins_hdmi1[] = {
0206     D(10, 6), D(12, 2), D(12, 1),
0207 };
0208
0209 static const unsigned int pins_hdmi2[] = {
0210     D(8, 3), D(8, 5), D(8, 6),
0211 };
0212
0213 static const unsigned int pins_hdmi3[] = {
0214     D(7, 4), D(7, 6), D(7, 7),
0215 };
0216
0217 static const struct sppctl_grp sp7021grps_hdmi[] = {
0218     EGRP("HDMI_TX1", 1, pins_hdmi1),
0219     EGRP("HDMI_TX2", 2, pins_hdmi2),
0220     EGRP("HDMI_TX3", 3, pins_hdmi3),
0221 };
0222
0223 static const unsigned int pins_eadc[] = {
0224     D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6),
0225 };
0226
0227 static const struct sppctl_grp sp7021grps_eadc[] = {
0228     EGRP("AUD_EXT_ADC_IFX0", 1, pins_eadc),
0229 };
0230
0231 static const unsigned int pins_edac[] = {
0232     D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), D(3, 4),
0233 };
0234
0235 static const struct sppctl_grp sp7021grps_edac[] = {
0236     EGRP("AUD_EXT_DAC_IFX0", 1, pins_edac),
0237 };
0238
0239 static const unsigned int pins_spdi[] = {
0240     D(2, 4),
0241 };
0242
0243 static const struct sppctl_grp sp7021grps_spdi[] = {
0244     EGRP("AUD_IEC_RX0", 1, pins_spdi),
0245 };
0246
0247 static const unsigned int pins_spdo[] = {
0248     D(3, 6),
0249 };
0250
0251 static const struct sppctl_grp sp7021grps_spdo[] = {
0252     EGRP("AUD_IEC_TX0", 1, pins_spdo),
0253 };
0254
0255 static const unsigned int pins_tdmt[] = {
0256     D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2),
0257 };
0258
0259 static const struct sppctl_grp sp7021grps_tdmt[] = {
0260     EGRP("TDMTX_IFX0", 1, pins_tdmt),
0261 };
0262
0263 static const unsigned int pins_tdmr[] = {
0264     D(1, 7), D(2, 0), D(2, 1), D(2, 2),
0265 };
0266
0267 static const struct sppctl_grp sp7021grps_tdmr[] = {
0268     EGRP("TDMRX_IFX0", 1, pins_tdmr),
0269 };
0270
0271 static const unsigned int pins_pdmr[] = {
0272     D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3),
0273 };
0274
0275 static const struct sppctl_grp sp7021grps_pdmr[] = {
0276     EGRP("PDMRX_IFX0", 1, pins_pdmr),
0277 };
0278
0279 static const unsigned int pins_pcmt[] = {
0280     D(3, 7), D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4),
0281 };
0282
0283 static const struct sppctl_grp sp7021grps_pcmt[] = {
0284     EGRP("PCM_IEC_TX", 1, pins_pcmt),
0285 };
0286
0287 static const unsigned int pins_lcdi[] = {
0288     D(1, 4), D(1, 5), D(1, 6), D(1, 7), D(2, 0), D(2, 1), D(2, 2), D(2, 3),
0289     D(2, 4), D(2, 5), D(2, 6), D(2, 7), D(3, 0), D(3, 1), D(3, 2), D(3, 3),
0290     D(3, 4), D(3, 5), D(3, 6), D(3, 7), D(4, 0), D(4, 1), D(4, 2), D(4, 3),
0291     D(4, 4), D(4, 5), D(4, 6), D(4, 7),
0292 };
0293
0294 static const struct sppctl_grp sp7021grps_lcdi[] = {
0295     EGRP("LCDIF", 1, pins_lcdi),
0296 };
0297
0298 static const unsigned int pins_dvdd[] = {
0299     D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7),
0300     D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5),
0301 };
0302
0303 static const struct sppctl_grp sp7021grps_dvdd[] = {
0304     EGRP("DVD_DSP_DEBUG", 1, pins_dvdd),
0305 };
0306
0307 static const unsigned int pins_i2cd[] = {
0308     D(1, 0), D(1, 1),
0309 };
0310
0311 static const struct sppctl_grp sp7021grps_i2cd[] = {
0312     EGRP("I2C_DEBUG", 1, pins_i2cd),
0313 };
0314
0315 static const unsigned int pins_i2cs[] = {
0316     D(0, 0), D(0, 1),
0317 };
0318
0319 static const struct sppctl_grp sp7021grps_i2cs[] = {
0320     EGRP("I2C_SLAVE", 1, pins_i2cs),
0321 };
0322
0323 static const unsigned int pins_wakp[] = {
0324     D(10, 5),
0325 };
0326
0327 static const struct sppctl_grp sp7021grps_wakp[] = {
0328     EGRP("WAKEUP", 1, pins_wakp),
0329 };
0330
0331 static const unsigned int pins_u2ax[] = {
0332     D(2, 0), D(2, 1), D(3, 0), D(3, 1),
0333 };
0334
0335 static const struct sppctl_grp sp7021grps_u2ax[] = {
0336     EGRP("UART2AXI", 1, pins_u2ax),
0337 };
0338
0339 static const unsigned int pins_u0ic[] = {
0340     D(0, 0), D(0, 1), D(0, 4), D(0, 5), D(1, 0), D(1, 1),
0341 };
0342
0343 static const struct sppctl_grp sp7021grps_u0ic[] = {
0344     EGRP("USB0_I2C", 1, pins_u0ic),
0345 };
0346
0347 static const unsigned int pins_u1ic[] = {
0348     D(0, 2), D(0, 3), D(0, 6), D(0, 7), D(1, 2), D(1, 3),
0349 };
0350
0351 static const struct sppctl_grp sp7021grps_u1ic[] = {
0352     EGRP("USB1_I2C", 1, pins_u1ic),
0353 };
0354
0355 static const unsigned int pins_u0ot[] = {
0356     D(11, 2),
0357 };
0358
0359 static const struct sppctl_grp sp7021grps_u0ot[] = {
0360     EGRP("USB0_OTG", 1, pins_u0ot),
0361 };
0362
0363 static const unsigned int pins_u1ot[] = {
0364     D(11, 3),
0365 };
0366
0367 static const struct sppctl_grp sp7021grps_u1ot[] = {
0368     EGRP("USB1_OTG", 1, pins_u1ot),
0369 };
0370
0371 static const unsigned int pins_uphd[] = {
0372     D(0, 1), D(0, 2), D(0, 3), D(7, 4), D(7, 5), D(7, 6),
0373     D(7, 7), D(8, 0), D(8, 1), D(8, 2), D(8, 3),
0374     D(9, 7), D(10, 2), D(10, 3), D(10, 4),
0375 };
0376
0377 static const struct sppctl_grp sp7021grps_up0d[] = {
0378     EGRP("UPHY0_DEBUG", 1, pins_uphd),
0379 };
0380
0381 static const struct sppctl_grp sp7021grps_up1d[] = {
0382     EGRP("UPHY1_DEBUG", 1, pins_uphd),
0383 };
0384
0385 static const unsigned int pins_upex[] = {
0386     D(0, 0), D(0, 1), D(0, 2), D(0, 3), D(0, 4), D(0, 5), D(0, 6), D(0, 7),
0387     D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7),
0388     D(2, 0), D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7),
0389     D(3, 0), D(3, 1), D(3, 2), D(3, 3), D(3, 4), D(3, 5), D(3, 6), D(3, 7),
0390     D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7),
0391     D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7),
0392     D(6, 0), D(6, 1), D(6, 2), D(6, 3), D(6, 4), D(6, 5), D(6, 6), D(6, 7),
0393     D(7, 0), D(7, 1), D(7, 2), D(7, 3), D(7, 4), D(7, 5), D(7, 6), D(7, 7),
0394     D(8, 0), D(8, 1), D(8, 2), D(8, 3), D(8, 4), D(8, 5), D(8, 6), D(8, 7),
0395     D(9, 0), D(9, 1), D(9, 2), D(9, 3), D(9, 4), D(9, 5), D(9, 6), D(9, 7),
0396     D(10, 0), D(10, 1), D(10, 2), D(10, 3), D(10, 4), D(10, 5), D(10, 6), D(10, 7),
0397 };
0398
0399 static const struct sppctl_grp sp7021grps_upex[] = {
0400     EGRP("UPHY0_EXT", 1, pins_upex),
0401 };
0402
0403 static const unsigned int pins_prp1[] = {
0404     D(0, 6), D(0, 7),
0405     D(1, 0), D(1, 1), D(1, 2), D(1, 3), D(1, 4), D(1, 5), D(1, 6), D(1, 7),
0406     D(2, 1), D(2, 2), D(2, 3), D(2, 4), D(2, 5), D(2, 6), D(2, 7),
0407     D(3, 0), D(3, 1), D(3, 2),
0408 };
0409
0410 static const unsigned int pins_prp2[] = {
0411     D(3, 4), D(3, 6), D(3, 7),
0412     D(4, 0), D(4, 1), D(4, 2), D(4, 3), D(4, 4), D(4, 5), D(4, 6), D(4, 7),
0413     D(5, 0), D(5, 1), D(5, 2), D(5, 3), D(5, 4), D(5, 5), D(5, 6), D(5, 7),
0414     D(6, 4),
0415 };
0416
0417 static const struct sppctl_grp sp7021grps_prbp[] = {
0418     EGRP("PROBE_PORT1", 1, pins_prp1),
0419     EGRP("PROBE_PORT2", 2, pins_prp2),
0420 };
0421
0422 /*
0423  * Due to compatible reason, the first valid item should start at the third
0424  * position of the array. Please keep the first two items of the table
0425  * no use (dummy).
0426  */
0427 const struct sppctl_func sppctl_list_funcs[] = {
0428     FNCN("", pinmux_type_fpmx, 0x00, 0, 0),
0429     FNCN("", pinmux_type_fpmx, 0x00, 0, 0),
0430
0431     FNCN("L2SW_CLK_OUT",        pinmux_type_fpmx, 0x00, 0, 7),
0432     FNCN("L2SW_MAC_SMI_MDC",    pinmux_type_fpmx, 0x00, 8, 7),
0433     FNCN("L2SW_LED_FLASH0",     pinmux_type_fpmx, 0x01, 0, 7),
0434     FNCN("L2SW_LED_FLASH1",     pinmux_type_fpmx, 0x01, 8, 7),
0435     FNCN("L2SW_LED_ON0",        pinmux_type_fpmx, 0x02, 0, 7),
0436     FNCN("L2SW_LED_ON1",        pinmux_type_fpmx, 0x02, 8, 7),
0437     FNCN("L2SW_MAC_SMI_MDIO",   pinmux_type_fpmx, 0x03, 0, 7),
0438     FNCN("L2SW_P0_MAC_RMII_TXEN",   pinmux_type_fpmx, 0x03, 8, 7),
0439     FNCN("L2SW_P0_MAC_RMII_TXD0",   pinmux_type_fpmx, 0x04, 0, 7),
0440     FNCN("L2SW_P0_MAC_RMII_TXD1",   pinmux_type_fpmx, 0x04, 8, 7),
0441     FNCN("L2SW_P0_MAC_RMII_CRSDV",  pinmux_type_fpmx, 0x05, 0, 7),
0442     FNCN("L2SW_P0_MAC_RMII_RXD0",   pinmux_type_fpmx, 0x05, 8, 7),
0443     FNCN("L2SW_P0_MAC_RMII_RXD1",   pinmux_type_fpmx, 0x06, 0, 7),
0444     FNCN("L2SW_P0_MAC_RMII_RXER",   pinmux_type_fpmx, 0x06, 8, 7),
0445     FNCN("L2SW_P1_MAC_RMII_TXEN",   pinmux_type_fpmx, 0x07, 0, 7),
0446     FNCN("L2SW_P1_MAC_RMII_TXD0",   pinmux_type_fpmx, 0x07, 8, 7),
0447     FNCN("L2SW_P1_MAC_RMII_TXD1",   pinmux_type_fpmx, 0x08, 0, 7),
0448     FNCN("L2SW_P1_MAC_RMII_CRSDV",  pinmux_type_fpmx, 0x08, 8, 7),
0449     FNCN("L2SW_P1_MAC_RMII_RXD0",   pinmux_type_fpmx, 0x09, 0, 7),
0450     FNCN("L2SW_P1_MAC_RMII_RXD1",   pinmux_type_fpmx, 0x09, 8, 7),
0451     FNCN("L2SW_P1_MAC_RMII_RXER",   pinmux_type_fpmx, 0x0A, 0, 7),
0452     FNCN("DAISY_MODE",      pinmux_type_fpmx, 0x0A, 8, 7),
0453     FNCN("SDIO_CLK",        pinmux_type_fpmx, 0x0B, 0, 7),    /* 1x SDIO */
0454     FNCN("SDIO_CMD",        pinmux_type_fpmx, 0x0B, 8, 7),
0455     FNCN("SDIO_D0",         pinmux_type_fpmx, 0x0C, 0, 7),
0456     FNCN("SDIO_D1",         pinmux_type_fpmx, 0x0C, 8, 7),
0457     FNCN("SDIO_D2",         pinmux_type_fpmx, 0x0D, 0, 7),
0458     FNCN("SDIO_D3",         pinmux_type_fpmx, 0x0D, 8, 7),
0459     FNCN("PWM0",            pinmux_type_fpmx, 0x0E, 0, 7),    /* 8x PWM */
0460     FNCN("PWM1",            pinmux_type_fpmx, 0x0E, 8, 7),
0461     FNCN("PWM2",            pinmux_type_fpmx, 0x0F, 0, 7),
0462     FNCN("PWM3",            pinmux_type_fpmx, 0x0F, 8, 7),
0463
0464     FNCN("PWM4",            pinmux_type_fpmx, 0x10, 0, 7),
0465     FNCN("PWM5",            pinmux_type_fpmx, 0x10, 8, 7),
0466     FNCN("PWM6",            pinmux_type_fpmx, 0x11, 0, 7),
0467     FNCN("PWM7",            pinmux_type_fpmx, 0x11, 8, 7),
0468     FNCN("ICM0_D",          pinmux_type_fpmx, 0x12, 0, 7),    /* 4x Input captures */
0469     FNCN("ICM1_D",          pinmux_type_fpmx, 0x12, 8, 7),
0470     FNCN("ICM2_D",          pinmux_type_fpmx, 0x13, 0, 7),
0471     FNCN("ICM3_D",          pinmux_type_fpmx, 0x13, 8, 7),
0472     FNCN("ICM0_CLK",        pinmux_type_fpmx, 0x14, 0, 7),
0473     FNCN("ICM1_CLK",        pinmux_type_fpmx, 0x14, 8, 7),
0474     FNCN("ICM2_CLK",        pinmux_type_fpmx, 0x15, 0, 7),
0475     FNCN("ICM3_CLK",        pinmux_type_fpmx, 0x15, 8, 7),
0476     FNCN("SPIM0_INT",       pinmux_type_fpmx, 0x16, 0, 7),    /* 4x SPI masters */
0477     FNCN("SPIM0_CLK",       pinmux_type_fpmx, 0x16, 8, 7),
0478     FNCN("SPIM0_EN",        pinmux_type_fpmx, 0x17, 0, 7),
0479     FNCN("SPIM0_DO",        pinmux_type_fpmx, 0x17, 8, 7),
0480     FNCN("SPIM0_DI",        pinmux_type_fpmx, 0x18, 0, 7),
0481     FNCN("SPIM1_INT",       pinmux_type_fpmx, 0x18, 8, 7),
0482     FNCN("SPIM1_CLK",       pinmux_type_fpmx, 0x19, 0, 7),
0483     FNCN("SPIM1_EN",        pinmux_type_fpmx, 0x19, 8, 7),
0484     FNCN("SPIM1_DO",        pinmux_type_fpmx, 0x1A, 0, 7),
0485     FNCN("SPIM1_DI",        pinmux_type_fpmx, 0x1A, 8, 7),
0486     FNCN("SPIM2_INT",       pinmux_type_fpmx, 0x1B, 0, 7),
0487     FNCN("SPIM2_CLK",       pinmux_type_fpmx, 0x1B, 8, 7),
0488     FNCN("SPIM2_EN",        pinmux_type_fpmx, 0x1C, 0, 7),
0489     FNCN("SPIM2_DO",        pinmux_type_fpmx, 0x1C, 8, 7),
0490     FNCN("SPIM2_DI",        pinmux_type_fpmx, 0x1D, 0, 7),
0491     FNCN("SPIM3_INT",       pinmux_type_fpmx, 0x1D, 8, 7),
0492     FNCN("SPIM3_CLK",       pinmux_type_fpmx, 0x1E, 0, 7),
0493     FNCN("SPIM3_EN",        pinmux_type_fpmx, 0x1E, 8, 7),
0494     FNCN("SPIM3_DO",        pinmux_type_fpmx, 0x1F, 0, 7),
0495     FNCN("SPIM3_DI",        pinmux_type_fpmx, 0x1F, 8, 7),
0496
0497     FNCN("SPI0S_INT",       pinmux_type_fpmx, 0x20, 0, 7),    /* 4x SPI slaves */
0498     FNCN("SPI0S_CLK",       pinmux_type_fpmx, 0x20, 8, 7),
0499     FNCN("SPI0S_EN",        pinmux_type_fpmx, 0x21, 0, 7),
0500     FNCN("SPI0S_DO",        pinmux_type_fpmx, 0x21, 8, 7),
0501     FNCN("SPI0S_DI",        pinmux_type_fpmx, 0x22, 0, 7),
0502     FNCN("SPI1S_INT",       pinmux_type_fpmx, 0x22, 8, 7),
0503     FNCN("SPI1S_CLK",       pinmux_type_fpmx, 0x23, 0, 7),
0504     FNCN("SPI1S_EN",        pinmux_type_fpmx, 0x23, 8, 7),
0505     FNCN("SPI1S_DO",        pinmux_type_fpmx, 0x24, 0, 7),
0506     FNCN("SPI1S_DI",        pinmux_type_fpmx, 0x24, 8, 7),
0507     FNCN("SPI2S_INT",       pinmux_type_fpmx, 0x25, 0, 7),
0508     FNCN("SPI2S_CLK",       pinmux_type_fpmx, 0x25, 8, 7),
0509     FNCN("SPI2S_EN",        pinmux_type_fpmx, 0x26, 0, 7),
0510     FNCN("SPI2S_DO",        pinmux_type_fpmx, 0x26, 8, 7),
0511     FNCN("SPI2S_DI",        pinmux_type_fpmx, 0x27, 0, 7),
0512     FNCN("SPI3S_INT",       pinmux_type_fpmx, 0x27, 8, 7),
0513     FNCN("SPI3S_CLK",       pinmux_type_fpmx, 0x28, 0, 7),
0514     FNCN("SPI3S_EN",        pinmux_type_fpmx, 0x28, 8, 7),
0515     FNCN("SPI3S_DO",        pinmux_type_fpmx, 0x29, 0, 7),
0516     FNCN("SPI3S_DI",        pinmux_type_fpmx, 0x29, 8, 7),
0517     FNCN("I2CM0_CLK",       pinmux_type_fpmx, 0x2A, 0, 7),    /* 4x I2C masters */
0518     FNCN("I2CM0_DAT",       pinmux_type_fpmx, 0x2A, 8, 7),
0519     FNCN("I2CM1_CLK",       pinmux_type_fpmx, 0x2B, 0, 7),
0520     FNCN("I2CM1_DAT",       pinmux_type_fpmx, 0x2B, 8, 7),
0521     FNCN("I2CM2_CLK",       pinmux_type_fpmx, 0x2C, 0, 7),
0522     FNCN("I2CM2_DAT",       pinmux_type_fpmx, 0x2C, 8, 7),
0523     FNCN("I2CM3_CLK",       pinmux_type_fpmx, 0x2D, 0, 7),
0524     FNCN("I2CM3_DAT",       pinmux_type_fpmx, 0x2D, 8, 7),
0525     FNCN("UA1_TX",          pinmux_type_fpmx, 0x2E, 0, 7),    /* 4x UARTS */
0526     FNCN("UA1_RX",          pinmux_type_fpmx, 0x2E, 8, 7),
0527     FNCN("UA1_CTS",         pinmux_type_fpmx, 0x2F, 0, 7),
0528     FNCN("UA1_RTS",         pinmux_type_fpmx, 0x2F, 8, 7),
0529
0530     FNCN("UA2_TX",          pinmux_type_fpmx, 0x30, 0, 7),
0531     FNCN("UA2_RX",          pinmux_type_fpmx, 0x30, 8, 7),
0532     FNCN("UA2_CTS",         pinmux_type_fpmx, 0x31, 0, 7),
0533     FNCN("UA2_RTS",         pinmux_type_fpmx, 0x31, 8, 7),
0534     FNCN("UA3_TX",          pinmux_type_fpmx, 0x32, 0, 7),
0535     FNCN("UA3_RX",          pinmux_type_fpmx, 0x32, 8, 7),
0536     FNCN("UA3_CTS",         pinmux_type_fpmx, 0x33, 0, 7),
0537     FNCN("UA3_RTS",         pinmux_type_fpmx, 0x33, 8, 7),
0538     FNCN("UA4_TX",          pinmux_type_fpmx, 0x34, 0, 7),
0539     FNCN("UA4_RX",          pinmux_type_fpmx, 0x34, 8, 7),
0540     FNCN("UA4_CTS",         pinmux_type_fpmx, 0x35, 0, 7),
0541     FNCN("UA4_RTS",         pinmux_type_fpmx, 0x35, 8, 7),
0542     FNCN("TIMER0_INT",      pinmux_type_fpmx, 0x36, 0, 7),    /* 4x timer int. */
0543     FNCN("TIMER1_INT",      pinmux_type_fpmx, 0x36, 8, 7),
0544     FNCN("TIMER2_INT",      pinmux_type_fpmx, 0x37, 0, 7),
0545     FNCN("TIMER3_INT",      pinmux_type_fpmx, 0x37, 8, 7),
0546     FNCN("GPIO_INT0",       pinmux_type_fpmx, 0x38, 0, 7),    /* 8x GPIO int. */
0547     FNCN("GPIO_INT1",       pinmux_type_fpmx, 0x38, 8, 7),
0548     FNCN("GPIO_INT2",       pinmux_type_fpmx, 0x39, 0, 7),
0549     FNCN("GPIO_INT3",       pinmux_type_fpmx, 0x39, 8, 7),
0550     FNCN("GPIO_INT4",       pinmux_type_fpmx, 0x3A, 0, 7),
0551     FNCN("GPIO_INT5",       pinmux_type_fpmx, 0x3A, 8, 7),
0552     FNCN("GPIO_INT6",       pinmux_type_fpmx, 0x3B, 0, 7),
0553     FNCN("GPIO_INT7",       pinmux_type_fpmx, 0x3B, 8, 7),
0554
0555     /* MOON1 register */
0556     FNCE("SPI_FLASH",       pinmux_type_grp, 0x01,  0, 2, sp7021grps_spif),
0557     FNCE("SPI_FLASH_4BIT",  pinmux_type_grp, 0x01,  2, 2, sp7021grps_spi4),
0558     FNCE("SPI_NAND",        pinmux_type_grp, 0x01,  4, 1, sp7021grps_snan),
0559     FNCE("CARD0_EMMC",      pinmux_type_grp, 0x01,  5, 1, sp7021grps_emmc),
0560     FNCE("SD_CARD",         pinmux_type_grp, 0x01,  6, 1, sp7021grps_sdsd),
0561     FNCE("UA0",             pinmux_type_grp, 0x01,  7, 1, sp7021grps_uar0),
0562     FNCE("ACHIP_DEBUG",     pinmux_type_grp, 0x01,  8, 2, sp7021grps_adbg),
0563     FNCE("ACHIP_UA2AXI",    pinmux_type_grp, 0x01, 10, 2, sp7021grps_au2x),
0564     FNCE("FPGA_IFX",        pinmux_type_grp, 0x01, 12, 1, sp7021grps_fpga),
0565     FNCE("HDMI_TX",         pinmux_type_grp, 0x01, 13, 2, sp7021grps_hdmi),
0566
0567     FNCE("AUD_EXT_ADC_IFX0", pinmux_type_grp, 0x01, 15, 1, sp7021grps_eadc),
0568     FNCE("AUD_EXT_DAC_IFX0", pinmux_type_grp, 0x02,  0, 1, sp7021grps_edac),
0569     FNCE("SPDIF_RX",        pinmux_type_grp, 0x02,  2, 1, sp7021grps_spdi),
0570     FNCE("SPDIF_TX",        pinmux_type_grp, 0x02,  3, 1, sp7021grps_spdo),
0571     FNCE("TDMTX_IFX0",      pinmux_type_grp, 0x02,  4, 1, sp7021grps_tdmt),
0572     FNCE("TDMRX_IFX0",      pinmux_type_grp, 0x02,  5, 1, sp7021grps_tdmr),
0573     FNCE("PDMRX_IFX0",      pinmux_type_grp, 0x02,  6, 1, sp7021grps_pdmr),
0574     FNCE("PCM_IEC_TX",      pinmux_type_grp, 0x02,  7, 1, sp7021grps_pcmt),
0575     FNCE("LCDIF",           pinmux_type_grp, 0x04,  6, 1, sp7021grps_lcdi),
0576     FNCE("DVD_DSP_DEBUG",   pinmux_type_grp, 0x02,  8, 1, sp7021grps_dvdd),
0577     FNCE("I2C_DEBUG",       pinmux_type_grp, 0x02,  9, 1, sp7021grps_i2cd),
0578     FNCE("I2C_SLAVE",       pinmux_type_grp, 0x02, 10, 1, sp7021grps_i2cs),
0579     FNCE("WAKEUP",          pinmux_type_grp, 0x02, 11, 1, sp7021grps_wakp),
0580     FNCE("UART2AXI",        pinmux_type_grp, 0x02, 12, 2, sp7021grps_u2ax),
0581     FNCE("USB0_I2C",        pinmux_type_grp, 0x02, 14, 2, sp7021grps_u0ic),
0582     FNCE("USB1_I2C",        pinmux_type_grp, 0x03,  0, 2, sp7021grps_u1ic),
0583     FNCE("USB0_OTG",        pinmux_type_grp, 0x03,  2, 1, sp7021grps_u0ot),
0584     FNCE("USB1_OTG",        pinmux_type_grp, 0x03,  3, 1, sp7021grps_u1ot),
0585     FNCE("UPHY0_DEBUG",     pinmux_type_grp, 0x03,  4, 1, sp7021grps_up0d),
0586     FNCE("UPHY1_DEBUG",     pinmux_type_grp, 0x03,  5, 1, sp7021grps_up1d),
0587     FNCE("UPHY0_EXT",       pinmux_type_grp, 0x03,  6, 1, sp7021grps_upex),
0588     FNCE("PROBE_PORT",      pinmux_type_grp, 0x03,  7, 2, sp7021grps_prbp),
0589 };
0590
0591 const size_t sppctl_list_funcs_sz = ARRAY_SIZE(sppctl_list_funcs);