pinctrl/sunplus/sppctl.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * SP7021 Pin Controller Driver.
0004  * Copyright (C) Sunplus Tech / Tibbo Tech.
0005  */
0006
0007 #ifndef __SPPCTL_H__
0008 #define __SPPCTL_H__
0009
0010 #include <linux/bits.h>
0011 #include <linux/gpio/driver.h>
0012 #include <linux/kernel.h>
0013 #include <linux/pinctrl/pinctrl.h>
0014 #include <linux/spinlock.h>
0015 #include <linux/types.h>
0016
0017 #define SPPCTL_MODULE_NAME      "sppctl_sp7021"
0018
0019 #define SPPCTL_GPIO_OFF_FIRST       0x00
0020 #define SPPCTL_GPIO_OFF_MASTER      0x00
0021 #define SPPCTL_GPIO_OFF_OE      0x20
0022 #define SPPCTL_GPIO_OFF_OUT     0x40
0023 #define SPPCTL_GPIO_OFF_IN      0x60
0024 #define SPPCTL_GPIO_OFF_IINV        0x80
0025 #define SPPCTL_GPIO_OFF_OINV        0xa0
0026 #define SPPCTL_GPIO_OFF_OD      0xc0
0027
0028 #define SPPCTL_FULLY_PINMUX_MASK_MASK   GENMASK(22, 16)
0029 #define SPPCTL_FULLY_PINMUX_SEL_MASK    GENMASK(6, 0)
0030 #define SPPCTL_FULLY_PINMUX_UPPER_SHIFT 8
0031
0032 /*
0033  * Mask-fields and control-fields of MOON registers of SP7021 are
0034  * arranged as shown below:
0035  *
0036  *  register |  mask-fields | control-fields
0037  * ----------+--------------+----------------
0038  *  base[0]  |  (31 : 16)   |   (15 : 0)
0039  *  base[1]  |  (31 : 24)   |   (15 : 0)
0040  *  base[2]  |  (31 : 24)   |   (15 : 0)
0041  *     :     |      :       |       :
0042  *
0043  * where mask-fields are used to protect control-fields from write-in
0044  * accidentally. Set the corresponding bits in the mask-field before
0045  * you write a value into a control-field.
0046  */
0047 #define SPPCTL_MOON_REG_MASK_SHIFT  16
0048 #define SPPCTL_SET_MOON_REG_BIT(bit)    (BIT((bit) + SPPCTL_MOON_REG_MASK_SHIFT) | BIT(bit))
0049 #define SPPCTL_CLR_MOON_REG_BIT(bit)    BIT((bit) + SPPCTL_MOON_REG_MASK_SHIFT)
0050
0051 #define SPPCTL_IOP_CONFIGS      0xff
0052
0053 #define FNCE(n, r, o, bo, bl, g) { \
0054     .name = n, \
0055     .type = r, \
0056     .roff = o, \
0057     .boff = bo, \
0058     .blen = bl, \
0059     .grps = (g), \
0060     .gnum = ARRAY_SIZE(g), \
0061 }
0062
0063 #define FNCN(n, r, o, bo, bl) { \
0064     .name = n, \
0065     .type = r, \
0066     .roff = o, \
0067     .boff = bo, \
0068     .blen = bl, \
0069     .grps = NULL, \
0070     .gnum = 0, \
0071 }
0072
0073 #define EGRP(n, v, p) { \
0074     .name = n, \
0075     .gval = (v), \
0076     .pins = (p), \
0077     .pnum = ARRAY_SIZE(p), \
0078 }
0079
0080 /**
0081  * enum mux_first_reg - Define modes of access of FIRST register
0082  * @mux_f_mux:  Set the corresponding pin to a fully-pinmux pin
0083  * @mux_f_gpio: Set the corresponding pin to a GPIO or IOP pin
0084  * @mux_f_keep: Don't change (keep intact)
0085  */
0086 enum mux_first_reg {
0087     mux_f_mux = 0,
0088     mux_f_gpio = 1,
0089     mux_f_keep = 2,
0090 };
0091
0092 /**
0093  * enum mux_master_reg - Define modes of access of MASTER register
0094  * @mux_m_iop:  Set the corresponding pin to an IO processor (IOP) pin
0095  * @mux_m_gpio: Set the corresponding pin to a digital GPIO pin
0096  * @mux_m_keep: Don't change (keep intact)
0097  */
0098 enum mux_master_reg {
0099     mux_m_iop = 0,
0100     mux_m_gpio = 1,
0101     mux_m_keep = 2,
0102 };
0103
0104 /**
0105  * enum pinmux_type - Define types of pinmux pins
0106  * @pinmux_type_fpmx: A fully-pinmux pin
0107  * @pinmux_type_grp:  A group-pinmux pin
0108  */
0109 enum pinmux_type {
0110     pinmux_type_fpmx,
0111     pinmux_type_grp,
0112 };
0113
0114 /**
0115  * struct grp2fp_map - A map storing indexes
0116  * @f_idx: an index to function table
0117  * @g_idx: an index to group table
0118  */
0119 struct grp2fp_map {
0120     u16 f_idx;
0121     u16 g_idx;
0122 };
0123
0124 struct sppctl_gpio_chip;
0125
0126 struct sppctl_pdata {
0127     void __iomem *moon2_base;   /* MOON2                                 */
0128     void __iomem *gpioxt_base;  /* MASTER, OE, OUT, IN, I_INV, O_INV, OD */
0129     void __iomem *first_base;   /* FIRST                                 */
0130     void __iomem *moon1_base;   /* MOON1               */
0131
0132     struct pinctrl_desc pctl_desc;
0133     struct pinctrl_dev *pctl_dev;
0134     struct pinctrl_gpio_range pctl_grange;
0135     struct sppctl_gpio_chip *spp_gchip;
0136
0137     char const **unq_grps;
0138     size_t unq_grps_sz;
0139     struct grp2fp_map *g2fp_maps;
0140 };
0141
0142 struct sppctl_grp {
0143     const char * const name;
0144     const u8 gval;                  /* group number   */
0145     const unsigned * const pins;    /* list of pins   */
0146     const unsigned int pnum;        /* number of pins */
0147 };
0148
0149 struct sppctl_func {
0150     const char * const name;
0151     const enum pinmux_type type;    /* function type          */
0152     const u8 roff;                  /* register offset        */
0153     const u8 boff;                  /* bit offset             */
0154     const u8 blen;                  /* bit length             */
0155     const struct sppctl_grp * const grps; /* list of groups   */
0156     const unsigned int gnum;        /* number of groups       */
0157 };
0158
0159 extern const struct sppctl_func sppctl_list_funcs[];
0160 extern const char * const sppctl_pmux_list_s[];
0161 extern const char * const sppctl_gpio_list_s[];
0162 extern const struct pinctrl_pin_desc sppctl_pins_all[];
0163 extern const unsigned int sppctl_pins_gpio[];
0164
0165 extern const size_t sppctl_list_funcs_sz;
0166 extern const size_t sppctl_pmux_list_sz;
0167 extern const size_t sppctl_gpio_list_sz;
0168 extern const size_t sppctl_pins_all_sz;
0169
0170 #endif