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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * SP7021 Pin Controller Driver.
0004  * Copyright (C) Sunplus Tech / Tibbo Tech.
0005  */
0006 
0007 #include <linux/bitfield.h>
0008 #include <linux/device.h>
0009 #include <linux/err.h>
0010 #include <linux/gpio/driver.h>
0011 #include <linux/init.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/of_device.h>
0015 #include <linux/overflow.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/seq_file.h>
0018 #include <linux/slab.h>
0019 
0020 #include <linux/pinctrl/pinconf.h>
0021 #include <linux/pinctrl/pinconf-generic.h>
0022 #include <linux/pinctrl/pinmux.h>
0023 
0024 #include <dt-bindings/pinctrl/sppctl-sp7021.h>
0025 
0026 #include "../core.h"
0027 #include "../pinctrl-utils.h"
0028 
0029 #include "sppctl.h"
0030 
0031 struct sppctl_gpio_chip {
0032     void __iomem *gpioxt_base;  /* MASTER, OE, OUT, IN, I_INV, O_INV, OD */
0033     void __iomem *first_base;   /* GPIO_FIRST                            */
0034 
0035     struct gpio_chip chip;
0036     spinlock_t lock;        /* lock for accessing OE register        */
0037 };
0038 
0039 static inline u32 sppctl_first_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
0040 {
0041     return readl(spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off);
0042 }
0043 
0044 static inline void sppctl_first_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off)
0045 {
0046     writel(val, spp_gchip->first_base + SPPCTL_GPIO_OFF_FIRST + off);
0047 }
0048 
0049 static inline u32 sppctl_gpio_master_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
0050 {
0051     return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off);
0052 }
0053 
0054 static inline void sppctl_gpio_master_writel(struct sppctl_gpio_chip *spp_gchip, u32 val,
0055                          u32 off)
0056 {
0057     writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_MASTER + off);
0058 }
0059 
0060 static inline u32 sppctl_gpio_oe_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
0061 {
0062     return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off);
0063 }
0064 
0065 static inline void sppctl_gpio_oe_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off)
0066 {
0067     writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OE + off);
0068 }
0069 
0070 static inline void sppctl_gpio_out_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off)
0071 {
0072     writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OUT + off);
0073 }
0074 
0075 static inline u32 sppctl_gpio_in_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
0076 {
0077     return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IN + off);
0078 }
0079 
0080 static inline u32 sppctl_gpio_iinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
0081 {
0082     return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off);
0083 }
0084 
0085 static inline void sppctl_gpio_iinv_writel(struct sppctl_gpio_chip *spp_gchip, u32 val,
0086                        u32 off)
0087 {
0088     writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_IINV + off);
0089 }
0090 
0091 static inline u32 sppctl_gpio_oinv_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
0092 {
0093     return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off);
0094 }
0095 
0096 static inline void sppctl_gpio_oinv_writel(struct sppctl_gpio_chip *spp_gchip, u32 val,
0097                        u32 off)
0098 {
0099     writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OINV + off);
0100 }
0101 
0102 static inline u32 sppctl_gpio_od_readl(struct sppctl_gpio_chip *spp_gchip, u32 off)
0103 {
0104     return readl(spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off);
0105 }
0106 
0107 static inline void sppctl_gpio_od_writel(struct sppctl_gpio_chip *spp_gchip, u32 val, u32 off)
0108 {
0109     writel(val, spp_gchip->gpioxt_base + SPPCTL_GPIO_OFF_OD + off);
0110 }
0111 
0112 static inline u32 sppctl_get_reg_and_bit_offset(unsigned int offset, u32 *reg_off)
0113 {
0114     u32 bit_off;
0115 
0116     /* Each register has 32 bits. */
0117     *reg_off = (offset / 32) * 4;
0118     bit_off = offset % 32;
0119 
0120     return bit_off;
0121 }
0122 
0123 static inline u32 sppctl_get_moon_reg_and_bit_offset(unsigned int offset, u32 *reg_off)
0124 {
0125     u32 bit_off;
0126 
0127     /*
0128      * Each MOON register has 32 bits. Upper 16-bit word are mask-fields.
0129      * The lower 16-bit word are the control-fields. The corresponding
0130      * bits in mask-field should be set then you can write something to
0131      * control-field.
0132      */
0133     *reg_off = (offset / 16) * 4;
0134     bit_off = offset % 16;
0135 
0136     return bit_off;
0137 }
0138 
0139 static inline u32 sppctl_prep_moon_reg_and_offset(unsigned int offset, u32 *reg_off, int val)
0140 {
0141     u32 bit_off;
0142 
0143     bit_off = sppctl_get_moon_reg_and_bit_offset(offset, reg_off);
0144     if (val)
0145         return SPPCTL_SET_MOON_REG_BIT(bit_off);
0146     else
0147         return SPPCTL_CLR_MOON_REG_BIT(bit_off);
0148 }
0149 
0150 /**
0151  * sppctl_func_set() - Set pin of fully-pinmux function.
0152  *
0153  * Mask-fields and control-fields of fully-pinmux function of SP7021 are
0154  * arranged as shown below:
0155  *
0156  *  func# | register |  mask-field  | control-field
0157  * -------+----------+--------------+---------------
0158  *    0   | base[0]  |  (22 : 16)   |   ( 6 : 0)
0159  *    1   | base[0]  |  (30 : 24)   |   (14 : 8)
0160  *    2   | base[1]  |  (22 : 16)   |   ( 6 : 0)
0161  *    3   | baeg[1]  |  (30 : 24)   |   (14 : 8)
0162  *    :   |    :     |      :       |       :
0163  *
0164  * where mask-fields are used to protect control-fields from write-in
0165  * accidentally. Set the corresponding bits in the mask-field before
0166  * you write a value into a control-field.
0167  *
0168  * Control-fields are used to set where the function pin is going to
0169  * be routed to.
0170  *
0171  * Note that mask-fields and control-fields of even number of 'func'
0172  * are located at bits (22:16) and (6:0), while odd number of 'func's
0173  * are located at bits (30:24) and (14:8).
0174  */
0175 static void sppctl_func_set(struct sppctl_pdata *pctl, u8 func, u8 val)
0176 {
0177     u32 reg, offset;
0178 
0179     /*
0180      * Note that upper 16-bit word are mask-fields and lower 16-bit
0181      * word are the control-fields. Set corresponding bits in mask-
0182      * field before write to a control-field.
0183      */
0184     reg = SPPCTL_FULLY_PINMUX_MASK_MASK | val;
0185 
0186     /*
0187      * MUXF_L2SW_CLK_OUT is the first fully-pinmux pin
0188      * and its register offset is 0.
0189      */
0190     func -= MUXF_L2SW_CLK_OUT;
0191 
0192     /*
0193      * Check if 'func' is an odd number or not. Mask and control-
0194      * fields of odd number 'func' is located at upper portion of
0195      * a register. Extra shift is needed.
0196      */
0197     if (func & BIT(0))
0198         reg <<= SPPCTL_FULLY_PINMUX_UPPER_SHIFT;
0199 
0200     /* Convert func# to register offset w.r.t. base register. */
0201     offset = func * 2;
0202     offset &= GENMASK(31, 2);
0203 
0204     writel(reg, pctl->moon2_base + offset);
0205 }
0206 
0207 /**
0208  * sppctl_gmx_set() - Set pin of group-pinmux.
0209  *
0210  * Mask-fields and control-fields of group-pinmux function of SP7021 are
0211  * arranged as shown below:
0212  *
0213  *  register |  mask-fields | control-fields
0214  * ----------+--------------+----------------
0215  *  base[0]  |  (31 : 16)   |   (15 : 0)
0216  *  base[1]  |  (31 : 24)   |   (15 : 0)
0217  *  base[2]  |  (31 : 24)   |   (15 : 0)
0218  *     :     |      :       |       :
0219  *
0220  * where mask-fields are used to protect control-fields from write-in
0221  * accidentally. Set the corresponding bits in the mask-field before
0222  * you write a value into a control-field.
0223  *
0224  * Control-fields are used to set where the function pin is going to
0225  * be routed to. A control-field consists of one or more bits.
0226  */
0227 static void sppctl_gmx_set(struct sppctl_pdata *pctl, u8 reg_off, u8 bit_off, u8 bit_sz,
0228                u8 val)
0229 {
0230     u32 mask, reg;
0231 
0232     /*
0233      * Note that upper 16-bit word are mask-fields and lower 16-bit
0234      * word are the control-fields. Set corresponding bits in mask-
0235      * field before write to a control-field.
0236      */
0237     mask = GENMASK(bit_sz - 1, 0) << SPPCTL_MOON_REG_MASK_SHIFT;
0238     reg = (mask | val) << bit_off;
0239 
0240     writel(reg, pctl->moon1_base + reg_off * 4);
0241 }
0242 
0243 /**
0244  * sppctl_first_get() - get bit of FIRST register.
0245  *
0246  * There are 4 FIRST registers. Each has 32 control-bits.
0247  * Totally, there are 4 * 32 = 128 control-bits.
0248  * Control-bits are arranged as shown below:
0249  *
0250  *  registers | control-bits
0251  * -----------+--------------
0252  *  first[0]  |  (31 :  0)
0253  *  first[1]  |  (63 : 32)
0254  *  first[2]  |  (95 : 64)
0255  *  first[3]  | (127 : 96)
0256  *
0257  * Each control-bit sets type of a GPIO pin.
0258  *   0: a fully-pinmux pin
0259  *   1: a GPIO or IOP pin
0260  */
0261 static int sppctl_first_get(struct gpio_chip *chip, unsigned int offset)
0262 {
0263     struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
0264     u32 reg_off, bit_off, reg;
0265 
0266     bit_off = sppctl_get_reg_and_bit_offset(offset, &reg_off);
0267     reg = sppctl_first_readl(spp_gchip, reg_off);
0268 
0269     return (reg & BIT(bit_off)) ? 1 : 0;
0270 }
0271 
0272 /**
0273  * sppctl_master_get() - get bit of MASTER register.
0274  *
0275  * There are 8 MASTER registers. Each has 16 mask-bits and 16 control-bits.
0276  * Upper 16-bit of MASTER registers are mask-bits while lower 16-bit are
0277  * control-bits. Totally, there are 128 mask-bits and 128 control-bits.
0278  * They are arranged as shown below:
0279  *
0280  *  register  |  mask-bits  | control-bits
0281  * -----------+-------------+--------------
0282  *  master[0] |  (15 :   0) |  (15 :   0)
0283  *  master[1] |  (31 :  16) |  (31 :  16)
0284  *  master[2] |  (47 :  32) |  (47 :  32)
0285  *     :      |      :      |      :
0286  *  master[7] | (127 : 112) | (127 : 112)
0287  *
0288  * where mask-bits are used to protect control-bits from write-in
0289  * accidentally. Set the corresponding mask-bit before you write
0290  * a value into a control-bit.
0291  *
0292  * Each control-bit sets type of a GPIO pin when FIRST bit is 1.
0293  *   0: a IOP pin
0294  *   1: a GPIO pin
0295  */
0296 static int sppctl_master_get(struct gpio_chip *chip, unsigned int offset)
0297 {
0298     struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
0299     u32 reg_off, bit_off, reg;
0300 
0301     bit_off = sppctl_get_moon_reg_and_bit_offset(offset, &reg_off);
0302     reg = sppctl_gpio_master_readl(spp_gchip, reg_off);
0303     return (reg & BIT(bit_off)) ? 1 : 0;
0304 }
0305 
0306 static void sppctl_first_master_set(struct gpio_chip *chip, unsigned int offset,
0307                     enum mux_first_reg first, enum mux_master_reg master)
0308 {
0309     struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
0310     u32 reg_off, bit_off, reg;
0311     enum mux_first_reg val;
0312 
0313     /* FIRST register */
0314     if (first != mux_f_keep) {
0315         bit_off = sppctl_get_reg_and_bit_offset(offset, &reg_off);
0316         reg = sppctl_first_readl(spp_gchip, reg_off);
0317         val = (reg & BIT(bit_off)) ? mux_f_gpio : mux_f_mux;
0318 
0319         if (first != val)
0320             switch (first) {
0321             case mux_f_gpio:
0322                 reg |= BIT(bit_off);
0323                 sppctl_first_writel(spp_gchip, reg, reg_off);
0324                 break;
0325 
0326             case mux_f_mux:
0327                 reg &= ~BIT(bit_off);
0328                 sppctl_first_writel(spp_gchip, reg, reg_off);
0329                 break;
0330 
0331             case mux_f_keep:
0332                 break;
0333             }
0334     }
0335 
0336     /* MASTER register */
0337     if (master != mux_m_keep) {
0338         reg = sppctl_prep_moon_reg_and_offset(offset, &reg_off, (master == mux_m_gpio));
0339         sppctl_gpio_master_writel(spp_gchip, reg, reg_off);
0340     }
0341 }
0342 
0343 static void sppctl_gpio_input_inv_set(struct gpio_chip *chip, unsigned int offset)
0344 {
0345     struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
0346     u32 reg_off, reg;
0347 
0348     reg = sppctl_prep_moon_reg_and_offset(offset, &reg_off, 1);
0349     sppctl_gpio_iinv_writel(spp_gchip, reg, reg_off);
0350 }
0351 
0352 static void sppctl_gpio_output_inv_set(struct gpio_chip *chip, unsigned int offset)
0353 {
0354     struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
0355     u32 reg_off, reg;
0356 
0357     reg = sppctl_prep_moon_reg_and_offset(offset, &reg_off, 1);
0358     sppctl_gpio_oinv_writel(spp_gchip, reg, reg_off);
0359 }
0360 
0361 static int sppctl_gpio_output_od_get(struct gpio_chip *chip, unsigned int offset)
0362 {
0363     struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
0364     u32 reg_off, bit_off, reg;
0365 
0366     bit_off = sppctl_get_moon_reg_and_bit_offset(offset, &reg_off);
0367     reg = sppctl_gpio_od_readl(spp_gchip, reg_off);
0368 
0369     return (reg & BIT(bit_off)) ? 1 : 0;
0370 }
0371 
0372 static void sppctl_gpio_output_od_set(struct gpio_chip *chip, unsigned int offset,
0373                       unsigned int val)
0374 {
0375     struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
0376     u32 reg_off, reg;
0377 
0378     reg = sppctl_prep_moon_reg_and_offset(offset, &reg_off, val);
0379     sppctl_gpio_od_writel(spp_gchip, reg, reg_off);
0380 }
0381 
0382 static int sppctl_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
0383 {
0384     struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
0385     u32 reg_off, bit_off, reg;
0386 
0387     bit_off = sppctl_get_moon_reg_and_bit_offset(offset, &reg_off);
0388     reg = sppctl_gpio_oe_readl(spp_gchip, reg_off);
0389 
0390     return (reg & BIT(bit_off)) ? 0 : 1;
0391 }
0392 
0393 static int sppctl_gpio_inv_get(struct gpio_chip *chip, unsigned int offset)
0394 {
0395     struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
0396     u32 reg_off, bit_off, reg;
0397     unsigned long flags;
0398 
0399     bit_off = sppctl_get_moon_reg_and_bit_offset(offset, &reg_off);
0400 
0401     spin_lock_irqsave(&spp_gchip->lock, flags);
0402 
0403     if (sppctl_gpio_get_direction(chip, offset))
0404         reg = sppctl_gpio_iinv_readl(spp_gchip, reg_off);
0405     else
0406         reg = sppctl_gpio_oinv_readl(spp_gchip, reg_off);
0407 
0408     spin_unlock_irqrestore(&spp_gchip->lock, flags);
0409 
0410     return (reg & BIT(bit_off)) ? 1 : 0;
0411 }
0412 
0413 static int sppctl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
0414 {
0415     struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
0416     unsigned long flags;
0417     u32 reg_off, reg;
0418 
0419     reg = sppctl_prep_moon_reg_and_offset(offset, &reg_off, 0);
0420 
0421     spin_lock_irqsave(&spp_gchip->lock, flags);
0422 
0423     sppctl_gpio_oe_writel(spp_gchip, reg, reg_off);
0424 
0425     spin_unlock_irqrestore(&spp_gchip->lock, flags);
0426     return 0;
0427 }
0428 
0429 static int sppctl_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int val)
0430 {
0431     struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
0432     unsigned long flags;
0433     u32 reg_off, reg;
0434 
0435     reg = sppctl_prep_moon_reg_and_offset(offset, &reg_off, 1);
0436 
0437     spin_lock_irqsave(&spp_gchip->lock, flags);
0438 
0439     sppctl_gpio_oe_writel(spp_gchip, reg, reg_off);
0440 
0441     if (val < 0) {
0442         spin_unlock_irqrestore(&spp_gchip->lock, flags);
0443         return 0;
0444     }
0445 
0446     reg = sppctl_prep_moon_reg_and_offset(offset, &reg_off, val);
0447     sppctl_gpio_out_writel(spp_gchip, reg, reg_off);
0448 
0449     spin_unlock_irqrestore(&spp_gchip->lock, flags);
0450     return 0;
0451 }
0452 
0453 static int sppctl_gpio_get(struct gpio_chip *chip, unsigned int offset)
0454 {
0455     struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
0456     u32 reg_off, bit_off, reg;
0457 
0458     bit_off = sppctl_get_reg_and_bit_offset(offset, &reg_off);
0459     reg = sppctl_gpio_in_readl(spp_gchip, reg_off);
0460 
0461     return (reg & BIT(bit_off)) ? 1 : 0;
0462 }
0463 
0464 static void sppctl_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
0465 {
0466     struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
0467     u32 reg_off, reg;
0468 
0469     reg = sppctl_prep_moon_reg_and_offset(offset, &reg_off, val);
0470     sppctl_gpio_out_writel(spp_gchip, reg, reg_off);
0471 }
0472 
0473 static int sppctl_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
0474                   unsigned long config)
0475 {
0476     enum pin_config_param param = pinconf_to_config_param(config);
0477     struct sppctl_gpio_chip *spp_gchip = gpiochip_get_data(chip);
0478     u32 reg_off, reg;
0479 
0480     switch (param) {
0481     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0482         reg = sppctl_prep_moon_reg_and_offset(offset, &reg_off, 1);
0483         sppctl_gpio_od_writel(spp_gchip, reg, reg_off);
0484         break;
0485 
0486     case PIN_CONFIG_INPUT_ENABLE:
0487         break;
0488 
0489     case PIN_CONFIG_OUTPUT:
0490         return sppctl_gpio_direction_output(chip, offset, 0);
0491 
0492     case PIN_CONFIG_PERSIST_STATE:
0493         return -ENOTSUPP;
0494 
0495     default:
0496         return -EINVAL;
0497     }
0498 
0499     return 0;
0500 }
0501 
0502 #ifdef CONFIG_DEBUG_FS
0503 static void sppctl_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
0504 {
0505     const char *label;
0506     int i;
0507 
0508     for (i = 0; i < chip->ngpio; i++) {
0509         label = gpiochip_is_requested(chip, i);
0510         if (!label)
0511             label = "";
0512 
0513         seq_printf(s, " gpio-%03d (%-16.16s | %-16.16s)", i + chip->base,
0514                chip->names[i], label);
0515         seq_printf(s, " %c", sppctl_gpio_get_direction(chip, i) ? 'I' : 'O');
0516         seq_printf(s, ":%d", sppctl_gpio_get(chip, i));
0517         seq_printf(s, " %s", sppctl_first_get(chip, i) ? "gpi" : "mux");
0518         seq_printf(s, " %s", sppctl_master_get(chip, i) ? "gpi" : "iop");
0519         seq_printf(s, " %s", sppctl_gpio_inv_get(chip, i) ? "inv" : "   ");
0520         seq_printf(s, " %s", sppctl_gpio_output_od_get(chip, i) ? "oDr" : "");
0521         seq_puts(s, "\n");
0522     }
0523 }
0524 #endif
0525 
0526 static int sppctl_gpio_new(struct platform_device *pdev, struct sppctl_pdata *pctl)
0527 {
0528     struct sppctl_gpio_chip *spp_gchip;
0529     struct gpio_chip *gchip;
0530     int err;
0531 
0532     spp_gchip = devm_kzalloc(&pdev->dev, sizeof(*spp_gchip), GFP_KERNEL);
0533     if (!spp_gchip)
0534         return -ENOMEM;
0535     pctl->spp_gchip = spp_gchip;
0536 
0537     spp_gchip->gpioxt_base  = pctl->gpioxt_base;
0538     spp_gchip->first_base   = pctl->first_base;
0539     spin_lock_init(&spp_gchip->lock);
0540 
0541     gchip                   = &spp_gchip->chip;
0542     gchip->label            = SPPCTL_MODULE_NAME;
0543     gchip->parent           = &pdev->dev;
0544     gchip->owner            = THIS_MODULE;
0545     gchip->request          = gpiochip_generic_request;
0546     gchip->free             = gpiochip_generic_free;
0547     gchip->get_direction    = sppctl_gpio_get_direction;
0548     gchip->direction_input  = sppctl_gpio_direction_input;
0549     gchip->direction_output = sppctl_gpio_direction_output;
0550     gchip->get              = sppctl_gpio_get;
0551     gchip->set              = sppctl_gpio_set;
0552     gchip->set_config       = sppctl_gpio_set_config;
0553 #ifdef CONFIG_DEBUG_FS
0554     gchip->dbg_show         = sppctl_gpio_dbg_show;
0555 #endif
0556     gchip->base             = -1;
0557     gchip->ngpio            = sppctl_gpio_list_sz;
0558     gchip->names            = sppctl_gpio_list_s;
0559     gchip->of_gpio_n_cells  = 2;
0560 
0561     pctl->pctl_grange.npins = gchip->ngpio;
0562     pctl->pctl_grange.name  = gchip->label;
0563     pctl->pctl_grange.gc    = gchip;
0564 
0565     err = devm_gpiochip_add_data(&pdev->dev, gchip, spp_gchip);
0566     if (err)
0567         return dev_err_probe(&pdev->dev, err, "Failed to add gpiochip!\n");
0568 
0569     return 0;
0570 }
0571 
0572 static int sppctl_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
0573                  unsigned long *config)
0574 {
0575     struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
0576     unsigned int param = pinconf_to_config_param(*config);
0577     unsigned int arg;
0578 
0579     switch (param) {
0580     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0581         if (!sppctl_gpio_output_od_get(&pctl->spp_gchip->chip, pin))
0582             return -EINVAL;
0583         arg = 0;
0584         break;
0585 
0586     case PIN_CONFIG_OUTPUT:
0587         if (!sppctl_first_get(&pctl->spp_gchip->chip, pin))
0588             return -EINVAL;
0589         if (!sppctl_master_get(&pctl->spp_gchip->chip, pin))
0590             return -EINVAL;
0591         if (sppctl_gpio_get_direction(&pctl->spp_gchip->chip, pin))
0592             return -EINVAL;
0593         arg = sppctl_gpio_get(&pctl->spp_gchip->chip, pin);
0594         break;
0595 
0596     default:
0597         return -EOPNOTSUPP;
0598     }
0599     *config = pinconf_to_config_packed(param, arg);
0600 
0601     return 0;
0602 }
0603 
0604 static int sppctl_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
0605                  unsigned long *configs, unsigned int num_configs)
0606 {
0607     struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
0608     int i;
0609 
0610     /* Special handling for IOP pins */
0611     if (configs[0] == SPPCTL_IOP_CONFIGS) {
0612         sppctl_first_master_set(&pctl->spp_gchip->chip, pin, mux_f_gpio, mux_m_iop);
0613         return 0;
0614     }
0615 
0616     for (i = 0; i < num_configs; i++) {
0617         if (configs[i] & SPPCTL_PCTL_L_OUT)
0618             sppctl_gpio_direction_output(&pctl->spp_gchip->chip, pin, 0);
0619         if (configs[i] & SPPCTL_PCTL_L_OU1)
0620             sppctl_gpio_direction_output(&pctl->spp_gchip->chip, pin, 1);
0621         if (configs[i] & SPPCTL_PCTL_L_INV)
0622             sppctl_gpio_input_inv_set(&pctl->spp_gchip->chip, pin);
0623         if (configs[i] & SPPCTL_PCTL_L_ONV)
0624             sppctl_gpio_output_inv_set(&pctl->spp_gchip->chip, pin);
0625         if (configs[i] & SPPCTL_PCTL_L_ODR)
0626             sppctl_gpio_output_od_set(&pctl->spp_gchip->chip, pin, 1);
0627     }
0628 
0629     return 0;
0630 }
0631 
0632 static const struct pinconf_ops sppctl_pconf_ops = {
0633     .is_generic     = true,
0634     .pin_config_get = sppctl_pin_config_get,
0635     .pin_config_set = sppctl_pin_config_set,
0636 };
0637 
0638 static int sppctl_get_functions_count(struct pinctrl_dev *pctldev)
0639 {
0640     return sppctl_list_funcs_sz;
0641 }
0642 
0643 static const char *sppctl_get_function_name(struct pinctrl_dev *pctldev,
0644                         unsigned int selector)
0645 {
0646     return sppctl_list_funcs[selector].name;
0647 }
0648 
0649 static int sppctl_get_function_groups(struct pinctrl_dev *pctldev, unsigned int selector,
0650                       const char * const **groups, unsigned int *num_groups)
0651 {
0652     struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
0653     const struct sppctl_func *f = &sppctl_list_funcs[selector];
0654     int i;
0655 
0656     *num_groups = 0;
0657     switch (f->type) {
0658     case pinmux_type_fpmx:
0659         *num_groups = sppctl_pmux_list_sz;
0660         *groups = sppctl_pmux_list_s;
0661         break;
0662 
0663     case pinmux_type_grp:
0664         if (!f->grps)
0665             break;
0666 
0667         *num_groups = f->gnum;
0668         for (i = 0; i < pctl->unq_grps_sz; i++)
0669             if (pctl->g2fp_maps[i].f_idx == selector)
0670                 break;
0671         *groups = &pctl->unq_grps[i];
0672         break;
0673 
0674     default:
0675         dev_err(pctldev->dev, "Unknown pinmux (selector: %d, type: %d)\n",
0676             selector, f->type);
0677         break;
0678     }
0679 
0680     return 0;
0681 }
0682 
0683 /**
0684  * sppctl_fully_pinmux_conv - Convert GPIO# to fully-pinmux control-field setting
0685  *
0686  * Each fully-pinmux function can be mapped to any of GPIO 8 ~ 71 by
0687  * settings its control-field. Refer to following table:
0688  *
0689  * control-field |  GPIO
0690  * --------------+--------
0691  *        0      |  No map
0692  *        1      |    8
0693  *        2      |    9
0694  *        3      |   10
0695  *        :      |    :
0696  *       65      |   71
0697  */
0698 static inline int sppctl_fully_pinmux_conv(unsigned int offset)
0699 {
0700     return (offset < 8) ? 0 : offset - 7;
0701 }
0702 
0703 static int sppctl_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
0704               unsigned int group_selector)
0705 {
0706     const struct sppctl_func *f = &sppctl_list_funcs[func_selector];
0707     struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
0708     struct grp2fp_map g2fpm = pctl->g2fp_maps[group_selector];
0709     int i;
0710 
0711     switch (f->type) {
0712     case pinmux_type_fpmx:
0713         sppctl_first_master_set(&pctl->spp_gchip->chip, group_selector,
0714                     mux_f_mux, mux_m_keep);
0715         sppctl_func_set(pctl, func_selector, sppctl_fully_pinmux_conv(group_selector));
0716         break;
0717 
0718     case pinmux_type_grp:
0719         for (i = 0; i < f->grps[g2fpm.g_idx].pnum; i++)
0720             sppctl_first_master_set(&pctl->spp_gchip->chip,
0721                         f->grps[g2fpm.g_idx].pins[i],
0722                         mux_f_mux, mux_m_keep);
0723         sppctl_gmx_set(pctl, f->roff, f->boff, f->blen, f->grps[g2fpm.g_idx].gval);
0724         break;
0725 
0726     default:
0727         dev_err(pctldev->dev, "Unknown pinmux type (func_selector: %d, type: %d)\n",
0728             func_selector, f->type);
0729         break;
0730     }
0731 
0732     return 0;
0733 }
0734 
0735 static int sppctl_gpio_request_enable(struct pinctrl_dev *pctldev,
0736                       struct pinctrl_gpio_range *range, unsigned int offset)
0737 {
0738     struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
0739     int g_f, g_m;
0740 
0741     g_f = sppctl_first_get(&pctl->spp_gchip->chip, offset);
0742     g_m = sppctl_master_get(&pctl->spp_gchip->chip, offset);
0743     if (g_f == mux_f_gpio && g_m == mux_m_gpio)
0744         return 0;
0745 
0746     sppctl_first_master_set(&pctl->spp_gchip->chip, offset, mux_f_gpio, mux_m_gpio);
0747     return 0;
0748 }
0749 
0750 static const struct pinmux_ops sppctl_pinmux_ops = {
0751     .get_functions_count = sppctl_get_functions_count,
0752     .get_function_name   = sppctl_get_function_name,
0753     .get_function_groups = sppctl_get_function_groups,
0754     .set_mux             = sppctl_set_mux,
0755     .gpio_request_enable = sppctl_gpio_request_enable,
0756     .strict              = true,
0757 };
0758 
0759 static int sppctl_get_groups_count(struct pinctrl_dev *pctldev)
0760 {
0761     struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
0762 
0763     return pctl->unq_grps_sz;
0764 }
0765 
0766 static const char *sppctl_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector)
0767 {
0768     struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
0769 
0770     return pctl->unq_grps[selector];
0771 }
0772 
0773 static int sppctl_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
0774                  const unsigned int **pins, unsigned int *num_pins)
0775 {
0776     struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
0777     struct grp2fp_map g2fpm = pctl->g2fp_maps[selector];
0778     const struct sppctl_func *f;
0779 
0780     f = &sppctl_list_funcs[g2fpm.f_idx];
0781     *num_pins = 0;
0782 
0783     /* Except group-pinmux, each group has 1 pin. */
0784     if (f->type != pinmux_type_grp) {
0785         *num_pins = 1;
0786         *pins = &sppctl_pins_gpio[selector];
0787         return 0;
0788     }
0789 
0790     /* Group-pinmux may have more than one pin. */
0791     if (!f->grps)
0792         return 0;
0793 
0794     if (f->gnum < 1)
0795         return 0;
0796 
0797     *num_pins = f->grps[g2fpm.g_idx].pnum;
0798     *pins = f->grps[g2fpm.g_idx].pins;
0799 
0800     return 0;
0801 }
0802 
0803 #ifdef CONFIG_DEBUG_FS
0804 static void sppctl_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
0805                 unsigned int offset)
0806 {
0807     struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
0808     const char *pin_type;
0809     u8 first, master;
0810 
0811     first = sppctl_first_get(&pctl->spp_gchip->chip, offset);
0812     master = sppctl_master_get(&pctl->spp_gchip->chip, offset);
0813     if (first)
0814         if (master)
0815             pin_type = "GPIO";
0816         else
0817             pin_type = " IOP";
0818     else
0819         pin_type = " MUX";
0820     seq_printf(s, " %s", pin_type);
0821 }
0822 #endif
0823 
0824 static int sppctl_dt_node_to_map(struct pinctrl_dev *pctldev, struct device_node *np_config,
0825                  struct pinctrl_map **map, unsigned int *num_maps)
0826 {
0827     struct sppctl_pdata *pctl = pinctrl_dev_get_drvdata(pctldev);
0828     int nmG = of_property_count_strings(np_config, "groups");
0829     const struct sppctl_func *f = NULL;
0830     u8 pin_num, pin_type, pin_func;
0831     struct device_node *parent;
0832     unsigned long *configs;
0833     struct property *prop;
0834     const char *s_f, *s_g;
0835 
0836     const __be32 *list;
0837     u32 dt_pin, dt_fun;
0838     int i, size = 0;
0839 
0840     list = of_get_property(np_config, "sunplus,pins", &size);
0841 
0842     if (nmG <= 0)
0843         nmG = 0;
0844 
0845     parent = of_get_parent(np_config);
0846     *num_maps = size / sizeof(*list);
0847 
0848     /*
0849      * Process property:
0850      *     sunplus,pins = < u32 u32 u32 ... >;
0851      *
0852      * Each 32-bit integer defines a individual pin in which:
0853      *
0854      *   Bit 32~24: defines GPIO pin number. Its range is 0 ~ 98.
0855      *   Bit 23~16: defines types: (1) fully-pinmux pins
0856      *                             (2) IO processor pins
0857      *                             (3) digital GPIO pins
0858      *   Bit 15~8:  defines pins of peripherals (which are defined in
0859      *              'include/dt-binging/pinctrl/sppctl.h').
0860      *   Bit 7~0:   defines types or initial-state of digital GPIO pins.
0861      */
0862     for (i = 0; i < (*num_maps); i++) {
0863         dt_pin = be32_to_cpu(list[i]);
0864         pin_num = FIELD_GET(GENMASK(31, 24), dt_pin);
0865 
0866         if (pin_num >= sppctl_pins_all_sz) {
0867             dev_err(pctldev->dev, "Invalid pin property at index %d (0x%08x)\n",
0868                 i, dt_pin);
0869             return -EINVAL;
0870         }
0871     }
0872 
0873     *map = kcalloc(*num_maps + nmG, sizeof(**map), GFP_KERNEL);
0874     if (*map == NULL)
0875         return -ENOMEM;
0876 
0877     for (i = 0; i < (*num_maps); i++) {
0878         dt_pin = be32_to_cpu(list[i]);
0879         pin_num = FIELD_GET(GENMASK(31, 24), dt_pin);
0880         pin_type = FIELD_GET(GENMASK(23, 16), dt_pin);
0881         pin_func = FIELD_GET(GENMASK(15, 8), dt_pin);
0882         (*map)[i].name = parent->name;
0883 
0884         if (pin_type == SPPCTL_PCTL_G_GPIO) {
0885             /* A digital GPIO pin */
0886             (*map)[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
0887             (*map)[i].data.configs.num_configs = 1;
0888             (*map)[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_num);
0889             configs = kmalloc(sizeof(*configs), GFP_KERNEL);
0890             *configs = FIELD_GET(GENMASK(7, 0), dt_pin);
0891             (*map)[i].data.configs.configs = configs;
0892 
0893             dev_dbg(pctldev->dev, "%s: GPIO (%s)\n",
0894                 (*map)[i].data.configs.group_or_pin,
0895                 (*configs & (SPPCTL_PCTL_L_OUT | SPPCTL_PCTL_L_OU1)) ?
0896                 "OUT" : "IN");
0897         } else if (pin_type == SPPCTL_PCTL_G_IOPP) {
0898             /* A IO Processor (IOP) pin */
0899             (*map)[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
0900             (*map)[i].data.configs.num_configs = 1;
0901             (*map)[i].data.configs.group_or_pin = pin_get_name(pctldev, pin_num);
0902             configs = kmalloc(sizeof(*configs), GFP_KERNEL);
0903             *configs = SPPCTL_IOP_CONFIGS;
0904             (*map)[i].data.configs.configs = configs;
0905 
0906             dev_dbg(pctldev->dev, "%s: IOP\n",
0907                 (*map)[i].data.configs.group_or_pin);
0908         } else {
0909             /* A fully-pinmux pin */
0910             (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP;
0911             (*map)[i].data.mux.function = sppctl_list_funcs[pin_func].name;
0912             (*map)[i].data.mux.group = pin_get_name(pctldev, pin_num);
0913 
0914             dev_dbg(pctldev->dev, "%s: %s\n", (*map)[i].data.mux.group,
0915                 (*map)[i].data.mux.function);
0916         }
0917     }
0918 
0919     /*
0920      * Process properties:
0921      *     function = "xxx";
0922      *     groups = "yyy";
0923      */
0924     if (nmG > 0 && of_property_read_string(np_config, "function", &s_f) == 0) {
0925         of_property_for_each_string(np_config, "groups", prop, s_g) {
0926             (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
0927             (*map)[*num_maps].data.mux.function = s_f;
0928             (*map)[*num_maps].data.mux.group = s_g;
0929             (*num_maps)++;
0930 
0931             dev_dbg(pctldev->dev, "%s: %s\n", s_f, s_g);
0932         }
0933     }
0934 
0935     /*
0936      * Process property:
0937      *     sunplus,zerofunc = < u32 u32 u32 ...>
0938      */
0939     list = of_get_property(np_config, "sunplus,zerofunc", &size);
0940     if (list) {
0941         for (i = 0; i < (size / sizeof(*list)); i++) {
0942             dt_fun = be32_to_cpu(list[i]);
0943             if (dt_fun >= sppctl_list_funcs_sz) {
0944                 dev_err(pctldev->dev, "Zero-func %d out of range!\n",
0945                     dt_fun);
0946                 continue;
0947             }
0948 
0949             f = &sppctl_list_funcs[dt_fun];
0950             switch (f->type) {
0951             case pinmux_type_fpmx:
0952                 sppctl_func_set(pctl, dt_fun, 0);
0953                 dev_dbg(pctldev->dev, "%s: No map\n", f->name);
0954                 break;
0955 
0956             case pinmux_type_grp:
0957                 sppctl_gmx_set(pctl, f->roff, f->boff, f->blen, 0);
0958                 dev_dbg(pctldev->dev, "%s: No map\n", f->name);
0959                 break;
0960 
0961             default:
0962                 dev_err(pctldev->dev, "Wrong zero-group: %d (%s)\n",
0963                     dt_fun, f->name);
0964                 break;
0965             }
0966         }
0967     }
0968 
0969     of_node_put(parent);
0970     dev_dbg(pctldev->dev, "%d pins mapped\n", *num_maps);
0971     return 0;
0972 }
0973 
0974 static const struct pinctrl_ops sppctl_pctl_ops = {
0975     .get_groups_count = sppctl_get_groups_count,
0976     .get_group_name   = sppctl_get_group_name,
0977     .get_group_pins   = sppctl_get_group_pins,
0978 #ifdef CONFIG_DEBUG_FS
0979     .pin_dbg_show     = sppctl_pin_dbg_show,
0980 #endif
0981     .dt_node_to_map   = sppctl_dt_node_to_map,
0982     .dt_free_map      = pinctrl_utils_free_map,
0983 };
0984 
0985 static int sppctl_group_groups(struct platform_device *pdev)
0986 {
0987     struct sppctl_pdata *sppctl = platform_get_drvdata(pdev);
0988     int i, k, j;
0989 
0990     /* Calculate number of total group (GPIO + group-pinmux group). */
0991     sppctl->unq_grps_sz = sppctl_gpio_list_sz;
0992     for (i = 0; i < sppctl_list_funcs_sz; i++)
0993         if (sppctl_list_funcs[i].type == pinmux_type_grp)
0994             sppctl->unq_grps_sz += sppctl_list_funcs[i].gnum;
0995 
0996     sppctl->unq_grps = devm_kcalloc(&pdev->dev, sppctl->unq_grps_sz + 1,
0997                     sizeof(*sppctl->unq_grps), GFP_KERNEL);
0998     if (!sppctl->unq_grps)
0999         return -ENOMEM;
1000 
1001     sppctl->g2fp_maps = devm_kcalloc(&pdev->dev, sppctl->unq_grps_sz + 1,
1002                      sizeof(*sppctl->g2fp_maps), GFP_KERNEL);
1003     if (!sppctl->g2fp_maps)
1004         return -ENOMEM;
1005 
1006     /* Add GPIO pins. */
1007     for (i = 0; i < sppctl_gpio_list_sz; i++) {
1008         sppctl->unq_grps[i] = sppctl_gpio_list_s[i];
1009         sppctl->g2fp_maps[i].f_idx = 0;
1010         sppctl->g2fp_maps[i].g_idx = i;
1011     }
1012 
1013     /* Add group-pinmux to end of GPIO pins. */
1014     j = sppctl_gpio_list_sz;
1015     for (i = 0; i < sppctl_list_funcs_sz; i++) {
1016         if (sppctl_list_funcs[i].type != pinmux_type_grp)
1017             continue;
1018 
1019         for (k = 0; k < sppctl_list_funcs[i].gnum; k++) {
1020             sppctl->unq_grps[j] = sppctl_list_funcs[i].grps[k].name;
1021             sppctl->g2fp_maps[j].f_idx = i;
1022             sppctl->g2fp_maps[j].g_idx = k;
1023             j++;
1024         }
1025     }
1026 
1027     return 0;
1028 }
1029 
1030 static int sppctl_pinctrl_init(struct platform_device *pdev)
1031 {
1032     struct sppctl_pdata *sppctl = platform_get_drvdata(pdev);
1033     int err;
1034 
1035     sppctl->pctl_desc.owner   = THIS_MODULE;
1036     sppctl->pctl_desc.name    = dev_name(&pdev->dev);
1037     sppctl->pctl_desc.pins    = sppctl_pins_all;
1038     sppctl->pctl_desc.npins   = sppctl_pins_all_sz;
1039     sppctl->pctl_desc.pctlops = &sppctl_pctl_ops;
1040     sppctl->pctl_desc.confops = &sppctl_pconf_ops;
1041     sppctl->pctl_desc.pmxops  = &sppctl_pinmux_ops;
1042 
1043     err = sppctl_group_groups(pdev);
1044     if (err)
1045         return err;
1046 
1047     err = devm_pinctrl_register_and_init(&pdev->dev, &sppctl->pctl_desc,
1048                          sppctl, &sppctl->pctl_dev);
1049     if (err)
1050         return dev_err_probe(&pdev->dev, err, "Failed to register pinctrl!\n");
1051 
1052     pinctrl_enable(sppctl->pctl_dev);
1053     return 0;
1054 }
1055 
1056 static int sppctl_resource_map(struct platform_device *pdev, struct sppctl_pdata *sppctl)
1057 {
1058     sppctl->moon2_base = devm_platform_ioremap_resource_byname(pdev, "moon2");
1059     if (IS_ERR(sppctl->moon2_base))
1060         return PTR_ERR(sppctl->moon2_base);
1061 
1062     sppctl->gpioxt_base = devm_platform_ioremap_resource_byname(pdev, "gpioxt");
1063     if (IS_ERR(sppctl->gpioxt_base))
1064         return PTR_ERR(sppctl->gpioxt_base);
1065 
1066     sppctl->first_base = devm_platform_ioremap_resource_byname(pdev, "first");
1067     if (IS_ERR(sppctl->first_base))
1068         return PTR_ERR(sppctl->first_base);
1069 
1070     sppctl->moon1_base = devm_platform_ioremap_resource_byname(pdev, "moon1");
1071     if (IS_ERR(sppctl->moon1_base))
1072         return PTR_ERR(sppctl->moon1_base);
1073 
1074     return 0;
1075 }
1076 
1077 static int sppctl_probe(struct platform_device *pdev)
1078 {
1079     struct sppctl_pdata *sppctl;
1080     int ret;
1081 
1082     sppctl = devm_kzalloc(&pdev->dev, sizeof(*sppctl), GFP_KERNEL);
1083     if (!sppctl)
1084         return -ENOMEM;
1085     platform_set_drvdata(pdev, sppctl);
1086 
1087     ret = sppctl_resource_map(pdev, sppctl);
1088     if (ret)
1089         return ret;
1090 
1091     ret = sppctl_gpio_new(pdev, sppctl);
1092     if (ret)
1093         return ret;
1094 
1095     ret = sppctl_pinctrl_init(pdev);
1096     if (ret)
1097         return ret;
1098 
1099     pinctrl_add_gpio_range(sppctl->pctl_dev, &sppctl->pctl_grange);
1100 
1101     return 0;
1102 }
1103 
1104 static const struct of_device_id sppctl_match_table[] = {
1105     { .compatible = "sunplus,sp7021-pctl" },
1106     { /* sentinel */ }
1107 };
1108 
1109 static struct platform_driver sppctl_pinctrl_driver = {
1110     .driver = {
1111         .name           = SPPCTL_MODULE_NAME,
1112         .of_match_table = sppctl_match_table,
1113     },
1114     .probe  = sppctl_probe,
1115 };
1116 builtin_platform_driver(sppctl_pinctrl_driver)
1117 
1118 MODULE_AUTHOR("Dvorkin Dmitry <dvorkin@tibbo.com>");
1119 MODULE_AUTHOR("Wells Lu <wellslutw@gmail.com>");
1120 MODULE_DESCRIPTION("Sunplus SP7021 Pin Control and GPIO driver");
1121 MODULE_LICENSE("GPL v2");
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