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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) Maxime Coquelin 2015
0004  * Copyright (C) STMicroelectronics 2017
0005  * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
0006  *
0007  * Heavily based on Mediatek's pinctrl driver
0008  */
0009 #include <linux/clk.h>
0010 #include <linux/gpio/driver.h>
0011 #include <linux/hwspinlock.h>
0012 #include <linux/io.h>
0013 #include <linux/irq.h>
0014 #include <linux/mfd/syscon.h>
0015 #include <linux/module.h>
0016 #include <linux/of.h>
0017 #include <linux/of_address.h>
0018 #include <linux/of_device.h>
0019 #include <linux/of_irq.h>
0020 #include <linux/pinctrl/consumer.h>
0021 #include <linux/pinctrl/machine.h>
0022 #include <linux/pinctrl/pinconf.h>
0023 #include <linux/pinctrl/pinconf-generic.h>
0024 #include <linux/pinctrl/pinctrl.h>
0025 #include <linux/pinctrl/pinmux.h>
0026 #include <linux/platform_device.h>
0027 #include <linux/property.h>
0028 #include <linux/regmap.h>
0029 #include <linux/reset.h>
0030 #include <linux/slab.h>
0031 
0032 #include "../core.h"
0033 #include "../pinconf.h"
0034 #include "../pinctrl-utils.h"
0035 #include "pinctrl-stm32.h"
0036 
0037 #define STM32_GPIO_MODER    0x00
0038 #define STM32_GPIO_TYPER    0x04
0039 #define STM32_GPIO_SPEEDR   0x08
0040 #define STM32_GPIO_PUPDR    0x0c
0041 #define STM32_GPIO_IDR      0x10
0042 #define STM32_GPIO_ODR      0x14
0043 #define STM32_GPIO_BSRR     0x18
0044 #define STM32_GPIO_LCKR     0x1c
0045 #define STM32_GPIO_AFRL     0x20
0046 #define STM32_GPIO_AFRH     0x24
0047 #define STM32_GPIO_SECCFGR  0x30
0048 
0049 /* custom bitfield to backup pin status */
0050 #define STM32_GPIO_BKP_MODE_SHIFT   0
0051 #define STM32_GPIO_BKP_MODE_MASK    GENMASK(1, 0)
0052 #define STM32_GPIO_BKP_ALT_SHIFT    2
0053 #define STM32_GPIO_BKP_ALT_MASK     GENMASK(5, 2)
0054 #define STM32_GPIO_BKP_SPEED_SHIFT  6
0055 #define STM32_GPIO_BKP_SPEED_MASK   GENMASK(7, 6)
0056 #define STM32_GPIO_BKP_PUPD_SHIFT   8
0057 #define STM32_GPIO_BKP_PUPD_MASK    GENMASK(9, 8)
0058 #define STM32_GPIO_BKP_TYPE     10
0059 #define STM32_GPIO_BKP_VAL      11
0060 
0061 #define STM32_GPIO_PINS_PER_BANK 16
0062 #define STM32_GPIO_IRQ_LINE  16
0063 
0064 #define SYSCFG_IRQMUX_MASK GENMASK(3, 0)
0065 
0066 #define gpio_range_to_bank(chip) \
0067         container_of(chip, struct stm32_gpio_bank, range)
0068 
0069 #define HWSPNLCK_TIMEOUT    1000 /* usec */
0070 
0071 static const char * const stm32_gpio_functions[] = {
0072     "gpio", "af0", "af1",
0073     "af2", "af3", "af4",
0074     "af5", "af6", "af7",
0075     "af8", "af9", "af10",
0076     "af11", "af12", "af13",
0077     "af14", "af15", "analog",
0078 };
0079 
0080 struct stm32_pinctrl_group {
0081     const char *name;
0082     unsigned long config;
0083     unsigned pin;
0084 };
0085 
0086 struct stm32_gpio_bank {
0087     void __iomem *base;
0088     struct clk *clk;
0089     struct reset_control *rstc;
0090     spinlock_t lock;
0091     struct gpio_chip gpio_chip;
0092     struct pinctrl_gpio_range range;
0093     struct fwnode_handle *fwnode;
0094     struct irq_domain *domain;
0095     u32 bank_nr;
0096     u32 bank_ioport_nr;
0097     u32 pin_backup[STM32_GPIO_PINS_PER_BANK];
0098     u8 irq_type[STM32_GPIO_PINS_PER_BANK];
0099     bool secure_control;
0100 };
0101 
0102 struct stm32_pinctrl {
0103     struct device *dev;
0104     struct pinctrl_dev *pctl_dev;
0105     struct pinctrl_desc pctl_desc;
0106     struct stm32_pinctrl_group *groups;
0107     unsigned ngroups;
0108     const char **grp_names;
0109     struct stm32_gpio_bank *banks;
0110     unsigned nbanks;
0111     const struct stm32_pinctrl_match_data *match_data;
0112     struct irq_domain   *domain;
0113     struct regmap       *regmap;
0114     struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK];
0115     struct hwspinlock *hwlock;
0116     struct stm32_desc_pin *pins;
0117     u32 npins;
0118     u32 pkg;
0119     u16 irqmux_map;
0120     spinlock_t irqmux_lock;
0121 };
0122 
0123 static inline int stm32_gpio_pin(int gpio)
0124 {
0125     return gpio % STM32_GPIO_PINS_PER_BANK;
0126 }
0127 
0128 static inline u32 stm32_gpio_get_mode(u32 function)
0129 {
0130     switch (function) {
0131     case STM32_PIN_GPIO:
0132         return 0;
0133     case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
0134         return 2;
0135     case STM32_PIN_ANALOG:
0136         return 3;
0137     }
0138 
0139     return 0;
0140 }
0141 
0142 static inline u32 stm32_gpio_get_alt(u32 function)
0143 {
0144     switch (function) {
0145     case STM32_PIN_GPIO:
0146         return 0;
0147     case STM32_PIN_AF(0) ... STM32_PIN_AF(15):
0148         return function - 1;
0149     case STM32_PIN_ANALOG:
0150         return 0;
0151     }
0152 
0153     return 0;
0154 }
0155 
0156 static void stm32_gpio_backup_value(struct stm32_gpio_bank *bank,
0157                     u32 offset, u32 value)
0158 {
0159     bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL);
0160     bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL;
0161 }
0162 
0163 static void stm32_gpio_backup_mode(struct stm32_gpio_bank *bank, u32 offset,
0164                    u32 mode, u32 alt)
0165 {
0166     bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK |
0167                       STM32_GPIO_BKP_ALT_MASK);
0168     bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT;
0169     bank->pin_backup[offset] |= alt << STM32_GPIO_BKP_ALT_SHIFT;
0170 }
0171 
0172 static void stm32_gpio_backup_driving(struct stm32_gpio_bank *bank, u32 offset,
0173                       u32 drive)
0174 {
0175     bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_TYPE);
0176     bank->pin_backup[offset] |= drive << STM32_GPIO_BKP_TYPE;
0177 }
0178 
0179 static void stm32_gpio_backup_speed(struct stm32_gpio_bank *bank, u32 offset,
0180                     u32 speed)
0181 {
0182     bank->pin_backup[offset] &= ~STM32_GPIO_BKP_SPEED_MASK;
0183     bank->pin_backup[offset] |= speed << STM32_GPIO_BKP_SPEED_SHIFT;
0184 }
0185 
0186 static void stm32_gpio_backup_bias(struct stm32_gpio_bank *bank, u32 offset,
0187                    u32 bias)
0188 {
0189     bank->pin_backup[offset] &= ~STM32_GPIO_BKP_PUPD_MASK;
0190     bank->pin_backup[offset] |= bias << STM32_GPIO_BKP_PUPD_SHIFT;
0191 }
0192 
0193 /* GPIO functions */
0194 
0195 static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank,
0196     unsigned offset, int value)
0197 {
0198     stm32_gpio_backup_value(bank, offset, value);
0199 
0200     if (!value)
0201         offset += STM32_GPIO_PINS_PER_BANK;
0202 
0203     writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR);
0204 }
0205 
0206 static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset)
0207 {
0208     struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
0209     struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
0210     struct pinctrl_gpio_range *range;
0211     int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK);
0212 
0213     range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin);
0214     if (!range) {
0215         dev_err(pctl->dev, "pin %d not in range.\n", pin);
0216         return -EINVAL;
0217     }
0218 
0219     return pinctrl_gpio_request(chip->base + offset);
0220 }
0221 
0222 static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset)
0223 {
0224     pinctrl_gpio_free(chip->base + offset);
0225 }
0226 
0227 static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset)
0228 {
0229     struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
0230 
0231     return !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset));
0232 }
0233 
0234 static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
0235 {
0236     struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
0237 
0238     __stm32_gpio_set(bank, offset, value);
0239 }
0240 
0241 static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
0242 {
0243     return pinctrl_gpio_direction_input(chip->base + offset);
0244 }
0245 
0246 static int stm32_gpio_direction_output(struct gpio_chip *chip,
0247     unsigned offset, int value)
0248 {
0249     struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
0250 
0251     __stm32_gpio_set(bank, offset, value);
0252     pinctrl_gpio_direction_output(chip->base + offset);
0253 
0254     return 0;
0255 }
0256 
0257 
0258 static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
0259 {
0260     struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
0261     struct irq_fwspec fwspec;
0262 
0263     fwspec.fwnode = bank->fwnode;
0264     fwspec.param_count = 2;
0265     fwspec.param[0] = offset;
0266     fwspec.param[1] = IRQ_TYPE_NONE;
0267 
0268     return irq_create_fwspec_mapping(&fwspec);
0269 }
0270 
0271 static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
0272 {
0273     struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
0274     int pin = stm32_gpio_pin(offset);
0275     int ret;
0276     u32 mode, alt;
0277 
0278     stm32_pmx_get_mode(bank, pin, &mode, &alt);
0279     if ((alt == 0) && (mode == 0))
0280         ret = GPIO_LINE_DIRECTION_IN;
0281     else if ((alt == 0) && (mode == 1))
0282         ret = GPIO_LINE_DIRECTION_OUT;
0283     else
0284         ret = -EINVAL;
0285 
0286     return ret;
0287 }
0288 
0289 static int stm32_gpio_init_valid_mask(struct gpio_chip *chip,
0290                       unsigned long *valid_mask,
0291                       unsigned int ngpios)
0292 {
0293     struct stm32_gpio_bank *bank = gpiochip_get_data(chip);
0294     struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
0295     unsigned int i;
0296     u32 sec;
0297 
0298     /* All gpio are valid per default */
0299     bitmap_fill(valid_mask, ngpios);
0300 
0301     if (bank->secure_control) {
0302         /* Tag secured pins as invalid */
0303         sec = readl_relaxed(bank->base + STM32_GPIO_SECCFGR);
0304 
0305         for (i = 0; i < ngpios; i++) {
0306             if (sec & BIT(i)) {
0307                 clear_bit(i, valid_mask);
0308                 dev_dbg(pctl->dev, "No access to gpio %d - %d\n", bank->bank_nr, i);
0309             }
0310         }
0311     }
0312 
0313     return 0;
0314 }
0315 
0316 static const struct gpio_chip stm32_gpio_template = {
0317     .request        = stm32_gpio_request,
0318     .free           = stm32_gpio_free,
0319     .get            = stm32_gpio_get,
0320     .set            = stm32_gpio_set,
0321     .direction_input    = stm32_gpio_direction_input,
0322     .direction_output   = stm32_gpio_direction_output,
0323     .to_irq         = stm32_gpio_to_irq,
0324     .get_direction      = stm32_gpio_get_direction,
0325     .set_config     = gpiochip_generic_config,
0326     .init_valid_mask    = stm32_gpio_init_valid_mask,
0327 };
0328 
0329 static void stm32_gpio_irq_trigger(struct irq_data *d)
0330 {
0331     struct stm32_gpio_bank *bank = d->domain->host_data;
0332     int level;
0333 
0334     /* Do not access the GPIO if this is not LEVEL triggered IRQ. */
0335     if (!(bank->irq_type[d->hwirq] & IRQ_TYPE_LEVEL_MASK))
0336         return;
0337 
0338     /* If level interrupt type then retrig */
0339     level = stm32_gpio_get(&bank->gpio_chip, d->hwirq);
0340     if ((level == 0 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_LOW) ||
0341         (level == 1 && bank->irq_type[d->hwirq] == IRQ_TYPE_LEVEL_HIGH))
0342         irq_chip_retrigger_hierarchy(d);
0343 }
0344 
0345 static void stm32_gpio_irq_eoi(struct irq_data *d)
0346 {
0347     irq_chip_eoi_parent(d);
0348     stm32_gpio_irq_trigger(d);
0349 };
0350 
0351 static int stm32_gpio_set_type(struct irq_data *d, unsigned int type)
0352 {
0353     struct stm32_gpio_bank *bank = d->domain->host_data;
0354     u32 parent_type;
0355 
0356     switch (type) {
0357     case IRQ_TYPE_EDGE_RISING:
0358     case IRQ_TYPE_EDGE_FALLING:
0359     case IRQ_TYPE_EDGE_BOTH:
0360         parent_type = type;
0361         break;
0362     case IRQ_TYPE_LEVEL_HIGH:
0363         parent_type = IRQ_TYPE_EDGE_RISING;
0364         break;
0365     case IRQ_TYPE_LEVEL_LOW:
0366         parent_type = IRQ_TYPE_EDGE_FALLING;
0367         break;
0368     default:
0369         return -EINVAL;
0370     }
0371 
0372     bank->irq_type[d->hwirq] = type;
0373 
0374     return irq_chip_set_type_parent(d, parent_type);
0375 };
0376 
0377 static int stm32_gpio_irq_request_resources(struct irq_data *irq_data)
0378 {
0379     struct stm32_gpio_bank *bank = irq_data->domain->host_data;
0380     struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
0381     int ret;
0382 
0383     ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq);
0384     if (ret)
0385         return ret;
0386 
0387     ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq);
0388     if (ret) {
0389         dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
0390             irq_data->hwirq);
0391         return ret;
0392     }
0393 
0394     return 0;
0395 }
0396 
0397 static void stm32_gpio_irq_release_resources(struct irq_data *irq_data)
0398 {
0399     struct stm32_gpio_bank *bank = irq_data->domain->host_data;
0400 
0401     gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq);
0402 }
0403 
0404 static void stm32_gpio_irq_unmask(struct irq_data *d)
0405 {
0406     irq_chip_unmask_parent(d);
0407     stm32_gpio_irq_trigger(d);
0408 }
0409 
0410 static struct irq_chip stm32_gpio_irq_chip = {
0411     .name       = "stm32gpio",
0412     .irq_eoi    = stm32_gpio_irq_eoi,
0413     .irq_ack    = irq_chip_ack_parent,
0414     .irq_mask   = irq_chip_mask_parent,
0415     .irq_unmask = stm32_gpio_irq_unmask,
0416     .irq_set_type   = stm32_gpio_set_type,
0417     .irq_set_wake   = irq_chip_set_wake_parent,
0418     .irq_request_resources = stm32_gpio_irq_request_resources,
0419     .irq_release_resources = stm32_gpio_irq_release_resources,
0420 };
0421 
0422 static int stm32_gpio_domain_translate(struct irq_domain *d,
0423                        struct irq_fwspec *fwspec,
0424                        unsigned long *hwirq,
0425                        unsigned int *type)
0426 {
0427     if ((fwspec->param_count != 2) ||
0428         (fwspec->param[0] >= STM32_GPIO_IRQ_LINE))
0429         return -EINVAL;
0430 
0431     *hwirq = fwspec->param[0];
0432     *type = fwspec->param[1];
0433     return 0;
0434 }
0435 
0436 static int stm32_gpio_domain_activate(struct irq_domain *d,
0437                       struct irq_data *irq_data, bool reserve)
0438 {
0439     struct stm32_gpio_bank *bank = d->host_data;
0440     struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
0441     int ret = 0;
0442 
0443     if (pctl->hwlock) {
0444         ret = hwspin_lock_timeout_in_atomic(pctl->hwlock,
0445                             HWSPNLCK_TIMEOUT);
0446         if (ret) {
0447             dev_err(pctl->dev, "Can't get hwspinlock\n");
0448             return ret;
0449         }
0450     }
0451 
0452     regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_ioport_nr);
0453 
0454     if (pctl->hwlock)
0455         hwspin_unlock_in_atomic(pctl->hwlock);
0456 
0457     return ret;
0458 }
0459 
0460 static int stm32_gpio_domain_alloc(struct irq_domain *d,
0461                    unsigned int virq,
0462                    unsigned int nr_irqs, void *data)
0463 {
0464     struct stm32_gpio_bank *bank = d->host_data;
0465     struct irq_fwspec *fwspec = data;
0466     struct irq_fwspec parent_fwspec;
0467     struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
0468     irq_hw_number_t hwirq = fwspec->param[0];
0469     unsigned long flags;
0470     int ret = 0;
0471 
0472     /*
0473      * Check first that the IRQ MUX of that line is free.
0474      * gpio irq mux is shared between several banks, protect with a lock
0475      */
0476     spin_lock_irqsave(&pctl->irqmux_lock, flags);
0477 
0478     if (pctl->irqmux_map & BIT(hwirq)) {
0479         dev_err(pctl->dev, "irq line %ld already requested.\n", hwirq);
0480         ret = -EBUSY;
0481     } else {
0482         pctl->irqmux_map |= BIT(hwirq);
0483     }
0484 
0485     spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
0486     if (ret)
0487         return ret;
0488 
0489     parent_fwspec.fwnode = d->parent->fwnode;
0490     parent_fwspec.param_count = 2;
0491     parent_fwspec.param[0] = fwspec->param[0];
0492     parent_fwspec.param[1] = fwspec->param[1];
0493 
0494     irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip,
0495                       bank);
0496 
0497     return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec);
0498 }
0499 
0500 static void stm32_gpio_domain_free(struct irq_domain *d, unsigned int virq,
0501                    unsigned int nr_irqs)
0502 {
0503     struct stm32_gpio_bank *bank = d->host_data;
0504     struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
0505     struct irq_data *irq_data = irq_domain_get_irq_data(d, virq);
0506     unsigned long flags, hwirq = irq_data->hwirq;
0507 
0508     irq_domain_free_irqs_common(d, virq, nr_irqs);
0509 
0510     spin_lock_irqsave(&pctl->irqmux_lock, flags);
0511     pctl->irqmux_map &= ~BIT(hwirq);
0512     spin_unlock_irqrestore(&pctl->irqmux_lock, flags);
0513 }
0514 
0515 static const struct irq_domain_ops stm32_gpio_domain_ops = {
0516     .translate  = stm32_gpio_domain_translate,
0517     .alloc      = stm32_gpio_domain_alloc,
0518     .free       = stm32_gpio_domain_free,
0519     .activate   = stm32_gpio_domain_activate,
0520 };
0521 
0522 /* Pinctrl functions */
0523 static struct stm32_pinctrl_group *
0524 stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin)
0525 {
0526     int i;
0527 
0528     for (i = 0; i < pctl->ngroups; i++) {
0529         struct stm32_pinctrl_group *grp = pctl->groups + i;
0530 
0531         if (grp->pin == pin)
0532             return grp;
0533     }
0534 
0535     return NULL;
0536 }
0537 
0538 static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl,
0539         u32 pin_num, u32 fnum)
0540 {
0541     int i, k;
0542 
0543     for (i = 0; i < pctl->npins; i++) {
0544         const struct stm32_desc_pin *pin = pctl->pins + i;
0545         const struct stm32_desc_function *func = pin->functions;
0546 
0547         if (pin->pin.number != pin_num)
0548             continue;
0549 
0550         for (k = 0; k < STM32_CONFIG_NUM; k++) {
0551             if (func->num == fnum)
0552                 return true;
0553             func++;
0554         }
0555 
0556         break;
0557     }
0558 
0559     dev_err(pctl->dev, "invalid function %d on pin %d .\n", fnum, pin_num);
0560 
0561     return false;
0562 }
0563 
0564 static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl,
0565         u32 pin, u32 fnum, struct stm32_pinctrl_group *grp,
0566         struct pinctrl_map **map, unsigned *reserved_maps,
0567         unsigned *num_maps)
0568 {
0569     if (*num_maps == *reserved_maps)
0570         return -ENOSPC;
0571 
0572     (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
0573     (*map)[*num_maps].data.mux.group = grp->name;
0574 
0575     if (!stm32_pctrl_is_function_valid(pctl, pin, fnum))
0576         return -EINVAL;
0577 
0578     (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum];
0579     (*num_maps)++;
0580 
0581     return 0;
0582 }
0583 
0584 static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
0585                       struct device_node *node,
0586                       struct pinctrl_map **map,
0587                       unsigned *reserved_maps,
0588                       unsigned *num_maps)
0589 {
0590     struct stm32_pinctrl *pctl;
0591     struct stm32_pinctrl_group *grp;
0592     struct property *pins;
0593     u32 pinfunc, pin, func;
0594     unsigned long *configs;
0595     unsigned int num_configs;
0596     bool has_config = 0;
0597     unsigned reserve = 0;
0598     int num_pins, num_funcs, maps_per_pin, i, err = 0;
0599 
0600     pctl = pinctrl_dev_get_drvdata(pctldev);
0601 
0602     pins = of_find_property(node, "pinmux", NULL);
0603     if (!pins) {
0604         dev_err(pctl->dev, "missing pins property in node %pOFn .\n",
0605                 node);
0606         return -EINVAL;
0607     }
0608 
0609     err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
0610         &num_configs);
0611     if (err)
0612         return err;
0613 
0614     if (num_configs)
0615         has_config = 1;
0616 
0617     num_pins = pins->length / sizeof(u32);
0618     num_funcs = num_pins;
0619     maps_per_pin = 0;
0620     if (num_funcs)
0621         maps_per_pin++;
0622     if (has_config && num_pins >= 1)
0623         maps_per_pin++;
0624 
0625     if (!num_pins || !maps_per_pin) {
0626         err = -EINVAL;
0627         goto exit;
0628     }
0629 
0630     reserve = num_pins * maps_per_pin;
0631 
0632     err = pinctrl_utils_reserve_map(pctldev, map,
0633             reserved_maps, num_maps, reserve);
0634     if (err)
0635         goto exit;
0636 
0637     for (i = 0; i < num_pins; i++) {
0638         err = of_property_read_u32_index(node, "pinmux",
0639                 i, &pinfunc);
0640         if (err)
0641             goto exit;
0642 
0643         pin = STM32_GET_PIN_NO(pinfunc);
0644         func = STM32_GET_PIN_FUNC(pinfunc);
0645 
0646         if (!stm32_pctrl_is_function_valid(pctl, pin, func)) {
0647             err = -EINVAL;
0648             goto exit;
0649         }
0650 
0651         grp = stm32_pctrl_find_group_by_pin(pctl, pin);
0652         if (!grp) {
0653             dev_err(pctl->dev, "unable to match pin %d to group\n",
0654                     pin);
0655             err = -EINVAL;
0656             goto exit;
0657         }
0658 
0659         err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
0660                 reserved_maps, num_maps);
0661         if (err)
0662             goto exit;
0663 
0664         if (has_config) {
0665             err = pinctrl_utils_add_map_configs(pctldev, map,
0666                     reserved_maps, num_maps, grp->name,
0667                     configs, num_configs,
0668                     PIN_MAP_TYPE_CONFIGS_GROUP);
0669             if (err)
0670                 goto exit;
0671         }
0672     }
0673 
0674 exit:
0675     kfree(configs);
0676     return err;
0677 }
0678 
0679 static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
0680                  struct device_node *np_config,
0681                  struct pinctrl_map **map, unsigned *num_maps)
0682 {
0683     struct device_node *np;
0684     unsigned reserved_maps;
0685     int ret;
0686 
0687     *map = NULL;
0688     *num_maps = 0;
0689     reserved_maps = 0;
0690 
0691     for_each_child_of_node(np_config, np) {
0692         ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map,
0693                 &reserved_maps, num_maps);
0694         if (ret < 0) {
0695             pinctrl_utils_free_map(pctldev, *map, *num_maps);
0696             of_node_put(np);
0697             return ret;
0698         }
0699     }
0700 
0701     return 0;
0702 }
0703 
0704 static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
0705 {
0706     struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0707 
0708     return pctl->ngroups;
0709 }
0710 
0711 static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev,
0712                           unsigned group)
0713 {
0714     struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0715 
0716     return pctl->groups[group].name;
0717 }
0718 
0719 static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
0720                       unsigned group,
0721                       const unsigned **pins,
0722                       unsigned *num_pins)
0723 {
0724     struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0725 
0726     *pins = (unsigned *)&pctl->groups[group].pin;
0727     *num_pins = 1;
0728 
0729     return 0;
0730 }
0731 
0732 static const struct pinctrl_ops stm32_pctrl_ops = {
0733     .dt_node_to_map     = stm32_pctrl_dt_node_to_map,
0734     .dt_free_map        = pinctrl_utils_free_map,
0735     .get_groups_count   = stm32_pctrl_get_groups_count,
0736     .get_group_name     = stm32_pctrl_get_group_name,
0737     .get_group_pins     = stm32_pctrl_get_group_pins,
0738 };
0739 
0740 
0741 /* Pinmux functions */
0742 
0743 static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
0744 {
0745     return ARRAY_SIZE(stm32_gpio_functions);
0746 }
0747 
0748 static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev,
0749                        unsigned selector)
0750 {
0751     return stm32_gpio_functions[selector];
0752 }
0753 
0754 static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev,
0755                      unsigned function,
0756                      const char * const **groups,
0757                      unsigned * const num_groups)
0758 {
0759     struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0760 
0761     *groups = pctl->grp_names;
0762     *num_groups = pctl->ngroups;
0763 
0764     return 0;
0765 }
0766 
0767 static int stm32_pmx_set_mode(struct stm32_gpio_bank *bank,
0768                   int pin, u32 mode, u32 alt)
0769 {
0770     struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
0771     u32 val;
0772     int alt_shift = (pin % 8) * 4;
0773     int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
0774     unsigned long flags;
0775     int err = 0;
0776 
0777     spin_lock_irqsave(&bank->lock, flags);
0778 
0779     if (pctl->hwlock) {
0780         err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
0781                             HWSPNLCK_TIMEOUT);
0782         if (err) {
0783             dev_err(pctl->dev, "Can't get hwspinlock\n");
0784             goto unlock;
0785         }
0786     }
0787 
0788     val = readl_relaxed(bank->base + alt_offset);
0789     val &= ~GENMASK(alt_shift + 3, alt_shift);
0790     val |= (alt << alt_shift);
0791     writel_relaxed(val, bank->base + alt_offset);
0792 
0793     val = readl_relaxed(bank->base + STM32_GPIO_MODER);
0794     val &= ~GENMASK(pin * 2 + 1, pin * 2);
0795     val |= mode << (pin * 2);
0796     writel_relaxed(val, bank->base + STM32_GPIO_MODER);
0797 
0798     if (pctl->hwlock)
0799         hwspin_unlock_in_atomic(pctl->hwlock);
0800 
0801     stm32_gpio_backup_mode(bank, pin, mode, alt);
0802 
0803 unlock:
0804     spin_unlock_irqrestore(&bank->lock, flags);
0805 
0806     return err;
0807 }
0808 
0809 void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode,
0810             u32 *alt)
0811 {
0812     u32 val;
0813     int alt_shift = (pin % 8) * 4;
0814     int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4;
0815     unsigned long flags;
0816 
0817     spin_lock_irqsave(&bank->lock, flags);
0818 
0819     val = readl_relaxed(bank->base + alt_offset);
0820     val &= GENMASK(alt_shift + 3, alt_shift);
0821     *alt = val >> alt_shift;
0822 
0823     val = readl_relaxed(bank->base + STM32_GPIO_MODER);
0824     val &= GENMASK(pin * 2 + 1, pin * 2);
0825     *mode = val >> (pin * 2);
0826 
0827     spin_unlock_irqrestore(&bank->lock, flags);
0828 }
0829 
0830 static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev,
0831                 unsigned function,
0832                 unsigned group)
0833 {
0834     bool ret;
0835     struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0836     struct stm32_pinctrl_group *g = pctl->groups + group;
0837     struct pinctrl_gpio_range *range;
0838     struct stm32_gpio_bank *bank;
0839     u32 mode, alt;
0840     int pin;
0841 
0842     ret = stm32_pctrl_is_function_valid(pctl, g->pin, function);
0843     if (!ret)
0844         return -EINVAL;
0845 
0846     range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin);
0847     if (!range) {
0848         dev_err(pctl->dev, "No gpio range defined.\n");
0849         return -EINVAL;
0850     }
0851 
0852     bank = gpiochip_get_data(range->gc);
0853     pin = stm32_gpio_pin(g->pin);
0854 
0855     mode = stm32_gpio_get_mode(function);
0856     alt = stm32_gpio_get_alt(function);
0857 
0858     return stm32_pmx_set_mode(bank, pin, mode, alt);
0859 }
0860 
0861 static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
0862             struct pinctrl_gpio_range *range, unsigned gpio,
0863             bool input)
0864 {
0865     struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc);
0866     int pin = stm32_gpio_pin(gpio);
0867 
0868     return stm32_pmx_set_mode(bank, pin, !input, 0);
0869 }
0870 
0871 static int stm32_pmx_request(struct pinctrl_dev *pctldev, unsigned int gpio)
0872 {
0873     struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0874     struct pinctrl_gpio_range *range;
0875 
0876     range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, gpio);
0877     if (!range) {
0878         dev_err(pctl->dev, "No gpio range defined.\n");
0879         return -EINVAL;
0880     }
0881 
0882     if (!gpiochip_line_is_valid(range->gc, stm32_gpio_pin(gpio))) {
0883         dev_warn(pctl->dev, "Can't access gpio %d\n", gpio);
0884         return -EACCES;
0885     }
0886 
0887     return 0;
0888 }
0889 
0890 static const struct pinmux_ops stm32_pmx_ops = {
0891     .get_functions_count    = stm32_pmx_get_funcs_cnt,
0892     .get_function_name  = stm32_pmx_get_func_name,
0893     .get_function_groups    = stm32_pmx_get_func_groups,
0894     .set_mux        = stm32_pmx_set_mux,
0895     .gpio_set_direction = stm32_pmx_gpio_set_direction,
0896     .request        = stm32_pmx_request,
0897     .strict         = true,
0898 };
0899 
0900 /* Pinconf functions */
0901 
0902 static int stm32_pconf_set_driving(struct stm32_gpio_bank *bank,
0903                    unsigned offset, u32 drive)
0904 {
0905     struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
0906     unsigned long flags;
0907     u32 val;
0908     int err = 0;
0909 
0910     spin_lock_irqsave(&bank->lock, flags);
0911 
0912     if (pctl->hwlock) {
0913         err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
0914                             HWSPNLCK_TIMEOUT);
0915         if (err) {
0916             dev_err(pctl->dev, "Can't get hwspinlock\n");
0917             goto unlock;
0918         }
0919     }
0920 
0921     val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
0922     val &= ~BIT(offset);
0923     val |= drive << offset;
0924     writel_relaxed(val, bank->base + STM32_GPIO_TYPER);
0925 
0926     if (pctl->hwlock)
0927         hwspin_unlock_in_atomic(pctl->hwlock);
0928 
0929     stm32_gpio_backup_driving(bank, offset, drive);
0930 
0931 unlock:
0932     spin_unlock_irqrestore(&bank->lock, flags);
0933 
0934     return err;
0935 }
0936 
0937 static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank,
0938     unsigned int offset)
0939 {
0940     unsigned long flags;
0941     u32 val;
0942 
0943     spin_lock_irqsave(&bank->lock, flags);
0944 
0945     val = readl_relaxed(bank->base + STM32_GPIO_TYPER);
0946     val &= BIT(offset);
0947 
0948     spin_unlock_irqrestore(&bank->lock, flags);
0949 
0950     return (val >> offset);
0951 }
0952 
0953 static int stm32_pconf_set_speed(struct stm32_gpio_bank *bank,
0954                  unsigned offset, u32 speed)
0955 {
0956     struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
0957     unsigned long flags;
0958     u32 val;
0959     int err = 0;
0960 
0961     spin_lock_irqsave(&bank->lock, flags);
0962 
0963     if (pctl->hwlock) {
0964         err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
0965                             HWSPNLCK_TIMEOUT);
0966         if (err) {
0967             dev_err(pctl->dev, "Can't get hwspinlock\n");
0968             goto unlock;
0969         }
0970     }
0971 
0972     val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
0973     val &= ~GENMASK(offset * 2 + 1, offset * 2);
0974     val |= speed << (offset * 2);
0975     writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR);
0976 
0977     if (pctl->hwlock)
0978         hwspin_unlock_in_atomic(pctl->hwlock);
0979 
0980     stm32_gpio_backup_speed(bank, offset, speed);
0981 
0982 unlock:
0983     spin_unlock_irqrestore(&bank->lock, flags);
0984 
0985     return err;
0986 }
0987 
0988 static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank,
0989     unsigned int offset)
0990 {
0991     unsigned long flags;
0992     u32 val;
0993 
0994     spin_lock_irqsave(&bank->lock, flags);
0995 
0996     val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR);
0997     val &= GENMASK(offset * 2 + 1, offset * 2);
0998 
0999     spin_unlock_irqrestore(&bank->lock, flags);
1000 
1001     return (val >> (offset * 2));
1002 }
1003 
1004 static int stm32_pconf_set_bias(struct stm32_gpio_bank *bank,
1005                 unsigned offset, u32 bias)
1006 {
1007     struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent);
1008     unsigned long flags;
1009     u32 val;
1010     int err = 0;
1011 
1012     spin_lock_irqsave(&bank->lock, flags);
1013 
1014     if (pctl->hwlock) {
1015         err = hwspin_lock_timeout_in_atomic(pctl->hwlock,
1016                             HWSPNLCK_TIMEOUT);
1017         if (err) {
1018             dev_err(pctl->dev, "Can't get hwspinlock\n");
1019             goto unlock;
1020         }
1021     }
1022 
1023     val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1024     val &= ~GENMASK(offset * 2 + 1, offset * 2);
1025     val |= bias << (offset * 2);
1026     writel_relaxed(val, bank->base + STM32_GPIO_PUPDR);
1027 
1028     if (pctl->hwlock)
1029         hwspin_unlock_in_atomic(pctl->hwlock);
1030 
1031     stm32_gpio_backup_bias(bank, offset, bias);
1032 
1033 unlock:
1034     spin_unlock_irqrestore(&bank->lock, flags);
1035 
1036     return err;
1037 }
1038 
1039 static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank,
1040     unsigned int offset)
1041 {
1042     unsigned long flags;
1043     u32 val;
1044 
1045     spin_lock_irqsave(&bank->lock, flags);
1046 
1047     val = readl_relaxed(bank->base + STM32_GPIO_PUPDR);
1048     val &= GENMASK(offset * 2 + 1, offset * 2);
1049 
1050     spin_unlock_irqrestore(&bank->lock, flags);
1051 
1052     return (val >> (offset * 2));
1053 }
1054 
1055 static bool stm32_pconf_get(struct stm32_gpio_bank *bank,
1056     unsigned int offset, bool dir)
1057 {
1058     unsigned long flags;
1059     u32 val;
1060 
1061     spin_lock_irqsave(&bank->lock, flags);
1062 
1063     if (dir)
1064         val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) &
1065              BIT(offset));
1066     else
1067         val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) &
1068              BIT(offset));
1069 
1070     spin_unlock_irqrestore(&bank->lock, flags);
1071 
1072     return val;
1073 }
1074 
1075 static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev,
1076         unsigned int pin, enum pin_config_param param,
1077         enum pin_config_param arg)
1078 {
1079     struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1080     struct pinctrl_gpio_range *range;
1081     struct stm32_gpio_bank *bank;
1082     int offset, ret = 0;
1083 
1084     range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1085     if (!range) {
1086         dev_err(pctl->dev, "No gpio range defined.\n");
1087         return -EINVAL;
1088     }
1089 
1090     bank = gpiochip_get_data(range->gc);
1091     offset = stm32_gpio_pin(pin);
1092 
1093     if (!gpiochip_line_is_valid(range->gc, offset)) {
1094         dev_warn(pctl->dev, "Can't access gpio %d\n", pin);
1095         return -EACCES;
1096     }
1097 
1098     switch (param) {
1099     case PIN_CONFIG_DRIVE_PUSH_PULL:
1100         ret = stm32_pconf_set_driving(bank, offset, 0);
1101         break;
1102     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
1103         ret = stm32_pconf_set_driving(bank, offset, 1);
1104         break;
1105     case PIN_CONFIG_SLEW_RATE:
1106         ret = stm32_pconf_set_speed(bank, offset, arg);
1107         break;
1108     case PIN_CONFIG_BIAS_DISABLE:
1109         ret = stm32_pconf_set_bias(bank, offset, 0);
1110         break;
1111     case PIN_CONFIG_BIAS_PULL_UP:
1112         ret = stm32_pconf_set_bias(bank, offset, 1);
1113         break;
1114     case PIN_CONFIG_BIAS_PULL_DOWN:
1115         ret = stm32_pconf_set_bias(bank, offset, 2);
1116         break;
1117     case PIN_CONFIG_OUTPUT:
1118         __stm32_gpio_set(bank, offset, arg);
1119         ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false);
1120         break;
1121     default:
1122         ret = -ENOTSUPP;
1123     }
1124 
1125     return ret;
1126 }
1127 
1128 static int stm32_pconf_group_get(struct pinctrl_dev *pctldev,
1129                  unsigned group,
1130                  unsigned long *config)
1131 {
1132     struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1133 
1134     *config = pctl->groups[group].config;
1135 
1136     return 0;
1137 }
1138 
1139 static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
1140                  unsigned long *configs, unsigned num_configs)
1141 {
1142     struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1143     struct stm32_pinctrl_group *g = &pctl->groups[group];
1144     int i, ret;
1145 
1146     for (i = 0; i < num_configs; i++) {
1147         mutex_lock(&pctldev->mutex);
1148         ret = stm32_pconf_parse_conf(pctldev, g->pin,
1149             pinconf_to_config_param(configs[i]),
1150             pinconf_to_config_argument(configs[i]));
1151         mutex_unlock(&pctldev->mutex);
1152         if (ret < 0)
1153             return ret;
1154 
1155         g->config = configs[i];
1156     }
1157 
1158     return 0;
1159 }
1160 
1161 static int stm32_pconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
1162                unsigned long *configs, unsigned int num_configs)
1163 {
1164     int i, ret;
1165 
1166     for (i = 0; i < num_configs; i++) {
1167         ret = stm32_pconf_parse_conf(pctldev, pin,
1168                 pinconf_to_config_param(configs[i]),
1169                 pinconf_to_config_argument(configs[i]));
1170         if (ret < 0)
1171             return ret;
1172     }
1173 
1174     return 0;
1175 }
1176 
1177 static struct stm32_desc_pin *
1178 stm32_pconf_get_pin_desc_by_pin_number(struct stm32_pinctrl *pctl,
1179                        unsigned int pin_number)
1180 {
1181     struct stm32_desc_pin *pins = pctl->pins;
1182     int i;
1183 
1184     for (i = 0; i < pctl->npins; i++) {
1185         if (pins->pin.number == pin_number)
1186             return pins;
1187         pins++;
1188     }
1189     return NULL;
1190 }
1191 
1192 static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev,
1193                  struct seq_file *s,
1194                  unsigned int pin)
1195 {
1196     struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
1197     const struct stm32_desc_pin *pin_desc;
1198     struct pinctrl_gpio_range *range;
1199     struct stm32_gpio_bank *bank;
1200     int offset;
1201     u32 mode, alt, drive, speed, bias;
1202     static const char * const modes[] = {
1203             "input", "output", "alternate", "analog" };
1204     static const char * const speeds[] = {
1205             "low", "medium", "high", "very high" };
1206     static const char * const biasing[] = {
1207             "floating", "pull up", "pull down", "" };
1208     bool val;
1209 
1210     range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
1211     if (!range)
1212         return;
1213 
1214     bank = gpiochip_get_data(range->gc);
1215     offset = stm32_gpio_pin(pin);
1216 
1217     if (!gpiochip_line_is_valid(range->gc, offset)) {
1218         seq_puts(s, "NO ACCESS");
1219         return;
1220     }
1221 
1222     stm32_pmx_get_mode(bank, offset, &mode, &alt);
1223     bias = stm32_pconf_get_bias(bank, offset);
1224 
1225     seq_printf(s, "%s ", modes[mode]);
1226 
1227     switch (mode) {
1228     /* input */
1229     case 0:
1230         val = stm32_pconf_get(bank, offset, true);
1231         seq_printf(s, "- %s - %s",
1232                val ? "high" : "low",
1233                biasing[bias]);
1234         break;
1235 
1236     /* output */
1237     case 1:
1238         drive = stm32_pconf_get_driving(bank, offset);
1239         speed = stm32_pconf_get_speed(bank, offset);
1240         val = stm32_pconf_get(bank, offset, false);
1241         seq_printf(s, "- %s - %s - %s - %s %s",
1242                val ? "high" : "low",
1243                drive ? "open drain" : "push pull",
1244                biasing[bias],
1245                speeds[speed], "speed");
1246         break;
1247 
1248     /* alternate */
1249     case 2:
1250         drive = stm32_pconf_get_driving(bank, offset);
1251         speed = stm32_pconf_get_speed(bank, offset);
1252         pin_desc = stm32_pconf_get_pin_desc_by_pin_number(pctl, pin);
1253         if (!pin_desc)
1254             return;
1255 
1256         seq_printf(s, "%d (%s) - %s - %s - %s %s", alt,
1257                pin_desc->functions[alt + 1].name,
1258                drive ? "open drain" : "push pull",
1259                biasing[bias],
1260                speeds[speed], "speed");
1261         break;
1262 
1263     /* analog */
1264     case 3:
1265         break;
1266     }
1267 }
1268 
1269 static const struct pinconf_ops stm32_pconf_ops = {
1270     .pin_config_group_get   = stm32_pconf_group_get,
1271     .pin_config_group_set   = stm32_pconf_group_set,
1272     .pin_config_set     = stm32_pconf_set,
1273     .pin_config_dbg_show    = stm32_pconf_dbg_show,
1274 };
1275 
1276 static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, struct fwnode_handle *fwnode)
1277 {
1278     struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks];
1279     int bank_ioport_nr;
1280     struct pinctrl_gpio_range *range = &bank->range;
1281     struct fwnode_reference_args args;
1282     struct device *dev = pctl->dev;
1283     struct resource res;
1284     int npins = STM32_GPIO_PINS_PER_BANK;
1285     int bank_nr, err, i = 0;
1286 
1287     if (!IS_ERR(bank->rstc))
1288         reset_control_deassert(bank->rstc);
1289 
1290     if (of_address_to_resource(to_of_node(fwnode), 0, &res))
1291         return -ENODEV;
1292 
1293     bank->base = devm_ioremap_resource(dev, &res);
1294     if (IS_ERR(bank->base))
1295         return PTR_ERR(bank->base);
1296 
1297     err = clk_prepare_enable(bank->clk);
1298     if (err) {
1299         dev_err(dev, "failed to prepare_enable clk (%d)\n", err);
1300         return err;
1301     }
1302 
1303     bank->gpio_chip = stm32_gpio_template;
1304 
1305     fwnode_property_read_string(fwnode, "st,bank-name", &bank->gpio_chip.label);
1306 
1307     if (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, i, &args)) {
1308         bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK;
1309         bank->gpio_chip.base = args.args[1];
1310 
1311         /* get the last defined gpio line (offset + nb of pins) */
1312         npins = args.args[0] + args.args[2];
1313         while (!fwnode_property_get_reference_args(fwnode, "gpio-ranges", NULL, 3, ++i, &args))
1314             npins = max(npins, (int)(args.args[0] + args.args[2]));
1315     } else {
1316         bank_nr = pctl->nbanks;
1317         bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1318         range->name = bank->gpio_chip.label;
1319         range->id = bank_nr;
1320         range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK;
1321         range->base = range->id * STM32_GPIO_PINS_PER_BANK;
1322         range->npins = npins;
1323         range->gc = &bank->gpio_chip;
1324         pinctrl_add_gpio_range(pctl->pctl_dev,
1325                        &pctl->banks[bank_nr].range);
1326     }
1327 
1328     if (fwnode_property_read_u32(fwnode, "st,bank-ioport", &bank_ioport_nr))
1329         bank_ioport_nr = bank_nr;
1330 
1331     bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK;
1332 
1333     bank->gpio_chip.ngpio = npins;
1334     bank->gpio_chip.fwnode = fwnode;
1335     bank->gpio_chip.parent = dev;
1336     bank->bank_nr = bank_nr;
1337     bank->bank_ioport_nr = bank_ioport_nr;
1338     bank->secure_control = pctl->match_data->secure_control;
1339     spin_lock_init(&bank->lock);
1340 
1341     if (pctl->domain) {
1342         /* create irq hierarchical domain */
1343         bank->fwnode = fwnode;
1344 
1345         bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, STM32_GPIO_IRQ_LINE,
1346                                bank->fwnode, &stm32_gpio_domain_ops,
1347                                bank);
1348 
1349         if (!bank->domain) {
1350             err = -ENODEV;
1351             goto err_clk;
1352         }
1353     }
1354 
1355     err = gpiochip_add_data(&bank->gpio_chip, bank);
1356     if (err) {
1357         dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr);
1358         goto err_clk;
1359     }
1360 
1361     dev_info(dev, "%s bank added\n", bank->gpio_chip.label);
1362     return 0;
1363 
1364 err_clk:
1365     clk_disable_unprepare(bank->clk);
1366     return err;
1367 }
1368 
1369 static struct irq_domain *stm32_pctrl_get_irq_domain(struct platform_device *pdev)
1370 {
1371     struct device_node *np = pdev->dev.of_node;
1372     struct device_node *parent;
1373     struct irq_domain *domain;
1374 
1375     if (!of_find_property(np, "interrupt-parent", NULL))
1376         return NULL;
1377 
1378     parent = of_irq_find_parent(np);
1379     if (!parent)
1380         return ERR_PTR(-ENXIO);
1381 
1382     domain = irq_find_host(parent);
1383     if (!domain)
1384         /* domain not registered yet */
1385         return ERR_PTR(-EPROBE_DEFER);
1386 
1387     return domain;
1388 }
1389 
1390 static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev,
1391                struct stm32_pinctrl *pctl)
1392 {
1393     struct device_node *np = pdev->dev.of_node;
1394     struct device *dev = &pdev->dev;
1395     struct regmap *rm;
1396     int offset, ret, i;
1397     int mask, mask_width;
1398 
1399     pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1400     if (IS_ERR(pctl->regmap))
1401         return PTR_ERR(pctl->regmap);
1402 
1403     rm = pctl->regmap;
1404 
1405     ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset);
1406     if (ret)
1407         return ret;
1408 
1409     ret = of_property_read_u32_index(np, "st,syscfg", 2, &mask);
1410     if (ret)
1411         mask = SYSCFG_IRQMUX_MASK;
1412 
1413     mask_width = fls(mask);
1414 
1415     for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) {
1416         struct reg_field mux;
1417 
1418         mux.reg = offset + (i / 4) * 4;
1419         mux.lsb = (i % 4) * mask_width;
1420         mux.msb = mux.lsb + mask_width - 1;
1421 
1422         dev_dbg(dev, "irqmux%d: reg:%#x, lsb:%d, msb:%d\n",
1423             i, mux.reg, mux.lsb, mux.msb);
1424 
1425         pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux);
1426         if (IS_ERR(pctl->irqmux[i]))
1427             return PTR_ERR(pctl->irqmux[i]);
1428     }
1429 
1430     return 0;
1431 }
1432 
1433 static int stm32_pctrl_build_state(struct platform_device *pdev)
1434 {
1435     struct stm32_pinctrl *pctl = platform_get_drvdata(pdev);
1436     int i;
1437 
1438     pctl->ngroups = pctl->npins;
1439 
1440     /* Allocate groups */
1441     pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1442                     sizeof(*pctl->groups), GFP_KERNEL);
1443     if (!pctl->groups)
1444         return -ENOMEM;
1445 
1446     /* We assume that one pin is one group, use pin name as group name. */
1447     pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1448                        sizeof(*pctl->grp_names), GFP_KERNEL);
1449     if (!pctl->grp_names)
1450         return -ENOMEM;
1451 
1452     for (i = 0; i < pctl->npins; i++) {
1453         const struct stm32_desc_pin *pin = pctl->pins + i;
1454         struct stm32_pinctrl_group *group = pctl->groups + i;
1455 
1456         group->name = pin->pin.name;
1457         group->pin = pin->pin.number;
1458         pctl->grp_names[i] = pin->pin.name;
1459     }
1460 
1461     return 0;
1462 }
1463 
1464 static int stm32_pctrl_create_pins_tab(struct stm32_pinctrl *pctl,
1465                        struct stm32_desc_pin *pins)
1466 {
1467     const struct stm32_desc_pin *p;
1468     int i, nb_pins_available = 0;
1469 
1470     for (i = 0; i < pctl->match_data->npins; i++) {
1471         p = pctl->match_data->pins + i;
1472         if (pctl->pkg && !(pctl->pkg & p->pkg))
1473             continue;
1474         pins->pin = p->pin;
1475         memcpy((struct stm32_desc_pin *)pins->functions, p->functions,
1476                STM32_CONFIG_NUM * sizeof(struct stm32_desc_function));
1477         pins++;
1478         nb_pins_available++;
1479     }
1480 
1481     pctl->npins = nb_pins_available;
1482 
1483     return 0;
1484 }
1485 
1486 int stm32_pctl_probe(struct platform_device *pdev)
1487 {
1488     const struct stm32_pinctrl_match_data *match_data;
1489     struct fwnode_handle *child;
1490     struct device *dev = &pdev->dev;
1491     struct stm32_pinctrl *pctl;
1492     struct pinctrl_pin_desc *pins;
1493     int i, ret, hwlock_id;
1494     unsigned int banks;
1495 
1496     match_data = device_get_match_data(dev);
1497     if (!match_data)
1498         return -EINVAL;
1499 
1500     if (!device_property_present(dev, "pins-are-numbered")) {
1501         dev_err(dev, "only support pins-are-numbered format\n");
1502         return -EINVAL;
1503     }
1504 
1505     pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1506     if (!pctl)
1507         return -ENOMEM;
1508 
1509     platform_set_drvdata(pdev, pctl);
1510 
1511     /* check for IRQ controller (may require deferred probe) */
1512     pctl->domain = stm32_pctrl_get_irq_domain(pdev);
1513     if (IS_ERR(pctl->domain))
1514         return PTR_ERR(pctl->domain);
1515     if (!pctl->domain)
1516         dev_warn(dev, "pinctrl without interrupt support\n");
1517 
1518     /* hwspinlock is optional */
1519     hwlock_id = of_hwspin_lock_get_id(pdev->dev.of_node, 0);
1520     if (hwlock_id < 0) {
1521         if (hwlock_id == -EPROBE_DEFER)
1522             return hwlock_id;
1523     } else {
1524         pctl->hwlock = hwspin_lock_request_specific(hwlock_id);
1525     }
1526 
1527     spin_lock_init(&pctl->irqmux_lock);
1528 
1529     pctl->dev = dev;
1530     pctl->match_data = match_data;
1531 
1532     /*  get optional package information */
1533     if (!device_property_read_u32(dev, "st,package", &pctl->pkg))
1534         dev_dbg(pctl->dev, "package detected: %x\n", pctl->pkg);
1535 
1536     pctl->pins = devm_kcalloc(pctl->dev, pctl->match_data->npins,
1537                   sizeof(*pctl->pins), GFP_KERNEL);
1538     if (!pctl->pins)
1539         return -ENOMEM;
1540 
1541     ret = stm32_pctrl_create_pins_tab(pctl, pctl->pins);
1542     if (ret)
1543         return ret;
1544 
1545     ret = stm32_pctrl_build_state(pdev);
1546     if (ret) {
1547         dev_err(dev, "build state failed: %d\n", ret);
1548         return -EINVAL;
1549     }
1550 
1551     if (pctl->domain) {
1552         ret = stm32_pctrl_dt_setup_irq(pdev, pctl);
1553         if (ret)
1554             return ret;
1555     }
1556 
1557     pins = devm_kcalloc(&pdev->dev, pctl->npins, sizeof(*pins),
1558                 GFP_KERNEL);
1559     if (!pins)
1560         return -ENOMEM;
1561 
1562     for (i = 0; i < pctl->npins; i++)
1563         pins[i] = pctl->pins[i].pin;
1564 
1565     pctl->pctl_desc.name = dev_name(&pdev->dev);
1566     pctl->pctl_desc.owner = THIS_MODULE;
1567     pctl->pctl_desc.pins = pins;
1568     pctl->pctl_desc.npins = pctl->npins;
1569     pctl->pctl_desc.link_consumers = true;
1570     pctl->pctl_desc.confops = &stm32_pconf_ops;
1571     pctl->pctl_desc.pctlops = &stm32_pctrl_ops;
1572     pctl->pctl_desc.pmxops = &stm32_pmx_ops;
1573     pctl->dev = &pdev->dev;
1574 
1575     pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1576                            pctl);
1577 
1578     if (IS_ERR(pctl->pctl_dev)) {
1579         dev_err(&pdev->dev, "Failed pinctrl registration\n");
1580         return PTR_ERR(pctl->pctl_dev);
1581     }
1582 
1583     banks = gpiochip_node_count(dev);
1584     if (!banks) {
1585         dev_err(dev, "at least one GPIO bank is required\n");
1586         return -EINVAL;
1587     }
1588     pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks),
1589             GFP_KERNEL);
1590     if (!pctl->banks)
1591         return -ENOMEM;
1592 
1593     i = 0;
1594     for_each_gpiochip_node(dev, child) {
1595         struct stm32_gpio_bank *bank = &pctl->banks[i];
1596         struct device_node *np = to_of_node(child);
1597 
1598         bank->rstc = of_reset_control_get_exclusive(np, NULL);
1599         if (PTR_ERR(bank->rstc) == -EPROBE_DEFER) {
1600             fwnode_handle_put(child);
1601             return -EPROBE_DEFER;
1602         }
1603 
1604         bank->clk = of_clk_get_by_name(np, NULL);
1605         if (IS_ERR(bank->clk)) {
1606             if (PTR_ERR(bank->clk) != -EPROBE_DEFER)
1607                 dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk));
1608             fwnode_handle_put(child);
1609             return PTR_ERR(bank->clk);
1610         }
1611         i++;
1612     }
1613 
1614     for_each_gpiochip_node(dev, child) {
1615         ret = stm32_gpiolib_register_bank(pctl, child);
1616         if (ret) {
1617             fwnode_handle_put(child);
1618 
1619             for (i = 0; i < pctl->nbanks; i++)
1620                 clk_disable_unprepare(pctl->banks[i].clk);
1621 
1622             return ret;
1623         }
1624 
1625         pctl->nbanks++;
1626     }
1627 
1628     dev_info(dev, "Pinctrl STM32 initialized\n");
1629 
1630     return 0;
1631 }
1632 
1633 static int __maybe_unused stm32_pinctrl_restore_gpio_regs(
1634                     struct stm32_pinctrl *pctl, u32 pin)
1635 {
1636     const struct pin_desc *desc = pin_desc_get(pctl->pctl_dev, pin);
1637     u32 val, alt, mode, offset = stm32_gpio_pin(pin);
1638     struct pinctrl_gpio_range *range;
1639     struct stm32_gpio_bank *bank;
1640     bool pin_is_irq;
1641     int ret;
1642 
1643     range = pinctrl_find_gpio_range_from_pin(pctl->pctl_dev, pin);
1644     if (!range)
1645         return 0;
1646 
1647     if (!gpiochip_line_is_valid(range->gc, offset))
1648         return 0;
1649 
1650     pin_is_irq = gpiochip_line_is_irq(range->gc, offset);
1651 
1652     if (!desc || (!pin_is_irq && !desc->gpio_owner))
1653         return 0;
1654 
1655     bank = gpiochip_get_data(range->gc);
1656 
1657     alt = bank->pin_backup[offset] & STM32_GPIO_BKP_ALT_MASK;
1658     alt >>= STM32_GPIO_BKP_ALT_SHIFT;
1659     mode = bank->pin_backup[offset] & STM32_GPIO_BKP_MODE_MASK;
1660     mode >>= STM32_GPIO_BKP_MODE_SHIFT;
1661 
1662     ret = stm32_pmx_set_mode(bank, offset, mode, alt);
1663     if (ret)
1664         return ret;
1665 
1666     if (mode == 1) {
1667         val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_VAL);
1668         val = val >> STM32_GPIO_BKP_VAL;
1669         __stm32_gpio_set(bank, offset, val);
1670     }
1671 
1672     val = bank->pin_backup[offset] & BIT(STM32_GPIO_BKP_TYPE);
1673     val >>= STM32_GPIO_BKP_TYPE;
1674     ret = stm32_pconf_set_driving(bank, offset, val);
1675     if (ret)
1676         return ret;
1677 
1678     val = bank->pin_backup[offset] & STM32_GPIO_BKP_SPEED_MASK;
1679     val >>= STM32_GPIO_BKP_SPEED_SHIFT;
1680     ret = stm32_pconf_set_speed(bank, offset, val);
1681     if (ret)
1682         return ret;
1683 
1684     val = bank->pin_backup[offset] & STM32_GPIO_BKP_PUPD_MASK;
1685     val >>= STM32_GPIO_BKP_PUPD_SHIFT;
1686     ret = stm32_pconf_set_bias(bank, offset, val);
1687     if (ret)
1688         return ret;
1689 
1690     if (pin_is_irq)
1691         regmap_field_write(pctl->irqmux[offset], bank->bank_ioport_nr);
1692 
1693     return 0;
1694 }
1695 
1696 int __maybe_unused stm32_pinctrl_suspend(struct device *dev)
1697 {
1698     struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1699     int i;
1700 
1701     for (i = 0; i < pctl->nbanks; i++)
1702         clk_disable(pctl->banks[i].clk);
1703 
1704     return 0;
1705 }
1706 
1707 int __maybe_unused stm32_pinctrl_resume(struct device *dev)
1708 {
1709     struct stm32_pinctrl *pctl = dev_get_drvdata(dev);
1710     struct stm32_pinctrl_group *g = pctl->groups;
1711     int i;
1712 
1713     for (i = 0; i < pctl->nbanks; i++)
1714         clk_enable(pctl->banks[i].clk);
1715 
1716     for (i = 0; i < pctl->ngroups; i++, g++)
1717         stm32_pinctrl_restore_gpio_regs(pctl, g->pin);
1718 
1719     return 0;
1720 }
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