pinctrl/spear/pinctrl-spear3xx.c

0001 /*
0002  * Driver for the ST Microelectronics SPEAr3xx pinmux
0003  *
0004  * Copyright (C) 2012 ST Microelectronics
0005  * Viresh Kumar <vireshk@kernel.org>
0006  *
0007  * This file is licensed under the terms of the GNU General Public
0008  * License version 2. This program is licensed "as is" without any
0009  * warranty of any kind, whether express or implied.
0010  */
0011
0012 #include <linux/pinctrl/pinctrl.h>
0013
0014 #include "pinctrl-spear3xx.h"
0015
0016 /* pins */
0017 static const struct pinctrl_pin_desc spear3xx_pins[] = {
0018     SPEAR_PIN_0_TO_101,
0019 };
0020
0021 /* firda_pins */
0022 static const unsigned firda_pins[] = { 0, 1 };
0023 static struct spear_muxreg firda_muxreg[] = {
0024     {
0025         .reg = -1,
0026         .mask = PMX_FIRDA_MASK,
0027         .val = PMX_FIRDA_MASK,
0028     },
0029 };
0030
0031 static struct spear_modemux firda_modemux[] = {
0032     {
0033         .modes = ~0,
0034         .muxregs = firda_muxreg,
0035         .nmuxregs = ARRAY_SIZE(firda_muxreg),
0036     },
0037 };
0038
0039 struct spear_pingroup spear3xx_firda_pingroup = {
0040     .name = "firda_grp",
0041     .pins = firda_pins,
0042     .npins = ARRAY_SIZE(firda_pins),
0043     .modemuxs = firda_modemux,
0044     .nmodemuxs = ARRAY_SIZE(firda_modemux),
0045 };
0046
0047 static const char *const firda_grps[] = { "firda_grp" };
0048 struct spear_function spear3xx_firda_function = {
0049     .name = "firda",
0050     .groups = firda_grps,
0051     .ngroups = ARRAY_SIZE(firda_grps),
0052 };
0053
0054 /* i2c_pins */
0055 static const unsigned i2c_pins[] = { 4, 5 };
0056 static struct spear_muxreg i2c_muxreg[] = {
0057     {
0058         .reg = -1,
0059         .mask = PMX_I2C_MASK,
0060         .val = PMX_I2C_MASK,
0061     },
0062 };
0063
0064 static struct spear_modemux i2c_modemux[] = {
0065     {
0066         .modes = ~0,
0067         .muxregs = i2c_muxreg,
0068         .nmuxregs = ARRAY_SIZE(i2c_muxreg),
0069     },
0070 };
0071
0072 struct spear_pingroup spear3xx_i2c_pingroup = {
0073     .name = "i2c0_grp",
0074     .pins = i2c_pins,
0075     .npins = ARRAY_SIZE(i2c_pins),
0076     .modemuxs = i2c_modemux,
0077     .nmodemuxs = ARRAY_SIZE(i2c_modemux),
0078 };
0079
0080 static const char *const i2c_grps[] = { "i2c0_grp" };
0081 struct spear_function spear3xx_i2c_function = {
0082     .name = "i2c0",
0083     .groups = i2c_grps,
0084     .ngroups = ARRAY_SIZE(i2c_grps),
0085 };
0086
0087 /* ssp_cs_pins */
0088 static const unsigned ssp_cs_pins[] = { 34, 35, 36 };
0089 static struct spear_muxreg ssp_cs_muxreg[] = {
0090     {
0091         .reg = -1,
0092         .mask = PMX_SSP_CS_MASK,
0093         .val = PMX_SSP_CS_MASK,
0094     },
0095 };
0096
0097 static struct spear_modemux ssp_cs_modemux[] = {
0098     {
0099         .modes = ~0,
0100         .muxregs = ssp_cs_muxreg,
0101         .nmuxregs = ARRAY_SIZE(ssp_cs_muxreg),
0102     },
0103 };
0104
0105 struct spear_pingroup spear3xx_ssp_cs_pingroup = {
0106     .name = "ssp_cs_grp",
0107     .pins = ssp_cs_pins,
0108     .npins = ARRAY_SIZE(ssp_cs_pins),
0109     .modemuxs = ssp_cs_modemux,
0110     .nmodemuxs = ARRAY_SIZE(ssp_cs_modemux),
0111 };
0112
0113 static const char *const ssp_cs_grps[] = { "ssp_cs_grp" };
0114 struct spear_function spear3xx_ssp_cs_function = {
0115     .name = "ssp_cs",
0116     .groups = ssp_cs_grps,
0117     .ngroups = ARRAY_SIZE(ssp_cs_grps),
0118 };
0119
0120 /* ssp_pins */
0121 static const unsigned ssp_pins[] = { 6, 7, 8, 9 };
0122 static struct spear_muxreg ssp_muxreg[] = {
0123     {
0124         .reg = -1,
0125         .mask = PMX_SSP_MASK,
0126         .val = PMX_SSP_MASK,
0127     },
0128 };
0129
0130 static struct spear_modemux ssp_modemux[] = {
0131     {
0132         .modes = ~0,
0133         .muxregs = ssp_muxreg,
0134         .nmuxregs = ARRAY_SIZE(ssp_muxreg),
0135     },
0136 };
0137
0138 struct spear_pingroup spear3xx_ssp_pingroup = {
0139     .name = "ssp0_grp",
0140     .pins = ssp_pins,
0141     .npins = ARRAY_SIZE(ssp_pins),
0142     .modemuxs = ssp_modemux,
0143     .nmodemuxs = ARRAY_SIZE(ssp_modemux),
0144 };
0145
0146 static const char *const ssp_grps[] = { "ssp0_grp" };
0147 struct spear_function spear3xx_ssp_function = {
0148     .name = "ssp0",
0149     .groups = ssp_grps,
0150     .ngroups = ARRAY_SIZE(ssp_grps),
0151 };
0152
0153 /* mii_pins */
0154 static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
0155     21, 22, 23, 24, 25, 26, 27 };
0156 static struct spear_muxreg mii_muxreg[] = {
0157     {
0158         .reg = -1,
0159         .mask = PMX_MII_MASK,
0160         .val = PMX_MII_MASK,
0161     },
0162 };
0163
0164 static struct spear_modemux mii_modemux[] = {
0165     {
0166         .modes = ~0,
0167         .muxregs = mii_muxreg,
0168         .nmuxregs = ARRAY_SIZE(mii_muxreg),
0169     },
0170 };
0171
0172 struct spear_pingroup spear3xx_mii_pingroup = {
0173     .name = "mii0_grp",
0174     .pins = mii_pins,
0175     .npins = ARRAY_SIZE(mii_pins),
0176     .modemuxs = mii_modemux,
0177     .nmodemuxs = ARRAY_SIZE(mii_modemux),
0178 };
0179
0180 static const char *const mii_grps[] = { "mii0_grp" };
0181 struct spear_function spear3xx_mii_function = {
0182     .name = "mii0",
0183     .groups = mii_grps,
0184     .ngroups = ARRAY_SIZE(mii_grps),
0185 };
0186
0187 /* gpio0_pin0_pins */
0188 static const unsigned gpio0_pin0_pins[] = { 28 };
0189 static struct spear_muxreg gpio0_pin0_muxreg[] = {
0190     {
0191         .reg = -1,
0192         .mask = PMX_GPIO_PIN0_MASK,
0193         .val = PMX_GPIO_PIN0_MASK,
0194     },
0195 };
0196
0197 static struct spear_modemux gpio0_pin0_modemux[] = {
0198     {
0199         .modes = ~0,
0200         .muxregs = gpio0_pin0_muxreg,
0201         .nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg),
0202     },
0203 };
0204
0205 struct spear_pingroup spear3xx_gpio0_pin0_pingroup = {
0206     .name = "gpio0_pin0_grp",
0207     .pins = gpio0_pin0_pins,
0208     .npins = ARRAY_SIZE(gpio0_pin0_pins),
0209     .modemuxs = gpio0_pin0_modemux,
0210     .nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux),
0211 };
0212
0213 /* gpio0_pin1_pins */
0214 static const unsigned gpio0_pin1_pins[] = { 29 };
0215 static struct spear_muxreg gpio0_pin1_muxreg[] = {
0216     {
0217         .reg = -1,
0218         .mask = PMX_GPIO_PIN1_MASK,
0219         .val = PMX_GPIO_PIN1_MASK,
0220     },
0221 };
0222
0223 static struct spear_modemux gpio0_pin1_modemux[] = {
0224     {
0225         .modes = ~0,
0226         .muxregs = gpio0_pin1_muxreg,
0227         .nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg),
0228     },
0229 };
0230
0231 struct spear_pingroup spear3xx_gpio0_pin1_pingroup = {
0232     .name = "gpio0_pin1_grp",
0233     .pins = gpio0_pin1_pins,
0234     .npins = ARRAY_SIZE(gpio0_pin1_pins),
0235     .modemuxs = gpio0_pin1_modemux,
0236     .nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux),
0237 };
0238
0239 /* gpio0_pin2_pins */
0240 static const unsigned gpio0_pin2_pins[] = { 30 };
0241 static struct spear_muxreg gpio0_pin2_muxreg[] = {
0242     {
0243         .reg = -1,
0244         .mask = PMX_GPIO_PIN2_MASK,
0245         .val = PMX_GPIO_PIN2_MASK,
0246     },
0247 };
0248
0249 static struct spear_modemux gpio0_pin2_modemux[] = {
0250     {
0251         .modes = ~0,
0252         .muxregs = gpio0_pin2_muxreg,
0253         .nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg),
0254     },
0255 };
0256
0257 struct spear_pingroup spear3xx_gpio0_pin2_pingroup = {
0258     .name = "gpio0_pin2_grp",
0259     .pins = gpio0_pin2_pins,
0260     .npins = ARRAY_SIZE(gpio0_pin2_pins),
0261     .modemuxs = gpio0_pin2_modemux,
0262     .nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux),
0263 };
0264
0265 /* gpio0_pin3_pins */
0266 static const unsigned gpio0_pin3_pins[] = { 31 };
0267 static struct spear_muxreg gpio0_pin3_muxreg[] = {
0268     {
0269         .reg = -1,
0270         .mask = PMX_GPIO_PIN3_MASK,
0271         .val = PMX_GPIO_PIN3_MASK,
0272     },
0273 };
0274
0275 static struct spear_modemux gpio0_pin3_modemux[] = {
0276     {
0277         .modes = ~0,
0278         .muxregs = gpio0_pin3_muxreg,
0279         .nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg),
0280     },
0281 };
0282
0283 struct spear_pingroup spear3xx_gpio0_pin3_pingroup = {
0284     .name = "gpio0_pin3_grp",
0285     .pins = gpio0_pin3_pins,
0286     .npins = ARRAY_SIZE(gpio0_pin3_pins),
0287     .modemuxs = gpio0_pin3_modemux,
0288     .nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux),
0289 };
0290
0291 /* gpio0_pin4_pins */
0292 static const unsigned gpio0_pin4_pins[] = { 32 };
0293 static struct spear_muxreg gpio0_pin4_muxreg[] = {
0294     {
0295         .reg = -1,
0296         .mask = PMX_GPIO_PIN4_MASK,
0297         .val = PMX_GPIO_PIN4_MASK,
0298     },
0299 };
0300
0301 static struct spear_modemux gpio0_pin4_modemux[] = {
0302     {
0303         .modes = ~0,
0304         .muxregs = gpio0_pin4_muxreg,
0305         .nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg),
0306     },
0307 };
0308
0309 struct spear_pingroup spear3xx_gpio0_pin4_pingroup = {
0310     .name = "gpio0_pin4_grp",
0311     .pins = gpio0_pin4_pins,
0312     .npins = ARRAY_SIZE(gpio0_pin4_pins),
0313     .modemuxs = gpio0_pin4_modemux,
0314     .nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux),
0315 };
0316
0317 /* gpio0_pin5_pins */
0318 static const unsigned gpio0_pin5_pins[] = { 33 };
0319 static struct spear_muxreg gpio0_pin5_muxreg[] = {
0320     {
0321         .reg = -1,
0322         .mask = PMX_GPIO_PIN5_MASK,
0323         .val = PMX_GPIO_PIN5_MASK,
0324     },
0325 };
0326
0327 static struct spear_modemux gpio0_pin5_modemux[] = {
0328     {
0329         .modes = ~0,
0330         .muxregs = gpio0_pin5_muxreg,
0331         .nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg),
0332     },
0333 };
0334
0335 struct spear_pingroup spear3xx_gpio0_pin5_pingroup = {
0336     .name = "gpio0_pin5_grp",
0337     .pins = gpio0_pin5_pins,
0338     .npins = ARRAY_SIZE(gpio0_pin5_pins),
0339     .modemuxs = gpio0_pin5_modemux,
0340     .nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux),
0341 };
0342
0343 static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp",
0344     "gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp",
0345 };
0346 struct spear_function spear3xx_gpio0_function = {
0347     .name = "gpio0",
0348     .groups = gpio0_grps,
0349     .ngroups = ARRAY_SIZE(gpio0_grps),
0350 };
0351
0352 /* uart0_ext_pins */
0353 static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 };
0354 static struct spear_muxreg uart0_ext_muxreg[] = {
0355     {
0356         .reg = -1,
0357         .mask = PMX_UART0_MODEM_MASK,
0358         .val = PMX_UART0_MODEM_MASK,
0359     },
0360 };
0361
0362 static struct spear_modemux uart0_ext_modemux[] = {
0363     {
0364         .modes = ~0,
0365         .muxregs = uart0_ext_muxreg,
0366         .nmuxregs = ARRAY_SIZE(uart0_ext_muxreg),
0367     },
0368 };
0369
0370 struct spear_pingroup spear3xx_uart0_ext_pingroup = {
0371     .name = "uart0_ext_grp",
0372     .pins = uart0_ext_pins,
0373     .npins = ARRAY_SIZE(uart0_ext_pins),
0374     .modemuxs = uart0_ext_modemux,
0375     .nmodemuxs = ARRAY_SIZE(uart0_ext_modemux),
0376 };
0377
0378 static const char *const uart0_ext_grps[] = { "uart0_ext_grp" };
0379 struct spear_function spear3xx_uart0_ext_function = {
0380     .name = "uart0_ext",
0381     .groups = uart0_ext_grps,
0382     .ngroups = ARRAY_SIZE(uart0_ext_grps),
0383 };
0384
0385 /* uart0_pins */
0386 static const unsigned uart0_pins[] = { 2, 3 };
0387 static struct spear_muxreg uart0_muxreg[] = {
0388     {
0389         .reg = -1,
0390         .mask = PMX_UART0_MASK,
0391         .val = PMX_UART0_MASK,
0392     },
0393 };
0394
0395 static struct spear_modemux uart0_modemux[] = {
0396     {
0397         .modes = ~0,
0398         .muxregs = uart0_muxreg,
0399         .nmuxregs = ARRAY_SIZE(uart0_muxreg),
0400     },
0401 };
0402
0403 struct spear_pingroup spear3xx_uart0_pingroup = {
0404     .name = "uart0_grp",
0405     .pins = uart0_pins,
0406     .npins = ARRAY_SIZE(uart0_pins),
0407     .modemuxs = uart0_modemux,
0408     .nmodemuxs = ARRAY_SIZE(uart0_modemux),
0409 };
0410
0411 static const char *const uart0_grps[] = { "uart0_grp" };
0412 struct spear_function spear3xx_uart0_function = {
0413     .name = "uart0",
0414     .groups = uart0_grps,
0415     .ngroups = ARRAY_SIZE(uart0_grps),
0416 };
0417
0418 /* timer_0_1_pins */
0419 static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 };
0420 static struct spear_muxreg timer_0_1_muxreg[] = {
0421     {
0422         .reg = -1,
0423         .mask = PMX_TIMER_0_1_MASK,
0424         .val = PMX_TIMER_0_1_MASK,
0425     },
0426 };
0427
0428 static struct spear_modemux timer_0_1_modemux[] = {
0429     {
0430         .modes = ~0,
0431         .muxregs = timer_0_1_muxreg,
0432         .nmuxregs = ARRAY_SIZE(timer_0_1_muxreg),
0433     },
0434 };
0435
0436 struct spear_pingroup spear3xx_timer_0_1_pingroup = {
0437     .name = "timer_0_1_grp",
0438     .pins = timer_0_1_pins,
0439     .npins = ARRAY_SIZE(timer_0_1_pins),
0440     .modemuxs = timer_0_1_modemux,
0441     .nmodemuxs = ARRAY_SIZE(timer_0_1_modemux),
0442 };
0443
0444 static const char *const timer_0_1_grps[] = { "timer_0_1_grp" };
0445 struct spear_function spear3xx_timer_0_1_function = {
0446     .name = "timer_0_1",
0447     .groups = timer_0_1_grps,
0448     .ngroups = ARRAY_SIZE(timer_0_1_grps),
0449 };
0450
0451 /* timer_2_3_pins */
0452 static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 };
0453 static struct spear_muxreg timer_2_3_muxreg[] = {
0454     {
0455         .reg = -1,
0456         .mask = PMX_TIMER_2_3_MASK,
0457         .val = PMX_TIMER_2_3_MASK,
0458     },
0459 };
0460
0461 static struct spear_modemux timer_2_3_modemux[] = {
0462     {
0463         .modes = ~0,
0464         .muxregs = timer_2_3_muxreg,
0465         .nmuxregs = ARRAY_SIZE(timer_2_3_muxreg),
0466     },
0467 };
0468
0469 struct spear_pingroup spear3xx_timer_2_3_pingroup = {
0470     .name = "timer_2_3_grp",
0471     .pins = timer_2_3_pins,
0472     .npins = ARRAY_SIZE(timer_2_3_pins),
0473     .modemuxs = timer_2_3_modemux,
0474     .nmodemuxs = ARRAY_SIZE(timer_2_3_modemux),
0475 };
0476
0477 static const char *const timer_2_3_grps[] = { "timer_2_3_grp" };
0478 struct spear_function spear3xx_timer_2_3_function = {
0479     .name = "timer_2_3",
0480     .groups = timer_2_3_grps,
0481     .ngroups = ARRAY_SIZE(timer_2_3_grps),
0482 };
0483
0484 /* Define muxreg arrays */
0485 DEFINE_MUXREG(firda_pins, 0, PMX_FIRDA_MASK, 0);
0486 DEFINE_MUXREG(i2c_pins, 0, PMX_I2C_MASK, 0);
0487 DEFINE_MUXREG(ssp_cs_pins, 0, PMX_SSP_CS_MASK, 0);
0488 DEFINE_MUXREG(ssp_pins, 0, PMX_SSP_MASK, 0);
0489 DEFINE_MUXREG(mii_pins, 0, PMX_MII_MASK, 0);
0490 DEFINE_MUXREG(gpio0_pin0_pins, 0, PMX_GPIO_PIN0_MASK, 0);
0491 DEFINE_MUXREG(gpio0_pin1_pins, 0, PMX_GPIO_PIN1_MASK, 0);
0492 DEFINE_MUXREG(gpio0_pin2_pins, 0, PMX_GPIO_PIN2_MASK, 0);
0493 DEFINE_MUXREG(gpio0_pin3_pins, 0, PMX_GPIO_PIN3_MASK, 0);
0494 DEFINE_MUXREG(gpio0_pin4_pins, 0, PMX_GPIO_PIN4_MASK, 0);
0495 DEFINE_MUXREG(gpio0_pin5_pins, 0, PMX_GPIO_PIN5_MASK, 0);
0496 DEFINE_MUXREG(uart0_ext_pins, 0, PMX_UART0_MODEM_MASK, 0);
0497 DEFINE_MUXREG(uart0_pins, 0, PMX_UART0_MASK, 0);
0498 DEFINE_MUXREG(timer_0_1_pins, 0, PMX_TIMER_0_1_MASK, 0);
0499 DEFINE_MUXREG(timer_2_3_pins, 0, PMX_TIMER_2_3_MASK, 0);
0500
0501 static struct spear_gpio_pingroup spear3xx_gpio_pingroup[] = {
0502     GPIO_PINGROUP(firda_pins),
0503     GPIO_PINGROUP(i2c_pins),
0504     GPIO_PINGROUP(ssp_cs_pins),
0505     GPIO_PINGROUP(ssp_pins),
0506     GPIO_PINGROUP(mii_pins),
0507     GPIO_PINGROUP(gpio0_pin0_pins),
0508     GPIO_PINGROUP(gpio0_pin1_pins),
0509     GPIO_PINGROUP(gpio0_pin2_pins),
0510     GPIO_PINGROUP(gpio0_pin3_pins),
0511     GPIO_PINGROUP(gpio0_pin4_pins),
0512     GPIO_PINGROUP(gpio0_pin5_pins),
0513     GPIO_PINGROUP(uart0_ext_pins),
0514     GPIO_PINGROUP(uart0_pins),
0515     GPIO_PINGROUP(timer_0_1_pins),
0516     GPIO_PINGROUP(timer_2_3_pins),
0517 };
0518
0519 struct spear_pinctrl_machdata spear3xx_machdata = {
0520     .pins = spear3xx_pins,
0521     .npins = ARRAY_SIZE(spear3xx_pins),
0522     .gpio_pingroups = spear3xx_gpio_pingroup,
0523     .ngpio_pingroups = ARRAY_SIZE(spear3xx_gpio_pingroup),
0524 };