pinctrl/spear/pinctrl-spear.h

0001 /*
0002  * Driver header file for the ST Microelectronics SPEAr pinmux
0003  *
0004  * Copyright (C) 2012 ST Microelectronics
0005  * Viresh Kumar <vireshk@kernel.org>
0006  *
0007  * This file is licensed under the terms of the GNU General Public
0008  * License version 2. This program is licensed "as is" without any
0009  * warranty of any kind, whether express or implied.
0010  */
0011
0012 #ifndef __PINMUX_SPEAR_H__
0013 #define __PINMUX_SPEAR_H__
0014
0015 #include <linux/gpio/driver.h>
0016 #include <linux/io.h>
0017 #include <linux/pinctrl/pinctrl.h>
0018 #include <linux/regmap.h>
0019 #include <linux/types.h>
0020
0021 struct platform_device;
0022 struct device;
0023 struct spear_pmx;
0024
0025 /**
0026  * struct spear_pmx_mode - SPEAr pmx mode
0027  * @name: name of pmx mode
0028  * @mode: mode id
0029  * @reg: register for configuring this mode
0030  * @mask: mask of this mode in reg
0031  * @val: val to be configured at reg after doing (val & mask)
0032  */
0033 struct spear_pmx_mode {
0034     const char *const name;
0035     u16 mode;
0036     u16 reg;
0037     u16 mask;
0038     u32 val;
0039 };
0040
0041 /**
0042  * struct spear_muxreg - SPEAr mux reg configuration
0043  * @reg: register offset
0044  * @mask: mask bits
0045  * @val: val to be written on mask bits
0046  */
0047 struct spear_muxreg {
0048     u16 reg;
0049     u32 mask;
0050     u32 val;
0051 };
0052
0053 struct spear_gpio_pingroup {
0054     const unsigned *pins;
0055     unsigned npins;
0056     struct spear_muxreg *muxregs;
0057     u8 nmuxregs;
0058 };
0059
0060 /* ste: set to enable */
0061 #define DEFINE_MUXREG(__pins, __muxreg, __mask, __ste)      \
0062 static struct spear_muxreg __pins##_muxregs[] = {       \
0063     {                           \
0064         .reg = __muxreg,                \
0065         .mask = __mask,                 \
0066         .val = __ste ? __mask : 0,          \
0067     },                          \
0068 }
0069
0070 #define DEFINE_2_MUXREG(__pins, __muxreg1, __muxreg2, __mask, __ste1, __ste2) \
0071 static struct spear_muxreg __pins##_muxregs[] = {       \
0072     {                           \
0073         .reg = __muxreg1,               \
0074         .mask = __mask,                 \
0075         .val = __ste1 ? __mask : 0,         \
0076     }, {                            \
0077         .reg = __muxreg2,               \
0078         .mask = __mask,                 \
0079         .val = __ste2 ? __mask : 0,         \
0080     },                          \
0081 }
0082
0083 #define GPIO_PINGROUP(__pins)                   \
0084     {                           \
0085         .pins = __pins,                 \
0086         .npins = ARRAY_SIZE(__pins),            \
0087         .muxregs = __pins##_muxregs,            \
0088         .nmuxregs = ARRAY_SIZE(__pins##_muxregs),   \
0089     }
0090
0091 /**
0092  * struct spear_modemux - SPEAr mode mux configuration
0093  * @modes: mode ids supported by this group of muxregs
0094  * @nmuxregs: number of muxreg configurations to be done for modes
0095  * @muxregs: array of muxreg configurations to be done for modes
0096  */
0097 struct spear_modemux {
0098     u16 modes;
0099     u8 nmuxregs;
0100     struct spear_muxreg *muxregs;
0101 };
0102
0103 /**
0104  * struct spear_pingroup - SPEAr pin group configurations
0105  * @name: name of pin group
0106  * @pins: array containing pin numbers
0107  * @npins: size of pins array
0108  * @modemuxs: array of modemux configurations for this pin group
0109  * @nmodemuxs: size of array modemuxs
0110  *
0111  * A representation of a group of pins in the SPEAr pin controller. Each group
0112  * allows some parameter or parameters to be configured.
0113  */
0114 struct spear_pingroup {
0115     const char *name;
0116     const unsigned *pins;
0117     unsigned npins;
0118     struct spear_modemux *modemuxs;
0119     unsigned nmodemuxs;
0120 };
0121
0122 /**
0123  * struct spear_function - SPEAr pinctrl mux function
0124  * @name: The name of the function, exported to pinctrl core.
0125  * @groups: An array of pin groups that may select this function.
0126  * @ngroups: The number of entries in @groups.
0127  */
0128 struct spear_function {
0129     const char *name;
0130     const char *const *groups;
0131     unsigned ngroups;
0132 };
0133
0134 /**
0135  * struct spear_pinctrl_machdata - SPEAr pin controller machine driver
0136  *  configuration
0137  * @pins: An array describing all pins the pin controller affects.
0138  *  All pins which are also GPIOs must be listed first within the *array,
0139  *  and be numbered identically to the GPIO controller's *numbering.
0140  * @npins: The numbmer of entries in @pins.
0141  * @functions: An array describing all mux functions the SoC supports.
0142  * @nfunctions: The numbmer of entries in @functions.
0143  * @groups: An array describing all pin groups the pin SoC supports.
0144  * @ngroups: The numbmer of entries in @groups.
0145  * @gpio_pingroups: gpio pingroups
0146  * @ngpio_pingroups: gpio pingroups count
0147  *
0148  * @modes_supported: Does SoC support modes
0149  * @mode: mode configured from probe
0150  * @pmx_modes: array of modes supported by SoC
0151  * @npmx_modes: number of entries in pmx_modes.
0152  */
0153 struct spear_pinctrl_machdata {
0154     const struct pinctrl_pin_desc *pins;
0155     unsigned npins;
0156     struct spear_function **functions;
0157     unsigned nfunctions;
0158     struct spear_pingroup **groups;
0159     unsigned ngroups;
0160     struct spear_gpio_pingroup *gpio_pingroups;
0161     void (*gpio_request_endisable)(struct spear_pmx *pmx, int offset,
0162             bool enable);
0163     unsigned ngpio_pingroups;
0164
0165     bool modes_supported;
0166     u16 mode;
0167     struct spear_pmx_mode **pmx_modes;
0168     unsigned npmx_modes;
0169 };
0170
0171 /**
0172  * struct spear_pmx - SPEAr pinctrl mux
0173  * @dev: pointer to struct dev of platform_device registered
0174  * @pctl: pointer to struct pinctrl_dev
0175  * @machdata: pointer to SoC or machine specific structure
0176  * @regmap: regmap of pinmux controller
0177  */
0178 struct spear_pmx {
0179     struct device *dev;
0180     struct pinctrl_dev *pctl;
0181     struct spear_pinctrl_machdata *machdata;
0182     struct regmap *regmap;
0183 };
0184
0185 /* exported routines */
0186 static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg)
0187 {
0188     u32 val;
0189
0190     regmap_read(pmx->regmap, reg, &val);
0191     return val;
0192 }
0193
0194 static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg)
0195 {
0196     regmap_write(pmx->regmap, reg, val);
0197 }
0198
0199 void pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
0200 void pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup,
0201                  unsigned count, u16 reg);
0202 int spear_pinctrl_probe(struct platform_device *pdev,
0203             struct spear_pinctrl_machdata *machdata);
0204
0205 #define SPEAR_PIN_0_TO_101      \
0206     PINCTRL_PIN(0, "PLGPIO0"),  \
0207     PINCTRL_PIN(1, "PLGPIO1"),  \
0208     PINCTRL_PIN(2, "PLGPIO2"),  \
0209     PINCTRL_PIN(3, "PLGPIO3"),  \
0210     PINCTRL_PIN(4, "PLGPIO4"),  \
0211     PINCTRL_PIN(5, "PLGPIO5"),  \
0212     PINCTRL_PIN(6, "PLGPIO6"),  \
0213     PINCTRL_PIN(7, "PLGPIO7"),  \
0214     PINCTRL_PIN(8, "PLGPIO8"),  \
0215     PINCTRL_PIN(9, "PLGPIO9"),  \
0216     PINCTRL_PIN(10, "PLGPIO10"),    \
0217     PINCTRL_PIN(11, "PLGPIO11"),    \
0218     PINCTRL_PIN(12, "PLGPIO12"),    \
0219     PINCTRL_PIN(13, "PLGPIO13"),    \
0220     PINCTRL_PIN(14, "PLGPIO14"),    \
0221     PINCTRL_PIN(15, "PLGPIO15"),    \
0222     PINCTRL_PIN(16, "PLGPIO16"),    \
0223     PINCTRL_PIN(17, "PLGPIO17"),    \
0224     PINCTRL_PIN(18, "PLGPIO18"),    \
0225     PINCTRL_PIN(19, "PLGPIO19"),    \
0226     PINCTRL_PIN(20, "PLGPIO20"),    \
0227     PINCTRL_PIN(21, "PLGPIO21"),    \
0228     PINCTRL_PIN(22, "PLGPIO22"),    \
0229     PINCTRL_PIN(23, "PLGPIO23"),    \
0230     PINCTRL_PIN(24, "PLGPIO24"),    \
0231     PINCTRL_PIN(25, "PLGPIO25"),    \
0232     PINCTRL_PIN(26, "PLGPIO26"),    \
0233     PINCTRL_PIN(27, "PLGPIO27"),    \
0234     PINCTRL_PIN(28, "PLGPIO28"),    \
0235     PINCTRL_PIN(29, "PLGPIO29"),    \
0236     PINCTRL_PIN(30, "PLGPIO30"),    \
0237     PINCTRL_PIN(31, "PLGPIO31"),    \
0238     PINCTRL_PIN(32, "PLGPIO32"),    \
0239     PINCTRL_PIN(33, "PLGPIO33"),    \
0240     PINCTRL_PIN(34, "PLGPIO34"),    \
0241     PINCTRL_PIN(35, "PLGPIO35"),    \
0242     PINCTRL_PIN(36, "PLGPIO36"),    \
0243     PINCTRL_PIN(37, "PLGPIO37"),    \
0244     PINCTRL_PIN(38, "PLGPIO38"),    \
0245     PINCTRL_PIN(39, "PLGPIO39"),    \
0246     PINCTRL_PIN(40, "PLGPIO40"),    \
0247     PINCTRL_PIN(41, "PLGPIO41"),    \
0248     PINCTRL_PIN(42, "PLGPIO42"),    \
0249     PINCTRL_PIN(43, "PLGPIO43"),    \
0250     PINCTRL_PIN(44, "PLGPIO44"),    \
0251     PINCTRL_PIN(45, "PLGPIO45"),    \
0252     PINCTRL_PIN(46, "PLGPIO46"),    \
0253     PINCTRL_PIN(47, "PLGPIO47"),    \
0254     PINCTRL_PIN(48, "PLGPIO48"),    \
0255     PINCTRL_PIN(49, "PLGPIO49"),    \
0256     PINCTRL_PIN(50, "PLGPIO50"),    \
0257     PINCTRL_PIN(51, "PLGPIO51"),    \
0258     PINCTRL_PIN(52, "PLGPIO52"),    \
0259     PINCTRL_PIN(53, "PLGPIO53"),    \
0260     PINCTRL_PIN(54, "PLGPIO54"),    \
0261     PINCTRL_PIN(55, "PLGPIO55"),    \
0262     PINCTRL_PIN(56, "PLGPIO56"),    \
0263     PINCTRL_PIN(57, "PLGPIO57"),    \
0264     PINCTRL_PIN(58, "PLGPIO58"),    \
0265     PINCTRL_PIN(59, "PLGPIO59"),    \
0266     PINCTRL_PIN(60, "PLGPIO60"),    \
0267     PINCTRL_PIN(61, "PLGPIO61"),    \
0268     PINCTRL_PIN(62, "PLGPIO62"),    \
0269     PINCTRL_PIN(63, "PLGPIO63"),    \
0270     PINCTRL_PIN(64, "PLGPIO64"),    \
0271     PINCTRL_PIN(65, "PLGPIO65"),    \
0272     PINCTRL_PIN(66, "PLGPIO66"),    \
0273     PINCTRL_PIN(67, "PLGPIO67"),    \
0274     PINCTRL_PIN(68, "PLGPIO68"),    \
0275     PINCTRL_PIN(69, "PLGPIO69"),    \
0276     PINCTRL_PIN(70, "PLGPIO70"),    \
0277     PINCTRL_PIN(71, "PLGPIO71"),    \
0278     PINCTRL_PIN(72, "PLGPIO72"),    \
0279     PINCTRL_PIN(73, "PLGPIO73"),    \
0280     PINCTRL_PIN(74, "PLGPIO74"),    \
0281     PINCTRL_PIN(75, "PLGPIO75"),    \
0282     PINCTRL_PIN(76, "PLGPIO76"),    \
0283     PINCTRL_PIN(77, "PLGPIO77"),    \
0284     PINCTRL_PIN(78, "PLGPIO78"),    \
0285     PINCTRL_PIN(79, "PLGPIO79"),    \
0286     PINCTRL_PIN(80, "PLGPIO80"),    \
0287     PINCTRL_PIN(81, "PLGPIO81"),    \
0288     PINCTRL_PIN(82, "PLGPIO82"),    \
0289     PINCTRL_PIN(83, "PLGPIO83"),    \
0290     PINCTRL_PIN(84, "PLGPIO84"),    \
0291     PINCTRL_PIN(85, "PLGPIO85"),    \
0292     PINCTRL_PIN(86, "PLGPIO86"),    \
0293     PINCTRL_PIN(87, "PLGPIO87"),    \
0294     PINCTRL_PIN(88, "PLGPIO88"),    \
0295     PINCTRL_PIN(89, "PLGPIO89"),    \
0296     PINCTRL_PIN(90, "PLGPIO90"),    \
0297     PINCTRL_PIN(91, "PLGPIO91"),    \
0298     PINCTRL_PIN(92, "PLGPIO92"),    \
0299     PINCTRL_PIN(93, "PLGPIO93"),    \
0300     PINCTRL_PIN(94, "PLGPIO94"),    \
0301     PINCTRL_PIN(95, "PLGPIO95"),    \
0302     PINCTRL_PIN(96, "PLGPIO96"),    \
0303     PINCTRL_PIN(97, "PLGPIO97"),    \
0304     PINCTRL_PIN(98, "PLGPIO98"),    \
0305     PINCTRL_PIN(99, "PLGPIO99"),    \
0306     PINCTRL_PIN(100, "PLGPIO100"),  \
0307     PINCTRL_PIN(101, "PLGPIO101")
0308
0309 #define SPEAR_PIN_102_TO_245        \
0310     PINCTRL_PIN(102, "PLGPIO102"),  \
0311     PINCTRL_PIN(103, "PLGPIO103"),  \
0312     PINCTRL_PIN(104, "PLGPIO104"),  \
0313     PINCTRL_PIN(105, "PLGPIO105"),  \
0314     PINCTRL_PIN(106, "PLGPIO106"),  \
0315     PINCTRL_PIN(107, "PLGPIO107"),  \
0316     PINCTRL_PIN(108, "PLGPIO108"),  \
0317     PINCTRL_PIN(109, "PLGPIO109"),  \
0318     PINCTRL_PIN(110, "PLGPIO110"),  \
0319     PINCTRL_PIN(111, "PLGPIO111"),  \
0320     PINCTRL_PIN(112, "PLGPIO112"),  \
0321     PINCTRL_PIN(113, "PLGPIO113"),  \
0322     PINCTRL_PIN(114, "PLGPIO114"),  \
0323     PINCTRL_PIN(115, "PLGPIO115"),  \
0324     PINCTRL_PIN(116, "PLGPIO116"),  \
0325     PINCTRL_PIN(117, "PLGPIO117"),  \
0326     PINCTRL_PIN(118, "PLGPIO118"),  \
0327     PINCTRL_PIN(119, "PLGPIO119"),  \
0328     PINCTRL_PIN(120, "PLGPIO120"),  \
0329     PINCTRL_PIN(121, "PLGPIO121"),  \
0330     PINCTRL_PIN(122, "PLGPIO122"),  \
0331     PINCTRL_PIN(123, "PLGPIO123"),  \
0332     PINCTRL_PIN(124, "PLGPIO124"),  \
0333     PINCTRL_PIN(125, "PLGPIO125"),  \
0334     PINCTRL_PIN(126, "PLGPIO126"),  \
0335     PINCTRL_PIN(127, "PLGPIO127"),  \
0336     PINCTRL_PIN(128, "PLGPIO128"),  \
0337     PINCTRL_PIN(129, "PLGPIO129"),  \
0338     PINCTRL_PIN(130, "PLGPIO130"),  \
0339     PINCTRL_PIN(131, "PLGPIO131"),  \
0340     PINCTRL_PIN(132, "PLGPIO132"),  \
0341     PINCTRL_PIN(133, "PLGPIO133"),  \
0342     PINCTRL_PIN(134, "PLGPIO134"),  \
0343     PINCTRL_PIN(135, "PLGPIO135"),  \
0344     PINCTRL_PIN(136, "PLGPIO136"),  \
0345     PINCTRL_PIN(137, "PLGPIO137"),  \
0346     PINCTRL_PIN(138, "PLGPIO138"),  \
0347     PINCTRL_PIN(139, "PLGPIO139"),  \
0348     PINCTRL_PIN(140, "PLGPIO140"),  \
0349     PINCTRL_PIN(141, "PLGPIO141"),  \
0350     PINCTRL_PIN(142, "PLGPIO142"),  \
0351     PINCTRL_PIN(143, "PLGPIO143"),  \
0352     PINCTRL_PIN(144, "PLGPIO144"),  \
0353     PINCTRL_PIN(145, "PLGPIO145"),  \
0354     PINCTRL_PIN(146, "PLGPIO146"),  \
0355     PINCTRL_PIN(147, "PLGPIO147"),  \
0356     PINCTRL_PIN(148, "PLGPIO148"),  \
0357     PINCTRL_PIN(149, "PLGPIO149"),  \
0358     PINCTRL_PIN(150, "PLGPIO150"),  \
0359     PINCTRL_PIN(151, "PLGPIO151"),  \
0360     PINCTRL_PIN(152, "PLGPIO152"),  \
0361     PINCTRL_PIN(153, "PLGPIO153"),  \
0362     PINCTRL_PIN(154, "PLGPIO154"),  \
0363     PINCTRL_PIN(155, "PLGPIO155"),  \
0364     PINCTRL_PIN(156, "PLGPIO156"),  \
0365     PINCTRL_PIN(157, "PLGPIO157"),  \
0366     PINCTRL_PIN(158, "PLGPIO158"),  \
0367     PINCTRL_PIN(159, "PLGPIO159"),  \
0368     PINCTRL_PIN(160, "PLGPIO160"),  \
0369     PINCTRL_PIN(161, "PLGPIO161"),  \
0370     PINCTRL_PIN(162, "PLGPIO162"),  \
0371     PINCTRL_PIN(163, "PLGPIO163"),  \
0372     PINCTRL_PIN(164, "PLGPIO164"),  \
0373     PINCTRL_PIN(165, "PLGPIO165"),  \
0374     PINCTRL_PIN(166, "PLGPIO166"),  \
0375     PINCTRL_PIN(167, "PLGPIO167"),  \
0376     PINCTRL_PIN(168, "PLGPIO168"),  \
0377     PINCTRL_PIN(169, "PLGPIO169"),  \
0378     PINCTRL_PIN(170, "PLGPIO170"),  \
0379     PINCTRL_PIN(171, "PLGPIO171"),  \
0380     PINCTRL_PIN(172, "PLGPIO172"),  \
0381     PINCTRL_PIN(173, "PLGPIO173"),  \
0382     PINCTRL_PIN(174, "PLGPIO174"),  \
0383     PINCTRL_PIN(175, "PLGPIO175"),  \
0384     PINCTRL_PIN(176, "PLGPIO176"),  \
0385     PINCTRL_PIN(177, "PLGPIO177"),  \
0386     PINCTRL_PIN(178, "PLGPIO178"),  \
0387     PINCTRL_PIN(179, "PLGPIO179"),  \
0388     PINCTRL_PIN(180, "PLGPIO180"),  \
0389     PINCTRL_PIN(181, "PLGPIO181"),  \
0390     PINCTRL_PIN(182, "PLGPIO182"),  \
0391     PINCTRL_PIN(183, "PLGPIO183"),  \
0392     PINCTRL_PIN(184, "PLGPIO184"),  \
0393     PINCTRL_PIN(185, "PLGPIO185"),  \
0394     PINCTRL_PIN(186, "PLGPIO186"),  \
0395     PINCTRL_PIN(187, "PLGPIO187"),  \
0396     PINCTRL_PIN(188, "PLGPIO188"),  \
0397     PINCTRL_PIN(189, "PLGPIO189"),  \
0398     PINCTRL_PIN(190, "PLGPIO190"),  \
0399     PINCTRL_PIN(191, "PLGPIO191"),  \
0400     PINCTRL_PIN(192, "PLGPIO192"),  \
0401     PINCTRL_PIN(193, "PLGPIO193"),  \
0402     PINCTRL_PIN(194, "PLGPIO194"),  \
0403     PINCTRL_PIN(195, "PLGPIO195"),  \
0404     PINCTRL_PIN(196, "PLGPIO196"),  \
0405     PINCTRL_PIN(197, "PLGPIO197"),  \
0406     PINCTRL_PIN(198, "PLGPIO198"),  \
0407     PINCTRL_PIN(199, "PLGPIO199"),  \
0408     PINCTRL_PIN(200, "PLGPIO200"),  \
0409     PINCTRL_PIN(201, "PLGPIO201"),  \
0410     PINCTRL_PIN(202, "PLGPIO202"),  \
0411     PINCTRL_PIN(203, "PLGPIO203"),  \
0412     PINCTRL_PIN(204, "PLGPIO204"),  \
0413     PINCTRL_PIN(205, "PLGPIO205"),  \
0414     PINCTRL_PIN(206, "PLGPIO206"),  \
0415     PINCTRL_PIN(207, "PLGPIO207"),  \
0416     PINCTRL_PIN(208, "PLGPIO208"),  \
0417     PINCTRL_PIN(209, "PLGPIO209"),  \
0418     PINCTRL_PIN(210, "PLGPIO210"),  \
0419     PINCTRL_PIN(211, "PLGPIO211"),  \
0420     PINCTRL_PIN(212, "PLGPIO212"),  \
0421     PINCTRL_PIN(213, "PLGPIO213"),  \
0422     PINCTRL_PIN(214, "PLGPIO214"),  \
0423     PINCTRL_PIN(215, "PLGPIO215"),  \
0424     PINCTRL_PIN(216, "PLGPIO216"),  \
0425     PINCTRL_PIN(217, "PLGPIO217"),  \
0426     PINCTRL_PIN(218, "PLGPIO218"),  \
0427     PINCTRL_PIN(219, "PLGPIO219"),  \
0428     PINCTRL_PIN(220, "PLGPIO220"),  \
0429     PINCTRL_PIN(221, "PLGPIO221"),  \
0430     PINCTRL_PIN(222, "PLGPIO222"),  \
0431     PINCTRL_PIN(223, "PLGPIO223"),  \
0432     PINCTRL_PIN(224, "PLGPIO224"),  \
0433     PINCTRL_PIN(225, "PLGPIO225"),  \
0434     PINCTRL_PIN(226, "PLGPIO226"),  \
0435     PINCTRL_PIN(227, "PLGPIO227"),  \
0436     PINCTRL_PIN(228, "PLGPIO228"),  \
0437     PINCTRL_PIN(229, "PLGPIO229"),  \
0438     PINCTRL_PIN(230, "PLGPIO230"),  \
0439     PINCTRL_PIN(231, "PLGPIO231"),  \
0440     PINCTRL_PIN(232, "PLGPIO232"),  \
0441     PINCTRL_PIN(233, "PLGPIO233"),  \
0442     PINCTRL_PIN(234, "PLGPIO234"),  \
0443     PINCTRL_PIN(235, "PLGPIO235"),  \
0444     PINCTRL_PIN(236, "PLGPIO236"),  \
0445     PINCTRL_PIN(237, "PLGPIO237"),  \
0446     PINCTRL_PIN(238, "PLGPIO238"),  \
0447     PINCTRL_PIN(239, "PLGPIO239"),  \
0448     PINCTRL_PIN(240, "PLGPIO240"),  \
0449     PINCTRL_PIN(241, "PLGPIO241"),  \
0450     PINCTRL_PIN(242, "PLGPIO242"),  \
0451     PINCTRL_PIN(243, "PLGPIO243"),  \
0452     PINCTRL_PIN(244, "PLGPIO244"),  \
0453     PINCTRL_PIN(245, "PLGPIO245")
0454
0455 #endif /* __PINMUX_SPEAR_H__ */