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0001 /*
0002  * SPEAr platform PLGPIO driver
0003  *
0004  * Copyright (C) 2012 ST Microelectronics
0005  * Viresh Kumar <viresh.kumar@linaro.org>
0006  *
0007  * This file is licensed under the terms of the GNU General Public
0008  * License version 2. This program is licensed "as is" without any
0009  * warranty of any kind, whether express or implied.
0010  */
0011 
0012 #include <linux/clk.h>
0013 #include <linux/err.h>
0014 #include <linux/gpio/driver.h>
0015 #include <linux/io.h>
0016 #include <linux/init.h>
0017 #include <linux/mfd/syscon.h>
0018 #include <linux/of.h>
0019 #include <linux/of_platform.h>
0020 #include <linux/pinctrl/consumer.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/pm.h>
0023 #include <linux/regmap.h>
0024 #include <linux/spinlock.h>
0025 
0026 #define MAX_GPIO_PER_REG        32
0027 #define PIN_OFFSET(pin)         (pin % MAX_GPIO_PER_REG)
0028 #define REG_OFFSET(base, reg, pin)  (base + reg + (pin / MAX_GPIO_PER_REG) \
0029                             * sizeof(int *))
0030 
0031 /*
0032  * plgpio pins in all machines are not one to one mapped, bitwise with registers
0033  * bits. These set of macros define register masks for which below functions
0034  * (pin_to_offset and offset_to_pin) are required to be called.
0035  */
0036 #define PTO_ENB_REG     0x001
0037 #define PTO_WDATA_REG       0x002
0038 #define PTO_DIR_REG     0x004
0039 #define PTO_IE_REG      0x008
0040 #define PTO_RDATA_REG       0x010
0041 #define PTO_MIS_REG     0x020
0042 
0043 struct plgpio_regs {
0044     u32 enb;        /* enable register */
0045     u32 wdata;      /* write data register */
0046     u32 dir;        /* direction set register */
0047     u32 rdata;      /* read data register */
0048     u32 ie;         /* interrupt enable register */
0049     u32 mis;        /* mask interrupt status register */
0050     u32 eit;        /* edge interrupt type */
0051 };
0052 
0053 /*
0054  * struct plgpio: plgpio driver specific structure
0055  *
0056  * lock: lock for guarding gpio registers
0057  * base: base address of plgpio block
0058  * chip: gpio framework specific chip information structure
0059  * p2o: function ptr for pin to offset conversion. This is required only for
0060  *  machines where mapping b/w pin and offset is not 1-to-1.
0061  * o2p: function ptr for offset to pin conversion. This is required only for
0062  *  machines where mapping b/w pin and offset is not 1-to-1.
0063  * p2o_regs: mask of registers for which p2o and o2p are applicable
0064  * regs: register offsets
0065  * csave_regs: context save registers for standby/sleep/hibernate cases
0066  */
0067 struct plgpio {
0068     spinlock_t      lock;
0069     struct regmap       *regmap;
0070     struct clk      *clk;
0071     struct gpio_chip    chip;
0072     int         (*p2o)(int pin);    /* pin_to_offset */
0073     int         (*o2p)(int offset); /* offset_to_pin */
0074     u32         p2o_regs;
0075     struct plgpio_regs  regs;
0076 #ifdef CONFIG_PM_SLEEP
0077     struct plgpio_regs  *csave_regs;
0078 #endif
0079 };
0080 
0081 /* register manipulation inline functions */
0082 static inline u32 is_plgpio_set(struct regmap *regmap, u32 pin, u32 reg)
0083 {
0084     u32 offset = PIN_OFFSET(pin);
0085     u32 reg_off = REG_OFFSET(0, reg, pin);
0086     u32 val;
0087 
0088     regmap_read(regmap, reg_off, &val);
0089 
0090     return !!(val & (1 << offset));
0091 }
0092 
0093 static inline void plgpio_reg_set(struct regmap *regmap, u32 pin, u32 reg)
0094 {
0095     u32 offset = PIN_OFFSET(pin);
0096     u32 reg_off = REG_OFFSET(0, reg, pin);
0097     u32 mask;
0098 
0099     mask = 1 << offset;
0100     regmap_update_bits(regmap, reg_off, mask, mask);
0101 }
0102 
0103 static inline void plgpio_reg_reset(struct regmap *regmap, u32 pin, u32 reg)
0104 {
0105     u32 offset = PIN_OFFSET(pin);
0106     u32 reg_off = REG_OFFSET(0, reg, pin);
0107     u32 mask;
0108 
0109     mask = 1 << offset;
0110     regmap_update_bits(regmap, reg_off, mask, 0);
0111 }
0112 
0113 
0114 /* gpio framework specific routines */
0115 static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset)
0116 {
0117     struct plgpio *plgpio = gpiochip_get_data(chip);
0118     unsigned long flags;
0119 
0120     /* get correct offset for "offset" pin */
0121     if (plgpio->p2o && (plgpio->p2o_regs & PTO_DIR_REG)) {
0122         offset = plgpio->p2o(offset);
0123         if (offset == -1)
0124             return -EINVAL;
0125     }
0126 
0127     spin_lock_irqsave(&plgpio->lock, flags);
0128     plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.dir);
0129     spin_unlock_irqrestore(&plgpio->lock, flags);
0130 
0131     return 0;
0132 }
0133 
0134 static int plgpio_direction_output(struct gpio_chip *chip, unsigned offset,
0135         int value)
0136 {
0137     struct plgpio *plgpio = gpiochip_get_data(chip);
0138     unsigned long flags;
0139     unsigned dir_offset = offset, wdata_offset = offset, tmp;
0140 
0141     /* get correct offset for "offset" pin */
0142     if (plgpio->p2o && (plgpio->p2o_regs & (PTO_DIR_REG | PTO_WDATA_REG))) {
0143         tmp = plgpio->p2o(offset);
0144         if (tmp == -1)
0145             return -EINVAL;
0146 
0147         if (plgpio->p2o_regs & PTO_DIR_REG)
0148             dir_offset = tmp;
0149         if (plgpio->p2o_regs & PTO_WDATA_REG)
0150             wdata_offset = tmp;
0151     }
0152 
0153     spin_lock_irqsave(&plgpio->lock, flags);
0154     if (value)
0155         plgpio_reg_set(plgpio->regmap, wdata_offset,
0156                 plgpio->regs.wdata);
0157     else
0158         plgpio_reg_reset(plgpio->regmap, wdata_offset,
0159                 plgpio->regs.wdata);
0160 
0161     plgpio_reg_reset(plgpio->regmap, dir_offset, plgpio->regs.dir);
0162     spin_unlock_irqrestore(&plgpio->lock, flags);
0163 
0164     return 0;
0165 }
0166 
0167 static int plgpio_get_value(struct gpio_chip *chip, unsigned offset)
0168 {
0169     struct plgpio *plgpio = gpiochip_get_data(chip);
0170 
0171     if (offset >= chip->ngpio)
0172         return -EINVAL;
0173 
0174     /* get correct offset for "offset" pin */
0175     if (plgpio->p2o && (plgpio->p2o_regs & PTO_RDATA_REG)) {
0176         offset = plgpio->p2o(offset);
0177         if (offset == -1)
0178             return -EINVAL;
0179     }
0180 
0181     return is_plgpio_set(plgpio->regmap, offset, plgpio->regs.rdata);
0182 }
0183 
0184 static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
0185 {
0186     struct plgpio *plgpio = gpiochip_get_data(chip);
0187 
0188     if (offset >= chip->ngpio)
0189         return;
0190 
0191     /* get correct offset for "offset" pin */
0192     if (plgpio->p2o && (plgpio->p2o_regs & PTO_WDATA_REG)) {
0193         offset = plgpio->p2o(offset);
0194         if (offset == -1)
0195             return;
0196     }
0197 
0198     if (value)
0199         plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.wdata);
0200     else
0201         plgpio_reg_reset(plgpio->regmap, offset, plgpio->regs.wdata);
0202 }
0203 
0204 static int plgpio_request(struct gpio_chip *chip, unsigned offset)
0205 {
0206     struct plgpio *plgpio = gpiochip_get_data(chip);
0207     int gpio = chip->base + offset;
0208     unsigned long flags;
0209     int ret = 0;
0210 
0211     if (offset >= chip->ngpio)
0212         return -EINVAL;
0213 
0214     ret = pinctrl_gpio_request(gpio);
0215     if (ret)
0216         return ret;
0217 
0218     if (!IS_ERR(plgpio->clk)) {
0219         ret = clk_enable(plgpio->clk);
0220         if (ret)
0221             goto err0;
0222     }
0223 
0224     if (plgpio->regs.enb == -1)
0225         return 0;
0226 
0227     /*
0228      * put gpio in IN mode before enabling it. This make enabling gpio safe
0229      */
0230     ret = plgpio_direction_input(chip, offset);
0231     if (ret)
0232         goto err1;
0233 
0234     /* get correct offset for "offset" pin */
0235     if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
0236         offset = plgpio->p2o(offset);
0237         if (offset == -1) {
0238             ret = -EINVAL;
0239             goto err1;
0240         }
0241     }
0242 
0243     spin_lock_irqsave(&plgpio->lock, flags);
0244     plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.enb);
0245     spin_unlock_irqrestore(&plgpio->lock, flags);
0246     return 0;
0247 
0248 err1:
0249     if (!IS_ERR(plgpio->clk))
0250         clk_disable(plgpio->clk);
0251 err0:
0252     pinctrl_gpio_free(gpio);
0253     return ret;
0254 }
0255 
0256 static void plgpio_free(struct gpio_chip *chip, unsigned offset)
0257 {
0258     struct plgpio *plgpio = gpiochip_get_data(chip);
0259     int gpio = chip->base + offset;
0260     unsigned long flags;
0261 
0262     if (offset >= chip->ngpio)
0263         return;
0264 
0265     if (plgpio->regs.enb == -1)
0266         goto disable_clk;
0267 
0268     /* get correct offset for "offset" pin */
0269     if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
0270         offset = plgpio->p2o(offset);
0271         if (offset == -1)
0272             return;
0273     }
0274 
0275     spin_lock_irqsave(&plgpio->lock, flags);
0276     plgpio_reg_reset(plgpio->regmap, offset, plgpio->regs.enb);
0277     spin_unlock_irqrestore(&plgpio->lock, flags);
0278 
0279 disable_clk:
0280     if (!IS_ERR(plgpio->clk))
0281         clk_disable(plgpio->clk);
0282 
0283     pinctrl_gpio_free(gpio);
0284 }
0285 
0286 /* PLGPIO IRQ */
0287 static void plgpio_irq_disable(struct irq_data *d)
0288 {
0289     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0290     struct plgpio *plgpio = gpiochip_get_data(gc);
0291     int offset = d->hwirq;
0292     unsigned long flags;
0293 
0294     /* get correct offset for "offset" pin */
0295     if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
0296         offset = plgpio->p2o(offset);
0297         if (offset == -1)
0298             return;
0299     }
0300 
0301     spin_lock_irqsave(&plgpio->lock, flags);
0302     plgpio_reg_set(plgpio->regmap, offset, plgpio->regs.ie);
0303     spin_unlock_irqrestore(&plgpio->lock, flags);
0304 }
0305 
0306 static void plgpio_irq_enable(struct irq_data *d)
0307 {
0308     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0309     struct plgpio *plgpio = gpiochip_get_data(gc);
0310     int offset = d->hwirq;
0311     unsigned long flags;
0312 
0313     /* get correct offset for "offset" pin */
0314     if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
0315         offset = plgpio->p2o(offset);
0316         if (offset == -1)
0317             return;
0318     }
0319 
0320     spin_lock_irqsave(&plgpio->lock, flags);
0321     plgpio_reg_reset(plgpio->regmap, offset, plgpio->regs.ie);
0322     spin_unlock_irqrestore(&plgpio->lock, flags);
0323 }
0324 
0325 static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger)
0326 {
0327     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0328     struct plgpio *plgpio = gpiochip_get_data(gc);
0329     int offset = d->hwirq;
0330     u32 reg_off;
0331     unsigned int supported_type = 0, val;
0332 
0333     if (offset >= plgpio->chip.ngpio)
0334         return -EINVAL;
0335 
0336     if (plgpio->regs.eit == -1)
0337         supported_type = IRQ_TYPE_LEVEL_HIGH;
0338     else
0339         supported_type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
0340 
0341     if (!(trigger & supported_type))
0342         return -EINVAL;
0343 
0344     if (plgpio->regs.eit == -1)
0345         return 0;
0346 
0347     reg_off = REG_OFFSET(0, plgpio->regs.eit, offset);
0348     regmap_read(plgpio->regmap, reg_off, &val);
0349 
0350     offset = PIN_OFFSET(offset);
0351     if (trigger & IRQ_TYPE_EDGE_RISING)
0352         regmap_write(plgpio->regmap, reg_off, val | (1 << offset));
0353     else
0354         regmap_write(plgpio->regmap, reg_off, val & ~(1 << offset));
0355 
0356     return 0;
0357 }
0358 
0359 static struct irq_chip plgpio_irqchip = {
0360     .name       = "PLGPIO",
0361     .irq_enable = plgpio_irq_enable,
0362     .irq_disable    = plgpio_irq_disable,
0363     .irq_set_type   = plgpio_irq_set_type,
0364 };
0365 
0366 static void plgpio_irq_handler(struct irq_desc *desc)
0367 {
0368     struct gpio_chip *gc = irq_desc_get_handler_data(desc);
0369     struct plgpio *plgpio = gpiochip_get_data(gc);
0370     struct irq_chip *irqchip = irq_desc_get_chip(desc);
0371     int regs_count, count, pin, offset, i = 0;
0372     u32 pending;
0373     unsigned long pendingl;
0374 
0375     count = plgpio->chip.ngpio;
0376     regs_count = DIV_ROUND_UP(count, MAX_GPIO_PER_REG);
0377 
0378     chained_irq_enter(irqchip, desc);
0379     /* check all plgpio MIS registers for a possible interrupt */
0380     for (; i < regs_count; i++) {
0381         regmap_read(plgpio->regmap, plgpio->regs.mis +
0382             i * sizeof(int *), &pending);
0383         if (!pending)
0384             continue;
0385 
0386         /* clear interrupts */
0387         regmap_write(plgpio->regmap, plgpio->regs.mis +
0388             i * sizeof(int *), ~pending);
0389         /*
0390          * clear extra bits in last register having gpios < MAX/REG
0391          * ex: Suppose there are max 102 plgpios. then last register
0392          * must have only (102 - MAX_GPIO_PER_REG * 3) = 6 relevant bits
0393          * so, we must not take other 28 bits into consideration for
0394          * checking interrupt. so clear those bits.
0395          */
0396         count = count - i * MAX_GPIO_PER_REG;
0397         if (count < MAX_GPIO_PER_REG)
0398             pending &= (1 << count) - 1;
0399 
0400         pendingl = pending;
0401         for_each_set_bit(offset, &pendingl, MAX_GPIO_PER_REG) {
0402             /* get correct pin for "offset" */
0403             if (plgpio->o2p && (plgpio->p2o_regs & PTO_MIS_REG)) {
0404                 pin = plgpio->o2p(offset);
0405                 if (pin == -1)
0406                     continue;
0407             } else
0408                 pin = offset;
0409 
0410             /* get correct irq line number */
0411             pin = i * MAX_GPIO_PER_REG + pin;
0412             generic_handle_domain_irq(gc->irq.domain, pin);
0413         }
0414     }
0415     chained_irq_exit(irqchip, desc);
0416 }
0417 
0418 /*
0419  * pin to offset and offset to pin converter functions
0420  *
0421  * In spear310 there is inconsistency among bit positions in plgpio regiseters,
0422  * for different plgpio pins. For example: for pin 27, bit offset is 23, pin
0423  * 28-33 are not supported, pin 95 has offset bit 95, bit 100 has offset bit 1
0424  */
0425 static int spear310_p2o(int pin)
0426 {
0427     int offset = pin;
0428 
0429     if (pin <= 27)
0430         offset += 4;
0431     else if (pin <= 33)
0432         offset = -1;
0433     else if (pin <= 97)
0434         offset -= 2;
0435     else if (pin <= 101)
0436         offset = 101 - pin;
0437     else
0438         offset = -1;
0439 
0440     return offset;
0441 }
0442 
0443 static int spear310_o2p(int offset)
0444 {
0445     if (offset <= 3)
0446         return 101 - offset;
0447     else if (offset <= 31)
0448         return offset - 4;
0449     else
0450         return offset + 2;
0451 }
0452 
0453 static int plgpio_probe_dt(struct platform_device *pdev, struct plgpio *plgpio)
0454 {
0455     struct device_node *np = pdev->dev.of_node;
0456     int ret = -EINVAL;
0457     u32 val;
0458 
0459     if (of_machine_is_compatible("st,spear310")) {
0460         plgpio->p2o = spear310_p2o;
0461         plgpio->o2p = spear310_o2p;
0462         plgpio->p2o_regs = PTO_WDATA_REG | PTO_DIR_REG | PTO_IE_REG |
0463             PTO_RDATA_REG | PTO_MIS_REG;
0464     }
0465 
0466     if (!of_property_read_u32(np, "st-plgpio,ngpio", &val)) {
0467         plgpio->chip.ngpio = val;
0468     } else {
0469         dev_err(&pdev->dev, "DT: Invalid ngpio field\n");
0470         goto end;
0471     }
0472 
0473     if (!of_property_read_u32(np, "st-plgpio,enb-reg", &val))
0474         plgpio->regs.enb = val;
0475     else
0476         plgpio->regs.enb = -1;
0477 
0478     if (!of_property_read_u32(np, "st-plgpio,wdata-reg", &val)) {
0479         plgpio->regs.wdata = val;
0480     } else {
0481         dev_err(&pdev->dev, "DT: Invalid wdata reg\n");
0482         goto end;
0483     }
0484 
0485     if (!of_property_read_u32(np, "st-plgpio,dir-reg", &val)) {
0486         plgpio->regs.dir = val;
0487     } else {
0488         dev_err(&pdev->dev, "DT: Invalid dir reg\n");
0489         goto end;
0490     }
0491 
0492     if (!of_property_read_u32(np, "st-plgpio,ie-reg", &val)) {
0493         plgpio->regs.ie = val;
0494     } else {
0495         dev_err(&pdev->dev, "DT: Invalid ie reg\n");
0496         goto end;
0497     }
0498 
0499     if (!of_property_read_u32(np, "st-plgpio,rdata-reg", &val)) {
0500         plgpio->regs.rdata = val;
0501     } else {
0502         dev_err(&pdev->dev, "DT: Invalid rdata reg\n");
0503         goto end;
0504     }
0505 
0506     if (!of_property_read_u32(np, "st-plgpio,mis-reg", &val)) {
0507         plgpio->regs.mis = val;
0508     } else {
0509         dev_err(&pdev->dev, "DT: Invalid mis reg\n");
0510         goto end;
0511     }
0512 
0513     if (!of_property_read_u32(np, "st-plgpio,eit-reg", &val))
0514         plgpio->regs.eit = val;
0515     else
0516         plgpio->regs.eit = -1;
0517 
0518     return 0;
0519 
0520 end:
0521     return ret;
0522 }
0523 
0524 static int plgpio_probe(struct platform_device *pdev)
0525 {
0526     struct device_node *regmap_np;
0527     struct plgpio *plgpio;
0528     int ret, irq;
0529 
0530     plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL);
0531     if (!plgpio)
0532         return -ENOMEM;
0533 
0534     regmap_np = of_parse_phandle(pdev->dev.of_node, "regmap", 0);
0535     if (regmap_np) {
0536         plgpio->regmap = device_node_to_regmap(regmap_np);
0537         of_node_put(regmap_np);
0538         if (IS_ERR(plgpio->regmap)) {
0539             dev_err(&pdev->dev, "Retrieve regmap failed (%pe)\n",
0540                 plgpio->regmap);
0541             return PTR_ERR(plgpio->regmap);
0542         }
0543     } else {
0544         plgpio->regmap = device_node_to_regmap(pdev->dev.of_node);
0545         if (IS_ERR(plgpio->regmap)) {
0546             dev_err(&pdev->dev, "Init regmap failed (%pe)\n",
0547                 plgpio->regmap);
0548             return PTR_ERR(plgpio->regmap);
0549         }
0550     }
0551 
0552     ret = plgpio_probe_dt(pdev, plgpio);
0553     if (ret) {
0554         dev_err(&pdev->dev, "DT probe failed\n");
0555         return ret;
0556     }
0557 
0558     plgpio->clk = devm_clk_get(&pdev->dev, NULL);
0559     if (IS_ERR(plgpio->clk))
0560         dev_warn(&pdev->dev, "clk_get() failed, work without it\n");
0561 
0562 #ifdef CONFIG_PM_SLEEP
0563     plgpio->csave_regs = devm_kcalloc(&pdev->dev,
0564             DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG),
0565             sizeof(*plgpio->csave_regs),
0566             GFP_KERNEL);
0567     if (!plgpio->csave_regs)
0568         return -ENOMEM;
0569 #endif
0570 
0571     platform_set_drvdata(pdev, plgpio);
0572     spin_lock_init(&plgpio->lock);
0573 
0574     plgpio->chip.base = -1;
0575     plgpio->chip.request = plgpio_request;
0576     plgpio->chip.free = plgpio_free;
0577     plgpio->chip.direction_input = plgpio_direction_input;
0578     plgpio->chip.direction_output = plgpio_direction_output;
0579     plgpio->chip.get = plgpio_get_value;
0580     plgpio->chip.set = plgpio_set_value;
0581     plgpio->chip.label = dev_name(&pdev->dev);
0582     plgpio->chip.parent = &pdev->dev;
0583     plgpio->chip.owner = THIS_MODULE;
0584 
0585     if (!IS_ERR(plgpio->clk)) {
0586         ret = clk_prepare(plgpio->clk);
0587         if (ret) {
0588             dev_err(&pdev->dev, "clk prepare failed\n");
0589             return ret;
0590         }
0591     }
0592 
0593     irq = platform_get_irq(pdev, 0);
0594     if (irq > 0) {
0595         struct gpio_irq_chip *girq;
0596 
0597         girq = &plgpio->chip.irq;
0598         girq->chip = &plgpio_irqchip;
0599         girq->parent_handler = plgpio_irq_handler;
0600         girq->num_parents = 1;
0601         girq->parents = devm_kcalloc(&pdev->dev, 1,
0602                          sizeof(*girq->parents),
0603                          GFP_KERNEL);
0604         if (!girq->parents)
0605             return -ENOMEM;
0606         girq->parents[0] = irq;
0607         girq->default_type = IRQ_TYPE_NONE;
0608         girq->handler = handle_simple_irq;
0609         dev_info(&pdev->dev, "PLGPIO registering with IRQs\n");
0610     } else {
0611         dev_info(&pdev->dev, "PLGPIO registering without IRQs\n");
0612     }
0613 
0614     ret = gpiochip_add_data(&plgpio->chip, plgpio);
0615     if (ret) {
0616         dev_err(&pdev->dev, "unable to add gpio chip\n");
0617         goto unprepare_clk;
0618     }
0619 
0620     return 0;
0621 
0622 unprepare_clk:
0623     if (!IS_ERR(plgpio->clk))
0624         clk_unprepare(plgpio->clk);
0625 
0626     return ret;
0627 }
0628 
0629 #ifdef CONFIG_PM_SLEEP
0630 static int plgpio_suspend(struct device *dev)
0631 {
0632     struct plgpio *plgpio = dev_get_drvdata(dev);
0633     int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
0634     u32 off;
0635 
0636     for (i = 0; i < reg_count; i++) {
0637         off = i * sizeof(int *);
0638 
0639         if (plgpio->regs.enb != -1)
0640             regmap_read(plgpio->regmap, plgpio->regs.enb + off,
0641                 &plgpio->csave_regs[i].enb);
0642         if (plgpio->regs.eit != -1)
0643             regmap_read(plgpio->regmap, plgpio->regs.eit + off,
0644                 &plgpio->csave_regs[i].eit);
0645         regmap_read(plgpio->regmap, plgpio->regs.wdata + off,
0646                 &plgpio->csave_regs[i].wdata);
0647         regmap_read(plgpio->regmap, plgpio->regs.dir + off,
0648                 &plgpio->csave_regs[i].dir);
0649         regmap_read(plgpio->regmap, plgpio->regs.ie + off,
0650                 &plgpio->csave_regs[i].ie);
0651     }
0652 
0653     return 0;
0654 }
0655 
0656 /*
0657  * This is used to correct the values in end registers. End registers contain
0658  * extra bits that might be used for other purpose in platform. So, we shouldn't
0659  * overwrite these bits. This macro, reads given register again, preserves other
0660  * bit values (non-plgpio bits), and retain captured value (plgpio bits).
0661  */
0662 #define plgpio_prepare_reg(__reg, _off, _mask, _tmp)        \
0663 {                               \
0664     regmap_read(plgpio->regmap, plgpio->regs.__reg + _off, &_tmp); \
0665     _tmp &= ~_mask;                     \
0666     plgpio->csave_regs[i].__reg =               \
0667         _tmp | (plgpio->csave_regs[i].__reg & _mask);   \
0668 }
0669 
0670 static int plgpio_resume(struct device *dev)
0671 {
0672     struct plgpio *plgpio = dev_get_drvdata(dev);
0673     int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
0674     u32 off;
0675     u32 mask, tmp;
0676 
0677     for (i = 0; i < reg_count; i++) {
0678         off = i * sizeof(int *);
0679 
0680         if (i == reg_count - 1) {
0681             mask = (1 << (plgpio->chip.ngpio - i *
0682                         MAX_GPIO_PER_REG)) - 1;
0683 
0684             if (plgpio->regs.enb != -1)
0685                 plgpio_prepare_reg(enb, off, mask, tmp);
0686 
0687             if (plgpio->regs.eit != -1)
0688                 plgpio_prepare_reg(eit, off, mask, tmp);
0689 
0690             plgpio_prepare_reg(wdata, off, mask, tmp);
0691             plgpio_prepare_reg(dir, off, mask, tmp);
0692             plgpio_prepare_reg(ie, off, mask, tmp);
0693         }
0694 
0695         regmap_write(plgpio->regmap, plgpio->regs.wdata + off,
0696             plgpio->csave_regs[i].wdata);
0697 
0698         regmap_write(plgpio->regmap, plgpio->regs.dir + off,
0699             plgpio->csave_regs[i].dir);
0700 
0701         if (plgpio->regs.eit != -1)
0702             regmap_write(plgpio->regmap, plgpio->regs.eit + off,
0703                 plgpio->csave_regs[i].eit);
0704 
0705         regmap_write(plgpio->regmap, plgpio->regs.ie + off,
0706             plgpio->csave_regs[i].ie);
0707 
0708         if (plgpio->regs.enb != -1)
0709             regmap_write(plgpio->regmap, plgpio->regs.enb + off,
0710                 plgpio->csave_regs[i].enb);
0711     }
0712 
0713     return 0;
0714 }
0715 #endif
0716 
0717 static SIMPLE_DEV_PM_OPS(plgpio_dev_pm_ops, plgpio_suspend, plgpio_resume);
0718 
0719 static const struct of_device_id plgpio_of_match[] = {
0720     { .compatible = "st,spear-plgpio" },
0721     {}
0722 };
0723 
0724 static struct platform_driver plgpio_driver = {
0725     .probe = plgpio_probe,
0726     .driver = {
0727         .name = "spear-plgpio",
0728         .pm = &plgpio_dev_pm_ops,
0729         .of_match_table = plgpio_of_match,
0730     },
0731 };
0732 
0733 static int __init plgpio_init(void)
0734 {
0735     return platform_driver_register(&plgpio_driver);
0736 }
0737 subsys_initcall(plgpio_init);
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