pinctrl/samsung/pinctrl-samsung.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
0004  *
0005  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
0006  *      http://www.samsung.com
0007  * Copyright (c) 2012 Linaro Ltd
0008  *      http://www.linaro.org
0009  *
0010  * Author: Thomas Abraham <thomas.ab@samsung.com>
0011  */
0012
0013 #ifndef __PINCTRL_SAMSUNG_H
0014 #define __PINCTRL_SAMSUNG_H
0015
0016 #include <linux/pinctrl/pinctrl.h>
0017 #include <linux/pinctrl/pinmux.h>
0018 #include <linux/pinctrl/pinconf.h>
0019 #include <linux/pinctrl/consumer.h>
0020 #include <linux/pinctrl/machine.h>
0021
0022 #include <linux/gpio/driver.h>
0023
0024 /**
0025  * enum pincfg_type - possible pin configuration types supported.
0026  * @PINCFG_TYPE_FUNC: Function configuration.
0027  * @PINCFG_TYPE_DAT: Pin value configuration.
0028  * @PINCFG_TYPE_PUD: Pull up/down configuration.
0029  * @PINCFG_TYPE_DRV: Drive strength configuration.
0030  * @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
0031  * @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode.
0032  */
0033 enum pincfg_type {
0034     PINCFG_TYPE_FUNC,
0035     PINCFG_TYPE_DAT,
0036     PINCFG_TYPE_PUD,
0037     PINCFG_TYPE_DRV,
0038     PINCFG_TYPE_CON_PDN,
0039     PINCFG_TYPE_PUD_PDN,
0040
0041     PINCFG_TYPE_NUM
0042 };
0043
0044 /*
0045  * pin configuration (pull up/down and drive strength) type and its value are
0046  * packed together into a 16-bits. The upper 8-bits represent the configuration
0047  * type and the lower 8-bits hold the value of the configuration type.
0048  */
0049 #define PINCFG_TYPE_MASK        0xFF
0050 #define PINCFG_VALUE_SHIFT      8
0051 #define PINCFG_VALUE_MASK       (0xFF << PINCFG_VALUE_SHIFT)
0052 #define PINCFG_PACK(type, value)    (((value) << PINCFG_VALUE_SHIFT) | type)
0053 #define PINCFG_UNPACK_TYPE(cfg)     ((cfg) & PINCFG_TYPE_MASK)
0054 #define PINCFG_UNPACK_VALUE(cfg)    (((cfg) & PINCFG_VALUE_MASK) >> \
0055                         PINCFG_VALUE_SHIFT)
0056 /*
0057  * Values for the pin CON register, choosing pin function.
0058  * The basic set (input and output) are same between: S3C24xx, S3C64xx, S5PV210,
0059  * Exynos ARMv7, Exynos ARMv8, Tesla FSD.
0060  */
0061 #define PIN_CON_FUNC_INPUT      0x0
0062 #define PIN_CON_FUNC_OUTPUT     0x1
0063
0064 /**
0065  * enum eint_type - possible external interrupt types.
0066  * @EINT_TYPE_NONE: bank does not support external interrupts
0067  * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
0068  * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
0069  * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
0070  *
0071  * Samsung GPIO controller groups all the available pins into banks. The pins
0072  * in a pin bank can support external gpio interrupts or external wakeup
0073  * interrupts or no interrupts at all. From a software perspective, the only
0074  * difference between external gpio and external wakeup interrupts is that
0075  * the wakeup interrupts can additionally wakeup the system if it is in
0076  * suspended state.
0077  */
0078 enum eint_type {
0079     EINT_TYPE_NONE,
0080     EINT_TYPE_GPIO,
0081     EINT_TYPE_WKUP,
0082     EINT_TYPE_WKUP_MUX,
0083 };
0084
0085 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
0086 #define PIN_NAME_LENGTH 10
0087
0088 #define PIN_GROUP(n, p, f)              \
0089     {                       \
0090         .name       = n,            \
0091         .pins       = p,            \
0092         .num_pins   = ARRAY_SIZE(p),    \
0093         .func       = f         \
0094     }
0095
0096 #define PMX_FUNC(n, g)                  \
0097     {                       \
0098         .name       = n,            \
0099         .groups     = g,            \
0100         .num_groups = ARRAY_SIZE(g),    \
0101     }
0102
0103 struct samsung_pinctrl_drv_data;
0104
0105 /**
0106  * struct samsung_pin_bank_type: pin bank type description
0107  * @fld_width: widths of configuration bitfields (0 if unavailable)
0108  * @reg_offset: offsets of configuration registers (don't care of width is 0)
0109  */
0110 struct samsung_pin_bank_type {
0111     u8 fld_width[PINCFG_TYPE_NUM];
0112     u8 reg_offset[PINCFG_TYPE_NUM];
0113 };
0114
0115 /**
0116  * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
0117  * @type: type of the bank (register offsets and bitfield widths)
0118  * @pctl_offset: starting offset of the pin-bank registers.
0119  * @pctl_res_idx: index of base address for pin-bank registers.
0120  * @nr_pins: number of pins included in this bank.
0121  * @eint_func: function to set in CON register to configure pin as EINT.
0122  * @eint_type: type of the external interrupt supported by the bank.
0123  * @eint_mask: bit mask of pins which support EINT function.
0124  * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
0125  * @name: name to be prefixed for each pin in this pin bank.
0126  */
0127 struct samsung_pin_bank_data {
0128     const struct samsung_pin_bank_type *type;
0129     u32     pctl_offset;
0130     u8      pctl_res_idx;
0131     u8      nr_pins;
0132     u8      eint_func;
0133     enum eint_type  eint_type;
0134     u32     eint_mask;
0135     u32     eint_offset;
0136     const char  *name;
0137 };
0138
0139 /**
0140  * struct samsung_pin_bank: represent a controller pin-bank.
0141  * @type: type of the bank (register offsets and bitfield widths)
0142  * @pctl_base: base address of the pin-bank registers
0143  * @pctl_offset: starting offset of the pin-bank registers.
0144  * @nr_pins: number of pins included in this bank.
0145  * @eint_base: base address of the pin-bank EINT registers.
0146  * @eint_func: function to set in CON register to configure pin as EINT.
0147  * @eint_type: type of the external interrupt supported by the bank.
0148  * @eint_mask: bit mask of pins which support EINT function.
0149  * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
0150  * @name: name to be prefixed for each pin in this pin bank.
0151  * @pin_base: starting pin number of the bank.
0152  * @soc_priv: per-bank private data for SoC-specific code.
0153  * @of_node: OF node of the bank.
0154  * @drvdata: link to controller driver data
0155  * @irq_domain: IRQ domain of the bank.
0156  * @gpio_chip: GPIO chip of the bank.
0157  * @grange: linux gpio pin range supported by this bank.
0158  * @irq_chip: link to irq chip for external gpio and wakeup interrupts.
0159  * @slock: spinlock protecting bank registers
0160  * @pm_save: saved register values during suspend
0161  */
0162 struct samsung_pin_bank {
0163     const struct samsung_pin_bank_type *type;
0164     void __iomem    *pctl_base;
0165     u32     pctl_offset;
0166     u8      nr_pins;
0167     void __iomem    *eint_base;
0168     u8      eint_func;
0169     enum eint_type  eint_type;
0170     u32     eint_mask;
0171     u32     eint_offset;
0172     const char  *name;
0173
0174     u32     pin_base;
0175     void        *soc_priv;
0176     struct fwnode_handle *fwnode;
0177     struct samsung_pinctrl_drv_data *drvdata;
0178     struct irq_domain *irq_domain;
0179     struct gpio_chip gpio_chip;
0180     struct pinctrl_gpio_range grange;
0181     struct exynos_irq_chip *irq_chip;
0182     raw_spinlock_t slock;
0183
0184     u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
0185 };
0186
0187 /**
0188  * struct samsung_retention_data: runtime pin-bank retention control data.
0189  * @regs: array of PMU registers to control pad retention.
0190  * @nr_regs: number of registers in @regs array.
0191  * @value: value to store to registers to turn off retention.
0192  * @refcnt: atomic counter if retention control affects more than one bank.
0193  * @priv: retention control code private data
0194  * @enable: platform specific callback to enter retention mode.
0195  * @disable: platform specific callback to exit retention mode.
0196  **/
0197 struct samsung_retention_ctrl {
0198     const u32   *regs;
0199     int     nr_regs;
0200     u32     value;
0201     atomic_t    *refcnt;
0202     void        *priv;
0203     void        (*enable)(struct samsung_pinctrl_drv_data *);
0204     void        (*disable)(struct samsung_pinctrl_drv_data *);
0205 };
0206
0207 /**
0208  * struct samsung_retention_data: represent a pin-bank retention control data.
0209  * @regs: array of PMU registers to control pad retention.
0210  * @nr_regs: number of registers in @regs array.
0211  * @value: value to store to registers to turn off retention.
0212  * @refcnt: atomic counter if retention control affects more than one bank.
0213  * @init: platform specific callback to initialize retention control.
0214  **/
0215 struct samsung_retention_data {
0216     const u32   *regs;
0217     int     nr_regs;
0218     u32     value;
0219     atomic_t    *refcnt;
0220     struct samsung_retention_ctrl *(*init)(struct samsung_pinctrl_drv_data *,
0221                     const struct samsung_retention_data *);
0222 };
0223
0224 /**
0225  * struct samsung_pin_ctrl: represent a pin controller.
0226  * @pin_banks: list of pin banks included in this controller.
0227  * @nr_banks: number of pin banks.
0228  * @nr_ext_resources: number of the extra base address for pin banks.
0229  * @retention_data: configuration data for retention control.
0230  * @eint_gpio_init: platform specific callback to setup the external gpio
0231  *  interrupts for the controller.
0232  * @eint_wkup_init: platform specific callback to setup the external wakeup
0233  *  interrupts for the controller.
0234  * @suspend: platform specific suspend callback, executed during pin controller
0235  *  device suspend, see samsung_pinctrl_suspend()
0236  * @resume: platform specific resume callback, executed during pin controller
0237  *  device suspend, see samsung_pinctrl_resume()
0238  *
0239  * External wakeup interrupts must define at least eint_wkup_init,
0240  * retention_data and suspend in order for proper suspend/resume to work.
0241  */
0242 struct samsung_pin_ctrl {
0243     const struct samsung_pin_bank_data *pin_banks;
0244     unsigned int    nr_banks;
0245     unsigned int    nr_ext_resources;
0246     const struct samsung_retention_data *retention_data;
0247
0248     int     (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
0249     int     (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
0250     void        (*suspend)(struct samsung_pinctrl_drv_data *);
0251     void        (*resume)(struct samsung_pinctrl_drv_data *);
0252 };
0253
0254 /**
0255  * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
0256  * @node: global list node
0257  * @virt_base: register base address of the controller; this will be equal
0258  *             to each bank samsung_pin_bank->pctl_base and used on legacy
0259  *             platforms (like S3C24XX or S3C64XX) which has to access the base
0260  *             through samsung_pinctrl_drv_data, not samsung_pin_bank).
0261  * @dev: device instance representing the controller.
0262  * @irq: interrpt number used by the controller to notify gpio interrupts.
0263  * @ctrl: pin controller instance managed by the driver.
0264  * @pctl: pin controller descriptor registered with the pinctrl subsystem.
0265  * @pctl_dev: cookie representing pinctrl device instance.
0266  * @pin_groups: list of pin groups available to the driver.
0267  * @nr_groups: number of such pin groups.
0268  * @pmx_functions: list of pin functions available to the driver.
0269  * @nr_function: number of such pin functions.
0270  * @pin_base: starting system wide pin number.
0271  * @nr_pins: number of pins supported by the controller.
0272  * @retention_ctrl: retention control runtime data.
0273  * @suspend: platform specific suspend callback, executed during pin controller
0274  *  device suspend, see samsung_pinctrl_suspend()
0275  * @resume: platform specific resume callback, executed during pin controller
0276  *  device suspend, see samsung_pinctrl_resume()
0277  */
0278 struct samsung_pinctrl_drv_data {
0279     struct list_head        node;
0280     void __iomem            *virt_base;
0281     struct device           *dev;
0282     int             irq;
0283
0284     struct pinctrl_desc     pctl;
0285     struct pinctrl_dev      *pctl_dev;
0286
0287     const struct samsung_pin_group  *pin_groups;
0288     unsigned int            nr_groups;
0289     const struct samsung_pmx_func   *pmx_functions;
0290     unsigned int            nr_functions;
0291
0292     struct samsung_pin_bank     *pin_banks;
0293     unsigned int            nr_banks;
0294     unsigned int            pin_base;
0295     unsigned int            nr_pins;
0296
0297     struct samsung_retention_ctrl   *retention_ctrl;
0298
0299     void (*suspend)(struct samsung_pinctrl_drv_data *);
0300     void (*resume)(struct samsung_pinctrl_drv_data *);
0301 };
0302
0303 /**
0304  * struct samsung_pinctrl_of_match_data: OF match device specific configuration data.
0305  * @ctrl: array of pin controller data.
0306  * @num_ctrl: size of array @ctrl.
0307  */
0308 struct samsung_pinctrl_of_match_data {
0309     const struct samsung_pin_ctrl   *ctrl;
0310     unsigned int            num_ctrl;
0311 };
0312
0313 /**
0314  * struct samsung_pin_group: represent group of pins of a pinmux function.
0315  * @name: name of the pin group, used to lookup the group.
0316  * @pins: the pins included in this group.
0317  * @num_pins: number of pins included in this group.
0318  * @func: the function number to be programmed when selected.
0319  */
0320 struct samsung_pin_group {
0321     const char      *name;
0322     const unsigned int  *pins;
0323     u8          num_pins;
0324     u8          func;
0325 };
0326
0327 /**
0328  * struct samsung_pmx_func: represent a pin function.
0329  * @name: name of the pin function, used to lookup the function.
0330  * @groups: one or more names of pin groups that provide this function.
0331  * @num_groups: number of groups included in @groups.
0332  */
0333 struct samsung_pmx_func {
0334     const char      *name;
0335     const char      **groups;
0336     u8          num_groups;
0337     u32         val;
0338 };
0339
0340 /* list of all exported SoC specific data */
0341 extern const struct samsung_pinctrl_of_match_data exynos3250_of_data;
0342 extern const struct samsung_pinctrl_of_match_data exynos4210_of_data;
0343 extern const struct samsung_pinctrl_of_match_data exynos4x12_of_data;
0344 extern const struct samsung_pinctrl_of_match_data exynos5250_of_data;
0345 extern const struct samsung_pinctrl_of_match_data exynos5260_of_data;
0346 extern const struct samsung_pinctrl_of_match_data exynos5410_of_data;
0347 extern const struct samsung_pinctrl_of_match_data exynos5420_of_data;
0348 extern const struct samsung_pinctrl_of_match_data exynos5433_of_data;
0349 extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
0350 extern const struct samsung_pinctrl_of_match_data exynos7885_of_data;
0351 extern const struct samsung_pinctrl_of_match_data exynos850_of_data;
0352 extern const struct samsung_pinctrl_of_match_data exynosautov9_of_data;
0353 extern const struct samsung_pinctrl_of_match_data fsd_of_data;
0354 extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
0355 extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
0356 extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
0357 extern const struct samsung_pinctrl_of_match_data s3c2440_of_data;
0358 extern const struct samsung_pinctrl_of_match_data s3c2450_of_data;
0359 extern const struct samsung_pinctrl_of_match_data s5pv210_of_data;
0360
0361 #endif /* __PINCTRL_SAMSUNG_H */