pinctrl/samsung/pinctrl-exynos.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Exynos specific definitions for Samsung pinctrl and gpiolib driver.
0004  *
0005  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
0006  *      http://www.samsung.com
0007  * Copyright (c) 2012 Linaro Ltd
0008  *      http://www.linaro.org
0009  *
0010  * This file contains the Exynos specific definitions for the Samsung
0011  * pinctrl/gpiolib interface drivers.
0012  *
0013  * Author: Thomas Abraham <thomas.ab@samsung.com>
0014  */
0015
0016 #ifndef __PINCTRL_SAMSUNG_EXYNOS_H
0017 #define __PINCTRL_SAMSUNG_EXYNOS_H
0018
0019 /* Values for the pin CON register */
0020 #define EXYNOS_PIN_CON_FUNC_EINT    0xf
0021
0022 /* External GPIO and wakeup interrupt related definitions */
0023 #define EXYNOS_GPIO_ECON_OFFSET     0x700
0024 #define EXYNOS_GPIO_EFLTCON_OFFSET  0x800
0025 #define EXYNOS_GPIO_EMASK_OFFSET    0x900
0026 #define EXYNOS_GPIO_EPEND_OFFSET    0xA00
0027 #define EXYNOS_WKUP_ECON_OFFSET     0xE00
0028 #define EXYNOS_WKUP_EMASK_OFFSET    0xF00
0029 #define EXYNOS_WKUP_EPEND_OFFSET    0xF40
0030 #define EXYNOS7_WKUP_ECON_OFFSET    0x700
0031 #define EXYNOS7_WKUP_EMASK_OFFSET   0x900
0032 #define EXYNOS7_WKUP_EPEND_OFFSET   0xA00
0033 #define EXYNOS_SVC_OFFSET       0xB08
0034
0035 /* helpers to access interrupt service register */
0036 #define EXYNOS_SVC_GROUP_SHIFT      3
0037 #define EXYNOS_SVC_GROUP_MASK       0x1f
0038 #define EXYNOS_SVC_NUM_MASK     7
0039 #define EXYNOS_SVC_GROUP(x)     ((x >> EXYNOS_SVC_GROUP_SHIFT) & \
0040                         EXYNOS_SVC_GROUP_MASK)
0041
0042 /* Exynos specific external interrupt trigger types */
0043 #define EXYNOS_EINT_LEVEL_LOW       0
0044 #define EXYNOS_EINT_LEVEL_HIGH      1
0045 #define EXYNOS_EINT_EDGE_FALLING    2
0046 #define EXYNOS_EINT_EDGE_RISING     3
0047 #define EXYNOS_EINT_EDGE_BOTH       4
0048 #define EXYNOS_EINT_CON_MASK        0xF
0049 #define EXYNOS_EINT_CON_LEN     4
0050
0051 #define EXYNOS_EINT_MAX_PER_BANK    8
0052 #define EXYNOS_EINT_NR_WKUP_EINT
0053
0054 #define EXYNOS_PIN_BANK_EINTN(pins, reg, id)        \
0055     {                       \
0056         .type       = &bank_type_off,   \
0057         .pctl_offset    = reg,          \
0058         .nr_pins    = pins,         \
0059         .eint_type  = EINT_TYPE_NONE,   \
0060         .name       = id            \
0061     }
0062
0063 #define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs)  \
0064     {                       \
0065         .type       = &bank_type_off,   \
0066         .pctl_offset    = reg,          \
0067         .nr_pins    = pins,         \
0068         .eint_type  = EINT_TYPE_GPIO,   \
0069         .eint_offset    = offs,         \
0070         .name       = id            \
0071     }
0072
0073 #define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs)  \
0074     {                       \
0075         .type       = &bank_type_alive, \
0076         .pctl_offset    = reg,          \
0077         .nr_pins    = pins,         \
0078         .eint_type  = EINT_TYPE_WKUP,   \
0079         .eint_offset    = offs,         \
0080         .name       = id            \
0081     }
0082
0083 #define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs)      \
0084     {                           \
0085         .type       = &exynos5433_bank_type_off,    \
0086         .pctl_offset    = reg,              \
0087         .nr_pins    = pins,             \
0088         .eint_type  = EINT_TYPE_GPIO,       \
0089         .eint_offset    = offs,             \
0090         .name       = id                \
0091     }
0092
0093 #define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs)      \
0094     {                           \
0095         .type       = &exynos5433_bank_type_alive,  \
0096         .pctl_offset    = reg,              \
0097         .nr_pins    = pins,             \
0098         .eint_type  = EINT_TYPE_WKUP,       \
0099         .eint_offset    = offs,             \
0100         .name       = id                \
0101     }
0102
0103 #define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \
0104     {                           \
0105         .type           = &exynos5433_bank_type_off,    \
0106         .pctl_offset    = reg,              \
0107         .nr_pins        = pins,             \
0108         .eint_type      = EINT_TYPE_WKUP,       \
0109         .eint_offset    = offs,             \
0110         .name           = id,               \
0111         .pctl_res_idx   = pctl_idx,         \
0112     }                           \
0113
0114 #define EXYNOS850_PIN_BANK_EINTN(pins, reg, id)         \
0115     {                           \
0116         .type       = &exynos850_bank_type_alive,   \
0117         .pctl_offset    = reg,              \
0118         .nr_pins    = pins,             \
0119         .eint_type  = EINT_TYPE_NONE,       \
0120         .name       = id                \
0121     }
0122
0123 #define EXYNOS850_PIN_BANK_EINTG(pins, reg, id, offs)       \
0124     {                           \
0125         .type       = &exynos850_bank_type_off, \
0126         .pctl_offset    = reg,              \
0127         .nr_pins    = pins,             \
0128         .eint_type  = EINT_TYPE_GPIO,       \
0129         .eint_offset    = offs,             \
0130         .name       = id                \
0131     }
0132
0133 #define EXYNOS850_PIN_BANK_EINTW(pins, reg, id, offs)       \
0134     {                           \
0135         .type       = &exynos850_bank_type_alive,   \
0136         .pctl_offset    = reg,              \
0137         .nr_pins    = pins,             \
0138         .eint_type  = EINT_TYPE_WKUP,       \
0139         .eint_offset    = offs,             \
0140         .name       = id                \
0141     }
0142
0143 /**
0144  * struct exynos_weint_data: irq specific data for all the wakeup interrupts
0145  * generated by the external wakeup interrupt controller.
0146  * @irq: interrupt number within the domain.
0147  * @bank: bank responsible for this interrupt
0148  */
0149 struct exynos_weint_data {
0150     unsigned int irq;
0151     struct samsung_pin_bank *bank;
0152 };
0153
0154 /**
0155  * struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts
0156  * generated by the external wakeup interrupt controller.
0157  * @nr_banks: count of banks being part of the mux
0158  * @banks: array of banks being part of the mux
0159  */
0160 struct exynos_muxed_weint_data {
0161     unsigned int nr_banks;
0162     struct samsung_pin_bank *banks[];
0163 };
0164
0165 int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d);
0166 int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d);
0167 void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata);
0168 void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata);
0169 struct samsung_retention_ctrl *
0170 exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata,
0171               const struct samsung_retention_data *data);
0172
0173 #endif /* __PINCTRL_SAMSUNG_EXYNOS_H */