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0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Exynos ARMv8 specific support for Samsung pinctrl/gpiolib driver
0004 // with eint support.
0005 //
0006 // Copyright (c) 2012 Samsung Electronics Co., Ltd.
0007 //      http://www.samsung.com
0008 // Copyright (c) 2012 Linaro Ltd
0009 //      http://www.linaro.org
0010 // Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
0011 //
0012 // This file contains the Samsung Exynos specific information required by the
0013 // the Samsung pinctrl/gpiolib driver. It also includes the implementation of
0014 // external gpio and wakeup interrupt support.
0015 
0016 #include <linux/slab.h>
0017 #include <linux/soc/samsung/exynos-regs-pmu.h>
0018 
0019 #include "pinctrl-samsung.h"
0020 #include "pinctrl-exynos.h"
0021 
0022 static const struct samsung_pin_bank_type bank_type_off = {
0023     .fld_width = { 4, 1, 2, 2, 2, 2, },
0024     .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
0025 };
0026 
0027 static const struct samsung_pin_bank_type bank_type_alive = {
0028     .fld_width = { 4, 1, 2, 2, },
0029     .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
0030 };
0031 
0032 /* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */
0033 static const struct samsung_pin_bank_type exynos5433_bank_type_off = {
0034     .fld_width = { 4, 1, 2, 4, 2, 2, },
0035     .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
0036 };
0037 
0038 static const struct samsung_pin_bank_type exynos5433_bank_type_alive = {
0039     .fld_width = { 4, 1, 2, 4, },
0040     .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
0041 };
0042 
0043 /*
0044  * Bank type for non-alive type. Bit fields:
0045  * CON: 4, DAT: 1, PUD: 4, DRV: 4, CONPDN: 2, PUDPDN: 4
0046  */
0047 static const struct samsung_pin_bank_type exynos850_bank_type_off  = {
0048     .fld_width = { 4, 1, 4, 4, 2, 4, },
0049     .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
0050 };
0051 
0052 /*
0053  * Bank type for alive type. Bit fields:
0054  * CON: 4, DAT: 1, PUD: 4, DRV: 4
0055  */
0056 static const struct samsung_pin_bank_type exynos850_bank_type_alive = {
0057     .fld_width = { 4, 1, 4, 4, },
0058     .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
0059 };
0060 
0061 /* Pad retention control code for accessing PMU regmap */
0062 static atomic_t exynos_shared_retention_refcnt;
0063 
0064 /* pin banks of exynos5433 pin-controller - ALIVE */
0065 static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = {
0066     /* Must start with EINTG banks, ordered by EINT group number. */
0067     EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
0068     EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
0069     EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
0070     EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
0071     EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),
0072     EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),
0073     EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1),
0074     EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1),
0075     EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1),
0076 };
0077 
0078 /* pin banks of exynos5433 pin-controller - AUD */
0079 static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = {
0080     /* Must start with EINTG banks, ordered by EINT group number. */
0081     EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
0082     EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
0083 };
0084 
0085 /* pin banks of exynos5433 pin-controller - CPIF */
0086 static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = {
0087     /* Must start with EINTG banks, ordered by EINT group number. */
0088     EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),
0089 };
0090 
0091 /* pin banks of exynos5433 pin-controller - eSE */
0092 static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = {
0093     /* Must start with EINTG banks, ordered by EINT group number. */
0094     EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),
0095 };
0096 
0097 /* pin banks of exynos5433 pin-controller - FINGER */
0098 static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = {
0099     /* Must start with EINTG banks, ordered by EINT group number. */
0100     EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),
0101 };
0102 
0103 /* pin banks of exynos5433 pin-controller - FSYS */
0104 static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = {
0105     /* Must start with EINTG banks, ordered by EINT group number. */
0106     EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),
0107     EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),
0108     EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),
0109     EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),
0110     EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),
0111     EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),
0112 };
0113 
0114 /* pin banks of exynos5433 pin-controller - IMEM */
0115 static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = {
0116     /* Must start with EINTG banks, ordered by EINT group number. */
0117     EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
0118 };
0119 
0120 /* pin banks of exynos5433 pin-controller - NFC */
0121 static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = {
0122     /* Must start with EINTG banks, ordered by EINT group number. */
0123     EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
0124 };
0125 
0126 /* pin banks of exynos5433 pin-controller - PERIC */
0127 static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = {
0128     /* Must start with EINTG banks, ordered by EINT group number. */
0129     EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),
0130     EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),
0131     EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),
0132     EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),
0133     EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),
0134     EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),
0135     EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),
0136     EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),
0137     EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),
0138     EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),
0139     EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),
0140     EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),
0141     EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),
0142     EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),
0143     EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),
0144     EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),
0145     EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
0146 };
0147 
0148 /* pin banks of exynos5433 pin-controller - TOUCH */
0149 static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = {
0150     /* Must start with EINTG banks, ordered by EINT group number. */
0151     EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
0152 };
0153 
0154 /* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */
0155 static const u32 exynos5433_retention_regs[] = {
0156     EXYNOS5433_PAD_RETENTION_TOP_OPTION,
0157     EXYNOS5433_PAD_RETENTION_UART_OPTION,
0158     EXYNOS5433_PAD_RETENTION_EBIA_OPTION,
0159     EXYNOS5433_PAD_RETENTION_EBIB_OPTION,
0160     EXYNOS5433_PAD_RETENTION_SPI_OPTION,
0161     EXYNOS5433_PAD_RETENTION_MIF_OPTION,
0162     EXYNOS5433_PAD_RETENTION_USBXTI_OPTION,
0163     EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION,
0164     EXYNOS5433_PAD_RETENTION_UFS_OPTION,
0165     EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION,
0166 };
0167 
0168 static const struct samsung_retention_data exynos5433_retention_data __initconst = {
0169     .regs    = exynos5433_retention_regs,
0170     .nr_regs = ARRAY_SIZE(exynos5433_retention_regs),
0171     .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
0172     .refcnt  = &exynos_shared_retention_refcnt,
0173     .init    = exynos_retention_init,
0174 };
0175 
0176 /* PMU retention control for audio pins can be tied to audio pin bank */
0177 static const u32 exynos5433_audio_retention_regs[] = {
0178     EXYNOS5433_PAD_RETENTION_AUD_OPTION,
0179 };
0180 
0181 static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = {
0182     .regs    = exynos5433_audio_retention_regs,
0183     .nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs),
0184     .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
0185     .init    = exynos_retention_init,
0186 };
0187 
0188 /* PMU retention control for mmc pins can be tied to fsys pin bank */
0189 static const u32 exynos5433_fsys_retention_regs[] = {
0190     EXYNOS5433_PAD_RETENTION_MMC0_OPTION,
0191     EXYNOS5433_PAD_RETENTION_MMC1_OPTION,
0192     EXYNOS5433_PAD_RETENTION_MMC2_OPTION,
0193 };
0194 
0195 static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = {
0196     .regs    = exynos5433_fsys_retention_regs,
0197     .nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs),
0198     .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
0199     .init    = exynos_retention_init,
0200 };
0201 
0202 /*
0203  * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
0204  * ten gpio/pin-mux/pinconfig controllers.
0205  */
0206 static const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = {
0207     {
0208         /* pin-controller instance 0 data */
0209         .pin_banks  = exynos5433_pin_banks0,
0210         .nr_banks   = ARRAY_SIZE(exynos5433_pin_banks0),
0211         .eint_wkup_init = exynos_eint_wkup_init,
0212         .suspend    = exynos_pinctrl_suspend,
0213         .resume     = exynos_pinctrl_resume,
0214         .nr_ext_resources = 1,
0215         .retention_data = &exynos5433_retention_data,
0216     }, {
0217         /* pin-controller instance 1 data */
0218         .pin_banks  = exynos5433_pin_banks1,
0219         .nr_banks   = ARRAY_SIZE(exynos5433_pin_banks1),
0220         .eint_gpio_init = exynos_eint_gpio_init,
0221         .suspend    = exynos_pinctrl_suspend,
0222         .resume     = exynos_pinctrl_resume,
0223         .retention_data = &exynos5433_audio_retention_data,
0224     }, {
0225         /* pin-controller instance 2 data */
0226         .pin_banks  = exynos5433_pin_banks2,
0227         .nr_banks   = ARRAY_SIZE(exynos5433_pin_banks2),
0228         .eint_gpio_init = exynos_eint_gpio_init,
0229         .suspend    = exynos_pinctrl_suspend,
0230         .resume     = exynos_pinctrl_resume,
0231         .retention_data = &exynos5433_retention_data,
0232     }, {
0233         /* pin-controller instance 3 data */
0234         .pin_banks  = exynos5433_pin_banks3,
0235         .nr_banks   = ARRAY_SIZE(exynos5433_pin_banks3),
0236         .eint_gpio_init = exynos_eint_gpio_init,
0237         .suspend    = exynos_pinctrl_suspend,
0238         .resume     = exynos_pinctrl_resume,
0239         .retention_data = &exynos5433_retention_data,
0240     }, {
0241         /* pin-controller instance 4 data */
0242         .pin_banks  = exynos5433_pin_banks4,
0243         .nr_banks   = ARRAY_SIZE(exynos5433_pin_banks4),
0244         .eint_gpio_init = exynos_eint_gpio_init,
0245         .suspend    = exynos_pinctrl_suspend,
0246         .resume     = exynos_pinctrl_resume,
0247         .retention_data = &exynos5433_retention_data,
0248     }, {
0249         /* pin-controller instance 5 data */
0250         .pin_banks  = exynos5433_pin_banks5,
0251         .nr_banks   = ARRAY_SIZE(exynos5433_pin_banks5),
0252         .eint_gpio_init = exynos_eint_gpio_init,
0253         .suspend    = exynos_pinctrl_suspend,
0254         .resume     = exynos_pinctrl_resume,
0255         .retention_data = &exynos5433_fsys_retention_data,
0256     }, {
0257         /* pin-controller instance 6 data */
0258         .pin_banks  = exynos5433_pin_banks6,
0259         .nr_banks   = ARRAY_SIZE(exynos5433_pin_banks6),
0260         .eint_gpio_init = exynos_eint_gpio_init,
0261         .suspend    = exynos_pinctrl_suspend,
0262         .resume     = exynos_pinctrl_resume,
0263         .retention_data = &exynos5433_retention_data,
0264     }, {
0265         /* pin-controller instance 7 data */
0266         .pin_banks  = exynos5433_pin_banks7,
0267         .nr_banks   = ARRAY_SIZE(exynos5433_pin_banks7),
0268         .eint_gpio_init = exynos_eint_gpio_init,
0269         .suspend    = exynos_pinctrl_suspend,
0270         .resume     = exynos_pinctrl_resume,
0271         .retention_data = &exynos5433_retention_data,
0272     }, {
0273         /* pin-controller instance 8 data */
0274         .pin_banks  = exynos5433_pin_banks8,
0275         .nr_banks   = ARRAY_SIZE(exynos5433_pin_banks8),
0276         .eint_gpio_init = exynos_eint_gpio_init,
0277         .suspend    = exynos_pinctrl_suspend,
0278         .resume     = exynos_pinctrl_resume,
0279         .retention_data = &exynos5433_retention_data,
0280     }, {
0281         /* pin-controller instance 9 data */
0282         .pin_banks  = exynos5433_pin_banks9,
0283         .nr_banks   = ARRAY_SIZE(exynos5433_pin_banks9),
0284         .eint_gpio_init = exynos_eint_gpio_init,
0285         .suspend    = exynos_pinctrl_suspend,
0286         .resume     = exynos_pinctrl_resume,
0287         .retention_data = &exynos5433_retention_data,
0288     },
0289 };
0290 
0291 const struct samsung_pinctrl_of_match_data exynos5433_of_data __initconst = {
0292     .ctrl       = exynos5433_pin_ctrl,
0293     .num_ctrl   = ARRAY_SIZE(exynos5433_pin_ctrl),
0294 };
0295 
0296 /* pin banks of exynos7 pin-controller - ALIVE */
0297 static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = {
0298     /* Must start with EINTG banks, ordered by EINT group number. */
0299     EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
0300     EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
0301     EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
0302     EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
0303 };
0304 
0305 /* pin banks of exynos7 pin-controller - BUS0 */
0306 static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = {
0307     /* Must start with EINTG banks, ordered by EINT group number. */
0308     EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
0309     EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
0310     EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
0311     EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),
0312     EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
0313     EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
0314     EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
0315     EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),
0316     EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),
0317     EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),
0318     EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),
0319     EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),
0320     EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),
0321     EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
0322     EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),
0323 };
0324 
0325 /* pin banks of exynos7 pin-controller - NFC */
0326 static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = {
0327     /* Must start with EINTG banks, ordered by EINT group number. */
0328     EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
0329 };
0330 
0331 /* pin banks of exynos7 pin-controller - TOUCH */
0332 static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = {
0333     /* Must start with EINTG banks, ordered by EINT group number. */
0334     EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
0335 };
0336 
0337 /* pin banks of exynos7 pin-controller - FF */
0338 static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = {
0339     /* Must start with EINTG banks, ordered by EINT group number. */
0340     EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
0341 };
0342 
0343 /* pin banks of exynos7 pin-controller - ESE */
0344 static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = {
0345     /* Must start with EINTG banks, ordered by EINT group number. */
0346     EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
0347 };
0348 
0349 /* pin banks of exynos7 pin-controller - FSYS0 */
0350 static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = {
0351     /* Must start with EINTG banks, ordered by EINT group number. */
0352     EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
0353 };
0354 
0355 /* pin banks of exynos7 pin-controller - FSYS1 */
0356 static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
0357     /* Must start with EINTG banks, ordered by EINT group number. */
0358     EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
0359     EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
0360     EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
0361     EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
0362 };
0363 
0364 /* pin banks of exynos7 pin-controller - BUS1 */
0365 static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
0366     /* Must start with EINTG banks, ordered by EINT group number. */
0367     EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
0368     EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
0369     EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
0370     EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
0371     EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
0372     EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
0373     EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
0374     EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
0375     EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
0376     EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
0377 };
0378 
0379 static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = {
0380     /* Must start with EINTG banks, ordered by EINT group number. */
0381     EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
0382     EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
0383 };
0384 
0385 static const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
0386     {
0387         /* pin-controller instance 0 Alive data */
0388         .pin_banks  = exynos7_pin_banks0,
0389         .nr_banks   = ARRAY_SIZE(exynos7_pin_banks0),
0390         .eint_wkup_init = exynos_eint_wkup_init,
0391     }, {
0392         /* pin-controller instance 1 BUS0 data */
0393         .pin_banks  = exynos7_pin_banks1,
0394         .nr_banks   = ARRAY_SIZE(exynos7_pin_banks1),
0395         .eint_gpio_init = exynos_eint_gpio_init,
0396     }, {
0397         /* pin-controller instance 2 NFC data */
0398         .pin_banks  = exynos7_pin_banks2,
0399         .nr_banks   = ARRAY_SIZE(exynos7_pin_banks2),
0400         .eint_gpio_init = exynos_eint_gpio_init,
0401     }, {
0402         /* pin-controller instance 3 TOUCH data */
0403         .pin_banks  = exynos7_pin_banks3,
0404         .nr_banks   = ARRAY_SIZE(exynos7_pin_banks3),
0405         .eint_gpio_init = exynos_eint_gpio_init,
0406     }, {
0407         /* pin-controller instance 4 FF data */
0408         .pin_banks  = exynos7_pin_banks4,
0409         .nr_banks   = ARRAY_SIZE(exynos7_pin_banks4),
0410         .eint_gpio_init = exynos_eint_gpio_init,
0411     }, {
0412         /* pin-controller instance 5 ESE data */
0413         .pin_banks  = exynos7_pin_banks5,
0414         .nr_banks   = ARRAY_SIZE(exynos7_pin_banks5),
0415         .eint_gpio_init = exynos_eint_gpio_init,
0416     }, {
0417         /* pin-controller instance 6 FSYS0 data */
0418         .pin_banks  = exynos7_pin_banks6,
0419         .nr_banks   = ARRAY_SIZE(exynos7_pin_banks6),
0420         .eint_gpio_init = exynos_eint_gpio_init,
0421     }, {
0422         /* pin-controller instance 7 FSYS1 data */
0423         .pin_banks  = exynos7_pin_banks7,
0424         .nr_banks   = ARRAY_SIZE(exynos7_pin_banks7),
0425         .eint_gpio_init = exynos_eint_gpio_init,
0426     }, {
0427         /* pin-controller instance 8 BUS1 data */
0428         .pin_banks  = exynos7_pin_banks8,
0429         .nr_banks   = ARRAY_SIZE(exynos7_pin_banks8),
0430         .eint_gpio_init = exynos_eint_gpio_init,
0431     }, {
0432         /* pin-controller instance 9 AUD data */
0433         .pin_banks  = exynos7_pin_banks9,
0434         .nr_banks   = ARRAY_SIZE(exynos7_pin_banks9),
0435         .eint_gpio_init = exynos_eint_gpio_init,
0436     },
0437 };
0438 
0439 const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = {
0440     .ctrl       = exynos7_pin_ctrl,
0441     .num_ctrl   = ARRAY_SIZE(exynos7_pin_ctrl),
0442 };
0443 
0444 /* pin banks of exynos7885 pin-controller 0 (ALIVE) */
0445 static const struct samsung_pin_bank_data exynos7885_pin_banks0[] __initconst = {
0446     EXYNOS_PIN_BANK_EINTN(3, 0x000, "etc0"),
0447     EXYNOS_PIN_BANK_EINTN(3, 0x020, "etc1"),
0448     EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa0", 0x00),
0449     EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa1", 0x04),
0450     EXYNOS850_PIN_BANK_EINTW(8, 0x080, "gpa2", 0x08),
0451     EXYNOS850_PIN_BANK_EINTW(5, 0x0a0, "gpq0", 0x0c),
0452 };
0453 
0454 /* pin banks of exynos7885 pin-controller 1 (DISPAUD) */
0455 static const struct samsung_pin_bank_data exynos7885_pin_banks1[] __initconst = {
0456     EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
0457     EXYNOS850_PIN_BANK_EINTG(4, 0x020, "gpb1", 0x04),
0458     EXYNOS850_PIN_BANK_EINTG(5, 0x040, "gpb2", 0x08),
0459 };
0460 
0461 /* pin banks of exynos7885 pin-controller 2 (FSYS) */
0462 static const struct samsung_pin_bank_data exynos7885_pin_banks2[] __initconst = {
0463     EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00),
0464     EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf2", 0x04),
0465     EXYNOS850_PIN_BANK_EINTG(6, 0x040, "gpf3", 0x08),
0466     EXYNOS850_PIN_BANK_EINTG(6, 0x060, "gpf4", 0x0c),
0467 };
0468 
0469 /* pin banks of exynos7885 pin-controller 3 (TOP) */
0470 static const struct samsung_pin_bank_data exynos7885_pin_banks3[] __initconst = {
0471     EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpp0", 0x00),
0472     EXYNOS850_PIN_BANK_EINTG(3, 0x020, "gpg0", 0x04),
0473     EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08),
0474     EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c),
0475     EXYNOS850_PIN_BANK_EINTG(3, 0x080, "gpp3", 0x10),
0476     EXYNOS850_PIN_BANK_EINTG(6, 0x0a0, "gpp4", 0x14),
0477     EXYNOS850_PIN_BANK_EINTG(4, 0x0c0, "gpp5", 0x18),
0478     EXYNOS850_PIN_BANK_EINTG(5, 0x0e0, "gpp6", 0x1c),
0479     EXYNOS850_PIN_BANK_EINTG(2, 0x100, "gpp7", 0x20),
0480     EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp8", 0x24),
0481     EXYNOS850_PIN_BANK_EINTG(8, 0x140, "gpg1", 0x28),
0482     EXYNOS850_PIN_BANK_EINTG(8, 0x160, "gpg2", 0x2c),
0483     EXYNOS850_PIN_BANK_EINTG(8, 0x180, "gpg3", 0x30),
0484     EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpg4", 0x34),
0485     EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpc0", 0x38),
0486     EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpc1", 0x3c),
0487     EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpc2", 0x40),
0488 };
0489 
0490 static const struct samsung_pin_ctrl exynos7885_pin_ctrl[] __initconst = {
0491     {
0492         /* pin-controller instance 0 Alive data */
0493         .pin_banks  = exynos7885_pin_banks0,
0494         .nr_banks   = ARRAY_SIZE(exynos7885_pin_banks0),
0495         .eint_gpio_init = exynos_eint_gpio_init,
0496         .eint_wkup_init = exynos_eint_wkup_init,
0497         .suspend    = exynos_pinctrl_suspend,
0498         .resume     = exynos_pinctrl_resume,
0499     }, {
0500         /* pin-controller instance 1 DISPAUD data */
0501         .pin_banks  = exynos7885_pin_banks1,
0502         .nr_banks   = ARRAY_SIZE(exynos7885_pin_banks1),
0503     }, {
0504         /* pin-controller instance 2 FSYS data */
0505         .pin_banks  = exynos7885_pin_banks2,
0506         .nr_banks   = ARRAY_SIZE(exynos7885_pin_banks2),
0507         .eint_gpio_init = exynos_eint_gpio_init,
0508         .suspend    = exynos_pinctrl_suspend,
0509         .resume     = exynos_pinctrl_resume,
0510     }, {
0511         /* pin-controller instance 3 TOP data */
0512         .pin_banks  = exynos7885_pin_banks3,
0513         .nr_banks   = ARRAY_SIZE(exynos7885_pin_banks3),
0514         .eint_gpio_init = exynos_eint_gpio_init,
0515         .suspend    = exynos_pinctrl_suspend,
0516         .resume     = exynos_pinctrl_resume,
0517     },
0518 };
0519 
0520 const struct samsung_pinctrl_of_match_data exynos7885_of_data __initconst = {
0521     .ctrl       = exynos7885_pin_ctrl,
0522     .num_ctrl   = ARRAY_SIZE(exynos7885_pin_ctrl),
0523 };
0524 
0525 /* pin banks of exynos850 pin-controller 0 (ALIVE) */
0526 static const struct samsung_pin_bank_data exynos850_pin_banks0[] __initconst = {
0527     /* Must start with EINTG banks, ordered by EINT group number. */
0528     EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
0529     EXYNOS850_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
0530     EXYNOS850_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
0531     EXYNOS850_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
0532     EXYNOS850_PIN_BANK_EINTW(4, 0x080, "gpa4", 0x10),
0533     EXYNOS850_PIN_BANK_EINTN(3, 0x0a0, "gpq0"),
0534 };
0535 
0536 /* pin banks of exynos850 pin-controller 1 (CMGP) */
0537 static const struct samsung_pin_bank_data exynos850_pin_banks1[] __initconst = {
0538     /* Must start with EINTG banks, ordered by EINT group number. */
0539     EXYNOS850_PIN_BANK_EINTW(1, 0x000, "gpm0", 0x00),
0540     EXYNOS850_PIN_BANK_EINTW(1, 0x020, "gpm1", 0x04),
0541     EXYNOS850_PIN_BANK_EINTW(1, 0x040, "gpm2", 0x08),
0542     EXYNOS850_PIN_BANK_EINTW(1, 0x060, "gpm3", 0x0c),
0543     EXYNOS850_PIN_BANK_EINTW(1, 0x080, "gpm4", 0x10),
0544     EXYNOS850_PIN_BANK_EINTW(1, 0x0a0, "gpm5", 0x14),
0545     EXYNOS850_PIN_BANK_EINTW(1, 0x0c0, "gpm6", 0x18),
0546     EXYNOS850_PIN_BANK_EINTW(1, 0x0e0, "gpm7", 0x1c),
0547 };
0548 
0549 /* pin banks of exynos850 pin-controller 2 (AUD) */
0550 static const struct samsung_pin_bank_data exynos850_pin_banks2[] __initconst = {
0551     /* Must start with EINTG banks, ordered by EINT group number. */
0552     EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
0553     EXYNOS850_PIN_BANK_EINTG(5, 0x020, "gpb1", 0x04),
0554 };
0555 
0556 /* pin banks of exynos850 pin-controller 3 (HSI) */
0557 static const struct samsung_pin_bank_data exynos850_pin_banks3[] __initconst = {
0558     /* Must start with EINTG banks, ordered by EINT group number. */
0559     EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf2", 0x00),
0560 };
0561 
0562 /* pin banks of exynos850 pin-controller 4 (CORE) */
0563 static const struct samsung_pin_bank_data exynos850_pin_banks4[] __initconst = {
0564     /* Must start with EINTG banks, ordered by EINT group number. */
0565     EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf0", 0x00),
0566     EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf1", 0x04),
0567 };
0568 
0569 /* pin banks of exynos850 pin-controller 5 (PERI) */
0570 static const struct samsung_pin_bank_data exynos850_pin_banks5[] __initconst = {
0571     /* Must start with EINTG banks, ordered by EINT group number. */
0572     EXYNOS850_PIN_BANK_EINTG(2, 0x000, "gpg0", 0x00),
0573     EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpp0", 0x04),
0574     EXYNOS850_PIN_BANK_EINTG(4, 0x040, "gpp1", 0x08),
0575     EXYNOS850_PIN_BANK_EINTG(4, 0x060, "gpp2", 0x0c),
0576     EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg1", 0x10),
0577     EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpg2", 0x14),
0578     EXYNOS850_PIN_BANK_EINTG(1, 0x0c0, "gpg3", 0x18),
0579     EXYNOS850_PIN_BANK_EINTG(3, 0x0e0, "gpc0", 0x1c),
0580     EXYNOS850_PIN_BANK_EINTG(6, 0x100, "gpc1", 0x20),
0581 };
0582 
0583 static const struct samsung_pin_ctrl exynos850_pin_ctrl[] __initconst = {
0584     {
0585         /* pin-controller instance 0 ALIVE data */
0586         .pin_banks  = exynos850_pin_banks0,
0587         .nr_banks   = ARRAY_SIZE(exynos850_pin_banks0),
0588         .eint_wkup_init = exynos_eint_wkup_init,
0589     }, {
0590         /* pin-controller instance 1 CMGP data */
0591         .pin_banks  = exynos850_pin_banks1,
0592         .nr_banks   = ARRAY_SIZE(exynos850_pin_banks1),
0593         .eint_wkup_init = exynos_eint_wkup_init,
0594     }, {
0595         /* pin-controller instance 2 AUD data */
0596         .pin_banks  = exynos850_pin_banks2,
0597         .nr_banks   = ARRAY_SIZE(exynos850_pin_banks2),
0598     }, {
0599         /* pin-controller instance 3 HSI data */
0600         .pin_banks  = exynos850_pin_banks3,
0601         .nr_banks   = ARRAY_SIZE(exynos850_pin_banks3),
0602         .eint_gpio_init = exynos_eint_gpio_init,
0603     }, {
0604         /* pin-controller instance 4 CORE data */
0605         .pin_banks  = exynos850_pin_banks4,
0606         .nr_banks   = ARRAY_SIZE(exynos850_pin_banks4),
0607         .eint_gpio_init = exynos_eint_gpio_init,
0608     }, {
0609         /* pin-controller instance 5 PERI data */
0610         .pin_banks  = exynos850_pin_banks5,
0611         .nr_banks   = ARRAY_SIZE(exynos850_pin_banks5),
0612         .eint_gpio_init = exynos_eint_gpio_init,
0613     },
0614 };
0615 
0616 const struct samsung_pinctrl_of_match_data exynos850_of_data __initconst = {
0617     .ctrl       = exynos850_pin_ctrl,
0618     .num_ctrl   = ARRAY_SIZE(exynos850_pin_ctrl),
0619 };
0620 
0621 /* pin banks of exynosautov9 pin-controller 0 (ALIVE) */
0622 static const struct samsung_pin_bank_data exynosautov9_pin_banks0[] __initconst = {
0623     EXYNOS850_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
0624     EXYNOS850_PIN_BANK_EINTW(2, 0x020, "gpa1", 0x04),
0625     EXYNOS850_PIN_BANK_EINTN(2, 0x040, "gpq0"),
0626 };
0627 
0628 /* pin banks of exynosautov9 pin-controller 1 (AUD) */
0629 static const struct samsung_pin_bank_data exynosautov9_pin_banks1[] __initconst = {
0630     EXYNOS850_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
0631     EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpb1", 0x04),
0632     EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpb2", 0x08),
0633     EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpb3", 0x0C),
0634 };
0635 
0636 /* pin banks of exynosautov9 pin-controller 2 (FSYS0) */
0637 static const struct samsung_pin_bank_data exynosautov9_pin_banks2[] __initconst = {
0638     EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf0", 0x00),
0639     EXYNOS850_PIN_BANK_EINTG(6, 0x020, "gpf1", 0x04),
0640 };
0641 
0642 /* pin banks of exynosautov9 pin-controller 3 (FSYS1) */
0643 static const struct samsung_pin_bank_data exynosautov9_pin_banks3[] __initconst = {
0644     EXYNOS850_PIN_BANK_EINTG(6, 0x000, "gpf8", 0x00),
0645 };
0646 
0647 /* pin banks of exynosautov9 pin-controller 4 (FSYS2) */
0648 static const struct samsung_pin_bank_data exynosautov9_pin_banks4[] __initconst = {
0649     EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpf2", 0x00),
0650     EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpf3", 0x04),
0651     EXYNOS850_PIN_BANK_EINTG(7, 0x040, "gpf4", 0x08),
0652     EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpf5", 0x0C),
0653     EXYNOS850_PIN_BANK_EINTG(7, 0x080, "gpf6", 0x10),
0654 };
0655 
0656 /* pin banks of exynosautov9 pin-controller 5 (PERIC0) */
0657 static const struct samsung_pin_bank_data exynosautov9_pin_banks5[] __initconst = {
0658     EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp0", 0x00),
0659     EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp1", 0x04),
0660     EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp2", 0x08),
0661     EXYNOS850_PIN_BANK_EINTG(5, 0x060, "gpg0", 0x0C),
0662 };
0663 
0664 /* pin banks of exynosautov9 pin-controller 6 (PERIC1) */
0665 static const struct samsung_pin_bank_data exynosautov9_pin_banks6[] __initconst = {
0666     EXYNOS850_PIN_BANK_EINTG(8, 0x000, "gpp3", 0x00),
0667     EXYNOS850_PIN_BANK_EINTG(8, 0x020, "gpp4", 0x04),
0668     EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpp5", 0x08),
0669     EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpg1", 0x0C),
0670     EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpg2", 0x10),
0671     EXYNOS850_PIN_BANK_EINTG(4, 0x0A0, "gpg3", 0x14),
0672 };
0673 
0674 static const struct samsung_pin_ctrl exynosautov9_pin_ctrl[] __initconst = {
0675     {
0676         /* pin-controller instance 0 ALIVE data */
0677         .pin_banks      = exynosautov9_pin_banks0,
0678         .nr_banks       = ARRAY_SIZE(exynosautov9_pin_banks0),
0679         .eint_wkup_init = exynos_eint_wkup_init,
0680         .suspend        = exynos_pinctrl_suspend,
0681         .resume         = exynos_pinctrl_resume,
0682     }, {
0683         /* pin-controller instance 1 AUD data */
0684         .pin_banks      = exynosautov9_pin_banks1,
0685         .nr_banks       = ARRAY_SIZE(exynosautov9_pin_banks1),
0686     }, {
0687         /* pin-controller instance 2 FSYS0 data */
0688         .pin_banks      = exynosautov9_pin_banks2,
0689         .nr_banks       = ARRAY_SIZE(exynosautov9_pin_banks2),
0690         .eint_gpio_init = exynos_eint_gpio_init,
0691         .suspend        = exynos_pinctrl_suspend,
0692         .resume         = exynos_pinctrl_resume,
0693     }, {
0694         /* pin-controller instance 3 FSYS1 data */
0695         .pin_banks      = exynosautov9_pin_banks3,
0696         .nr_banks       = ARRAY_SIZE(exynosautov9_pin_banks3),
0697         .eint_gpio_init = exynos_eint_gpio_init,
0698         .suspend        = exynos_pinctrl_suspend,
0699         .resume         = exynos_pinctrl_resume,
0700     }, {
0701         /* pin-controller instance 4 FSYS2 data */
0702         .pin_banks      = exynosautov9_pin_banks4,
0703         .nr_banks       = ARRAY_SIZE(exynosautov9_pin_banks4),
0704         .eint_gpio_init = exynos_eint_gpio_init,
0705         .suspend        = exynos_pinctrl_suspend,
0706         .resume         = exynos_pinctrl_resume,
0707     }, {
0708         /* pin-controller instance 5 PERIC0 data */
0709         .pin_banks      = exynosautov9_pin_banks5,
0710         .nr_banks       = ARRAY_SIZE(exynosautov9_pin_banks5),
0711         .eint_gpio_init = exynos_eint_gpio_init,
0712         .suspend        = exynos_pinctrl_suspend,
0713         .resume         = exynos_pinctrl_resume,
0714     }, {
0715         /* pin-controller instance 6 PERIC1 data */
0716         .pin_banks      = exynosautov9_pin_banks6,
0717         .nr_banks       = ARRAY_SIZE(exynosautov9_pin_banks6),
0718         .eint_gpio_init = exynos_eint_gpio_init,
0719         .suspend        = exynos_pinctrl_suspend,
0720         .resume         = exynos_pinctrl_resume,
0721     },
0722 };
0723 
0724 const struct samsung_pinctrl_of_match_data exynosautov9_of_data __initconst = {
0725     .ctrl       = exynosautov9_pin_ctrl,
0726     .num_ctrl   = ARRAY_SIZE(exynosautov9_pin_ctrl),
0727 };
0728 
0729 /*
0730  * Pinctrl driver data for Tesla FSD SoC. FSD SoC includes three
0731  * gpio/pin-mux/pinconfig controllers.
0732  */
0733 
0734 /* pin banks of FSD pin-controller 0 (FSYS) */
0735 static const struct samsung_pin_bank_data fsd_pin_banks0[] __initconst = {
0736     EXYNOS850_PIN_BANK_EINTG(7, 0x00, "gpf0", 0x00),
0737     EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gpf1", 0x04),
0738     EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gpf6", 0x08),
0739     EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpf4", 0x0c),
0740     EXYNOS850_PIN_BANK_EINTG(6, 0x80, "gpf5", 0x10),
0741 };
0742 
0743 /* pin banks of FSD pin-controller 1 (PERIC) */
0744 static const struct samsung_pin_bank_data fsd_pin_banks1[] __initconst = {
0745     EXYNOS850_PIN_BANK_EINTG(4, 0x000, "gpc8", 0x00),
0746     EXYNOS850_PIN_BANK_EINTG(7, 0x020, "gpf2", 0x04),
0747     EXYNOS850_PIN_BANK_EINTG(8, 0x040, "gpf3", 0x08),
0748     EXYNOS850_PIN_BANK_EINTG(8, 0x060, "gpd0", 0x0c),
0749     EXYNOS850_PIN_BANK_EINTG(8, 0x080, "gpb0", 0x10),
0750     EXYNOS850_PIN_BANK_EINTG(8, 0x0a0, "gpb1", 0x14),
0751     EXYNOS850_PIN_BANK_EINTG(8, 0x0c0, "gpb4", 0x18),
0752     EXYNOS850_PIN_BANK_EINTG(4, 0x0e0, "gpb5", 0x1c),
0753     EXYNOS850_PIN_BANK_EINTG(8, 0x100, "gpb6", 0x20),
0754     EXYNOS850_PIN_BANK_EINTG(8, 0x120, "gpb7", 0x24),
0755     EXYNOS850_PIN_BANK_EINTG(5, 0x140, "gpd1", 0x28),
0756     EXYNOS850_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
0757     EXYNOS850_PIN_BANK_EINTG(7, 0x180, "gpd3", 0x30),
0758     EXYNOS850_PIN_BANK_EINTG(8, 0x1a0, "gpg0", 0x34),
0759     EXYNOS850_PIN_BANK_EINTG(8, 0x1c0, "gpg1", 0x38),
0760     EXYNOS850_PIN_BANK_EINTG(8, 0x1e0, "gpg2", 0x3c),
0761     EXYNOS850_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
0762     EXYNOS850_PIN_BANK_EINTG(8, 0x220, "gpg4", 0x44),
0763     EXYNOS850_PIN_BANK_EINTG(8, 0x240, "gpg5", 0x48),
0764     EXYNOS850_PIN_BANK_EINTG(8, 0x260, "gpg6", 0x4c),
0765     EXYNOS850_PIN_BANK_EINTG(8, 0x280, "gpg7", 0x50),
0766 };
0767 
0768 /* pin banks of FSD pin-controller 2 (PMU) */
0769 static const struct samsung_pin_bank_data fsd_pin_banks2[] __initconst = {
0770     EXYNOS850_PIN_BANK_EINTN(3, 0x00, "gpq0"),
0771 };
0772 
0773 static const struct samsung_pin_ctrl fsd_pin_ctrl[] __initconst = {
0774     {
0775         /* pin-controller instance 0 FSYS0 data */
0776         .pin_banks  = fsd_pin_banks0,
0777         .nr_banks   = ARRAY_SIZE(fsd_pin_banks0),
0778         .eint_gpio_init = exynos_eint_gpio_init,
0779         .suspend    = exynos_pinctrl_suspend,
0780         .resume     = exynos_pinctrl_resume,
0781     }, {
0782         /* pin-controller instance 1 PERIC data */
0783         .pin_banks  = fsd_pin_banks1,
0784         .nr_banks   = ARRAY_SIZE(fsd_pin_banks1),
0785         .eint_gpio_init = exynos_eint_gpio_init,
0786         .suspend    = exynos_pinctrl_suspend,
0787         .resume     = exynos_pinctrl_resume,
0788     }, {
0789         /* pin-controller instance 2 PMU data */
0790         .pin_banks  = fsd_pin_banks2,
0791         .nr_banks   = ARRAY_SIZE(fsd_pin_banks2),
0792     },
0793 };
0794 
0795 const struct samsung_pinctrl_of_match_data fsd_of_data __initconst = {
0796     .ctrl       = fsd_pin_ctrl,
0797     .num_ctrl   = ARRAY_SIZE(fsd_pin_ctrl),
0798 };
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