pinctrl/samsung/pinctrl-exynos-arm.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
0004 //
0005 // Copyright (c) 2012 Samsung Electronics Co., Ltd.
0006 //      http://www.samsung.com
0007 // Copyright (c) 2012 Linaro Ltd
0008 //      http://www.linaro.org
0009 //
0010 // Author: Thomas Abraham <thomas.ab@samsung.com>
0011 //
0012 // This file contains the Samsung Exynos specific information required by the
0013 // the Samsung pinctrl/gpiolib driver. It also includes the implementation of
0014 // external gpio and wakeup interrupt support.
0015
0016 #include <linux/device.h>
0017 #include <linux/of_address.h>
0018 #include <linux/slab.h>
0019 #include <linux/err.h>
0020 #include <linux/soc/samsung/exynos-regs-pmu.h>
0021
0022 #include "pinctrl-samsung.h"
0023 #include "pinctrl-exynos.h"
0024
0025 static const struct samsung_pin_bank_type bank_type_off = {
0026     .fld_width = { 4, 1, 2, 2, 2, 2, },
0027     .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
0028 };
0029
0030 static const struct samsung_pin_bank_type bank_type_alive = {
0031     .fld_width = { 4, 1, 2, 2, },
0032     .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
0033 };
0034
0035 /* Retention control for S5PV210 are located at the end of clock controller */
0036 #define S5P_OTHERS 0xE000
0037
0038 #define S5P_OTHERS_RET_IO       (1 << 31)
0039 #define S5P_OTHERS_RET_CF       (1 << 30)
0040 #define S5P_OTHERS_RET_MMC      (1 << 29)
0041 #define S5P_OTHERS_RET_UART     (1 << 28)
0042
0043 static void s5pv210_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
0044 {
0045     void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv;
0046     u32 tmp;
0047
0048     tmp = __raw_readl(clk_base + S5P_OTHERS);
0049     tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | S5P_OTHERS_RET_MMC |
0050         S5P_OTHERS_RET_UART);
0051     __raw_writel(tmp, clk_base + S5P_OTHERS);
0052 }
0053
0054 static struct samsung_retention_ctrl *
0055 s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata,
0056                const struct samsung_retention_data *data)
0057 {
0058     struct samsung_retention_ctrl *ctrl;
0059     struct device_node *np;
0060     void __iomem *clk_base;
0061
0062     ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL);
0063     if (!ctrl)
0064         return ERR_PTR(-ENOMEM);
0065
0066     np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock");
0067     if (!np) {
0068         pr_err("%s: failed to find clock controller DT node\n",
0069             __func__);
0070         return ERR_PTR(-ENODEV);
0071     }
0072
0073     clk_base = of_iomap(np, 0);
0074     of_node_put(np);
0075     if (!clk_base) {
0076         pr_err("%s: failed to map clock registers\n", __func__);
0077         return ERR_PTR(-EINVAL);
0078     }
0079
0080     ctrl->priv = (void __force *)clk_base;
0081     ctrl->disable = s5pv210_retention_disable;
0082
0083     return ctrl;
0084 }
0085
0086 static const struct samsung_retention_data s5pv210_retention_data __initconst = {
0087     .init    = s5pv210_retention_init,
0088 };
0089
0090 /* pin banks of s5pv210 pin-controller */
0091 static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
0092     /* Must start with EINTG banks, ordered by EINT group number. */
0093     EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
0094     EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
0095     EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
0096     EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
0097     EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
0098     EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
0099     EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
0100     EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),
0101     EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),
0102     EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),
0103     EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
0104     EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
0105     EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),
0106     EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
0107     EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
0108     EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
0109     EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
0110     EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
0111     EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
0112     EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
0113     EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
0114     EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
0115     EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
0116     EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
0117     EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
0118     EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
0119     EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
0120     EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
0121     EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
0122     EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
0123     EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
0124     EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
0125     EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
0126     EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
0127 };
0128
0129 static const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
0130     {
0131         /* pin-controller instance 0 data */
0132         .pin_banks  = s5pv210_pin_bank,
0133         .nr_banks   = ARRAY_SIZE(s5pv210_pin_bank),
0134         .eint_gpio_init = exynos_eint_gpio_init,
0135         .eint_wkup_init = exynos_eint_wkup_init,
0136         .suspend    = exynos_pinctrl_suspend,
0137         .resume     = exynos_pinctrl_resume,
0138         .retention_data = &s5pv210_retention_data,
0139     },
0140 };
0141
0142 const struct samsung_pinctrl_of_match_data s5pv210_of_data __initconst = {
0143     .ctrl       = s5pv210_pin_ctrl,
0144     .num_ctrl   = ARRAY_SIZE(s5pv210_pin_ctrl),
0145 };
0146
0147 /* Pad retention control code for accessing PMU regmap */
0148 static atomic_t exynos_shared_retention_refcnt;
0149
0150 /* pin banks of exynos3250 pin-controller 0 */
0151 static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = {
0152     /* Must start with EINTG banks, ordered by EINT group number. */
0153     EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
0154     EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
0155     EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb",  0x08),
0156     EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
0157     EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
0158     EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
0159     EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
0160 };
0161
0162 /* pin banks of exynos3250 pin-controller 1 */
0163 static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = {
0164     /* Must start with EINTG banks, ordered by EINT group number. */
0165     EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
0166     EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
0167     EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
0168     EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
0169     EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
0170     EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
0171     EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
0172     EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
0173     EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
0174     EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
0175     EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
0176     EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
0177     EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
0178     EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
0179     EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
0180     EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
0181 };
0182
0183 /*
0184  * PMU pad retention groups for Exynos3250 doesn't match pin banks, so handle
0185  * them all together
0186  */
0187 static const u32 exynos3250_retention_regs[] = {
0188     S5P_PAD_RET_MAUDIO_OPTION,
0189     S5P_PAD_RET_GPIO_OPTION,
0190     S5P_PAD_RET_UART_OPTION,
0191     S5P_PAD_RET_MMCA_OPTION,
0192     S5P_PAD_RET_MMCB_OPTION,
0193     S5P_PAD_RET_EBIA_OPTION,
0194     S5P_PAD_RET_EBIB_OPTION,
0195     S5P_PAD_RET_MMC2_OPTION,
0196     S5P_PAD_RET_SPI_OPTION,
0197 };
0198
0199 static const struct samsung_retention_data exynos3250_retention_data __initconst = {
0200     .regs    = exynos3250_retention_regs,
0201     .nr_regs = ARRAY_SIZE(exynos3250_retention_regs),
0202     .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
0203     .refcnt  = &exynos_shared_retention_refcnt,
0204     .init    = exynos_retention_init,
0205 };
0206
0207 /*
0208  * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
0209  * two gpio/pin-mux/pinconfig controllers.
0210  */
0211 static const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
0212     {
0213         /* pin-controller instance 0 data */
0214         .pin_banks  = exynos3250_pin_banks0,
0215         .nr_banks   = ARRAY_SIZE(exynos3250_pin_banks0),
0216         .eint_gpio_init = exynos_eint_gpio_init,
0217         .suspend    = exynos_pinctrl_suspend,
0218         .resume     = exynos_pinctrl_resume,
0219         .retention_data = &exynos3250_retention_data,
0220     }, {
0221         /* pin-controller instance 1 data */
0222         .pin_banks  = exynos3250_pin_banks1,
0223         .nr_banks   = ARRAY_SIZE(exynos3250_pin_banks1),
0224         .eint_gpio_init = exynos_eint_gpio_init,
0225         .eint_wkup_init = exynos_eint_wkup_init,
0226         .suspend    = exynos_pinctrl_suspend,
0227         .resume     = exynos_pinctrl_resume,
0228         .retention_data = &exynos3250_retention_data,
0229     },
0230 };
0231
0232 const struct samsung_pinctrl_of_match_data exynos3250_of_data __initconst = {
0233     .ctrl       = exynos3250_pin_ctrl,
0234     .num_ctrl   = ARRAY_SIZE(exynos3250_pin_ctrl),
0235 };
0236
0237 /* pin banks of exynos4210 pin-controller 0 */
0238 static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {
0239     /* Must start with EINTG banks, ordered by EINT group number. */
0240     EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
0241     EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
0242     EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
0243     EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
0244     EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
0245     EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
0246     EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
0247     EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
0248     EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
0249     EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
0250     EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
0251     EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
0252     EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
0253     EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
0254     EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
0255     EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
0256 };
0257
0258 /* pin banks of exynos4210 pin-controller 1 */
0259 static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = {
0260     /* Must start with EINTG banks, ordered by EINT group number. */
0261     EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
0262     EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
0263     EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
0264     EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
0265     EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
0266     EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
0267     EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
0268     EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
0269     EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
0270     EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
0271     EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
0272     EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
0273     EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
0274     EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
0275     EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
0276     EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
0277     EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
0278     EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
0279     EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
0280     EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
0281 };
0282
0283 /* pin banks of exynos4210 pin-controller 2 */
0284 static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = {
0285     /* Must start with EINTG banks, ordered by EINT group number. */
0286     EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
0287 };
0288
0289 /* PMU pad retention groups registers for Exynos4 (without audio) */
0290 static const u32 exynos4_retention_regs[] = {
0291     S5P_PAD_RET_GPIO_OPTION,
0292     S5P_PAD_RET_UART_OPTION,
0293     S5P_PAD_RET_MMCA_OPTION,
0294     S5P_PAD_RET_MMCB_OPTION,
0295     S5P_PAD_RET_EBIA_OPTION,
0296     S5P_PAD_RET_EBIB_OPTION,
0297 };
0298
0299 static const struct samsung_retention_data exynos4_retention_data __initconst = {
0300     .regs    = exynos4_retention_regs,
0301     .nr_regs = ARRAY_SIZE(exynos4_retention_regs),
0302     .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
0303     .refcnt  = &exynos_shared_retention_refcnt,
0304     .init    = exynos_retention_init,
0305 };
0306
0307 /* PMU retention control for audio pins can be tied to audio pin bank */
0308 static const u32 exynos4_audio_retention_regs[] = {
0309     S5P_PAD_RET_MAUDIO_OPTION,
0310 };
0311
0312 static const struct samsung_retention_data exynos4_audio_retention_data __initconst = {
0313     .regs    = exynos4_audio_retention_regs,
0314     .nr_regs = ARRAY_SIZE(exynos4_audio_retention_regs),
0315     .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
0316     .init    = exynos_retention_init,
0317 };
0318
0319 /*
0320  * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
0321  * three gpio/pin-mux/pinconfig controllers.
0322  */
0323 static const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
0324     {
0325         /* pin-controller instance 0 data */
0326         .pin_banks  = exynos4210_pin_banks0,
0327         .nr_banks   = ARRAY_SIZE(exynos4210_pin_banks0),
0328         .eint_gpio_init = exynos_eint_gpio_init,
0329         .suspend    = exynos_pinctrl_suspend,
0330         .resume     = exynos_pinctrl_resume,
0331         .retention_data = &exynos4_retention_data,
0332     }, {
0333         /* pin-controller instance 1 data */
0334         .pin_banks  = exynos4210_pin_banks1,
0335         .nr_banks   = ARRAY_SIZE(exynos4210_pin_banks1),
0336         .eint_gpio_init = exynos_eint_gpio_init,
0337         .eint_wkup_init = exynos_eint_wkup_init,
0338         .suspend    = exynos_pinctrl_suspend,
0339         .resume     = exynos_pinctrl_resume,
0340         .retention_data = &exynos4_retention_data,
0341     }, {
0342         /* pin-controller instance 2 data */
0343         .pin_banks  = exynos4210_pin_banks2,
0344         .nr_banks   = ARRAY_SIZE(exynos4210_pin_banks2),
0345         .retention_data = &exynos4_audio_retention_data,
0346     },
0347 };
0348
0349 const struct samsung_pinctrl_of_match_data exynos4210_of_data __initconst = {
0350     .ctrl       = exynos4210_pin_ctrl,
0351     .num_ctrl   = ARRAY_SIZE(exynos4210_pin_ctrl),
0352 };
0353
0354 /* pin banks of exynos4x12 pin-controller 0 */
0355 static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = {
0356     /* Must start with EINTG banks, ordered by EINT group number. */
0357     EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
0358     EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
0359     EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
0360     EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
0361     EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
0362     EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
0363     EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
0364     EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
0365     EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
0366     EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
0367     EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
0368     EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
0369     EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
0370 };
0371
0372 /* pin banks of exynos4x12 pin-controller 1 */
0373 static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = {
0374     /* Must start with EINTG banks, ordered by EINT group number. */
0375     EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
0376     EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
0377     EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
0378     EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
0379     EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
0380     EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
0381     EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
0382     EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
0383     EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
0384     EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
0385     EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
0386     EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
0387     EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
0388     EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
0389     EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
0390     EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
0391     EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
0392     EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
0393     EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
0394     EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
0395     EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
0396     EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
0397     EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
0398 };
0399
0400 /* pin banks of exynos4x12 pin-controller 2 */
0401 static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = {
0402     /* Must start with EINTG banks, ordered by EINT group number. */
0403     EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
0404 };
0405
0406 /* pin banks of exynos4x12 pin-controller 3 */
0407 static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = {
0408     /* Must start with EINTG banks, ordered by EINT group number. */
0409     EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
0410     EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
0411     EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
0412     EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
0413     EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
0414 };
0415
0416 /*
0417  * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
0418  * four gpio/pin-mux/pinconfig controllers.
0419  */
0420 static const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
0421     {
0422         /* pin-controller instance 0 data */
0423         .pin_banks  = exynos4x12_pin_banks0,
0424         .nr_banks   = ARRAY_SIZE(exynos4x12_pin_banks0),
0425         .eint_gpio_init = exynos_eint_gpio_init,
0426         .suspend    = exynos_pinctrl_suspend,
0427         .resume     = exynos_pinctrl_resume,
0428         .retention_data = &exynos4_retention_data,
0429     }, {
0430         /* pin-controller instance 1 data */
0431         .pin_banks  = exynos4x12_pin_banks1,
0432         .nr_banks   = ARRAY_SIZE(exynos4x12_pin_banks1),
0433         .eint_gpio_init = exynos_eint_gpio_init,
0434         .eint_wkup_init = exynos_eint_wkup_init,
0435         .suspend    = exynos_pinctrl_suspend,
0436         .resume     = exynos_pinctrl_resume,
0437         .retention_data = &exynos4_retention_data,
0438     }, {
0439         /* pin-controller instance 2 data */
0440         .pin_banks  = exynos4x12_pin_banks2,
0441         .nr_banks   = ARRAY_SIZE(exynos4x12_pin_banks2),
0442         .eint_gpio_init = exynos_eint_gpio_init,
0443         .suspend    = exynos_pinctrl_suspend,
0444         .resume     = exynos_pinctrl_resume,
0445         .retention_data = &exynos4_audio_retention_data,
0446     }, {
0447         /* pin-controller instance 3 data */
0448         .pin_banks  = exynos4x12_pin_banks3,
0449         .nr_banks   = ARRAY_SIZE(exynos4x12_pin_banks3),
0450         .eint_gpio_init = exynos_eint_gpio_init,
0451         .suspend    = exynos_pinctrl_suspend,
0452         .resume     = exynos_pinctrl_resume,
0453     },
0454 };
0455
0456 const struct samsung_pinctrl_of_match_data exynos4x12_of_data __initconst = {
0457     .ctrl       = exynos4x12_pin_ctrl,
0458     .num_ctrl   = ARRAY_SIZE(exynos4x12_pin_ctrl),
0459 };
0460
0461 /* pin banks of exynos5250 pin-controller 0 */
0462 static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = {
0463     /* Must start with EINTG banks, ordered by EINT group number. */
0464     EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
0465     EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
0466     EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
0467     EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
0468     EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
0469     EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
0470     EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
0471     EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
0472     EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
0473     EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
0474     EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
0475     EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
0476     EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
0477     EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
0478     EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
0479     EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
0480     EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
0481     EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
0482     EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
0483     EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
0484     EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
0485     EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
0486     EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
0487     EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
0488     EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
0489 };
0490
0491 /* pin banks of exynos5250 pin-controller 1 */
0492 static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = {
0493     /* Must start with EINTG banks, ordered by EINT group number. */
0494     EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
0495     EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
0496     EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
0497     EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
0498     EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
0499     EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
0500     EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
0501     EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
0502     EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
0503 };
0504
0505 /* pin banks of exynos5250 pin-controller 2 */
0506 static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = {
0507     /* Must start with EINTG banks, ordered by EINT group number. */
0508     EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
0509     EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
0510     EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
0511     EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
0512     EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
0513 };
0514
0515 /* pin banks of exynos5250 pin-controller 3 */
0516 static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = {
0517     /* Must start with EINTG banks, ordered by EINT group number. */
0518     EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
0519 };
0520
0521 /*
0522  * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
0523  * four gpio/pin-mux/pinconfig controllers.
0524  */
0525 static const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
0526     {
0527         /* pin-controller instance 0 data */
0528         .pin_banks  = exynos5250_pin_banks0,
0529         .nr_banks   = ARRAY_SIZE(exynos5250_pin_banks0),
0530         .eint_gpio_init = exynos_eint_gpio_init,
0531         .eint_wkup_init = exynos_eint_wkup_init,
0532         .suspend    = exynos_pinctrl_suspend,
0533         .resume     = exynos_pinctrl_resume,
0534         .retention_data = &exynos4_retention_data,
0535     }, {
0536         /* pin-controller instance 1 data */
0537         .pin_banks  = exynos5250_pin_banks1,
0538         .nr_banks   = ARRAY_SIZE(exynos5250_pin_banks1),
0539         .eint_gpio_init = exynos_eint_gpio_init,
0540         .suspend    = exynos_pinctrl_suspend,
0541         .resume     = exynos_pinctrl_resume,
0542         .retention_data = &exynos4_retention_data,
0543     }, {
0544         /* pin-controller instance 2 data */
0545         .pin_banks  = exynos5250_pin_banks2,
0546         .nr_banks   = ARRAY_SIZE(exynos5250_pin_banks2),
0547         .eint_gpio_init = exynos_eint_gpio_init,
0548         .suspend    = exynos_pinctrl_suspend,
0549         .resume     = exynos_pinctrl_resume,
0550     }, {
0551         /* pin-controller instance 3 data */
0552         .pin_banks  = exynos5250_pin_banks3,
0553         .nr_banks   = ARRAY_SIZE(exynos5250_pin_banks3),
0554         .eint_gpio_init = exynos_eint_gpio_init,
0555         .suspend    = exynos_pinctrl_suspend,
0556         .resume     = exynos_pinctrl_resume,
0557         .retention_data = &exynos4_audio_retention_data,
0558     },
0559 };
0560
0561 const struct samsung_pinctrl_of_match_data exynos5250_of_data __initconst = {
0562     .ctrl       = exynos5250_pin_ctrl,
0563     .num_ctrl   = ARRAY_SIZE(exynos5250_pin_ctrl),
0564 };
0565
0566 /* pin banks of exynos5260 pin-controller 0 */
0567 static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = {
0568     /* Must start with EINTG banks, ordered by EINT group number. */
0569     EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
0570     EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
0571     EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
0572     EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
0573     EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
0574     EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
0575     EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
0576     EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
0577     EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
0578     EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
0579     EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
0580     EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
0581     EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
0582     EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
0583     EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
0584     EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
0585     EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
0586     EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
0587     EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
0588     EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
0589     EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
0590 };
0591
0592 /* pin banks of exynos5260 pin-controller 1 */
0593 static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = {
0594     /* Must start with EINTG banks, ordered by EINT group number. */
0595     EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
0596     EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
0597     EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
0598     EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
0599     EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
0600 };
0601
0602 /* pin banks of exynos5260 pin-controller 2 */
0603 static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = {
0604     /* Must start with EINTG banks, ordered by EINT group number. */
0605     EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
0606     EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
0607 };
0608
0609 /*
0610  * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
0611  * three gpio/pin-mux/pinconfig controllers.
0612  */
0613 static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
0614     {
0615         /* pin-controller instance 0 data */
0616         .pin_banks  = exynos5260_pin_banks0,
0617         .nr_banks   = ARRAY_SIZE(exynos5260_pin_banks0),
0618         .eint_gpio_init = exynos_eint_gpio_init,
0619         .eint_wkup_init = exynos_eint_wkup_init,
0620         .suspend    = exynos_pinctrl_suspend,
0621         .resume     = exynos_pinctrl_resume,
0622     }, {
0623         /* pin-controller instance 1 data */
0624         .pin_banks  = exynos5260_pin_banks1,
0625         .nr_banks   = ARRAY_SIZE(exynos5260_pin_banks1),
0626         .eint_gpio_init = exynos_eint_gpio_init,
0627         .suspend    = exynos_pinctrl_suspend,
0628         .resume     = exynos_pinctrl_resume,
0629     }, {
0630         /* pin-controller instance 2 data */
0631         .pin_banks  = exynos5260_pin_banks2,
0632         .nr_banks   = ARRAY_SIZE(exynos5260_pin_banks2),
0633         .eint_gpio_init = exynos_eint_gpio_init,
0634         .suspend    = exynos_pinctrl_suspend,
0635         .resume     = exynos_pinctrl_resume,
0636     },
0637 };
0638
0639 const struct samsung_pinctrl_of_match_data exynos5260_of_data __initconst = {
0640     .ctrl       = exynos5260_pin_ctrl,
0641     .num_ctrl   = ARRAY_SIZE(exynos5260_pin_ctrl),
0642 };
0643
0644 /* pin banks of exynos5410 pin-controller 0 */
0645 static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = {
0646     /* Must start with EINTG banks, ordered by EINT group number. */
0647     EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
0648     EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
0649     EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
0650     EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
0651     EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
0652     EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
0653     EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
0654     EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
0655     EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20),
0656     EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24),
0657     EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28),
0658     EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c),
0659     EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30),
0660     EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34),
0661     EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38),
0662     EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c),
0663     EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40),
0664     EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44),
0665     EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48),
0666     EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c),
0667     EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50),
0668     EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
0669     EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"),
0670     EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"),
0671     EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"),
0672     EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"),
0673     EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"),
0674     EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"),
0675     EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"),
0676     EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"),
0677     EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"),
0678     EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
0679     EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
0680     EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
0681     EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
0682 };
0683
0684 /* pin banks of exynos5410 pin-controller 1 */
0685 static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = {
0686     /* Must start with EINTG banks, ordered by EINT group number. */
0687     EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00),
0688     EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04),
0689     EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08),
0690     EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c),
0691     EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10),
0692     EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14),
0693     EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18),
0694     EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c),
0695     EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20),
0696 };
0697
0698 /* pin banks of exynos5410 pin-controller 2 */
0699 static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = {
0700     /* Must start with EINTG banks, ordered by EINT group number. */
0701     EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
0702     EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
0703     EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
0704     EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
0705     EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
0706 };
0707
0708 /* pin banks of exynos5410 pin-controller 3 */
0709 static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = {
0710     /* Must start with EINTG banks, ordered by EINT group number. */
0711     EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
0712 };
0713
0714 /*
0715  * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes
0716  * four gpio/pin-mux/pinconfig controllers.
0717  */
0718 static const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = {
0719     {
0720         /* pin-controller instance 0 data */
0721         .pin_banks  = exynos5410_pin_banks0,
0722         .nr_banks   = ARRAY_SIZE(exynos5410_pin_banks0),
0723         .eint_gpio_init = exynos_eint_gpio_init,
0724         .eint_wkup_init = exynos_eint_wkup_init,
0725         .suspend    = exynos_pinctrl_suspend,
0726         .resume     = exynos_pinctrl_resume,
0727     }, {
0728         /* pin-controller instance 1 data */
0729         .pin_banks  = exynos5410_pin_banks1,
0730         .nr_banks   = ARRAY_SIZE(exynos5410_pin_banks1),
0731         .eint_gpio_init = exynos_eint_gpio_init,
0732         .suspend    = exynos_pinctrl_suspend,
0733         .resume     = exynos_pinctrl_resume,
0734     }, {
0735         /* pin-controller instance 2 data */
0736         .pin_banks  = exynos5410_pin_banks2,
0737         .nr_banks   = ARRAY_SIZE(exynos5410_pin_banks2),
0738         .eint_gpio_init = exynos_eint_gpio_init,
0739         .suspend    = exynos_pinctrl_suspend,
0740         .resume     = exynos_pinctrl_resume,
0741     }, {
0742         /* pin-controller instance 3 data */
0743         .pin_banks  = exynos5410_pin_banks3,
0744         .nr_banks   = ARRAY_SIZE(exynos5410_pin_banks3),
0745         .eint_gpio_init = exynos_eint_gpio_init,
0746         .suspend    = exynos_pinctrl_suspend,
0747         .resume     = exynos_pinctrl_resume,
0748     },
0749 };
0750
0751 const struct samsung_pinctrl_of_match_data exynos5410_of_data __initconst = {
0752     .ctrl       = exynos5410_pin_ctrl,
0753     .num_ctrl   = ARRAY_SIZE(exynos5410_pin_ctrl),
0754 };
0755
0756 /* pin banks of exynos5420 pin-controller 0 */
0757 static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
0758     /* Must start with EINTG banks, ordered by EINT group number. */
0759     EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
0760     EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
0761     EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
0762     EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
0763     EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
0764 };
0765
0766 /* pin banks of exynos5420 pin-controller 1 */
0767 static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = {
0768     /* Must start with EINTG banks, ordered by EINT group number. */
0769     EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
0770     EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
0771     EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
0772     EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
0773     EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
0774     EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
0775     EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
0776     EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
0777     EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
0778     EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
0779     EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
0780     EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
0781     EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
0782 };
0783
0784 /* pin banks of exynos5420 pin-controller 2 */
0785 static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = {
0786     /* Must start with EINTG banks, ordered by EINT group number. */
0787     EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
0788     EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
0789     EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
0790     EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
0791     EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
0792     EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
0793     EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
0794     EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
0795 };
0796
0797 /* pin banks of exynos5420 pin-controller 3 */
0798 static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = {
0799     /* Must start with EINTG banks, ordered by EINT group number. */
0800     EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
0801     EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
0802     EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
0803     EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
0804     EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
0805     EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
0806     EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
0807     EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
0808     EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
0809 };
0810
0811 /* pin banks of exynos5420 pin-controller 4 */
0812 static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = {
0813     /* Must start with EINTG banks, ordered by EINT group number. */
0814     EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
0815 };
0816
0817 /* PMU pad retention groups registers for Exynos5420 (without audio) */
0818 static const u32 exynos5420_retention_regs[] = {
0819     EXYNOS_PAD_RET_DRAM_OPTION,
0820     EXYNOS_PAD_RET_JTAG_OPTION,
0821     EXYNOS5420_PAD_RET_GPIO_OPTION,
0822     EXYNOS5420_PAD_RET_UART_OPTION,
0823     EXYNOS5420_PAD_RET_MMCA_OPTION,
0824     EXYNOS5420_PAD_RET_MMCB_OPTION,
0825     EXYNOS5420_PAD_RET_MMCC_OPTION,
0826     EXYNOS5420_PAD_RET_HSI_OPTION,
0827     EXYNOS_PAD_RET_EBIA_OPTION,
0828     EXYNOS_PAD_RET_EBIB_OPTION,
0829     EXYNOS5420_PAD_RET_SPI_OPTION,
0830     EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
0831 };
0832
0833 static const struct samsung_retention_data exynos5420_retention_data __initconst = {
0834     .regs    = exynos5420_retention_regs,
0835     .nr_regs = ARRAY_SIZE(exynos5420_retention_regs),
0836     .value   = EXYNOS_WAKEUP_FROM_LOWPWR,
0837     .refcnt  = &exynos_shared_retention_refcnt,
0838     .init    = exynos_retention_init,
0839 };
0840
0841 /*
0842  * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
0843  * four gpio/pin-mux/pinconfig controllers.
0844  */
0845 static const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
0846     {
0847         /* pin-controller instance 0 data */
0848         .pin_banks  = exynos5420_pin_banks0,
0849         .nr_banks   = ARRAY_SIZE(exynos5420_pin_banks0),
0850         .eint_gpio_init = exynos_eint_gpio_init,
0851         .eint_wkup_init = exynos_eint_wkup_init,
0852         .suspend    = exynos_pinctrl_suspend,
0853         .resume     = exynos_pinctrl_resume,
0854         .retention_data = &exynos5420_retention_data,
0855     }, {
0856         /* pin-controller instance 1 data */
0857         .pin_banks  = exynos5420_pin_banks1,
0858         .nr_banks   = ARRAY_SIZE(exynos5420_pin_banks1),
0859         .eint_gpio_init = exynos_eint_gpio_init,
0860         .suspend    = exynos_pinctrl_suspend,
0861         .resume     = exynos_pinctrl_resume,
0862         .retention_data = &exynos5420_retention_data,
0863     }, {
0864         /* pin-controller instance 2 data */
0865         .pin_banks  = exynos5420_pin_banks2,
0866         .nr_banks   = ARRAY_SIZE(exynos5420_pin_banks2),
0867         .eint_gpio_init = exynos_eint_gpio_init,
0868         .suspend    = exynos_pinctrl_suspend,
0869         .resume     = exynos_pinctrl_resume,
0870         .retention_data = &exynos5420_retention_data,
0871     }, {
0872         /* pin-controller instance 3 data */
0873         .pin_banks  = exynos5420_pin_banks3,
0874         .nr_banks   = ARRAY_SIZE(exynos5420_pin_banks3),
0875         .eint_gpio_init = exynos_eint_gpio_init,
0876         .suspend    = exynos_pinctrl_suspend,
0877         .resume     = exynos_pinctrl_resume,
0878         .retention_data = &exynos5420_retention_data,
0879     }, {
0880         /* pin-controller instance 4 data */
0881         .pin_banks  = exynos5420_pin_banks4,
0882         .nr_banks   = ARRAY_SIZE(exynos5420_pin_banks4),
0883         .eint_gpio_init = exynos_eint_gpio_init,
0884         .suspend    = exynos_pinctrl_suspend,
0885         .resume     = exynos_pinctrl_resume,
0886         .retention_data = &exynos4_audio_retention_data,
0887     },
0888 };
0889
0890 const struct samsung_pinctrl_of_match_data exynos5420_of_data __initconst = {
0891     .ctrl       = exynos5420_pin_ctrl,
0892     .num_ctrl   = ARRAY_SIZE(exynos5420_pin_ctrl),
0893 };