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0001 /* SPDX-License-Identifier: GPL-2.0
0002  *
0003  * SuperH Pin Function Controller Support
0004  *
0005  * Copyright (c) 2008 Magnus Damm
0006  */
0007 
0008 #ifndef __SH_PFC_H
0009 #define __SH_PFC_H
0010 
0011 #include <linux/bug.h>
0012 #include <linux/pinctrl/pinconf-generic.h>
0013 #include <linux/spinlock.h>
0014 #include <linux/stringify.h>
0015 
0016 enum {
0017     PINMUX_TYPE_NONE,
0018     PINMUX_TYPE_FUNCTION,
0019     PINMUX_TYPE_GPIO,
0020     PINMUX_TYPE_OUTPUT,
0021     PINMUX_TYPE_INPUT,
0022 };
0023 
0024 #define SH_PFC_PIN_NONE         U16_MAX
0025 
0026 #define SH_PFC_PIN_CFG_INPUT        (1 << 0)
0027 #define SH_PFC_PIN_CFG_OUTPUT       (1 << 1)
0028 #define SH_PFC_PIN_CFG_PULL_UP      (1 << 2)
0029 #define SH_PFC_PIN_CFG_PULL_DOWN    (1 << 3)
0030 #define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \
0031                      SH_PFC_PIN_CFG_PULL_DOWN)
0032 #define SH_PFC_PIN_CFG_IO_VOLTAGE   (1 << 4)
0033 #define SH_PFC_PIN_CFG_DRIVE_STRENGTH   (1 << 5)
0034 
0035 #define SH_PFC_PIN_VOLTAGE_18_33    (0 << 6)
0036 #define SH_PFC_PIN_VOLTAGE_25_33    (1 << 6)
0037 
0038 #define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
0039                      SH_PFC_PIN_VOLTAGE_18_33)
0040 #define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \
0041                      SH_PFC_PIN_VOLTAGE_25_33)
0042 
0043 #define SH_PFC_PIN_CFG_NO_GPIO      (1 << 31)
0044 
0045 struct sh_pfc_pin {
0046     const char *name;
0047     unsigned int configs;
0048     u16 pin;
0049     u16 enum_id;
0050 };
0051 
0052 #define SH_PFC_PIN_GROUP_ALIAS(alias, _name) {              \
0053     .name = #alias,                         \
0054     .pins = _name##_pins,                       \
0055     .mux = _name##_mux,                     \
0056     .nr_pins = ARRAY_SIZE(_name##_pins) +               \
0057     BUILD_BUG_ON_ZERO(sizeof(_name##_pins) != sizeof(_name##_mux)), \
0058 }
0059 #define SH_PFC_PIN_GROUP(name)  SH_PFC_PIN_GROUP_ALIAS(name, name)
0060 
0061 /*
0062  * Define a pin group referring to a subset of an array of pins.
0063  */
0064 #define SH_PFC_PIN_GROUP_SUBSET(_name, data, first, n) {        \
0065     .name = #_name,                         \
0066     .pins = data##_pins + first,                    \
0067     .mux = data##_mux + first,                  \
0068     .nr_pins = n +                          \
0069     BUILD_BUG_ON_ZERO(first + n > ARRAY_SIZE(data##_pins)) +    \
0070     BUILD_BUG_ON_ZERO(first + n > ARRAY_SIZE(data##_mux)),      \
0071 }
0072 
0073 /*
0074  * Define a pin group for the data pins of a resizable bus.
0075  * An optional 'suffix' argument is accepted, to be used when the same group
0076  * can appear on a different set of pins.
0077  */
0078 #define BUS_DATA_PIN_GROUP(base, n, ...)                \
0079     SH_PFC_PIN_GROUP_SUBSET(base##n##__VA_ARGS__, base##__VA_ARGS__, 0, n)
0080 
0081 struct sh_pfc_pin_group {
0082     const char *name;
0083     const unsigned int *pins;
0084     const unsigned int *mux;
0085     unsigned int nr_pins;
0086 };
0087 
0088 #define SH_PFC_FUNCTION(n) {                        \
0089     .name = #n,                         \
0090     .groups = n##_groups,                       \
0091     .nr_groups = ARRAY_SIZE(n##_groups),                \
0092 }
0093 
0094 struct sh_pfc_function {
0095     const char *name;
0096     const char * const *groups;
0097     unsigned int nr_groups;
0098 };
0099 
0100 struct pinmux_func {
0101     u16 enum_id;
0102     const char *name;
0103 };
0104 
0105 struct pinmux_cfg_reg {
0106     u32 reg;
0107     u8 reg_width, field_width;
0108 #ifdef DEBUG
0109     u16 nr_enum_ids;    /* for variable width regs only */
0110 #define SET_NR_ENUM_IDS(n)  .nr_enum_ids = n,
0111 #else
0112 #define SET_NR_ENUM_IDS(n)
0113 #endif
0114     const u16 *enum_ids;
0115     const s8 *var_field_width;
0116 };
0117 
0118 #define GROUP(...)  __VA_ARGS__
0119 
0120 /*
0121  * Describe a config register consisting of several fields of the same width
0122  *   - name: Register name (unused, for documentation purposes only)
0123  *   - r: Physical register address
0124  *   - r_width: Width of the register (in bits)
0125  *   - f_width: Width of the fixed-width register fields (in bits)
0126  *   - ids: For each register field (from left to right, i.e. MSB to LSB),
0127  *          2^f_width enum IDs must be specified, one for each possible
0128  *          combination of the register field bit values, all wrapped using
0129  *          the GROUP() macro.
0130  */
0131 #define PINMUX_CFG_REG(name, r, r_width, f_width, ids)          \
0132     .reg = r, .reg_width = r_width,                 \
0133     .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \
0134     BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
0135               (r_width / f_width) << f_width),      \
0136     .enum_ids = (const u16 [(r_width / f_width) << f_width]) { ids }
0137 
0138 /*
0139  * Describe a config register consisting of several fields of different widths
0140  *   - name: Register name (unused, for documentation purposes only)
0141  *   - r: Physical register address
0142  *   - r_width: Width of the register (in bits)
0143  *   - f_widths: List of widths of the register fields (in bits), from left
0144  *               to right (i.e. MSB to LSB), wrapped using the GROUP() macro.
0145  *               Reserved fields are indicated by negating the field width.
0146  *   - ids: For each non-reserved register field (from left to right, i.e. MSB
0147  *          to LSB), 2^f_widths[i] enum IDs must be specified, one for each
0148  *          possible combination of the register field bit values, all wrapped
0149  *          using the GROUP() macro.
0150  */
0151 #define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids)     \
0152     .reg = r, .reg_width = r_width,                 \
0153     .var_field_width = (const s8 []) { f_widths, 0 },       \
0154     SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16))   \
0155     .enum_ids = (const u16 []) { ids }
0156 
0157 struct pinmux_drive_reg_field {
0158     u16 pin;
0159     u8 offset;
0160     u8 size;
0161 };
0162 
0163 struct pinmux_drive_reg {
0164     u32 reg;
0165     const struct pinmux_drive_reg_field fields[10];
0166 };
0167 
0168 #define PINMUX_DRIVE_REG(name, r) \
0169     .reg = r, \
0170     .fields =
0171 
0172 struct pinmux_bias_reg {    /* At least one of puen/pud must exist */
0173     u32 puen;       /* Pull-enable or pull-up control register */
0174     u32 pud;        /* Pull-up/down or pull-down control register */
0175     const u16 pins[32];
0176 };
0177 
0178 #define PINMUX_BIAS_REG(name1, r1, name2, r2) \
0179     .puen = r1, \
0180     .pud = r2,  \
0181     .pins =
0182 
0183 struct pinmux_ioctrl_reg {
0184     u32 reg;
0185 };
0186 
0187 struct pinmux_data_reg {
0188     u32 reg;
0189     u8 reg_width;
0190     const u16 *enum_ids;
0191 };
0192 
0193 /*
0194  * Describe a data register
0195  *   - name: Register name (unused, for documentation purposes only)
0196  *   - r: Physical register address
0197  *   - r_width: Width of the register (in bits)
0198  *   - ids: For each register bit (from left to right, i.e. MSB to LSB), one
0199  *          enum ID must be specified, all wrapped using the GROUP() macro.
0200  */
0201 #define PINMUX_DATA_REG(name, r, r_width, ids)              \
0202     .reg = r, .reg_width = r_width +                \
0203     BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
0204               r_width),                 \
0205     .enum_ids = (const u16 [r_width]) { ids }
0206 
0207 struct pinmux_irq {
0208     const short *gpios;
0209 };
0210 
0211 /*
0212  * Describe the mapping from GPIOs to a single IRQ
0213  *   - ids...: List of GPIOs that are mapped to the same IRQ
0214  */
0215 #define PINMUX_IRQ(ids...) {                        \
0216     .gpios = (const short []) { ids, -1 }               \
0217 }
0218 
0219 struct pinmux_range {
0220     u16 begin;
0221     u16 end;
0222     u16 force;
0223 };
0224 
0225 struct sh_pfc_window {
0226     phys_addr_t phys;
0227     void __iomem *virt;
0228     unsigned long size;
0229 };
0230 
0231 struct sh_pfc_pin_range;
0232 
0233 struct sh_pfc {
0234     struct device *dev;
0235     const struct sh_pfc_soc_info *info;
0236     spinlock_t lock;
0237 
0238     unsigned int num_windows;
0239     struct sh_pfc_window *windows;
0240     unsigned int num_irqs;
0241     unsigned int *irqs;
0242 
0243     struct sh_pfc_pin_range *ranges;
0244     unsigned int nr_ranges;
0245 
0246     unsigned int nr_gpio_pins;
0247 
0248     struct sh_pfc_chip *gpio;
0249     u32 *saved_regs;
0250 };
0251 
0252 struct sh_pfc_soc_operations {
0253     int (*init)(struct sh_pfc *pfc);
0254     unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
0255     void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
0256              unsigned int bias);
0257     int (*pin_to_pocctrl)(unsigned int pin, u32 *pocctrl);
0258     int (*pin_to_portcr)(unsigned int pin);
0259 };
0260 
0261 struct sh_pfc_soc_info {
0262     const char *name;
0263     const struct sh_pfc_soc_operations *ops;
0264 
0265 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
0266     struct pinmux_range input;
0267     struct pinmux_range output;
0268     const struct pinmux_irq *gpio_irq;
0269     unsigned int gpio_irq_size;
0270 #endif
0271 
0272     struct pinmux_range function;
0273 
0274     const struct sh_pfc_pin *pins;
0275     unsigned int nr_pins;
0276     const struct sh_pfc_pin_group *groups;
0277     unsigned int nr_groups;
0278     const struct sh_pfc_function *functions;
0279     unsigned int nr_functions;
0280 
0281 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
0282     const struct pinmux_func *func_gpios;
0283     unsigned int nr_func_gpios;
0284 #endif
0285 
0286     const struct pinmux_cfg_reg *cfg_regs;
0287     const struct pinmux_drive_reg *drive_regs;
0288     const struct pinmux_bias_reg *bias_regs;
0289     const struct pinmux_ioctrl_reg *ioctrl_regs;
0290     const struct pinmux_data_reg *data_regs;
0291 
0292     const u16 *pinmux_data;
0293     unsigned int pinmux_data_size;
0294 
0295     u32 unlock_reg;     /* can be literal address or mask */
0296 };
0297 
0298 extern const struct sh_pfc_soc_info emev2_pinmux_info;
0299 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
0300 extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
0301 extern const struct sh_pfc_soc_info r8a7742_pinmux_info;
0302 extern const struct sh_pfc_soc_info r8a7743_pinmux_info;
0303 extern const struct sh_pfc_soc_info r8a7744_pinmux_info;
0304 extern const struct sh_pfc_soc_info r8a7745_pinmux_info;
0305 extern const struct sh_pfc_soc_info r8a77470_pinmux_info;
0306 extern const struct sh_pfc_soc_info r8a774a1_pinmux_info;
0307 extern const struct sh_pfc_soc_info r8a774b1_pinmux_info;
0308 extern const struct sh_pfc_soc_info r8a774c0_pinmux_info;
0309 extern const struct sh_pfc_soc_info r8a774e1_pinmux_info;
0310 extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
0311 extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
0312 extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
0313 extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
0314 extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
0315 extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
0316 extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
0317 extern const struct sh_pfc_soc_info r8a77950_pinmux_info;
0318 extern const struct sh_pfc_soc_info r8a77951_pinmux_info;
0319 extern const struct sh_pfc_soc_info r8a77960_pinmux_info;
0320 extern const struct sh_pfc_soc_info r8a77961_pinmux_info;
0321 extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
0322 extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
0323 extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
0324 extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
0325 extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
0326 extern const struct sh_pfc_soc_info r8a779a0_pinmux_info;
0327 extern const struct sh_pfc_soc_info r8a779f0_pinmux_info;
0328 extern const struct sh_pfc_soc_info r8a779g0_pinmux_info;
0329 extern const struct sh_pfc_soc_info sh7203_pinmux_info;
0330 extern const struct sh_pfc_soc_info sh7264_pinmux_info;
0331 extern const struct sh_pfc_soc_info sh7269_pinmux_info;
0332 extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
0333 extern const struct sh_pfc_soc_info sh7720_pinmux_info;
0334 extern const struct sh_pfc_soc_info sh7722_pinmux_info;
0335 extern const struct sh_pfc_soc_info sh7723_pinmux_info;
0336 extern const struct sh_pfc_soc_info sh7724_pinmux_info;
0337 extern const struct sh_pfc_soc_info sh7734_pinmux_info;
0338 extern const struct sh_pfc_soc_info sh7757_pinmux_info;
0339 extern const struct sh_pfc_soc_info sh7785_pinmux_info;
0340 extern const struct sh_pfc_soc_info sh7786_pinmux_info;
0341 extern const struct sh_pfc_soc_info shx3_pinmux_info;
0342 
0343 /* -----------------------------------------------------------------------------
0344  * Helper macros to create pin and port lists
0345  */
0346 
0347 /*
0348  * sh_pfc_soc_info pinmux_data array macros
0349  */
0350 
0351 /*
0352  * Describe generic pinmux data
0353  *   - data_or_mark: *_DATA or *_MARK enum ID
0354  *   - ids...: List of enum IDs to associate with data_or_mark
0355  */
0356 #define PINMUX_DATA(data_or_mark, ids...)   data_or_mark, ids, 0
0357 
0358 /*
0359  * Describe a pinmux configuration without GPIO function that needs
0360  * configuration in a Peripheral Function Select Register (IPSR)
0361  *   - ipsr: IPSR field (unused, for documentation purposes only)
0362  *   - fn: Function name, referring to a field in the IPSR
0363  */
0364 #define PINMUX_IPSR_NOGP(ipsr, fn)                  \
0365     PINMUX_DATA(fn##_MARK, FN_##fn)
0366 
0367 /*
0368  * Describe a pinmux configuration with GPIO function that needs configuration
0369  * in both a Peripheral Function Select Register (IPSR) and in a
0370  * GPIO/Peripheral Function Select Register (GPSR)
0371  *   - ipsr: IPSR field
0372  *   - fn: Function name, also referring to the IPSR field
0373  */
0374 #define PINMUX_IPSR_GPSR(ipsr, fn)                  \
0375     PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
0376 
0377 /*
0378  * Describe a pinmux configuration without GPIO function that needs
0379  * configuration in a Peripheral Function Select Register (IPSR), and where the
0380  * pinmux function has a representation in a Module Select Register (MOD_SEL).
0381  *   - ipsr: IPSR field (unused, for documentation purposes only)
0382  *   - fn: Function name, also referring to the IPSR field
0383  *   - msel: Module selector
0384  */
0385 #define PINMUX_IPSR_NOGM(ipsr, fn, msel)                \
0386     PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
0387 
0388 /*
0389  * Describe a pinmux configuration with GPIO function where the pinmux function
0390  * has no representation in a Peripheral Function Select Register (IPSR), but
0391  * instead solely depends on a group selection.
0392  *   - gpsr: GPSR field
0393  *   - fn: Function name, also referring to the GPSR field
0394  *   - gsel: Group selector
0395  */
0396 #define PINMUX_IPSR_NOFN(gpsr, fn, gsel)                \
0397     PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
0398 
0399 /*
0400  * Describe a pinmux configuration with GPIO function that needs configuration
0401  * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
0402  * Function Select Register (GPSR), and where the pinmux function has a
0403  * representation in a Module Select Register (MOD_SEL).
0404  *   - ipsr: IPSR field
0405  *   - fn: Function name, also referring to the IPSR field
0406  *   - msel: Module selector
0407  */
0408 #define PINMUX_IPSR_MSEL(ipsr, fn, msel)                \
0409     PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
0410 
0411 /*
0412  * Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with
0413  * an additional select register that controls physical multiplexing
0414  * with another pin.
0415  *   - ipsr: IPSR field
0416  *   - fn: Function name, also referring to the IPSR field
0417  *   - psel: Physical multiplexing selector
0418  *   - msel: Module selector
0419  */
0420 #define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \
0421     PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr)
0422 
0423 /*
0424  * Describe a pinmux configuration in which a pin is physically multiplexed
0425  * with other pins.
0426  *   - ipsr: IPSR field
0427  *   - fn: Function name
0428  *   - psel: Physical multiplexing selector
0429  */
0430 #define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
0431     PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr)
0432 
0433 /*
0434  * Describe a pinmux configuration for a single-function pin with GPIO
0435  * capability.
0436  *   - fn: Function name
0437  */
0438 #define PINMUX_SINGLE(fn)                       \
0439     PINMUX_DATA(fn##_MARK, FN_##fn)
0440 
0441 /*
0442  * GP port style (32 ports banks)
0443  */
0444 
0445 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg)              \
0446     fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
0447 #define PORT_GP_1(bank, pin, fn, sfx)   PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
0448 
0449 #define PORT_GP_CFG_2(bank, fn, sfx, cfg)               \
0450     PORT_GP_CFG_1(bank, 0,  fn, sfx, cfg),              \
0451     PORT_GP_CFG_1(bank, 1,  fn, sfx, cfg)
0452 #define PORT_GP_2(bank, fn, sfx)    PORT_GP_CFG_2(bank, fn, sfx, 0)
0453 
0454 #define PORT_GP_CFG_4(bank, fn, sfx, cfg)               \
0455     PORT_GP_CFG_2(bank, fn, sfx, cfg),              \
0456     PORT_GP_CFG_1(bank, 2,  fn, sfx, cfg),              \
0457     PORT_GP_CFG_1(bank, 3,  fn, sfx, cfg)
0458 #define PORT_GP_4(bank, fn, sfx)    PORT_GP_CFG_4(bank, fn, sfx, 0)
0459 
0460 #define PORT_GP_CFG_6(bank, fn, sfx, cfg)               \
0461     PORT_GP_CFG_4(bank, fn, sfx, cfg),              \
0462     PORT_GP_CFG_1(bank, 4,  fn, sfx, cfg),              \
0463     PORT_GP_CFG_1(bank, 5,  fn, sfx, cfg)
0464 #define PORT_GP_6(bank, fn, sfx)    PORT_GP_CFG_6(bank, fn, sfx, 0)
0465 
0466 #define PORT_GP_CFG_7(bank, fn, sfx, cfg)               \
0467     PORT_GP_CFG_6(bank, fn, sfx, cfg),              \
0468     PORT_GP_CFG_1(bank, 6,  fn, sfx, cfg)
0469 #define PORT_GP_7(bank, fn, sfx)    PORT_GP_CFG_7(bank, fn, sfx, 0)
0470 
0471 #define PORT_GP_CFG_8(bank, fn, sfx, cfg)               \
0472     PORT_GP_CFG_7(bank, fn, sfx, cfg),              \
0473     PORT_GP_CFG_1(bank, 7,  fn, sfx, cfg)
0474 #define PORT_GP_8(bank, fn, sfx)    PORT_GP_CFG_8(bank, fn, sfx, 0)
0475 
0476 #define PORT_GP_CFG_9(bank, fn, sfx, cfg)               \
0477     PORT_GP_CFG_8(bank, fn, sfx, cfg),              \
0478     PORT_GP_CFG_1(bank, 8,  fn, sfx, cfg)
0479 #define PORT_GP_9(bank, fn, sfx)    PORT_GP_CFG_9(bank, fn, sfx, 0)
0480 
0481 #define PORT_GP_CFG_10(bank, fn, sfx, cfg)              \
0482     PORT_GP_CFG_9(bank, fn, sfx, cfg),              \
0483     PORT_GP_CFG_1(bank, 9,  fn, sfx, cfg)
0484 #define PORT_GP_10(bank, fn, sfx)   PORT_GP_CFG_10(bank, fn, sfx, 0)
0485 
0486 #define PORT_GP_CFG_11(bank, fn, sfx, cfg)              \
0487     PORT_GP_CFG_10(bank, fn, sfx, cfg),             \
0488     PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
0489 #define PORT_GP_11(bank, fn, sfx)   PORT_GP_CFG_11(bank, fn, sfx, 0)
0490 
0491 #define PORT_GP_CFG_12(bank, fn, sfx, cfg)              \
0492     PORT_GP_CFG_11(bank, fn, sfx, cfg),             \
0493     PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
0494 #define PORT_GP_12(bank, fn, sfx)   PORT_GP_CFG_12(bank, fn, sfx, 0)
0495 
0496 #define PORT_GP_CFG_13(bank, fn, sfx, cfg)              \
0497     PORT_GP_CFG_12(bank, fn, sfx, cfg),             \
0498     PORT_GP_CFG_1(bank, 12, fn, sfx, cfg)
0499 #define PORT_GP_13(bank, fn, sfx)   PORT_GP_CFG_13(bank, fn, sfx, 0)
0500 
0501 #define PORT_GP_CFG_14(bank, fn, sfx, cfg)              \
0502     PORT_GP_CFG_13(bank, fn, sfx, cfg),             \
0503     PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
0504 #define PORT_GP_14(bank, fn, sfx)   PORT_GP_CFG_14(bank, fn, sfx, 0)
0505 
0506 #define PORT_GP_CFG_15(bank, fn, sfx, cfg)              \
0507     PORT_GP_CFG_14(bank, fn, sfx, cfg),             \
0508     PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
0509 #define PORT_GP_15(bank, fn, sfx)   PORT_GP_CFG_15(bank, fn, sfx, 0)
0510 
0511 #define PORT_GP_CFG_16(bank, fn, sfx, cfg)              \
0512     PORT_GP_CFG_15(bank, fn, sfx, cfg),             \
0513     PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
0514 #define PORT_GP_16(bank, fn, sfx)   PORT_GP_CFG_16(bank, fn, sfx, 0)
0515 
0516 #define PORT_GP_CFG_17(bank, fn, sfx, cfg)              \
0517     PORT_GP_CFG_16(bank, fn, sfx, cfg),             \
0518     PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
0519 #define PORT_GP_17(bank, fn, sfx)   PORT_GP_CFG_17(bank, fn, sfx, 0)
0520 
0521 #define PORT_GP_CFG_18(bank, fn, sfx, cfg)              \
0522     PORT_GP_CFG_17(bank, fn, sfx, cfg),             \
0523     PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
0524 #define PORT_GP_18(bank, fn, sfx)   PORT_GP_CFG_18(bank, fn, sfx, 0)
0525 
0526 #define PORT_GP_CFG_19(bank, fn, sfx, cfg)              \
0527     PORT_GP_CFG_18(bank, fn, sfx, cfg),             \
0528     PORT_GP_CFG_1(bank, 18, fn, sfx, cfg)
0529 #define PORT_GP_19(bank, fn, sfx)   PORT_GP_CFG_19(bank, fn, sfx, 0)
0530 
0531 #define PORT_GP_CFG_20(bank, fn, sfx, cfg)              \
0532     PORT_GP_CFG_19(bank, fn, sfx, cfg),             \
0533     PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
0534 #define PORT_GP_20(bank, fn, sfx)   PORT_GP_CFG_20(bank, fn, sfx, 0)
0535 
0536 #define PORT_GP_CFG_21(bank, fn, sfx, cfg)              \
0537     PORT_GP_CFG_20(bank, fn, sfx, cfg),             \
0538     PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
0539 #define PORT_GP_21(bank, fn, sfx)   PORT_GP_CFG_21(bank, fn, sfx, 0)
0540 
0541 #define PORT_GP_CFG_22(bank, fn, sfx, cfg)              \
0542     PORT_GP_CFG_21(bank, fn, sfx, cfg),             \
0543     PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
0544 #define PORT_GP_22(bank, fn, sfx)   PORT_GP_CFG_22(bank, fn, sfx, 0)
0545 
0546 #define PORT_GP_CFG_23(bank, fn, sfx, cfg)              \
0547     PORT_GP_CFG_22(bank, fn, sfx, cfg),             \
0548     PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
0549 #define PORT_GP_23(bank, fn, sfx)   PORT_GP_CFG_23(bank, fn, sfx, 0)
0550 
0551 #define PORT_GP_CFG_24(bank, fn, sfx, cfg)              \
0552     PORT_GP_CFG_23(bank, fn, sfx, cfg),             \
0553     PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
0554 #define PORT_GP_24(bank, fn, sfx)   PORT_GP_CFG_24(bank, fn, sfx, 0)
0555 
0556 #define PORT_GP_CFG_25(bank, fn, sfx, cfg)              \
0557     PORT_GP_CFG_24(bank, fn, sfx, cfg),             \
0558     PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)
0559 #define PORT_GP_25(bank, fn, sfx)   PORT_GP_CFG_25(bank, fn, sfx, 0)
0560 
0561 #define PORT_GP_CFG_26(bank, fn, sfx, cfg)              \
0562     PORT_GP_CFG_25(bank, fn, sfx, cfg),             \
0563     PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
0564 #define PORT_GP_26(bank, fn, sfx)   PORT_GP_CFG_26(bank, fn, sfx, 0)
0565 
0566 #define PORT_GP_CFG_27(bank, fn, sfx, cfg)              \
0567     PORT_GP_CFG_26(bank, fn, sfx, cfg),             \
0568     PORT_GP_CFG_1(bank, 26, fn, sfx, cfg)
0569 #define PORT_GP_27(bank, fn, sfx)   PORT_GP_CFG_27(bank, fn, sfx, 0)
0570 
0571 #define PORT_GP_CFG_28(bank, fn, sfx, cfg)              \
0572     PORT_GP_CFG_27(bank, fn, sfx, cfg),             \
0573     PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
0574 #define PORT_GP_28(bank, fn, sfx)   PORT_GP_CFG_28(bank, fn, sfx, 0)
0575 
0576 #define PORT_GP_CFG_29(bank, fn, sfx, cfg)              \
0577     PORT_GP_CFG_28(bank, fn, sfx, cfg),             \
0578     PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
0579 #define PORT_GP_29(bank, fn, sfx)   PORT_GP_CFG_29(bank, fn, sfx, 0)
0580 
0581 #define PORT_GP_CFG_30(bank, fn, sfx, cfg)              \
0582     PORT_GP_CFG_29(bank, fn, sfx, cfg),             \
0583     PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
0584 #define PORT_GP_30(bank, fn, sfx)   PORT_GP_CFG_30(bank, fn, sfx, 0)
0585 
0586 #define PORT_GP_CFG_31(bank, fn, sfx, cfg)              \
0587     PORT_GP_CFG_30(bank, fn, sfx, cfg),             \
0588     PORT_GP_CFG_1(bank, 30, fn, sfx, cfg)
0589 #define PORT_GP_31(bank, fn, sfx)   PORT_GP_CFG_31(bank, fn, sfx, 0)
0590 
0591 #define PORT_GP_CFG_32(bank, fn, sfx, cfg)              \
0592     PORT_GP_CFG_31(bank, fn, sfx, cfg),             \
0593     PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
0594 #define PORT_GP_32(bank, fn, sfx)   PORT_GP_CFG_32(bank, fn, sfx, 0)
0595 
0596 #define PORT_GP_32_REV(bank, fn, sfx)                   \
0597     PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
0598     PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
0599     PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
0600     PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
0601     PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
0602     PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
0603     PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
0604     PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
0605     PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
0606     PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
0607     PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
0608     PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx), \
0609     PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx), \
0610     PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx), \
0611     PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx), \
0612     PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)
0613 
0614 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
0615 #define _GP_ALL(bank, pin, name, sfx, cfg)  name##_##sfx
0616 #define GP_ALL(str)         CPU_ALL_GP(_GP_ALL, str)
0617 
0618 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
0619 #define _GP_GPIO(bank, _pin, _name, sfx, cfg) {             \
0620     .pin = (bank * 32) + _pin,                  \
0621     .name = __stringify(_name),                 \
0622     .enum_id = _name##_DATA,                    \
0623     .configs = cfg,                         \
0624 }
0625 #define PINMUX_GPIO_GP_ALL()        CPU_ALL_GP(_GP_GPIO, unused)
0626 
0627 /* PINMUX_DATA_GP_ALL -  Expand to a list of name_DATA, name_FN marks */
0628 #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
0629 #define PINMUX_DATA_GP_ALL()        CPU_ALL_GP(_GP_DATA, unused)
0630 
0631 /*
0632  * GP_ASSIGN_LAST() - Expand to an enum definition for the last GP pin
0633  *
0634  * The largest GP pin index is obtained by taking the size of a union,
0635  * containing one array per GP pin, sized by the corresponding pin index.
0636  * As the fields in the CPU_ALL_GP() macro definition are separated by commas,
0637  * while the members of a union must be terminated by semicolons, the commas
0638  * are absorbed by wrapping them inside dummy attributes.
0639  */
0640 #define _GP_ENTRY(bank, pin, name, sfx, cfg)                \
0641     deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated
0642 #define GP_ASSIGN_LAST()                        \
0643     GP_LAST = sizeof(union {                    \
0644         char dummy[0] __attribute__((deprecated,        \
0645         CPU_ALL_GP(_GP_ENTRY, unused),              \
0646         deprecated));                       \
0647     })
0648 
0649 /*
0650  * PORT style (linear pin space)
0651  */
0652 
0653 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
0654 
0655 #define PORT_10(pn, fn, pfx, sfx)                     \
0656     PORT_1(pn,   fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx),     \
0657     PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx),     \
0658     PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx),     \
0659     PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx),     \
0660     PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
0661 
0662 #define PORT_90(pn, fn, pfx, sfx)                     \
0663     PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
0664     PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
0665     PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
0666     PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
0667     PORT_10(pn+90, fn, pfx##9, sfx)
0668 
0669 /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
0670 #define _PORT_ALL(pn, pfx, sfx)     pfx##_##sfx
0671 #define PORT_ALL(str)           CPU_ALL_PORT(_PORT_ALL, PORT, str)
0672 
0673 /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
0674 #define PINMUX_GPIO(_pin)                       \
0675     [GPIO_##_pin] = {                       \
0676         .pin = (u16)-1,                     \
0677         .name = __stringify(GPIO_##_pin),           \
0678         .enum_id = _pin##_DATA,                 \
0679     }
0680 
0681 /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
0682 #define SH_PFC_PIN_CFG(_pin, cfgs) {                    \
0683     .pin = _pin,                            \
0684     .name = __stringify(PORT##_pin),                \
0685     .enum_id = PORT##_pin##_DATA,                   \
0686     .configs = cfgs,                        \
0687 }
0688 
0689 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
0690  *           PORT_name_OUT, PORT_name_IN marks
0691  */
0692 #define _PORT_DATA(pn, pfx, sfx)                    \
0693     PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0,          \
0694             PORT##pfx##_OUT, PORT##pfx##_IN)
0695 #define PINMUX_DATA_ALL()       CPU_ALL_PORT(_PORT_DATA, , unused)
0696 
0697 /*
0698  * PORT_ASSIGN_LAST() - Expand to an enum definition for the last PORT pin
0699  *
0700  * The largest PORT pin index is obtained by taking the size of a union,
0701  * containing one array per PORT pin, sized by the corresponding pin index.
0702  * As the fields in the CPU_ALL_PORT() macro definition are separated by
0703  * commas, while the members of a union must be terminated by semicolons, the
0704  * commas are absorbed by wrapping them inside dummy attributes.
0705  */
0706 #define _PORT_ENTRY(pn, pfx, sfx)                   \
0707     deprecated)); char pfx[pn] __attribute__((deprecated
0708 #define PORT_ASSIGN_LAST()                      \
0709     PORT_LAST = sizeof(union {                  \
0710         char dummy[0] __attribute__((deprecated,        \
0711         CPU_ALL_PORT(_PORT_ENTRY, PORT, unused),        \
0712         deprecated));                       \
0713     })
0714 
0715 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
0716 #define PINMUX_GPIO_FN(gpio, base, data_or_mark)            \
0717     [gpio - (base)] = {                     \
0718         .name = __stringify(gpio),              \
0719         .enum_id = data_or_mark,                \
0720     }
0721 #define GPIO_FN(str)                            \
0722     PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
0723 
0724 /*
0725  * Pins not associated with a GPIO port
0726  */
0727 
0728 #define PIN_NOGP_CFG(pin, name, fn, cfg)    fn(pin, name, cfg)
0729 #define PIN_NOGP(pin, name, fn)         fn(pin, name, 0)
0730 
0731 /* NOGP_ALL - Expand to a list of PIN_id */
0732 #define _NOGP_ALL(pin, name, cfg)       PIN_##pin
0733 #define NOGP_ALL()              CPU_ALL_NOGP(_NOGP_ALL)
0734 
0735 /* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */
0736 #define _NOGP_PINMUX(_pin, _name, cfg) {                \
0737     .pin = PIN_##_pin,                      \
0738     .name = "PIN_" _name,                       \
0739     .configs = SH_PFC_PIN_CFG_NO_GPIO | cfg,            \
0740 }
0741 #define PINMUX_NOGP_ALL()       CPU_ALL_NOGP(_NOGP_PINMUX)
0742 
0743 /*
0744  * PORTnCR helper macro for SH-Mobile/R-Mobile
0745  */
0746 #define PORTCR(nr, reg) {                       \
0747     PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, GROUP(-2, 2, -1, 3), \
0748                GROUP(                   \
0749         /* PULMD[1:0], handled by .set_bias() */        \
0750         /* IE and OE */                     \
0751         0, PORT##nr##_OUT, PORT##nr##_IN, 0,            \
0752         /* SEC, not supported */                \
0753         /* PTMD[2:0] */                     \
0754         PORT##nr##_FN0, PORT##nr##_FN1,             \
0755         PORT##nr##_FN2, PORT##nr##_FN3,             \
0756         PORT##nr##_FN4, PORT##nr##_FN5,             \
0757         PORT##nr##_FN6, PORT##nr##_FN7              \
0758     ))                              \
0759 }
0760 
0761 /*
0762  * GPIO number helper macro for R-Car
0763  */
0764 #define RCAR_GP_PIN(bank, pin)      (((bank) * 32) + (pin))
0765 
0766 /*
0767  * Bias helpers
0768  */
0769 const struct pinmux_bias_reg *
0770 rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin,
0771              unsigned int *bit);
0772 unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
0773 void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
0774               unsigned int bias);
0775 
0776 unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
0777 void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
0778                  unsigned int bias);
0779 
0780 #endif /* __SH_PFC_H */
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