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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * SuperH Pin Function Controller pinmux support.
0004  *
0005  * Copyright (C) 2012  Paul Mundt
0006  */
0007 
0008 #define DRV_NAME "sh-pfc"
0009 
0010 #include <linux/device.h>
0011 #include <linux/err.h>
0012 #include <linux/io.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/pinctrl/consumer.h>
0016 #include <linux/pinctrl/machine.h>
0017 #include <linux/pinctrl/pinconf.h>
0018 #include <linux/pinctrl/pinconf-generic.h>
0019 #include <linux/pinctrl/pinctrl.h>
0020 #include <linux/pinctrl/pinmux.h>
0021 #include <linux/slab.h>
0022 #include <linux/spinlock.h>
0023 
0024 #include "core.h"
0025 #include "../core.h"
0026 #include "../pinconf.h"
0027 
0028 struct sh_pfc_pin_config {
0029     u16 gpio_enabled:1;
0030     u16 mux_mark:15;
0031 };
0032 
0033 struct sh_pfc_pinctrl {
0034     struct pinctrl_dev *pctl;
0035     struct pinctrl_desc pctl_desc;
0036 
0037     struct sh_pfc *pfc;
0038 
0039     struct pinctrl_pin_desc *pins;
0040     struct sh_pfc_pin_config *configs;
0041 
0042     const char *func_prop_name;
0043     const char *groups_prop_name;
0044     const char *pins_prop_name;
0045 };
0046 
0047 static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
0048 {
0049     struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
0050 
0051     return pmx->pfc->info->nr_groups;
0052 }
0053 
0054 static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
0055                      unsigned selector)
0056 {
0057     struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
0058 
0059     return pmx->pfc->info->groups[selector].name;
0060 }
0061 
0062 static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
0063                  const unsigned **pins, unsigned *num_pins)
0064 {
0065     struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
0066 
0067     *pins = pmx->pfc->info->groups[selector].pins;
0068     *num_pins = pmx->pfc->info->groups[selector].nr_pins;
0069 
0070     return 0;
0071 }
0072 
0073 static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
0074                 unsigned offset)
0075 {
0076     seq_puts(s, DRV_NAME);
0077 }
0078 
0079 #ifdef CONFIG_OF
0080 static int sh_pfc_map_add_config(struct pinctrl_map *map,
0081                  const char *group_or_pin,
0082                  enum pinctrl_map_type type,
0083                  unsigned long *configs,
0084                  unsigned int num_configs)
0085 {
0086     unsigned long *cfgs;
0087 
0088     cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
0089                GFP_KERNEL);
0090     if (cfgs == NULL)
0091         return -ENOMEM;
0092 
0093     map->type = type;
0094     map->data.configs.group_or_pin = group_or_pin;
0095     map->data.configs.configs = cfgs;
0096     map->data.configs.num_configs = num_configs;
0097 
0098     return 0;
0099 }
0100 
0101 static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev,
0102                     struct device_node *np,
0103                     struct pinctrl_map **map,
0104                     unsigned int *num_maps, unsigned int *index)
0105 {
0106     struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
0107     struct device *dev = pmx->pfc->dev;
0108     struct pinctrl_map *maps = *map;
0109     unsigned int nmaps = *num_maps;
0110     unsigned int idx = *index;
0111     unsigned int num_configs;
0112     const char *function = NULL;
0113     unsigned long *configs;
0114     struct property *prop;
0115     unsigned int num_groups;
0116     unsigned int num_pins;
0117     const char *group;
0118     const char *pin;
0119     int ret;
0120 
0121     /* Support both the old Renesas-specific properties and the new standard
0122      * properties. Mixing old and new properties isn't allowed, neither
0123      * inside a subnode nor across subnodes.
0124      */
0125     if (!pmx->func_prop_name) {
0126         if (of_find_property(np, "groups", NULL) ||
0127             of_find_property(np, "pins", NULL)) {
0128             pmx->func_prop_name = "function";
0129             pmx->groups_prop_name = "groups";
0130             pmx->pins_prop_name = "pins";
0131         } else {
0132             pmx->func_prop_name = "renesas,function";
0133             pmx->groups_prop_name = "renesas,groups";
0134             pmx->pins_prop_name = "renesas,pins";
0135         }
0136     }
0137 
0138     /* Parse the function and configuration properties. At least a function
0139      * or one configuration must be specified.
0140      */
0141     ret = of_property_read_string(np, pmx->func_prop_name, &function);
0142     if (ret < 0 && ret != -EINVAL) {
0143         dev_err(dev, "Invalid function in DT\n");
0144         return ret;
0145     }
0146 
0147     ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
0148     if (ret < 0)
0149         return ret;
0150 
0151     if (!function && num_configs == 0) {
0152         dev_err(dev,
0153             "DT node must contain at least a function or config\n");
0154         ret = -ENODEV;
0155         goto done;
0156     }
0157 
0158     /* Count the number of pins and groups and reallocate mappings. */
0159     ret = of_property_count_strings(np, pmx->pins_prop_name);
0160     if (ret == -EINVAL) {
0161         num_pins = 0;
0162     } else if (ret < 0) {
0163         dev_err(dev, "Invalid pins list in DT\n");
0164         goto done;
0165     } else {
0166         num_pins = ret;
0167     }
0168 
0169     ret = of_property_count_strings(np, pmx->groups_prop_name);
0170     if (ret == -EINVAL) {
0171         num_groups = 0;
0172     } else if (ret < 0) {
0173         dev_err(dev, "Invalid pin groups list in DT\n");
0174         goto done;
0175     } else {
0176         num_groups = ret;
0177     }
0178 
0179     if (!num_pins && !num_groups) {
0180         dev_err(dev, "No pin or group provided in DT node\n");
0181         ret = -ENODEV;
0182         goto done;
0183     }
0184 
0185     if (function)
0186         nmaps += num_groups;
0187     if (configs)
0188         nmaps += num_pins + num_groups;
0189 
0190     maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL);
0191     if (maps == NULL) {
0192         ret = -ENOMEM;
0193         goto done;
0194     }
0195 
0196     *map = maps;
0197     *num_maps = nmaps;
0198 
0199     /* Iterate over pins and groups and create the mappings. */
0200     of_property_for_each_string(np, pmx->groups_prop_name, prop, group) {
0201         if (function) {
0202             maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
0203             maps[idx].data.mux.group = group;
0204             maps[idx].data.mux.function = function;
0205             idx++;
0206         }
0207 
0208         if (configs) {
0209             ret = sh_pfc_map_add_config(&maps[idx], group,
0210                             PIN_MAP_TYPE_CONFIGS_GROUP,
0211                             configs, num_configs);
0212             if (ret < 0)
0213                 goto done;
0214 
0215             idx++;
0216         }
0217     }
0218 
0219     if (!configs) {
0220         ret = 0;
0221         goto done;
0222     }
0223 
0224     of_property_for_each_string(np, pmx->pins_prop_name, prop, pin) {
0225         ret = sh_pfc_map_add_config(&maps[idx], pin,
0226                         PIN_MAP_TYPE_CONFIGS_PIN,
0227                         configs, num_configs);
0228         if (ret < 0)
0229             goto done;
0230 
0231         idx++;
0232     }
0233 
0234 done:
0235     *index = idx;
0236     kfree(configs);
0237     return ret;
0238 }
0239 
0240 static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev,
0241                    struct pinctrl_map *map, unsigned num_maps)
0242 {
0243     unsigned int i;
0244 
0245     if (map == NULL)
0246         return;
0247 
0248     for (i = 0; i < num_maps; ++i) {
0249         if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
0250             map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
0251             kfree(map[i].data.configs.configs);
0252     }
0253 
0254     kfree(map);
0255 }
0256 
0257 static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
0258                  struct device_node *np,
0259                  struct pinctrl_map **map, unsigned *num_maps)
0260 {
0261     struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
0262     struct device *dev = pmx->pfc->dev;
0263     struct device_node *child;
0264     unsigned int index;
0265     int ret;
0266 
0267     *map = NULL;
0268     *num_maps = 0;
0269     index = 0;
0270 
0271     for_each_child_of_node(np, child) {
0272         ret = sh_pfc_dt_subnode_to_map(pctldev, child, map, num_maps,
0273                            &index);
0274         if (ret < 0) {
0275             of_node_put(child);
0276             goto done;
0277         }
0278     }
0279 
0280     /* If no mapping has been found in child nodes try the config node. */
0281     if (*num_maps == 0) {
0282         ret = sh_pfc_dt_subnode_to_map(pctldev, np, map, num_maps,
0283                            &index);
0284         if (ret < 0)
0285             goto done;
0286     }
0287 
0288     if (*num_maps)
0289         return 0;
0290 
0291     dev_err(dev, "no mapping found in node %pOF\n", np);
0292     ret = -EINVAL;
0293 
0294 done:
0295     if (ret < 0)
0296         sh_pfc_dt_free_map(pctldev, *map, *num_maps);
0297 
0298     return ret;
0299 }
0300 #endif /* CONFIG_OF */
0301 
0302 static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
0303     .get_groups_count   = sh_pfc_get_groups_count,
0304     .get_group_name     = sh_pfc_get_group_name,
0305     .get_group_pins     = sh_pfc_get_group_pins,
0306     .pin_dbg_show       = sh_pfc_pin_dbg_show,
0307 #ifdef CONFIG_OF
0308     .dt_node_to_map     = sh_pfc_dt_node_to_map,
0309     .dt_free_map        = sh_pfc_dt_free_map,
0310 #endif
0311 };
0312 
0313 static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
0314 {
0315     struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
0316 
0317     return pmx->pfc->info->nr_functions;
0318 }
0319 
0320 static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
0321                         unsigned selector)
0322 {
0323     struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
0324 
0325     return pmx->pfc->info->functions[selector].name;
0326 }
0327 
0328 static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
0329                       unsigned selector,
0330                       const char * const **groups,
0331                       unsigned * const num_groups)
0332 {
0333     struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
0334 
0335     *groups = pmx->pfc->info->functions[selector].groups;
0336     *num_groups = pmx->pfc->info->functions[selector].nr_groups;
0337 
0338     return 0;
0339 }
0340 
0341 static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
0342                    unsigned group)
0343 {
0344     struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
0345     struct sh_pfc *pfc = pmx->pfc;
0346     const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
0347     unsigned long flags;
0348     unsigned int i;
0349     int ret = 0;
0350 
0351     dev_dbg(pctldev->dev, "Configuring pin group %s\n", grp->name);
0352 
0353     spin_lock_irqsave(&pfc->lock, flags);
0354 
0355     for (i = 0; i < grp->nr_pins; ++i) {
0356         int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
0357         struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
0358 
0359         /*
0360          * This driver cannot manage both gpio and mux when the gpio
0361          * pin is already enabled. So, this function fails.
0362          */
0363         if (cfg->gpio_enabled) {
0364             ret = -EBUSY;
0365             goto done;
0366         }
0367 
0368         ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
0369         if (ret < 0)
0370             goto done;
0371     }
0372 
0373     /* All group pins are configured, mark the pins as muxed */
0374     for (i = 0; i < grp->nr_pins; ++i) {
0375         int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
0376         struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
0377 
0378         cfg->mux_mark = grp->mux[i];
0379     }
0380 
0381 done:
0382     spin_unlock_irqrestore(&pfc->lock, flags);
0383     return ret;
0384 }
0385 
0386 static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
0387                       struct pinctrl_gpio_range *range,
0388                       unsigned offset)
0389 {
0390     struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
0391     struct sh_pfc *pfc = pmx->pfc;
0392     int idx = sh_pfc_get_pin_index(pfc, offset);
0393     struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
0394     unsigned long flags;
0395     int ret;
0396 
0397     spin_lock_irqsave(&pfc->lock, flags);
0398 
0399     if (!pfc->gpio && !cfg->mux_mark) {
0400         /* If GPIOs are handled externally the pin mux type needs to be
0401          * set to GPIO here.
0402          */
0403         const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
0404 
0405         ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
0406         if (ret < 0)
0407             goto done;
0408     }
0409 
0410     cfg->gpio_enabled = true;
0411 
0412     ret = 0;
0413 
0414 done:
0415     spin_unlock_irqrestore(&pfc->lock, flags);
0416 
0417     return ret;
0418 }
0419 
0420 static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
0421                      struct pinctrl_gpio_range *range,
0422                      unsigned offset)
0423 {
0424     struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
0425     struct sh_pfc *pfc = pmx->pfc;
0426     int idx = sh_pfc_get_pin_index(pfc, offset);
0427     struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
0428     unsigned long flags;
0429 
0430     spin_lock_irqsave(&pfc->lock, flags);
0431     cfg->gpio_enabled = false;
0432     /* If mux is already set, this configures it here */
0433     if (cfg->mux_mark)
0434         sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION);
0435     spin_unlock_irqrestore(&pfc->lock, flags);
0436 }
0437 
0438 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
0439 static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
0440                      struct pinctrl_gpio_range *range,
0441                      unsigned offset, bool input)
0442 {
0443     struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
0444     struct sh_pfc *pfc = pmx->pfc;
0445     int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
0446     int idx = sh_pfc_get_pin_index(pfc, offset);
0447     const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
0448     unsigned long flags;
0449     unsigned int dir;
0450     int ret;
0451 
0452     /* Check if the requested direction is supported by the pin. Not all
0453      * SoCs provide pin config data, so perform the check conditionally.
0454      */
0455     if (pin->configs) {
0456         dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT;
0457         if (!(pin->configs & dir))
0458             return -EINVAL;
0459     }
0460 
0461     spin_lock_irqsave(&pfc->lock, flags);
0462     ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
0463     spin_unlock_irqrestore(&pfc->lock, flags);
0464     return ret;
0465 }
0466 #else
0467 #define sh_pfc_gpio_set_direction   NULL
0468 #endif
0469 
0470 static const struct pinmux_ops sh_pfc_pinmux_ops = {
0471     .get_functions_count    = sh_pfc_get_functions_count,
0472     .get_function_name  = sh_pfc_get_function_name,
0473     .get_function_groups    = sh_pfc_get_function_groups,
0474     .set_mux        = sh_pfc_func_set_mux,
0475     .gpio_request_enable    = sh_pfc_gpio_request_enable,
0476     .gpio_disable_free  = sh_pfc_gpio_disable_free,
0477     .gpio_set_direction = sh_pfc_gpio_set_direction,
0478 };
0479 
0480 static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc,
0481         unsigned int pin, unsigned int *offset, unsigned int *size)
0482 {
0483     const struct pinmux_drive_reg_field *field;
0484     const struct pinmux_drive_reg *reg;
0485     unsigned int i;
0486 
0487     for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
0488         for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
0489             field = &reg->fields[i];
0490 
0491             if (field->size && field->pin == pin) {
0492                 *offset = field->offset;
0493                 *size = field->size;
0494 
0495                 return reg->reg;
0496             }
0497         }
0498     }
0499 
0500     return 0;
0501 }
0502 
0503 static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc,
0504                          unsigned int pin)
0505 {
0506     unsigned int offset;
0507     unsigned int size;
0508     u32 reg;
0509     u32 val;
0510 
0511     reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
0512     if (!reg)
0513         return -EINVAL;
0514 
0515     val = (sh_pfc_read(pfc, reg) >> offset) & GENMASK(size - 1, 0);
0516 
0517     /* Convert the value to mA based on a full drive strength value of 24mA.
0518      * We can make the full value configurable later if needed.
0519      */
0520     return (val + 1) * (size == 2 ? 6 : 3);
0521 }
0522 
0523 static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
0524                          unsigned int pin, u16 strength)
0525 {
0526     unsigned long flags;
0527     unsigned int offset;
0528     unsigned int size;
0529     unsigned int step;
0530     u32 reg;
0531     u32 val;
0532 
0533     reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
0534     if (!reg)
0535         return -EINVAL;
0536 
0537     step = size == 2 ? 6 : 3;
0538 
0539     if (strength < step || strength > 24)
0540         return -EINVAL;
0541 
0542     /* Convert the value from mA based on a full drive strength value of
0543      * 24mA. We can make the full value configurable later if needed.
0544      */
0545     strength = strength / step - 1;
0546 
0547     spin_lock_irqsave(&pfc->lock, flags);
0548 
0549     val = sh_pfc_read(pfc, reg);
0550     val &= ~GENMASK(offset + size - 1, offset);
0551     val |= strength << offset;
0552 
0553     sh_pfc_write(pfc, reg, val);
0554 
0555     spin_unlock_irqrestore(&pfc->lock, flags);
0556 
0557     return 0;
0558 }
0559 
0560 /* Check whether the requested parameter is supported for a pin. */
0561 static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
0562                     enum pin_config_param param)
0563 {
0564     int idx = sh_pfc_get_pin_index(pfc, _pin);
0565     const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
0566 
0567     switch (param) {
0568     case PIN_CONFIG_BIAS_DISABLE:
0569         return pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN;
0570 
0571     case PIN_CONFIG_BIAS_PULL_UP:
0572         return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
0573 
0574     case PIN_CONFIG_BIAS_PULL_DOWN:
0575         return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
0576 
0577     case PIN_CONFIG_DRIVE_STRENGTH:
0578         return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
0579 
0580     case PIN_CONFIG_POWER_SOURCE:
0581         return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
0582 
0583     default:
0584         return false;
0585     }
0586 }
0587 
0588 static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
0589                   unsigned long *config)
0590 {
0591     struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
0592     struct sh_pfc *pfc = pmx->pfc;
0593     enum pin_config_param param = pinconf_to_config_param(*config);
0594     unsigned long flags;
0595     unsigned int arg;
0596 
0597     if (!sh_pfc_pinconf_validate(pfc, _pin, param))
0598         return -ENOTSUPP;
0599 
0600     switch (param) {
0601     case PIN_CONFIG_BIAS_DISABLE:
0602     case PIN_CONFIG_BIAS_PULL_UP:
0603     case PIN_CONFIG_BIAS_PULL_DOWN: {
0604         unsigned int bias;
0605 
0606         if (!pfc->info->ops || !pfc->info->ops->get_bias)
0607             return -ENOTSUPP;
0608 
0609         spin_lock_irqsave(&pfc->lock, flags);
0610         bias = pfc->info->ops->get_bias(pfc, _pin);
0611         spin_unlock_irqrestore(&pfc->lock, flags);
0612 
0613         if (bias != param)
0614             return -EINVAL;
0615 
0616         arg = 0;
0617         break;
0618     }
0619 
0620     case PIN_CONFIG_DRIVE_STRENGTH: {
0621         int ret;
0622 
0623         ret = sh_pfc_pinconf_get_drive_strength(pfc, _pin);
0624         if (ret < 0)
0625             return ret;
0626 
0627         arg = ret;
0628         break;
0629     }
0630 
0631     case PIN_CONFIG_POWER_SOURCE: {
0632         int idx = sh_pfc_get_pin_index(pfc, _pin);
0633         const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
0634         unsigned int lower_voltage;
0635         u32 pocctrl, val;
0636         int bit;
0637 
0638         if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
0639             return -ENOTSUPP;
0640 
0641         bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl);
0642         if (WARN(bit < 0, "invalid pin %#x", _pin))
0643             return bit;
0644 
0645         val = sh_pfc_read(pfc, pocctrl);
0646 
0647         lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
0648             2500 : 1800;
0649 
0650         arg = (val & BIT(bit)) ? 3300 : lower_voltage;
0651         break;
0652     }
0653 
0654     default:
0655         return -ENOTSUPP;
0656     }
0657 
0658     *config = pinconf_to_config_packed(param, arg);
0659     return 0;
0660 }
0661 
0662 static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
0663                   unsigned long *configs, unsigned num_configs)
0664 {
0665     struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
0666     struct sh_pfc *pfc = pmx->pfc;
0667     enum pin_config_param param;
0668     unsigned long flags;
0669     unsigned int i;
0670 
0671     for (i = 0; i < num_configs; i++) {
0672         param = pinconf_to_config_param(configs[i]);
0673 
0674         if (!sh_pfc_pinconf_validate(pfc, _pin, param))
0675             return -ENOTSUPP;
0676 
0677         switch (param) {
0678         case PIN_CONFIG_BIAS_PULL_UP:
0679         case PIN_CONFIG_BIAS_PULL_DOWN:
0680         case PIN_CONFIG_BIAS_DISABLE:
0681             if (!pfc->info->ops || !pfc->info->ops->set_bias)
0682                 return -ENOTSUPP;
0683 
0684             spin_lock_irqsave(&pfc->lock, flags);
0685             pfc->info->ops->set_bias(pfc, _pin, param);
0686             spin_unlock_irqrestore(&pfc->lock, flags);
0687 
0688             break;
0689 
0690         case PIN_CONFIG_DRIVE_STRENGTH: {
0691             unsigned int arg =
0692                 pinconf_to_config_argument(configs[i]);
0693             int ret;
0694 
0695             ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
0696             if (ret < 0)
0697                 return ret;
0698 
0699             break;
0700         }
0701 
0702         case PIN_CONFIG_POWER_SOURCE: {
0703             unsigned int mV = pinconf_to_config_argument(configs[i]);
0704             int idx = sh_pfc_get_pin_index(pfc, _pin);
0705             const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
0706             unsigned int lower_voltage;
0707             u32 pocctrl, val;
0708             int bit;
0709 
0710             if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
0711                 return -ENOTSUPP;
0712 
0713             bit = pfc->info->ops->pin_to_pocctrl(_pin, &pocctrl);
0714             if (WARN(bit < 0, "invalid pin %#x", _pin))
0715                 return bit;
0716 
0717             lower_voltage = (pin->configs & SH_PFC_PIN_VOLTAGE_25_33) ?
0718                 2500 : 1800;
0719 
0720             if (mV != lower_voltage && mV != 3300)
0721                 return -EINVAL;
0722 
0723             spin_lock_irqsave(&pfc->lock, flags);
0724             val = sh_pfc_read(pfc, pocctrl);
0725             if (mV == 3300)
0726                 val |= BIT(bit);
0727             else
0728                 val &= ~BIT(bit);
0729             sh_pfc_write(pfc, pocctrl, val);
0730             spin_unlock_irqrestore(&pfc->lock, flags);
0731 
0732             break;
0733         }
0734 
0735         default:
0736             return -ENOTSUPP;
0737         }
0738     } /* for each config */
0739 
0740     return 0;
0741 }
0742 
0743 static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
0744                     unsigned long *configs,
0745                     unsigned num_configs)
0746 {
0747     struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
0748     const unsigned int *pins;
0749     unsigned int num_pins;
0750     unsigned int i, ret;
0751 
0752     pins = pmx->pfc->info->groups[group].pins;
0753     num_pins = pmx->pfc->info->groups[group].nr_pins;
0754 
0755     for (i = 0; i < num_pins; ++i) {
0756         ret = sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs);
0757         if (ret)
0758             return ret;
0759     }
0760 
0761     return 0;
0762 }
0763 
0764 static const struct pinconf_ops sh_pfc_pinconf_ops = {
0765     .is_generic         = true,
0766     .pin_config_get         = sh_pfc_pinconf_get,
0767     .pin_config_set         = sh_pfc_pinconf_set,
0768     .pin_config_group_set       = sh_pfc_pinconf_group_set,
0769     .pin_config_config_dbg_show = pinconf_generic_dump_config,
0770 };
0771 
0772 /* PFC ranges -> pinctrl pin descs */
0773 static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
0774 {
0775     unsigned int i;
0776 
0777     /* Allocate and initialize the pins and configs arrays. */
0778     pmx->pins = devm_kcalloc(pfc->dev,
0779                  pfc->info->nr_pins, sizeof(*pmx->pins),
0780                  GFP_KERNEL);
0781     if (unlikely(!pmx->pins))
0782         return -ENOMEM;
0783 
0784     pmx->configs = devm_kcalloc(pfc->dev,
0785                     pfc->info->nr_pins, sizeof(*pmx->configs),
0786                     GFP_KERNEL);
0787     if (unlikely(!pmx->configs))
0788         return -ENOMEM;
0789 
0790     for (i = 0; i < pfc->info->nr_pins; ++i) {
0791         const struct sh_pfc_pin *info = &pfc->info->pins[i];
0792         struct pinctrl_pin_desc *pin = &pmx->pins[i];
0793 
0794         /* If the pin number is equal to -1 all pins are considered */
0795         pin->number = info->pin != (u16)-1 ? info->pin : i;
0796         pin->name = info->name;
0797     }
0798 
0799     return 0;
0800 }
0801 
0802 int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
0803 {
0804     struct sh_pfc_pinctrl *pmx;
0805     int ret;
0806 
0807     pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
0808     if (unlikely(!pmx))
0809         return -ENOMEM;
0810 
0811     pmx->pfc = pfc;
0812 
0813     ret = sh_pfc_map_pins(pfc, pmx);
0814     if (ret < 0)
0815         return ret;
0816 
0817     pmx->pctl_desc.name = DRV_NAME;
0818     pmx->pctl_desc.owner = THIS_MODULE;
0819     pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
0820     pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
0821     pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
0822     pmx->pctl_desc.pins = pmx->pins;
0823     pmx->pctl_desc.npins = pfc->info->nr_pins;
0824 
0825     ret = devm_pinctrl_register_and_init(pfc->dev, &pmx->pctl_desc, pmx,
0826                          &pmx->pctl);
0827     if (ret) {
0828         dev_err(pfc->dev, "could not register: %i\n", ret);
0829 
0830         return ret;
0831     }
0832 
0833     return pinctrl_enable(pmx->pctl);
0834 }
0835 
0836 const struct pinmux_bias_reg *
0837 rcar_pin_to_bias_reg(const struct sh_pfc_soc_info *info, unsigned int pin,
0838              unsigned int *bit)
0839 {
0840     unsigned int i, j;
0841 
0842     for (i = 0; info->bias_regs[i].puen || info->bias_regs[i].pud; i++) {
0843         for (j = 0; j < ARRAY_SIZE(info->bias_regs[i].pins); j++) {
0844             if (info->bias_regs[i].pins[j] == pin) {
0845                 *bit = j;
0846                 return &info->bias_regs[i];
0847             }
0848         }
0849     }
0850 
0851     WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
0852 
0853     return NULL;
0854 }
0855 
0856 unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
0857 {
0858     const struct pinmux_bias_reg *reg;
0859     unsigned int bit;
0860 
0861     reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);
0862     if (!reg)
0863         return PIN_CONFIG_BIAS_DISABLE;
0864 
0865     if (reg->puen) {
0866         if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
0867             return PIN_CONFIG_BIAS_DISABLE;
0868         else if (!reg->pud || (sh_pfc_read(pfc, reg->pud) & BIT(bit)))
0869             return PIN_CONFIG_BIAS_PULL_UP;
0870         else
0871             return PIN_CONFIG_BIAS_PULL_DOWN;
0872     } else {
0873         if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
0874             return PIN_CONFIG_BIAS_PULL_DOWN;
0875         else
0876             return PIN_CONFIG_BIAS_DISABLE;
0877     }
0878 }
0879 
0880 void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
0881               unsigned int bias)
0882 {
0883     const struct pinmux_bias_reg *reg;
0884     u32 enable, updown;
0885     unsigned int bit;
0886 
0887     reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);
0888     if (!reg)
0889         return;
0890 
0891     if (reg->puen) {
0892         enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
0893         if (bias != PIN_CONFIG_BIAS_DISABLE) {
0894             enable |= BIT(bit);
0895 
0896             if (reg->pud) {
0897                 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
0898                 if (bias == PIN_CONFIG_BIAS_PULL_UP)
0899                     updown |= BIT(bit);
0900 
0901                 sh_pfc_write(pfc, reg->pud, updown);
0902             }
0903         }
0904         sh_pfc_write(pfc, reg->puen, enable);
0905     } else {
0906         enable = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
0907         if (bias == PIN_CONFIG_BIAS_PULL_DOWN)
0908             enable |= BIT(bit);
0909 
0910         sh_pfc_write(pfc, reg->pud, enable);
0911     }
0912 }
0913 
0914 #define PORTnCR_PULMD_OFF   (0 << 6)
0915 #define PORTnCR_PULMD_DOWN  (2 << 6)
0916 #define PORTnCR_PULMD_UP    (3 << 6)
0917 #define PORTnCR_PULMD_MASK  (3 << 6)
0918 
0919 unsigned int rmobile_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
0920 {
0921     void __iomem *reg = pfc->windows->virt +
0922                 pfc->info->ops->pin_to_portcr(pin);
0923     u32 value = ioread8(reg) & PORTnCR_PULMD_MASK;
0924 
0925     switch (value) {
0926     case PORTnCR_PULMD_UP:
0927         return PIN_CONFIG_BIAS_PULL_UP;
0928     case PORTnCR_PULMD_DOWN:
0929         return PIN_CONFIG_BIAS_PULL_DOWN;
0930     case PORTnCR_PULMD_OFF:
0931     default:
0932         return PIN_CONFIG_BIAS_DISABLE;
0933     }
0934 }
0935 
0936 void rmobile_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
0937                  unsigned int bias)
0938 {
0939     void __iomem *reg = pfc->windows->virt +
0940                 pfc->info->ops->pin_to_portcr(pin);
0941     u32 value = ioread8(reg) & ~PORTnCR_PULMD_MASK;
0942 
0943     switch (bias) {
0944     case PIN_CONFIG_BIAS_PULL_UP:
0945         value |= PORTnCR_PULMD_UP;
0946         break;
0947     case PIN_CONFIG_BIAS_PULL_DOWN:
0948         value |= PORTnCR_PULMD_DOWN;
0949         break;
0950     }
0951 
0952     iowrite8(value, reg);
0953 }
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