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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Renesas RZ/V2M Pin Control and GPIO driver core
0004  *
0005  * Based on:
0006  *   Renesas RZ/G2L Pin Control and GPIO driver core
0007  *
0008  * Copyright (C) 2022 Renesas Electronics Corporation.
0009  */
0010 
0011 #include <linux/bitfield.h>
0012 #include <linux/bitops.h>
0013 #include <linux/clk.h>
0014 #include <linux/gpio/driver.h>
0015 #include <linux/io.h>
0016 #include <linux/module.h>
0017 #include <linux/of_device.h>
0018 #include <linux/pinctrl/pinconf-generic.h>
0019 #include <linux/pinctrl/pinconf.h>
0020 #include <linux/pinctrl/pinctrl.h>
0021 #include <linux/pinctrl/pinmux.h>
0022 #include <linux/spinlock.h>
0023 
0024 #include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
0025 
0026 #include "../core.h"
0027 #include "../pinconf.h"
0028 #include "../pinmux.h"
0029 
0030 #define DRV_NAME    "pinctrl-rzv2m"
0031 
0032 /*
0033  * Use 16 lower bits [15:0] for pin identifier
0034  * Use 16 higher bits [31:16] for pin mux function
0035  */
0036 #define MUX_PIN_ID_MASK     GENMASK(15, 0)
0037 #define MUX_FUNC_MASK       GENMASK(31, 16)
0038 #define MUX_FUNC(pinconf)   FIELD_GET(MUX_FUNC_MASK, (pinconf))
0039 
0040 /* PIN capabilities */
0041 #define PIN_CFG_GRP_1_8V_2      1
0042 #define PIN_CFG_GRP_1_8V_3      2
0043 #define PIN_CFG_GRP_SWIO_1      3
0044 #define PIN_CFG_GRP_SWIO_2      4
0045 #define PIN_CFG_GRP_3_3V        5
0046 #define PIN_CFG_GRP_MASK        GENMASK(2, 0)
0047 #define PIN_CFG_BIAS            BIT(3)
0048 #define PIN_CFG_DRV         BIT(4)
0049 #define PIN_CFG_SLEW            BIT(5)
0050 
0051 #define RZV2M_MPXED_PIN_FUNCS       (PIN_CFG_BIAS | \
0052                      PIN_CFG_DRV | \
0053                      PIN_CFG_SLEW)
0054 
0055 /*
0056  * n indicates number of pins in the port, a is the register index
0057  * and f is pin configuration capabilities supported.
0058  */
0059 #define RZV2M_GPIO_PORT_PACK(n, a, f)   (((n) << 24) | ((a) << 16) | (f))
0060 #define RZV2M_GPIO_PORT_GET_PINCNT(x)   FIELD_GET(GENMASK(31, 24), (x))
0061 #define RZV2M_GPIO_PORT_GET_INDEX(x)    FIELD_GET(GENMASK(23, 16), (x))
0062 #define RZV2M_GPIO_PORT_GET_CFGS(x) FIELD_GET(GENMASK(15, 0), (x))
0063 
0064 #define RZV2M_DEDICATED_PORT_IDX    22
0065 
0066 /*
0067  * BIT(31) indicates dedicated pin, b is the register bits (b * 16)
0068  * and f is the pin configuration capabilities supported.
0069  */
0070 #define RZV2M_SINGLE_PIN        BIT(31)
0071 #define RZV2M_SINGLE_PIN_PACK(b, f) (RZV2M_SINGLE_PIN | \
0072                      ((RZV2M_DEDICATED_PORT_IDX) << 24) | \
0073                      ((b) << 16) | (f))
0074 #define RZV2M_SINGLE_PIN_GET_PORT(x)    FIELD_GET(GENMASK(30, 24), (x))
0075 #define RZV2M_SINGLE_PIN_GET_BIT(x) FIELD_GET(GENMASK(23, 16), (x))
0076 #define RZV2M_SINGLE_PIN_GET_CFGS(x)    FIELD_GET(GENMASK(15, 0), (x))
0077 
0078 #define RZV2M_PIN_ID_TO_PORT(id)    ((id) / RZV2M_PINS_PER_PORT)
0079 #define RZV2M_PIN_ID_TO_PIN(id)     ((id) % RZV2M_PINS_PER_PORT)
0080 
0081 #define DO(n)       (0x00 + (n) * 0x40)
0082 #define OE(n)       (0x04 + (n) * 0x40)
0083 #define IE(n)       (0x08 + (n) * 0x40)
0084 #define PFSEL(n)    (0x10 + (n) * 0x40)
0085 #define DI(n)       (0x20 + (n) * 0x40)
0086 #define PUPD(n)     (0x24 + (n) * 0x40)
0087 #define DRV(n)      ((n) < RZV2M_DEDICATED_PORT_IDX ? (0x28 + (n) * 0x40) \
0088                             : 0x590)
0089 #define SR(n)       ((n) < RZV2M_DEDICATED_PORT_IDX ? (0x2c + (n) * 0x40) \
0090                             : 0x594)
0091 #define DI_MSK(n)   (0x30 + (n) * 0x40)
0092 #define EN_MSK(n)   (0x34 + (n) * 0x40)
0093 
0094 #define PFC_MASK    0x07
0095 #define PUPD_MASK   0x03
0096 #define DRV_MASK    0x03
0097 
0098 struct rzv2m_dedicated_configs {
0099     const char *name;
0100     u32 config;
0101 };
0102 
0103 struct rzv2m_pinctrl_data {
0104     const char * const *port_pins;
0105     const u32 *port_pin_configs;
0106     const struct rzv2m_dedicated_configs *dedicated_pins;
0107     unsigned int n_port_pins;
0108     unsigned int n_dedicated_pins;
0109 };
0110 
0111 struct rzv2m_pinctrl {
0112     struct pinctrl_dev      *pctl;
0113     struct pinctrl_desc     desc;
0114     struct pinctrl_pin_desc     *pins;
0115 
0116     const struct rzv2m_pinctrl_data *data;
0117     void __iomem            *base;
0118     struct device           *dev;
0119     struct clk          *clk;
0120 
0121     struct gpio_chip        gpio_chip;
0122     struct pinctrl_gpio_range   gpio_range;
0123 
0124     spinlock_t          lock;
0125 };
0126 
0127 static const unsigned int drv_1_8V_group2_uA[] = { 1800, 3800, 7800, 11000 };
0128 static const unsigned int drv_1_8V_group3_uA[] = { 1600, 3200, 6400, 9600 };
0129 static const unsigned int drv_SWIO_group2_3_3V_uA[] = { 9000, 11000, 13000, 18000 };
0130 static const unsigned int drv_3_3V_group_uA[] = { 2000, 4000, 8000, 12000 };
0131 
0132 /* Helper for registers that have a write enable bit in the upper word */
0133 static void rzv2m_writel_we(void __iomem *addr, u8 shift, u8 value)
0134 {
0135     writel((BIT(16) | value) << shift, addr);
0136 }
0137 
0138 static void rzv2m_pinctrl_set_pfc_mode(struct rzv2m_pinctrl *pctrl,
0139                        u8 port, u8 pin, u8 func)
0140 {
0141     void __iomem *addr;
0142 
0143     /* Mask input/output */
0144     rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 1);
0145     rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 1);
0146 
0147     /* Select the function and set the write enable bits */
0148     addr = pctrl->base + PFSEL(port) + (pin / 4) * 4;
0149     writel(((PFC_MASK << 16) | func) << ((pin % 4) * 4), addr);
0150 
0151     /* Unmask input/output */
0152     rzv2m_writel_we(pctrl->base + EN_MSK(port), pin, 0);
0153     rzv2m_writel_we(pctrl->base + DI_MSK(port), pin, 0);
0154 };
0155 
0156 static int rzv2m_pinctrl_set_mux(struct pinctrl_dev *pctldev,
0157                  unsigned int func_selector,
0158                  unsigned int group_selector)
0159 {
0160     struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0161     struct function_desc *func;
0162     unsigned int i, *psel_val;
0163     struct group_desc *group;
0164     int *pins;
0165 
0166     func = pinmux_generic_get_function(pctldev, func_selector);
0167     if (!func)
0168         return -EINVAL;
0169     group = pinctrl_generic_get_group(pctldev, group_selector);
0170     if (!group)
0171         return -EINVAL;
0172 
0173     psel_val = func->data;
0174     pins = group->pins;
0175 
0176     for (i = 0; i < group->num_pins; i++) {
0177         dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n",
0178             RZV2M_PIN_ID_TO_PORT(pins[i]), RZV2M_PIN_ID_TO_PIN(pins[i]),
0179             psel_val[i]);
0180         rzv2m_pinctrl_set_pfc_mode(pctrl, RZV2M_PIN_ID_TO_PORT(pins[i]),
0181                        RZV2M_PIN_ID_TO_PIN(pins[i]), psel_val[i]);
0182     }
0183 
0184     return 0;
0185 };
0186 
0187 static int rzv2m_map_add_config(struct pinctrl_map *map,
0188                 const char *group_or_pin,
0189                 enum pinctrl_map_type type,
0190                 unsigned long *configs,
0191                 unsigned int num_configs)
0192 {
0193     unsigned long *cfgs;
0194 
0195     cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
0196                GFP_KERNEL);
0197     if (!cfgs)
0198         return -ENOMEM;
0199 
0200     map->type = type;
0201     map->data.configs.group_or_pin = group_or_pin;
0202     map->data.configs.configs = cfgs;
0203     map->data.configs.num_configs = num_configs;
0204 
0205     return 0;
0206 }
0207 
0208 static int rzv2m_dt_subnode_to_map(struct pinctrl_dev *pctldev,
0209                    struct device_node *np,
0210                    struct pinctrl_map **map,
0211                    unsigned int *num_maps,
0212                    unsigned int *index)
0213 {
0214     struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0215     struct pinctrl_map *maps = *map;
0216     unsigned int nmaps = *num_maps;
0217     unsigned long *configs = NULL;
0218     unsigned int *pins, *psel_val;
0219     unsigned int num_pinmux = 0;
0220     unsigned int idx = *index;
0221     unsigned int num_pins, i;
0222     unsigned int num_configs;
0223     struct property *pinmux;
0224     struct property *prop;
0225     int ret, gsel, fsel;
0226     const char **pin_fn;
0227     const char *pin;
0228 
0229     pinmux = of_find_property(np, "pinmux", NULL);
0230     if (pinmux)
0231         num_pinmux = pinmux->length / sizeof(u32);
0232 
0233     ret = of_property_count_strings(np, "pins");
0234     if (ret == -EINVAL) {
0235         num_pins = 0;
0236     } else if (ret < 0) {
0237         dev_err(pctrl->dev, "Invalid pins list in DT\n");
0238         return ret;
0239     } else {
0240         num_pins = ret;
0241     }
0242 
0243     if (!num_pinmux && !num_pins)
0244         return 0;
0245 
0246     if (num_pinmux && num_pins) {
0247         dev_err(pctrl->dev,
0248             "DT node must contain either a pinmux or pins and not both\n");
0249         return -EINVAL;
0250     }
0251 
0252     ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
0253     if (ret < 0)
0254         return ret;
0255 
0256     if (num_pins && !num_configs) {
0257         dev_err(pctrl->dev, "DT node must contain a config\n");
0258         ret = -ENODEV;
0259         goto done;
0260     }
0261 
0262     if (num_pinmux)
0263         nmaps += 1;
0264 
0265     if (num_pins)
0266         nmaps += num_pins;
0267 
0268     maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL);
0269     if (!maps) {
0270         ret = -ENOMEM;
0271         goto done;
0272     }
0273 
0274     *map = maps;
0275     *num_maps = nmaps;
0276     if (num_pins) {
0277         of_property_for_each_string(np, "pins", prop, pin) {
0278             ret = rzv2m_map_add_config(&maps[idx], pin,
0279                            PIN_MAP_TYPE_CONFIGS_PIN,
0280                            configs, num_configs);
0281             if (ret < 0)
0282                 goto done;
0283 
0284             idx++;
0285         }
0286         ret = 0;
0287         goto done;
0288     }
0289 
0290     pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL);
0291     psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val),
0292                 GFP_KERNEL);
0293     pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL);
0294     if (!pins || !psel_val || !pin_fn) {
0295         ret = -ENOMEM;
0296         goto done;
0297     }
0298 
0299     /* Collect pin locations and mux settings from DT properties */
0300     for (i = 0; i < num_pinmux; ++i) {
0301         u32 value;
0302 
0303         ret = of_property_read_u32_index(np, "pinmux", i, &value);
0304         if (ret)
0305             goto done;
0306         pins[i] = value & MUX_PIN_ID_MASK;
0307         psel_val[i] = MUX_FUNC(value);
0308     }
0309 
0310     /* Register a single pin group listing all the pins we read from DT */
0311     gsel = pinctrl_generic_add_group(pctldev, np->name, pins, num_pinmux, NULL);
0312     if (gsel < 0) {
0313         ret = gsel;
0314         goto done;
0315     }
0316 
0317     /*
0318      * Register a single group function where the 'data' is an array PSEL
0319      * register values read from DT.
0320      */
0321     pin_fn[0] = np->name;
0322     fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
0323                        psel_val);
0324     if (fsel < 0) {
0325         ret = fsel;
0326         goto remove_group;
0327     }
0328 
0329     maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
0330     maps[idx].data.mux.group = np->name;
0331     maps[idx].data.mux.function = np->name;
0332     idx++;
0333 
0334     dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux);
0335     ret = 0;
0336     goto done;
0337 
0338 remove_group:
0339     pinctrl_generic_remove_group(pctldev, gsel);
0340 done:
0341     *index = idx;
0342     kfree(configs);
0343     return ret;
0344 }
0345 
0346 static void rzv2m_dt_free_map(struct pinctrl_dev *pctldev,
0347                   struct pinctrl_map *map,
0348                   unsigned int num_maps)
0349 {
0350     unsigned int i;
0351 
0352     if (!map)
0353         return;
0354 
0355     for (i = 0; i < num_maps; ++i) {
0356         if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
0357             map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
0358             kfree(map[i].data.configs.configs);
0359     }
0360     kfree(map);
0361 }
0362 
0363 static int rzv2m_dt_node_to_map(struct pinctrl_dev *pctldev,
0364                 struct device_node *np,
0365                 struct pinctrl_map **map,
0366                 unsigned int *num_maps)
0367 {
0368     struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0369     struct device_node *child;
0370     unsigned int index;
0371     int ret;
0372 
0373     *map = NULL;
0374     *num_maps = 0;
0375     index = 0;
0376 
0377     for_each_child_of_node(np, child) {
0378         ret = rzv2m_dt_subnode_to_map(pctldev, child, map,
0379                           num_maps, &index);
0380         if (ret < 0) {
0381             of_node_put(child);
0382             goto done;
0383         }
0384     }
0385 
0386     if (*num_maps == 0) {
0387         ret = rzv2m_dt_subnode_to_map(pctldev, np, map,
0388                           num_maps, &index);
0389         if (ret < 0)
0390             goto done;
0391     }
0392 
0393     if (*num_maps)
0394         return 0;
0395 
0396     dev_err(pctrl->dev, "no mapping found in node %pOF\n", np);
0397     ret = -EINVAL;
0398 
0399 done:
0400     if (ret < 0)
0401         rzv2m_dt_free_map(pctldev, *map, *num_maps);
0402 
0403     return ret;
0404 }
0405 
0406 static int rzv2m_validate_gpio_pin(struct rzv2m_pinctrl *pctrl,
0407                    u32 cfg, u32 port, u8 bit)
0408 {
0409     u8 pincount = RZV2M_GPIO_PORT_GET_PINCNT(cfg);
0410     u32 port_index = RZV2M_GPIO_PORT_GET_INDEX(cfg);
0411     u32 data;
0412 
0413     if (bit >= pincount || port >= pctrl->data->n_port_pins)
0414         return -EINVAL;
0415 
0416     data = pctrl->data->port_pin_configs[port];
0417     if (port_index != RZV2M_GPIO_PORT_GET_INDEX(data))
0418         return -EINVAL;
0419 
0420     return 0;
0421 }
0422 
0423 static void rzv2m_rmw_pin_config(struct rzv2m_pinctrl *pctrl, u32 offset,
0424                  u8 shift, u32 mask, u32 val)
0425 {
0426     void __iomem *addr = pctrl->base + offset;
0427     unsigned long flags;
0428     u32 reg;
0429 
0430     spin_lock_irqsave(&pctrl->lock, flags);
0431     reg = readl(addr) & ~(mask << shift);
0432     writel(reg | (val << shift), addr);
0433     spin_unlock_irqrestore(&pctrl->lock, flags);
0434 }
0435 
0436 static int rzv2m_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
0437                      unsigned int _pin,
0438                      unsigned long *config)
0439 {
0440     struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0441     enum pin_config_param param = pinconf_to_config_param(*config);
0442     const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
0443     unsigned int *pin_data = pin->drv_data;
0444     unsigned int arg = 0;
0445     u32 port;
0446     u32 cfg;
0447     u8 bit;
0448     u32 val;
0449 
0450     if (!pin_data)
0451         return -EINVAL;
0452 
0453     if (*pin_data & RZV2M_SINGLE_PIN) {
0454         port = RZV2M_SINGLE_PIN_GET_PORT(*pin_data);
0455         cfg = RZV2M_SINGLE_PIN_GET_CFGS(*pin_data);
0456         bit = RZV2M_SINGLE_PIN_GET_BIT(*pin_data);
0457     } else {
0458         cfg = RZV2M_GPIO_PORT_GET_CFGS(*pin_data);
0459         port = RZV2M_PIN_ID_TO_PORT(_pin);
0460         bit = RZV2M_PIN_ID_TO_PIN(_pin);
0461 
0462         if (rzv2m_validate_gpio_pin(pctrl, *pin_data, RZV2M_PIN_ID_TO_PORT(_pin), bit))
0463             return -EINVAL;
0464     }
0465 
0466     switch (param) {
0467     case PIN_CONFIG_BIAS_DISABLE:
0468     case PIN_CONFIG_BIAS_PULL_UP:
0469     case PIN_CONFIG_BIAS_PULL_DOWN: {
0470         enum pin_config_param bias;
0471 
0472         if (!(cfg & PIN_CFG_BIAS))
0473             return -EINVAL;
0474 
0475         /* PUPD uses 2-bits per pin */
0476         bit *= 2;
0477 
0478         switch ((readl(pctrl->base + PUPD(port)) >> bit) & PUPD_MASK) {
0479         case 0:
0480             bias = PIN_CONFIG_BIAS_PULL_DOWN;
0481             break;
0482         case 2:
0483             bias = PIN_CONFIG_BIAS_PULL_UP;
0484             break;
0485         default:
0486             bias = PIN_CONFIG_BIAS_DISABLE;
0487         }
0488 
0489         if (bias != param)
0490             return -EINVAL;
0491         break;
0492     }
0493 
0494     case PIN_CONFIG_DRIVE_STRENGTH_UA:
0495         if (!(cfg & PIN_CFG_DRV))
0496             return -EINVAL;
0497 
0498         /* DRV uses 2-bits per pin */
0499         bit *= 2;
0500 
0501         val = (readl(pctrl->base + DRV(port)) >> bit) & DRV_MASK;
0502 
0503         switch (cfg & PIN_CFG_GRP_MASK) {
0504         case PIN_CFG_GRP_1_8V_2:
0505             arg = drv_1_8V_group2_uA[val];
0506             break;
0507         case PIN_CFG_GRP_1_8V_3:
0508             arg = drv_1_8V_group3_uA[val];
0509             break;
0510         case PIN_CFG_GRP_SWIO_2:
0511             arg = drv_SWIO_group2_3_3V_uA[val];
0512             break;
0513         case PIN_CFG_GRP_SWIO_1:
0514         case PIN_CFG_GRP_3_3V:
0515             arg = drv_3_3V_group_uA[val];
0516             break;
0517         default:
0518             return -EINVAL;
0519         }
0520 
0521         break;
0522 
0523     case PIN_CONFIG_SLEW_RATE:
0524         if (!(cfg & PIN_CFG_SLEW))
0525             return -EINVAL;
0526 
0527         arg = readl(pctrl->base + SR(port)) & BIT(bit);
0528         break;
0529 
0530     default:
0531         return -ENOTSUPP;
0532     }
0533 
0534     *config = pinconf_to_config_packed(param, arg);
0535 
0536     return 0;
0537 };
0538 
0539 static int rzv2m_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
0540                      unsigned int _pin,
0541                      unsigned long *_configs,
0542                      unsigned int num_configs)
0543 {
0544     struct rzv2m_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0545     const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
0546     unsigned int *pin_data = pin->drv_data;
0547     enum pin_config_param param;
0548     u32 port;
0549     unsigned int i;
0550     u32 cfg;
0551     u8 bit;
0552     u32 val;
0553 
0554     if (!pin_data)
0555         return -EINVAL;
0556 
0557     if (*pin_data & RZV2M_SINGLE_PIN) {
0558         port = RZV2M_SINGLE_PIN_GET_PORT(*pin_data);
0559         cfg = RZV2M_SINGLE_PIN_GET_CFGS(*pin_data);
0560         bit = RZV2M_SINGLE_PIN_GET_BIT(*pin_data);
0561     } else {
0562         cfg = RZV2M_GPIO_PORT_GET_CFGS(*pin_data);
0563         port = RZV2M_PIN_ID_TO_PORT(_pin);
0564         bit = RZV2M_PIN_ID_TO_PIN(_pin);
0565 
0566         if (rzv2m_validate_gpio_pin(pctrl, *pin_data, RZV2M_PIN_ID_TO_PORT(_pin), bit))
0567             return -EINVAL;
0568     }
0569 
0570     for (i = 0; i < num_configs; i++) {
0571         param = pinconf_to_config_param(_configs[i]);
0572         switch (param) {
0573         case PIN_CONFIG_BIAS_DISABLE:
0574         case PIN_CONFIG_BIAS_PULL_UP:
0575         case PIN_CONFIG_BIAS_PULL_DOWN:
0576             if (!(cfg & PIN_CFG_BIAS))
0577                 return -EINVAL;
0578 
0579             /* PUPD uses 2-bits per pin */
0580             bit *= 2;
0581 
0582             switch (param) {
0583             case PIN_CONFIG_BIAS_PULL_DOWN:
0584                 val = 0;
0585                 break;
0586             case PIN_CONFIG_BIAS_PULL_UP:
0587                 val = 2;
0588                 break;
0589             default:
0590                 val = 1;
0591             }
0592 
0593             rzv2m_rmw_pin_config(pctrl, PUPD(port), bit, PUPD_MASK, val);
0594             break;
0595 
0596         case PIN_CONFIG_DRIVE_STRENGTH_UA: {
0597             unsigned int arg = pinconf_to_config_argument(_configs[i]);
0598             const unsigned int *drv_strengths;
0599             unsigned int index;
0600 
0601             if (!(cfg & PIN_CFG_DRV))
0602                 return -EINVAL;
0603 
0604             switch (cfg & PIN_CFG_GRP_MASK) {
0605             case PIN_CFG_GRP_1_8V_2:
0606                 drv_strengths = drv_1_8V_group2_uA;
0607                 break;
0608             case PIN_CFG_GRP_1_8V_3:
0609                 drv_strengths = drv_1_8V_group3_uA;
0610                 break;
0611             case PIN_CFG_GRP_SWIO_2:
0612                 drv_strengths = drv_SWIO_group2_3_3V_uA;
0613                 break;
0614             case PIN_CFG_GRP_SWIO_1:
0615             case PIN_CFG_GRP_3_3V:
0616                 drv_strengths = drv_3_3V_group_uA;
0617                 break;
0618             default:
0619                 return -EINVAL;
0620             }
0621 
0622             for (index = 0; index < 4; index++) {
0623                 if (arg == drv_strengths[index])
0624                     break;
0625             }
0626             if (index >= 4)
0627                 return -EINVAL;
0628 
0629             /* DRV uses 2-bits per pin */
0630             bit *= 2;
0631 
0632             rzv2m_rmw_pin_config(pctrl, DRV(port), bit, DRV_MASK, index);
0633             break;
0634         }
0635 
0636         case PIN_CONFIG_SLEW_RATE: {
0637             unsigned int arg = pinconf_to_config_argument(_configs[i]);
0638 
0639             if (!(cfg & PIN_CFG_SLEW))
0640                 return -EINVAL;
0641 
0642             rzv2m_writel_we(pctrl->base + SR(port), bit, !arg);
0643             break;
0644         }
0645 
0646         default:
0647             return -EOPNOTSUPP;
0648         }
0649     }
0650 
0651     return 0;
0652 }
0653 
0654 static int rzv2m_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev,
0655                        unsigned int group,
0656                        unsigned long *configs,
0657                        unsigned int num_configs)
0658 {
0659     const unsigned int *pins;
0660     unsigned int i, npins;
0661     int ret;
0662 
0663     ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
0664     if (ret)
0665         return ret;
0666 
0667     for (i = 0; i < npins; i++) {
0668         ret = rzv2m_pinctrl_pinconf_set(pctldev, pins[i], configs,
0669                         num_configs);
0670         if (ret)
0671             return ret;
0672     }
0673 
0674     return 0;
0675 };
0676 
0677 static int rzv2m_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev,
0678                        unsigned int group,
0679                        unsigned long *config)
0680 {
0681     const unsigned int *pins;
0682     unsigned int i, npins, prev_config = 0;
0683     int ret;
0684 
0685     ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
0686     if (ret)
0687         return ret;
0688 
0689     for (i = 0; i < npins; i++) {
0690         ret = rzv2m_pinctrl_pinconf_get(pctldev, pins[i], config);
0691         if (ret)
0692             return ret;
0693 
0694         /* Check config matches previous pins */
0695         if (i && prev_config != *config)
0696             return -EOPNOTSUPP;
0697 
0698         prev_config = *config;
0699     }
0700 
0701     return 0;
0702 };
0703 
0704 static const struct pinctrl_ops rzv2m_pinctrl_pctlops = {
0705     .get_groups_count = pinctrl_generic_get_group_count,
0706     .get_group_name = pinctrl_generic_get_group_name,
0707     .get_group_pins = pinctrl_generic_get_group_pins,
0708     .dt_node_to_map = rzv2m_dt_node_to_map,
0709     .dt_free_map = rzv2m_dt_free_map,
0710 };
0711 
0712 static const struct pinmux_ops rzv2m_pinctrl_pmxops = {
0713     .get_functions_count = pinmux_generic_get_function_count,
0714     .get_function_name = pinmux_generic_get_function_name,
0715     .get_function_groups = pinmux_generic_get_function_groups,
0716     .set_mux = rzv2m_pinctrl_set_mux,
0717     .strict = true,
0718 };
0719 
0720 static const struct pinconf_ops rzv2m_pinctrl_confops = {
0721     .is_generic = true,
0722     .pin_config_get = rzv2m_pinctrl_pinconf_get,
0723     .pin_config_set = rzv2m_pinctrl_pinconf_set,
0724     .pin_config_group_set = rzv2m_pinctrl_pinconf_group_set,
0725     .pin_config_group_get = rzv2m_pinctrl_pinconf_group_get,
0726     .pin_config_config_dbg_show = pinconf_generic_dump_config,
0727 };
0728 
0729 static int rzv2m_gpio_request(struct gpio_chip *chip, unsigned int offset)
0730 {
0731     struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
0732     u32 port = RZV2M_PIN_ID_TO_PORT(offset);
0733     u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
0734     int ret;
0735 
0736     ret = pinctrl_gpio_request(chip->base + offset);
0737     if (ret)
0738         return ret;
0739 
0740     rzv2m_pinctrl_set_pfc_mode(pctrl, port, bit, 0);
0741 
0742     return 0;
0743 }
0744 
0745 static void rzv2m_gpio_set_direction(struct rzv2m_pinctrl *pctrl, u32 port,
0746                      u8 bit, bool output)
0747 {
0748     rzv2m_writel_we(pctrl->base + OE(port), bit, output);
0749     rzv2m_writel_we(pctrl->base + IE(port), bit, !output);
0750 }
0751 
0752 static int rzv2m_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
0753 {
0754     struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
0755     u32 port = RZV2M_PIN_ID_TO_PORT(offset);
0756     u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
0757 
0758     if (!(readl(pctrl->base + IE(port)) & BIT(bit)))
0759         return GPIO_LINE_DIRECTION_OUT;
0760 
0761     return GPIO_LINE_DIRECTION_IN;
0762 }
0763 
0764 static int rzv2m_gpio_direction_input(struct gpio_chip *chip,
0765                       unsigned int offset)
0766 {
0767     struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
0768     u32 port = RZV2M_PIN_ID_TO_PORT(offset);
0769     u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
0770 
0771     rzv2m_gpio_set_direction(pctrl, port, bit, false);
0772 
0773     return 0;
0774 }
0775 
0776 static void rzv2m_gpio_set(struct gpio_chip *chip, unsigned int offset,
0777                int value)
0778 {
0779     struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
0780     u32 port = RZV2M_PIN_ID_TO_PORT(offset);
0781     u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
0782 
0783     rzv2m_writel_we(pctrl->base + DO(port), bit, !!value);
0784 }
0785 
0786 static int rzv2m_gpio_direction_output(struct gpio_chip *chip,
0787                        unsigned int offset, int value)
0788 {
0789     struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
0790     u32 port = RZV2M_PIN_ID_TO_PORT(offset);
0791     u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
0792 
0793     rzv2m_gpio_set(chip, offset, value);
0794     rzv2m_gpio_set_direction(pctrl, port, bit, true);
0795 
0796     return 0;
0797 }
0798 
0799 static int rzv2m_gpio_get(struct gpio_chip *chip, unsigned int offset)
0800 {
0801     struct rzv2m_pinctrl *pctrl = gpiochip_get_data(chip);
0802     u32 port = RZV2M_PIN_ID_TO_PORT(offset);
0803     u8 bit = RZV2M_PIN_ID_TO_PIN(offset);
0804     int direction = rzv2m_gpio_get_direction(chip, offset);
0805 
0806     if (direction == GPIO_LINE_DIRECTION_IN)
0807         return !!(readl(pctrl->base + DI(port)) & BIT(bit));
0808     else
0809         return !!(readl(pctrl->base + DO(port)) & BIT(bit));
0810 }
0811 
0812 static void rzv2m_gpio_free(struct gpio_chip *chip, unsigned int offset)
0813 {
0814     pinctrl_gpio_free(chip->base + offset);
0815 
0816     /*
0817      * Set the GPIO as an input to ensure that the next GPIO request won't
0818      * drive the GPIO pin as an output.
0819      */
0820     rzv2m_gpio_direction_input(chip, offset);
0821 }
0822 
0823 static const char * const rzv2m_gpio_names[] = {
0824     "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
0825     "P0_8", "P0_9", "P0_10", "P0_11", "P0_12", "P0_13", "P0_14", "P0_15",
0826     "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
0827     "P1_8", "P1_9", "P1_10", "P1_11", "P1_12", "P1_13", "P1_14", "P1_15",
0828     "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
0829     "P2_8", "P2_9", "P2_10", "P2_11", "P2_12", "P2_13", "P2_14", "P2_15",
0830     "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
0831     "P3_8", "P3_9", "P3_10", "P3_11", "P3_12", "P3_13", "P3_14", "P3_15",
0832     "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
0833     "P4_8", "P4_9", "P4_10", "P4_11", "P4_12", "P4_13", "P4_14", "P4_15",
0834     "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
0835     "P5_8", "P5_9", "P5_10", "P5_11", "P5_12", "P5_13", "P5_14", "P5_15",
0836     "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
0837     "P6_8", "P6_9", "P6_10", "P6_11", "P6_12", "P6_13", "P6_14", "P6_15",
0838     "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
0839     "P7_8", "P7_9", "P7_10", "P7_11", "P7_12", "P7_13", "P7_14", "P7_15",
0840     "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
0841     "P8_8", "P8_9", "P8_10", "P8_11", "P8_12", "P8_13", "P8_14", "P8_15",
0842     "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
0843     "P9_8", "P9_9", "P9_10", "P9_11", "P9_12", "P9_13", "P9_14", "P9_15",
0844     "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7",
0845     "P10_8", "P10_9", "P10_10", "P10_11", "P10_12", "P10_13", "P10_14", "P10_15",
0846     "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7",
0847     "P11_8", "P11_9", "P11_10", "P11_11", "P11_12", "P11_13", "P11_14", "P11_15",
0848     "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7",
0849     "P12_8", "P12_9", "P12_10", "P12_11", "P12_12", "P12_13", "P12_14", "P12_15",
0850     "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7",
0851     "P13_8", "P13_9", "P13_10", "P13_11", "P13_12", "P13_13", "P13_14", "P13_15",
0852     "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7",
0853     "P14_8", "P14_9", "P14_10", "P14_11", "P14_12", "P14_13", "P14_14", "P14_15",
0854     "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7",
0855     "P15_8", "P15_9", "P15_10", "P15_11", "P15_12", "P15_13", "P15_14", "P15_15",
0856     "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7",
0857     "P16_8", "P16_9", "P16_10", "P16_11", "P16_12", "P16_13", "P16_14", "P16_15",
0858     "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7",
0859     "P17_8", "P17_9", "P17_10", "P17_11", "P17_12", "P17_13", "P17_14", "P17_15",
0860     "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7",
0861     "P18_8", "P18_9", "P18_10", "P18_11", "P18_12", "P18_13", "P18_14", "P18_15",
0862     "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7",
0863     "P19_8", "P19_9", "P19_10", "P19_11", "P19_12", "P19_13", "P19_14", "P19_15",
0864     "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7",
0865     "P20_8", "P20_9", "P20_10", "P20_11", "P20_12", "P20_13", "P20_14", "P20_15",
0866     "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7",
0867     "P21_8", "P21_9", "P21_10", "P21_11", "P21_12", "P21_13", "P21_14", "P21_15",
0868 };
0869 
0870 static const u32 rzv2m_gpio_configs[] = {
0871     RZV2M_GPIO_PORT_PACK(14, 0, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
0872     RZV2M_GPIO_PORT_PACK(16, 1, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
0873     RZV2M_GPIO_PORT_PACK(8,  2, PIN_CFG_GRP_1_8V_3 | RZV2M_MPXED_PIN_FUNCS),
0874     RZV2M_GPIO_PORT_PACK(16, 3, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
0875     RZV2M_GPIO_PORT_PACK(8,  4, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
0876     RZV2M_GPIO_PORT_PACK(4,  5, PIN_CFG_GRP_1_8V_3 | RZV2M_MPXED_PIN_FUNCS),
0877     RZV2M_GPIO_PORT_PACK(12, 6, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
0878     RZV2M_GPIO_PORT_PACK(6,  7, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
0879     RZV2M_GPIO_PORT_PACK(8,  8, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
0880     RZV2M_GPIO_PORT_PACK(8,  9, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
0881     RZV2M_GPIO_PORT_PACK(9,  10, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
0882     RZV2M_GPIO_PORT_PACK(9,  11, PIN_CFG_GRP_SWIO_1 | RZV2M_MPXED_PIN_FUNCS),
0883     RZV2M_GPIO_PORT_PACK(4,  12, PIN_CFG_GRP_3_3V | RZV2M_MPXED_PIN_FUNCS),
0884     RZV2M_GPIO_PORT_PACK(12, 13, PIN_CFG_GRP_3_3V | RZV2M_MPXED_PIN_FUNCS),
0885     RZV2M_GPIO_PORT_PACK(8,  14, PIN_CFG_GRP_3_3V | RZV2M_MPXED_PIN_FUNCS),
0886     RZV2M_GPIO_PORT_PACK(16, 15, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
0887     RZV2M_GPIO_PORT_PACK(14, 16, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
0888     RZV2M_GPIO_PORT_PACK(1,  17, PIN_CFG_GRP_SWIO_2 | RZV2M_MPXED_PIN_FUNCS),
0889     RZV2M_GPIO_PORT_PACK(0,  18, 0),
0890     RZV2M_GPIO_PORT_PACK(0,  19, 0),
0891     RZV2M_GPIO_PORT_PACK(3,  20, PIN_CFG_GRP_1_8V_2 | PIN_CFG_DRV),
0892     RZV2M_GPIO_PORT_PACK(1,  21, PIN_CFG_GRP_SWIO_1 | PIN_CFG_DRV | PIN_CFG_SLEW),
0893 };
0894 
0895 static const struct rzv2m_dedicated_configs rzv2m_dedicated_pins[] = {
0896     { "NAWPN", RZV2M_SINGLE_PIN_PACK(0,
0897         (PIN_CFG_GRP_SWIO_2 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
0898     { "IM0CLK", RZV2M_SINGLE_PIN_PACK(1,
0899         (PIN_CFG_GRP_SWIO_1 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
0900     { "IM1CLK", RZV2M_SINGLE_PIN_PACK(2,
0901         (PIN_CFG_GRP_SWIO_1 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
0902     { "DETDO", RZV2M_SINGLE_PIN_PACK(5,
0903         (PIN_CFG_GRP_1_8V_3 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
0904     { "DETMS", RZV2M_SINGLE_PIN_PACK(6,
0905         (PIN_CFG_GRP_1_8V_3 | PIN_CFG_DRV | PIN_CFG_SLEW)) },
0906     { "PCRSTOUTB", RZV2M_SINGLE_PIN_PACK(12,
0907         (PIN_CFG_GRP_3_3V | PIN_CFG_DRV | PIN_CFG_SLEW)) },
0908     { "USPWEN", RZV2M_SINGLE_PIN_PACK(14,
0909         (PIN_CFG_GRP_3_3V | PIN_CFG_DRV | PIN_CFG_SLEW)) },
0910 };
0911 
0912 static int rzv2m_gpio_register(struct rzv2m_pinctrl *pctrl)
0913 {
0914     struct device_node *np = pctrl->dev->of_node;
0915     struct gpio_chip *chip = &pctrl->gpio_chip;
0916     const char *name = dev_name(pctrl->dev);
0917     struct of_phandle_args of_args;
0918     int ret;
0919 
0920     ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args);
0921     if (ret) {
0922         dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");
0923         return ret;
0924     }
0925 
0926     if (of_args.args[0] != 0 || of_args.args[1] != 0 ||
0927         of_args.args[2] != pctrl->data->n_port_pins) {
0928         dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n");
0929         return -EINVAL;
0930     }
0931 
0932     chip->names = pctrl->data->port_pins;
0933     chip->request = rzv2m_gpio_request;
0934     chip->free = rzv2m_gpio_free;
0935     chip->get_direction = rzv2m_gpio_get_direction;
0936     chip->direction_input = rzv2m_gpio_direction_input;
0937     chip->direction_output = rzv2m_gpio_direction_output;
0938     chip->get = rzv2m_gpio_get;
0939     chip->set = rzv2m_gpio_set;
0940     chip->label = name;
0941     chip->parent = pctrl->dev;
0942     chip->owner = THIS_MODULE;
0943     chip->base = -1;
0944     chip->ngpio = of_args.args[2];
0945 
0946     pctrl->gpio_range.id = 0;
0947     pctrl->gpio_range.pin_base = 0;
0948     pctrl->gpio_range.base = 0;
0949     pctrl->gpio_range.npins = chip->ngpio;
0950     pctrl->gpio_range.name = chip->label;
0951     pctrl->gpio_range.gc = chip;
0952     ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl);
0953     if (ret) {
0954         dev_err(pctrl->dev, "failed to add GPIO controller\n");
0955         return ret;
0956     }
0957 
0958     dev_dbg(pctrl->dev, "Registered gpio controller\n");
0959 
0960     return 0;
0961 }
0962 
0963 static int rzv2m_pinctrl_register(struct rzv2m_pinctrl *pctrl)
0964 {
0965     struct pinctrl_pin_desc *pins;
0966     unsigned int i, j;
0967     u32 *pin_data;
0968     int ret;
0969 
0970     pctrl->desc.name = DRV_NAME;
0971     pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins;
0972     pctrl->desc.pctlops = &rzv2m_pinctrl_pctlops;
0973     pctrl->desc.pmxops = &rzv2m_pinctrl_pmxops;
0974     pctrl->desc.confops = &rzv2m_pinctrl_confops;
0975     pctrl->desc.owner = THIS_MODULE;
0976 
0977     pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL);
0978     if (!pins)
0979         return -ENOMEM;
0980 
0981     pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins,
0982                 sizeof(*pin_data), GFP_KERNEL);
0983     if (!pin_data)
0984         return -ENOMEM;
0985 
0986     pctrl->pins = pins;
0987     pctrl->desc.pins = pins;
0988 
0989     for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) {
0990         pins[i].number = i;
0991         pins[i].name = pctrl->data->port_pins[i];
0992         if (i && !(i % RZV2M_PINS_PER_PORT))
0993             j++;
0994         pin_data[i] = pctrl->data->port_pin_configs[j];
0995         pins[i].drv_data = &pin_data[i];
0996     }
0997 
0998     for (i = 0; i < pctrl->data->n_dedicated_pins; i++) {
0999         unsigned int index = pctrl->data->n_port_pins + i;
1000 
1001         pins[index].number = index;
1002         pins[index].name = pctrl->data->dedicated_pins[i].name;
1003         pin_data[index] = pctrl->data->dedicated_pins[i].config;
1004         pins[index].drv_data = &pin_data[index];
1005     }
1006 
1007     ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl,
1008                          &pctrl->pctl);
1009     if (ret) {
1010         dev_err(pctrl->dev, "pinctrl registration failed\n");
1011         return ret;
1012     }
1013 
1014     ret = pinctrl_enable(pctrl->pctl);
1015     if (ret) {
1016         dev_err(pctrl->dev, "pinctrl enable failed\n");
1017         return ret;
1018     }
1019 
1020     ret = rzv2m_gpio_register(pctrl);
1021     if (ret) {
1022         dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret);
1023         return ret;
1024     }
1025 
1026     return 0;
1027 }
1028 
1029 static void rzv2m_pinctrl_clk_disable(void *data)
1030 {
1031     clk_disable_unprepare(data);
1032 }
1033 
1034 static int rzv2m_pinctrl_probe(struct platform_device *pdev)
1035 {
1036     struct rzv2m_pinctrl *pctrl;
1037     int ret;
1038 
1039     pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1040     if (!pctrl)
1041         return -ENOMEM;
1042 
1043     pctrl->dev = &pdev->dev;
1044 
1045     pctrl->data = of_device_get_match_data(&pdev->dev);
1046     if (!pctrl->data)
1047         return -EINVAL;
1048 
1049     pctrl->base = devm_platform_ioremap_resource(pdev, 0);
1050     if (IS_ERR(pctrl->base))
1051         return PTR_ERR(pctrl->base);
1052 
1053     pctrl->clk = devm_clk_get(pctrl->dev, NULL);
1054     if (IS_ERR(pctrl->clk)) {
1055         ret = PTR_ERR(pctrl->clk);
1056         dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret);
1057         return ret;
1058     }
1059 
1060     spin_lock_init(&pctrl->lock);
1061 
1062     platform_set_drvdata(pdev, pctrl);
1063 
1064     ret = clk_prepare_enable(pctrl->clk);
1065     if (ret) {
1066         dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret);
1067         return ret;
1068     }
1069 
1070     ret = devm_add_action_or_reset(&pdev->dev, rzv2m_pinctrl_clk_disable,
1071                        pctrl->clk);
1072     if (ret) {
1073         dev_err(pctrl->dev,
1074             "failed to register GPIO clk disable action, %i\n",
1075             ret);
1076         return ret;
1077     }
1078 
1079     ret = rzv2m_pinctrl_register(pctrl);
1080     if (ret)
1081         return ret;
1082 
1083     dev_info(pctrl->dev, "%s support registered\n", DRV_NAME);
1084     return 0;
1085 }
1086 
1087 static struct rzv2m_pinctrl_data r9a09g011_data = {
1088     .port_pins = rzv2m_gpio_names,
1089     .port_pin_configs = rzv2m_gpio_configs,
1090     .dedicated_pins = rzv2m_dedicated_pins,
1091     .n_port_pins = ARRAY_SIZE(rzv2m_gpio_configs) * RZV2M_PINS_PER_PORT,
1092     .n_dedicated_pins = ARRAY_SIZE(rzv2m_dedicated_pins),
1093 };
1094 
1095 static const struct of_device_id rzv2m_pinctrl_of_table[] = {
1096     {
1097         .compatible = "renesas,r9a09g011-pinctrl",
1098         .data = &r9a09g011_data,
1099     },
1100     { /* sentinel */ }
1101 };
1102 
1103 static struct platform_driver rzv2m_pinctrl_driver = {
1104     .driver = {
1105         .name = DRV_NAME,
1106         .of_match_table = of_match_ptr(rzv2m_pinctrl_of_table),
1107     },
1108     .probe = rzv2m_pinctrl_probe,
1109 };
1110 
1111 static int __init rzv2m_pinctrl_init(void)
1112 {
1113     return platform_driver_register(&rzv2m_pinctrl_driver);
1114 }
1115 core_initcall(rzv2m_pinctrl_init);
1116 
1117 MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
1118 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/V2M");
1119 MODULE_LICENSE("GPL");
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