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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2014-2018 Renesas Electronics Europe Limited
0004  *
0005  * Phil Edworthy <phil.edworthy@renesas.com>
0006  * Based on a driver originally written by Michel Pollet at Renesas.
0007  */
0008 
0009 #include <dt-bindings/pinctrl/rzn1-pinctrl.h>
0010 #include <linux/clk.h>
0011 #include <linux/device.h>
0012 #include <linux/io.h>
0013 #include <linux/module.h>
0014 #include <linux/of.h>
0015 #include <linux/pinctrl/pinconf-generic.h>
0016 #include <linux/pinctrl/pinctrl.h>
0017 #include <linux/pinctrl/pinmux.h>
0018 #include <linux/platform_device.h>
0019 #include <linux/slab.h>
0020 #include "../core.h"
0021 #include "../pinconf.h"
0022 #include "../pinctrl-utils.h"
0023 
0024 /* Field positions and masks in the pinmux registers */
0025 #define RZN1_L1_PIN_DRIVE_STRENGTH  10
0026 #define RZN1_L1_PIN_DRIVE_STRENGTH_4MA  0
0027 #define RZN1_L1_PIN_DRIVE_STRENGTH_6MA  1
0028 #define RZN1_L1_PIN_DRIVE_STRENGTH_8MA  2
0029 #define RZN1_L1_PIN_DRIVE_STRENGTH_12MA 3
0030 #define RZN1_L1_PIN_PULL        8
0031 #define RZN1_L1_PIN_PULL_NONE       0
0032 #define RZN1_L1_PIN_PULL_UP     1
0033 #define RZN1_L1_PIN_PULL_DOWN       3
0034 #define RZN1_L1_FUNCTION        0
0035 #define RZN1_L1_FUNC_MASK       0xf
0036 #define RZN1_L1_FUNCTION_L2     0xf
0037 
0038 /*
0039  * The hardware manual describes two levels of multiplexing, but it's more
0040  * logical to think of the hardware as three levels, with level 3 consisting of
0041  * the multiplexing for Ethernet MDIO signals.
0042  *
0043  * Level 1 functions go from 0 to 9, with level 1 function '15' (0xf) specifying
0044  * that level 2 functions are used instead. Level 2 has a lot more options,
0045  * going from 0 to 61. Level 3 allows selection of MDIO functions which can be
0046  * floating, or one of seven internal peripherals. Unfortunately, there are two
0047  * level 2 functions that can select MDIO, and two MDIO channels so we have four
0048  * sets of level 3 functions.
0049  *
0050  * For this driver, we've compounded the numbers together, so:
0051  *    0 to   9 is level 1
0052  *   10 to  71 is 10 + level 2 number
0053  *   72 to  79 is 72 + MDIO0 source for level 2 MDIO function.
0054  *   80 to  87 is 80 + MDIO0 source for level 2 MDIO_E1 function.
0055  *   88 to  95 is 88 + MDIO1 source for level 2 MDIO function.
0056  *   96 to 103 is 96 + MDIO1 source for level 2 MDIO_E1 function.
0057  * Examples:
0058  *  Function 28 corresponds UART0
0059  *  Function 73 corresponds to MDIO0 to GMAC0
0060  *
0061  * There are 170 configurable pins (called PL_GPIO in the datasheet).
0062  */
0063 
0064 /*
0065  * Structure detailing the HW registers on the RZ/N1 devices.
0066  * Both the Level 1 mux registers and Level 2 mux registers have the same
0067  * structure. The only difference is that Level 2 has additional MDIO registers
0068  * at the end.
0069  */
0070 struct rzn1_pinctrl_regs {
0071     u32 conf[170];
0072     u32 pad0[86];
0073     u32 status_protect; /* 0x400 */
0074     /* MDIO mux registers, level2 only */
0075     u32 l2_mdio[2];
0076 };
0077 
0078 /**
0079  * struct rzn1_pmx_func - describes rzn1 pinmux functions
0080  * @name: the name of this specific function
0081  * @groups: corresponding pin groups
0082  * @num_groups: the number of groups
0083  */
0084 struct rzn1_pmx_func {
0085     const char *name;
0086     const char **groups;
0087     unsigned int num_groups;
0088 };
0089 
0090 /**
0091  * struct rzn1_pin_group - describes an rzn1 pin group
0092  * @name: the name of this specific pin group
0093  * @func: the name of the function selected by this group
0094  * @npins: the number of pins in this group array, i.e. the number of
0095  *  elements in .pins so we can iterate over that array
0096  * @pins: array of pins. Needed due to pinctrl_ops.get_group_pins()
0097  * @pin_ids: array of pin_ids, i.e. the value used to select the mux
0098  */
0099 struct rzn1_pin_group {
0100     const char *name;
0101     const char *func;
0102     unsigned int npins;
0103     unsigned int *pins;
0104     u8 *pin_ids;
0105 };
0106 
0107 struct rzn1_pinctrl {
0108     struct device *dev;
0109     struct clk *clk;
0110     struct pinctrl_dev *pctl;
0111     struct rzn1_pinctrl_regs __iomem *lev1;
0112     struct rzn1_pinctrl_regs __iomem *lev2;
0113     u32 lev1_protect_phys;
0114     u32 lev2_protect_phys;
0115     int mdio_func[2];
0116 
0117     struct rzn1_pin_group *groups;
0118     unsigned int ngroups;
0119 
0120     struct rzn1_pmx_func *functions;
0121     unsigned int nfunctions;
0122 };
0123 
0124 #define RZN1_PINS_PROP "pinmux"
0125 
0126 #define RZN1_PIN(pin) PINCTRL_PIN(pin, "pl_gpio"#pin)
0127 
0128 static const struct pinctrl_pin_desc rzn1_pins[] = {
0129     RZN1_PIN(0), RZN1_PIN(1), RZN1_PIN(2), RZN1_PIN(3), RZN1_PIN(4),
0130     RZN1_PIN(5), RZN1_PIN(6), RZN1_PIN(7), RZN1_PIN(8), RZN1_PIN(9),
0131     RZN1_PIN(10), RZN1_PIN(11), RZN1_PIN(12), RZN1_PIN(13), RZN1_PIN(14),
0132     RZN1_PIN(15), RZN1_PIN(16), RZN1_PIN(17), RZN1_PIN(18), RZN1_PIN(19),
0133     RZN1_PIN(20), RZN1_PIN(21), RZN1_PIN(22), RZN1_PIN(23), RZN1_PIN(24),
0134     RZN1_PIN(25), RZN1_PIN(26), RZN1_PIN(27), RZN1_PIN(28), RZN1_PIN(29),
0135     RZN1_PIN(30), RZN1_PIN(31), RZN1_PIN(32), RZN1_PIN(33), RZN1_PIN(34),
0136     RZN1_PIN(35), RZN1_PIN(36), RZN1_PIN(37), RZN1_PIN(38), RZN1_PIN(39),
0137     RZN1_PIN(40), RZN1_PIN(41), RZN1_PIN(42), RZN1_PIN(43), RZN1_PIN(44),
0138     RZN1_PIN(45), RZN1_PIN(46), RZN1_PIN(47), RZN1_PIN(48), RZN1_PIN(49),
0139     RZN1_PIN(50), RZN1_PIN(51), RZN1_PIN(52), RZN1_PIN(53), RZN1_PIN(54),
0140     RZN1_PIN(55), RZN1_PIN(56), RZN1_PIN(57), RZN1_PIN(58), RZN1_PIN(59),
0141     RZN1_PIN(60), RZN1_PIN(61), RZN1_PIN(62), RZN1_PIN(63), RZN1_PIN(64),
0142     RZN1_PIN(65), RZN1_PIN(66), RZN1_PIN(67), RZN1_PIN(68), RZN1_PIN(69),
0143     RZN1_PIN(70), RZN1_PIN(71), RZN1_PIN(72), RZN1_PIN(73), RZN1_PIN(74),
0144     RZN1_PIN(75), RZN1_PIN(76), RZN1_PIN(77), RZN1_PIN(78), RZN1_PIN(79),
0145     RZN1_PIN(80), RZN1_PIN(81), RZN1_PIN(82), RZN1_PIN(83), RZN1_PIN(84),
0146     RZN1_PIN(85), RZN1_PIN(86), RZN1_PIN(87), RZN1_PIN(88), RZN1_PIN(89),
0147     RZN1_PIN(90), RZN1_PIN(91), RZN1_PIN(92), RZN1_PIN(93), RZN1_PIN(94),
0148     RZN1_PIN(95), RZN1_PIN(96), RZN1_PIN(97), RZN1_PIN(98), RZN1_PIN(99),
0149     RZN1_PIN(100), RZN1_PIN(101), RZN1_PIN(102), RZN1_PIN(103),
0150     RZN1_PIN(104), RZN1_PIN(105), RZN1_PIN(106), RZN1_PIN(107),
0151     RZN1_PIN(108), RZN1_PIN(109), RZN1_PIN(110), RZN1_PIN(111),
0152     RZN1_PIN(112), RZN1_PIN(113), RZN1_PIN(114), RZN1_PIN(115),
0153     RZN1_PIN(116), RZN1_PIN(117), RZN1_PIN(118), RZN1_PIN(119),
0154     RZN1_PIN(120), RZN1_PIN(121), RZN1_PIN(122), RZN1_PIN(123),
0155     RZN1_PIN(124), RZN1_PIN(125), RZN1_PIN(126), RZN1_PIN(127),
0156     RZN1_PIN(128), RZN1_PIN(129), RZN1_PIN(130), RZN1_PIN(131),
0157     RZN1_PIN(132), RZN1_PIN(133), RZN1_PIN(134), RZN1_PIN(135),
0158     RZN1_PIN(136), RZN1_PIN(137), RZN1_PIN(138), RZN1_PIN(139),
0159     RZN1_PIN(140), RZN1_PIN(141), RZN1_PIN(142), RZN1_PIN(143),
0160     RZN1_PIN(144), RZN1_PIN(145), RZN1_PIN(146), RZN1_PIN(147),
0161     RZN1_PIN(148), RZN1_PIN(149), RZN1_PIN(150), RZN1_PIN(151),
0162     RZN1_PIN(152), RZN1_PIN(153), RZN1_PIN(154), RZN1_PIN(155),
0163     RZN1_PIN(156), RZN1_PIN(157), RZN1_PIN(158), RZN1_PIN(159),
0164     RZN1_PIN(160), RZN1_PIN(161), RZN1_PIN(162), RZN1_PIN(163),
0165     RZN1_PIN(164), RZN1_PIN(165), RZN1_PIN(166), RZN1_PIN(167),
0166     RZN1_PIN(168), RZN1_PIN(169),
0167 };
0168 
0169 enum {
0170     LOCK_LEVEL1 = 0x1,
0171     LOCK_LEVEL2 = 0x2,
0172     LOCK_ALL = LOCK_LEVEL1 | LOCK_LEVEL2,
0173 };
0174 
0175 static void rzn1_hw_set_lock(struct rzn1_pinctrl *ipctl, u8 lock, u8 value)
0176 {
0177     /*
0178      * The pinmux configuration is locked by writing the physical address of
0179      * the status_protect register to itself. It is unlocked by writing the
0180      * address | 1.
0181      */
0182     if (lock & LOCK_LEVEL1) {
0183         u32 val = ipctl->lev1_protect_phys | !(value & LOCK_LEVEL1);
0184 
0185         writel(val, &ipctl->lev1->status_protect);
0186     }
0187 
0188     if (lock & LOCK_LEVEL2) {
0189         u32 val = ipctl->lev2_protect_phys | !(value & LOCK_LEVEL2);
0190 
0191         writel(val, &ipctl->lev2->status_protect);
0192     }
0193 }
0194 
0195 static void rzn1_pinctrl_mdio_select(struct rzn1_pinctrl *ipctl, int mdio,
0196                      u32 func)
0197 {
0198     if (ipctl->mdio_func[mdio] >= 0 && ipctl->mdio_func[mdio] != func)
0199         dev_warn(ipctl->dev, "conflicting setting for mdio%d!\n", mdio);
0200     ipctl->mdio_func[mdio] = func;
0201 
0202     dev_dbg(ipctl->dev, "setting mdio%d to %u\n", mdio, func);
0203 
0204     writel(func, &ipctl->lev2->l2_mdio[mdio]);
0205 }
0206 
0207 /*
0208  * Using a composite pin description, set the hardware pinmux registers
0209  * with the corresponding values.
0210  * Make sure to unlock write protection and reset it afterward.
0211  *
0212  * NOTE: There is no protection for potential concurrency, it is assumed these
0213  * calls are serialized already.
0214  */
0215 static int rzn1_set_hw_pin_func(struct rzn1_pinctrl *ipctl, unsigned int pin,
0216                 u32 pin_config, u8 use_locks)
0217 {
0218     u32 l1_cache;
0219     u32 l2_cache;
0220     u32 l1;
0221     u32 l2;
0222 
0223     /* Level 3 MDIO multiplexing */
0224     if (pin_config >= RZN1_FUNC_MDIO0_HIGHZ &&
0225         pin_config <= RZN1_FUNC_MDIO1_E1_SWITCH) {
0226         int mdio_channel;
0227         u32 mdio_func;
0228 
0229         if (pin_config <= RZN1_FUNC_MDIO1_HIGHZ)
0230             mdio_channel = 0;
0231         else
0232             mdio_channel = 1;
0233 
0234         /* Get MDIO func, and convert the func to the level 2 number */
0235         if (pin_config <= RZN1_FUNC_MDIO0_SWITCH) {
0236             mdio_func = pin_config - RZN1_FUNC_MDIO0_HIGHZ;
0237             pin_config = RZN1_FUNC_ETH_MDIO;
0238         } else if (pin_config <= RZN1_FUNC_MDIO0_E1_SWITCH) {
0239             mdio_func = pin_config - RZN1_FUNC_MDIO0_E1_HIGHZ;
0240             pin_config = RZN1_FUNC_ETH_MDIO_E1;
0241         } else if (pin_config <= RZN1_FUNC_MDIO1_SWITCH) {
0242             mdio_func = pin_config - RZN1_FUNC_MDIO1_HIGHZ;
0243             pin_config = RZN1_FUNC_ETH_MDIO;
0244         } else {
0245             mdio_func = pin_config - RZN1_FUNC_MDIO1_E1_HIGHZ;
0246             pin_config = RZN1_FUNC_ETH_MDIO_E1;
0247         }
0248         rzn1_pinctrl_mdio_select(ipctl, mdio_channel, mdio_func);
0249     }
0250 
0251     /* Note here, we do not allow anything past the MDIO Mux values */
0252     if (pin >= ARRAY_SIZE(ipctl->lev1->conf) ||
0253         pin_config >= RZN1_FUNC_MDIO0_HIGHZ)
0254         return -EINVAL;
0255 
0256     l1 = readl(&ipctl->lev1->conf[pin]);
0257     l1_cache = l1;
0258     l2 = readl(&ipctl->lev2->conf[pin]);
0259     l2_cache = l2;
0260 
0261     dev_dbg(ipctl->dev, "setting func for pin %u to %u\n", pin, pin_config);
0262 
0263     l1 &= ~(RZN1_L1_FUNC_MASK << RZN1_L1_FUNCTION);
0264 
0265     if (pin_config < RZN1_FUNC_L2_OFFSET) {
0266         l1 |= (pin_config << RZN1_L1_FUNCTION);
0267     } else {
0268         l1 |= (RZN1_L1_FUNCTION_L2 << RZN1_L1_FUNCTION);
0269 
0270         l2 = pin_config - RZN1_FUNC_L2_OFFSET;
0271     }
0272 
0273     /* If either configuration changes, we update both anyway */
0274     if (l1 != l1_cache || l2 != l2_cache) {
0275         writel(l1, &ipctl->lev1->conf[pin]);
0276         writel(l2, &ipctl->lev2->conf[pin]);
0277     }
0278 
0279     return 0;
0280 }
0281 
0282 static const struct rzn1_pin_group *rzn1_pinctrl_find_group_by_name(
0283     const struct rzn1_pinctrl *ipctl, const char *name)
0284 {
0285     unsigned int i;
0286 
0287     for (i = 0; i < ipctl->ngroups; i++) {
0288         if (!strcmp(ipctl->groups[i].name, name))
0289             return &ipctl->groups[i];
0290     }
0291 
0292     return NULL;
0293 }
0294 
0295 static int rzn1_get_groups_count(struct pinctrl_dev *pctldev)
0296 {
0297     struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0298 
0299     return ipctl->ngroups;
0300 }
0301 
0302 static const char *rzn1_get_group_name(struct pinctrl_dev *pctldev,
0303                        unsigned int selector)
0304 {
0305     struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0306 
0307     return ipctl->groups[selector].name;
0308 }
0309 
0310 static int rzn1_get_group_pins(struct pinctrl_dev *pctldev,
0311                    unsigned int selector, const unsigned int **pins,
0312                    unsigned int *npins)
0313 {
0314     struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0315 
0316     if (selector >= ipctl->ngroups)
0317         return -EINVAL;
0318 
0319     *pins = ipctl->groups[selector].pins;
0320     *npins = ipctl->groups[selector].npins;
0321 
0322     return 0;
0323 }
0324 
0325 /*
0326  * This function is called for each pinctl 'Function' node.
0327  * Sub-nodes can be used to describe multiple 'Groups' for the 'Function'
0328  * If there aren't any sub-nodes, the 'Group' is essentially the 'Function'.
0329  * Each 'Group' uses pinmux = <...> to detail the pins and data used to select
0330  * the functionality. Each 'Group' has optional pin configurations that apply
0331  * to all pins in the 'Group'.
0332  */
0333 static int rzn1_dt_node_to_map_one(struct pinctrl_dev *pctldev,
0334                    struct device_node *np,
0335                    struct pinctrl_map **map,
0336                    unsigned int *num_maps)
0337 {
0338     struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0339     const struct rzn1_pin_group *grp;
0340     unsigned long *configs = NULL;
0341     unsigned int reserved_maps = *num_maps;
0342     unsigned int num_configs = 0;
0343     unsigned int reserve = 1;
0344     int ret;
0345 
0346     dev_dbg(ipctl->dev, "processing node %pOF\n", np);
0347 
0348     grp = rzn1_pinctrl_find_group_by_name(ipctl, np->name);
0349     if (!grp) {
0350         dev_err(ipctl->dev, "unable to find group for node %pOF\n", np);
0351 
0352         return -EINVAL;
0353     }
0354 
0355     /* Get the group's pin configuration */
0356     ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
0357                           &num_configs);
0358     if (ret < 0) {
0359         dev_err(ipctl->dev, "%pOF: could not parse property\n", np);
0360 
0361         return ret;
0362     }
0363 
0364     if (num_configs)
0365         reserve++;
0366 
0367     /* Increase the number of maps to cover this group */
0368     ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps,
0369                     reserve);
0370     if (ret < 0)
0371         goto out;
0372 
0373     /* Associate the group with the function */
0374     ret = pinctrl_utils_add_map_mux(pctldev, map, &reserved_maps, num_maps,
0375                     grp->name, grp->func);
0376     if (ret < 0)
0377         goto out;
0378 
0379     if (num_configs) {
0380         /* Associate the group's pin configuration with the group */
0381         ret = pinctrl_utils_add_map_configs(pctldev, map,
0382                 &reserved_maps, num_maps, grp->name,
0383                 configs, num_configs,
0384                 PIN_MAP_TYPE_CONFIGS_GROUP);
0385         if (ret < 0)
0386             goto out;
0387     }
0388 
0389     dev_dbg(pctldev->dev, "maps: function %s group %s (%d pins)\n",
0390         grp->func, grp->name, grp->npins);
0391 
0392 out:
0393     kfree(configs);
0394 
0395     return ret;
0396 }
0397 
0398 static int rzn1_dt_node_to_map(struct pinctrl_dev *pctldev,
0399                    struct device_node *np,
0400                    struct pinctrl_map **map,
0401                    unsigned int *num_maps)
0402 {
0403     struct device_node *child;
0404     int ret;
0405 
0406     *map = NULL;
0407     *num_maps = 0;
0408 
0409     ret = rzn1_dt_node_to_map_one(pctldev, np, map, num_maps);
0410     if (ret < 0)
0411         return ret;
0412 
0413     for_each_child_of_node(np, child) {
0414         ret = rzn1_dt_node_to_map_one(pctldev, child, map, num_maps);
0415         if (ret < 0) {
0416             of_node_put(child);
0417             return ret;
0418         }
0419     }
0420 
0421     return 0;
0422 }
0423 
0424 static const struct pinctrl_ops rzn1_pctrl_ops = {
0425     .get_groups_count = rzn1_get_groups_count,
0426     .get_group_name = rzn1_get_group_name,
0427     .get_group_pins = rzn1_get_group_pins,
0428     .dt_node_to_map = rzn1_dt_node_to_map,
0429     .dt_free_map = pinctrl_utils_free_map,
0430 };
0431 
0432 static int rzn1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
0433 {
0434     struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0435 
0436     return ipctl->nfunctions;
0437 }
0438 
0439 static const char *rzn1_pmx_get_func_name(struct pinctrl_dev *pctldev,
0440                       unsigned int selector)
0441 {
0442     struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0443 
0444     return ipctl->functions[selector].name;
0445 }
0446 
0447 static int rzn1_pmx_get_groups(struct pinctrl_dev *pctldev,
0448                    unsigned int selector,
0449                    const char * const **groups,
0450                    unsigned int * const num_groups)
0451 {
0452     struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0453 
0454     *groups = ipctl->functions[selector].groups;
0455     *num_groups = ipctl->functions[selector].num_groups;
0456 
0457     return 0;
0458 }
0459 
0460 static int rzn1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
0461             unsigned int group)
0462 {
0463     struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0464     struct rzn1_pin_group *grp = &ipctl->groups[group];
0465     unsigned int i, grp_pins = grp->npins;
0466 
0467     dev_dbg(ipctl->dev, "set mux %s(%d) group %s(%d)\n",
0468         ipctl->functions[selector].name, selector, grp->name, group);
0469 
0470     rzn1_hw_set_lock(ipctl, LOCK_ALL, LOCK_ALL);
0471     for (i = 0; i < grp_pins; i++)
0472         rzn1_set_hw_pin_func(ipctl, grp->pins[i], grp->pin_ids[i], 0);
0473     rzn1_hw_set_lock(ipctl, LOCK_ALL, 0);
0474 
0475     return 0;
0476 }
0477 
0478 static const struct pinmux_ops rzn1_pmx_ops = {
0479     .get_functions_count = rzn1_pmx_get_funcs_count,
0480     .get_function_name = rzn1_pmx_get_func_name,
0481     .get_function_groups = rzn1_pmx_get_groups,
0482     .set_mux = rzn1_set_mux,
0483 };
0484 
0485 static int rzn1_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
0486                 unsigned long *config)
0487 {
0488     struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0489     enum pin_config_param param = pinconf_to_config_param(*config);
0490     static const u32 reg_drive[4] = { 4, 6, 8, 12 };
0491     u32 pull, drive, l1mux;
0492     u32 l1, l2, arg = 0;
0493 
0494     if (pin >= ARRAY_SIZE(ipctl->lev1->conf))
0495         return -EINVAL;
0496 
0497     l1 = readl(&ipctl->lev1->conf[pin]);
0498 
0499     l1mux = l1 & RZN1_L1_FUNC_MASK;
0500     pull = (l1 >> RZN1_L1_PIN_PULL) & 0x3;
0501     drive = (l1 >> RZN1_L1_PIN_DRIVE_STRENGTH) & 0x3;
0502 
0503     switch (param) {
0504     case PIN_CONFIG_BIAS_PULL_UP:
0505         if (pull != RZN1_L1_PIN_PULL_UP)
0506             return -EINVAL;
0507         break;
0508     case PIN_CONFIG_BIAS_PULL_DOWN:
0509         if (pull != RZN1_L1_PIN_PULL_DOWN)
0510             return -EINVAL;
0511         break;
0512     case PIN_CONFIG_BIAS_DISABLE:
0513         if (pull != RZN1_L1_PIN_PULL_NONE)
0514             return -EINVAL;
0515         break;
0516     case PIN_CONFIG_DRIVE_STRENGTH:
0517         arg = reg_drive[drive];
0518         break;
0519     case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
0520         l2 = readl(&ipctl->lev2->conf[pin]);
0521         if (l1mux == RZN1_L1_FUNCTION_L2) {
0522             if (l2 != 0)
0523                 return -EINVAL;
0524         } else if (l1mux != RZN1_FUNC_HIGHZ) {
0525             return -EINVAL;
0526         }
0527         break;
0528     default:
0529         return -ENOTSUPP;
0530     }
0531 
0532     *config = pinconf_to_config_packed(param, arg);
0533 
0534     return 0;
0535 }
0536 
0537 static int rzn1_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
0538                 unsigned long *configs, unsigned int num_configs)
0539 {
0540     struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0541     enum pin_config_param param;
0542     unsigned int i;
0543     u32 l1, l1_cache;
0544     u32 drv;
0545     u32 arg;
0546 
0547     if (pin >= ARRAY_SIZE(ipctl->lev1->conf))
0548         return -EINVAL;
0549 
0550     l1 = readl(&ipctl->lev1->conf[pin]);
0551     l1_cache = l1;
0552 
0553     for (i = 0; i < num_configs; i++) {
0554         param = pinconf_to_config_param(configs[i]);
0555         arg = pinconf_to_config_argument(configs[i]);
0556 
0557         switch (param) {
0558         case PIN_CONFIG_BIAS_PULL_UP:
0559             dev_dbg(ipctl->dev, "set pin %d pull up\n", pin);
0560             l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
0561             l1 |= (RZN1_L1_PIN_PULL_UP << RZN1_L1_PIN_PULL);
0562             break;
0563         case PIN_CONFIG_BIAS_PULL_DOWN:
0564             dev_dbg(ipctl->dev, "set pin %d pull down\n", pin);
0565             l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
0566             l1 |= (RZN1_L1_PIN_PULL_DOWN << RZN1_L1_PIN_PULL);
0567             break;
0568         case PIN_CONFIG_BIAS_DISABLE:
0569             dev_dbg(ipctl->dev, "set pin %d bias off\n", pin);
0570             l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
0571             l1 |= (RZN1_L1_PIN_PULL_NONE << RZN1_L1_PIN_PULL);
0572             break;
0573         case PIN_CONFIG_DRIVE_STRENGTH:
0574             dev_dbg(ipctl->dev, "set pin %d drv %umA\n", pin, arg);
0575             switch (arg) {
0576             case 4:
0577                 drv = RZN1_L1_PIN_DRIVE_STRENGTH_4MA;
0578                 break;
0579             case 6:
0580                 drv = RZN1_L1_PIN_DRIVE_STRENGTH_6MA;
0581                 break;
0582             case 8:
0583                 drv = RZN1_L1_PIN_DRIVE_STRENGTH_8MA;
0584                 break;
0585             case 12:
0586                 drv = RZN1_L1_PIN_DRIVE_STRENGTH_12MA;
0587                 break;
0588             default:
0589                 dev_err(ipctl->dev,
0590                     "Drive strength %umA not supported\n",
0591                     arg);
0592 
0593                 return -EINVAL;
0594             }
0595 
0596             l1 &= ~(0x3 << RZN1_L1_PIN_DRIVE_STRENGTH);
0597             l1 |= (drv << RZN1_L1_PIN_DRIVE_STRENGTH);
0598             break;
0599 
0600         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
0601             dev_dbg(ipctl->dev, "set pin %d High-Z\n", pin);
0602             l1 &= ~RZN1_L1_FUNC_MASK;
0603             l1 |= RZN1_FUNC_HIGHZ;
0604             break;
0605         default:
0606             return -ENOTSUPP;
0607         }
0608     }
0609 
0610     if (l1 != l1_cache) {
0611         rzn1_hw_set_lock(ipctl, LOCK_LEVEL1, LOCK_LEVEL1);
0612         writel(l1, &ipctl->lev1->conf[pin]);
0613         rzn1_hw_set_lock(ipctl, LOCK_LEVEL1, 0);
0614     }
0615 
0616     return 0;
0617 }
0618 
0619 static int rzn1_pinconf_group_get(struct pinctrl_dev *pctldev,
0620                   unsigned int selector,
0621                   unsigned long *config)
0622 {
0623     struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0624     struct rzn1_pin_group *grp = &ipctl->groups[selector];
0625     unsigned long old = 0;
0626     unsigned int i;
0627 
0628     dev_dbg(ipctl->dev, "group get %s selector:%u\n", grp->name, selector);
0629 
0630     for (i = 0; i < grp->npins; i++) {
0631         if (rzn1_pinconf_get(pctldev, grp->pins[i], config))
0632             return -ENOTSUPP;
0633 
0634         /* configs do not match between two pins */
0635         if (i && (old != *config))
0636             return -ENOTSUPP;
0637 
0638         old = *config;
0639     }
0640 
0641     return 0;
0642 }
0643 
0644 static int rzn1_pinconf_group_set(struct pinctrl_dev *pctldev,
0645                   unsigned int selector,
0646                   unsigned long *configs,
0647                   unsigned int num_configs)
0648 {
0649     struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
0650     struct rzn1_pin_group *grp = &ipctl->groups[selector];
0651     unsigned int i;
0652     int ret;
0653 
0654     dev_dbg(ipctl->dev, "group set %s selector:%u configs:%p/%d\n",
0655         grp->name, selector, configs, num_configs);
0656 
0657     for (i = 0; i < grp->npins; i++) {
0658         unsigned int pin = grp->pins[i];
0659 
0660         ret = rzn1_pinconf_set(pctldev, pin, configs, num_configs);
0661         if (ret)
0662             return ret;
0663     }
0664 
0665     return 0;
0666 }
0667 
0668 static const struct pinconf_ops rzn1_pinconf_ops = {
0669     .is_generic = true,
0670     .pin_config_get = rzn1_pinconf_get,
0671     .pin_config_set = rzn1_pinconf_set,
0672     .pin_config_group_get = rzn1_pinconf_group_get,
0673     .pin_config_group_set = rzn1_pinconf_group_set,
0674     .pin_config_config_dbg_show = pinconf_generic_dump_config,
0675 };
0676 
0677 static struct pinctrl_desc rzn1_pinctrl_desc = {
0678     .pctlops = &rzn1_pctrl_ops,
0679     .pmxops = &rzn1_pmx_ops,
0680     .confops = &rzn1_pinconf_ops,
0681     .owner = THIS_MODULE,
0682 };
0683 
0684 static int rzn1_pinctrl_parse_groups(struct device_node *np,
0685                      struct rzn1_pin_group *grp,
0686                      struct rzn1_pinctrl *ipctl)
0687 {
0688     const __be32 *list;
0689     unsigned int i;
0690     int size;
0691 
0692     dev_dbg(ipctl->dev, "%s: %s\n", __func__, np->name);
0693 
0694     /* Initialise group */
0695     grp->name = np->name;
0696 
0697     /*
0698      * The binding format is
0699      *  pinmux = <PIN_FUNC_ID CONFIG ...>,
0700      * do sanity check and calculate pins number
0701      */
0702     list = of_get_property(np, RZN1_PINS_PROP, &size);
0703     if (!list) {
0704         dev_err(ipctl->dev,
0705             "no " RZN1_PINS_PROP " property in node %pOF\n", np);
0706 
0707         return -EINVAL;
0708     }
0709 
0710     if (!size) {
0711         dev_err(ipctl->dev, "Invalid " RZN1_PINS_PROP " in node %pOF\n",
0712             np);
0713 
0714         return -EINVAL;
0715     }
0716 
0717     grp->npins = size / sizeof(list[0]);
0718     grp->pin_ids = devm_kmalloc_array(ipctl->dev,
0719                       grp->npins, sizeof(grp->pin_ids[0]),
0720                       GFP_KERNEL);
0721     grp->pins = devm_kmalloc_array(ipctl->dev,
0722                        grp->npins, sizeof(grp->pins[0]),
0723                        GFP_KERNEL);
0724     if (!grp->pin_ids || !grp->pins)
0725         return -ENOMEM;
0726 
0727     for (i = 0; i < grp->npins; i++) {
0728         u32 pin_id = be32_to_cpu(*list++);
0729 
0730         grp->pins[i] = pin_id & 0xff;
0731         grp->pin_ids[i] = (pin_id >> 8) & 0x7f;
0732     }
0733 
0734     return grp->npins;
0735 }
0736 
0737 static int rzn1_pinctrl_count_function_groups(struct device_node *np)
0738 {
0739     struct device_node *child;
0740     int count = 0;
0741 
0742     if (of_property_count_u32_elems(np, RZN1_PINS_PROP) > 0)
0743         count++;
0744 
0745     for_each_child_of_node(np, child) {
0746         if (of_property_count_u32_elems(child, RZN1_PINS_PROP) > 0)
0747             count++;
0748     }
0749 
0750     return count;
0751 }
0752 
0753 static int rzn1_pinctrl_parse_functions(struct device_node *np,
0754                     struct rzn1_pinctrl *ipctl,
0755                     unsigned int index)
0756 {
0757     struct rzn1_pmx_func *func;
0758     struct rzn1_pin_group *grp;
0759     struct device_node *child;
0760     unsigned int i = 0;
0761     int ret;
0762 
0763     func = &ipctl->functions[index];
0764 
0765     /* Initialise function */
0766     func->name = np->name;
0767     func->num_groups = rzn1_pinctrl_count_function_groups(np);
0768     if (func->num_groups == 0) {
0769         dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
0770         return -EINVAL;
0771     }
0772     dev_dbg(ipctl->dev, "function %s has %d groups\n",
0773         np->name, func->num_groups);
0774 
0775     func->groups = devm_kmalloc_array(ipctl->dev,
0776                       func->num_groups, sizeof(char *),
0777                       GFP_KERNEL);
0778     if (!func->groups)
0779         return -ENOMEM;
0780 
0781     if (of_property_count_u32_elems(np, RZN1_PINS_PROP) > 0) {
0782         func->groups[i] = np->name;
0783         grp = &ipctl->groups[ipctl->ngroups];
0784         grp->func = func->name;
0785         ret = rzn1_pinctrl_parse_groups(np, grp, ipctl);
0786         if (ret < 0)
0787             return ret;
0788         i++;
0789         ipctl->ngroups++;
0790     }
0791 
0792     for_each_child_of_node(np, child) {
0793         func->groups[i] = child->name;
0794         grp = &ipctl->groups[ipctl->ngroups];
0795         grp->func = func->name;
0796         ret = rzn1_pinctrl_parse_groups(child, grp, ipctl);
0797         if (ret < 0) {
0798             of_node_put(child);
0799             return ret;
0800         }
0801         i++;
0802         ipctl->ngroups++;
0803     }
0804 
0805     dev_dbg(ipctl->dev, "function %s parsed %u/%u groups\n",
0806         np->name, i, func->num_groups);
0807 
0808     return 0;
0809 }
0810 
0811 static int rzn1_pinctrl_probe_dt(struct platform_device *pdev,
0812                  struct rzn1_pinctrl *ipctl)
0813 {
0814     struct device_node *np = pdev->dev.of_node;
0815     struct device_node *child;
0816     unsigned int maxgroups = 0;
0817     unsigned int i = 0;
0818     int nfuncs = 0;
0819     int ret;
0820 
0821     nfuncs = of_get_child_count(np);
0822     if (nfuncs <= 0)
0823         return 0;
0824 
0825     ipctl->nfunctions = nfuncs;
0826     ipctl->functions = devm_kmalloc_array(&pdev->dev, nfuncs,
0827                           sizeof(*ipctl->functions),
0828                           GFP_KERNEL);
0829     if (!ipctl->functions)
0830         return -ENOMEM;
0831 
0832     ipctl->ngroups = 0;
0833     for_each_child_of_node(np, child)
0834         maxgroups += rzn1_pinctrl_count_function_groups(child);
0835 
0836     ipctl->groups = devm_kmalloc_array(&pdev->dev,
0837                        maxgroups,
0838                        sizeof(*ipctl->groups),
0839                        GFP_KERNEL);
0840     if (!ipctl->groups)
0841         return -ENOMEM;
0842 
0843     for_each_child_of_node(np, child) {
0844         ret = rzn1_pinctrl_parse_functions(child, ipctl, i++);
0845         if (ret < 0) {
0846             of_node_put(child);
0847             return ret;
0848         }
0849     }
0850 
0851     return 0;
0852 }
0853 
0854 static int rzn1_pinctrl_probe(struct platform_device *pdev)
0855 {
0856     struct rzn1_pinctrl *ipctl;
0857     struct resource *res;
0858     int ret;
0859 
0860     /* Create state holders etc for this driver */
0861     ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
0862     if (!ipctl)
0863         return -ENOMEM;
0864 
0865     ipctl->mdio_func[0] = -1;
0866     ipctl->mdio_func[1] = -1;
0867 
0868     ipctl->lev1 = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
0869     if (IS_ERR(ipctl->lev1))
0870         return PTR_ERR(ipctl->lev1);
0871     ipctl->lev1_protect_phys = (u32)res->start + 0x400;
0872 
0873     ipctl->lev2 = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
0874     if (IS_ERR(ipctl->lev2))
0875         return PTR_ERR(ipctl->lev2);
0876     ipctl->lev2_protect_phys = (u32)res->start + 0x400;
0877 
0878     ipctl->clk = devm_clk_get(&pdev->dev, NULL);
0879     if (IS_ERR(ipctl->clk))
0880         return PTR_ERR(ipctl->clk);
0881     ret = clk_prepare_enable(ipctl->clk);
0882     if (ret)
0883         return ret;
0884 
0885     ipctl->dev = &pdev->dev;
0886     rzn1_pinctrl_desc.name = dev_name(&pdev->dev);
0887     rzn1_pinctrl_desc.pins = rzn1_pins;
0888     rzn1_pinctrl_desc.npins = ARRAY_SIZE(rzn1_pins);
0889 
0890     ret = rzn1_pinctrl_probe_dt(pdev, ipctl);
0891     if (ret) {
0892         dev_err(&pdev->dev, "fail to probe dt properties\n");
0893         goto err_clk;
0894     }
0895 
0896     platform_set_drvdata(pdev, ipctl);
0897 
0898     ret = devm_pinctrl_register_and_init(&pdev->dev, &rzn1_pinctrl_desc,
0899                          ipctl, &ipctl->pctl);
0900     if (ret) {
0901         dev_err(&pdev->dev, "could not register rzn1 pinctrl driver\n");
0902         goto err_clk;
0903     }
0904 
0905     ret = pinctrl_enable(ipctl->pctl);
0906     if (ret)
0907         goto err_clk;
0908 
0909     dev_info(&pdev->dev, "probed\n");
0910 
0911     return 0;
0912 
0913 err_clk:
0914     clk_disable_unprepare(ipctl->clk);
0915 
0916     return ret;
0917 }
0918 
0919 static int rzn1_pinctrl_remove(struct platform_device *pdev)
0920 {
0921     struct rzn1_pinctrl *ipctl = platform_get_drvdata(pdev);
0922 
0923     clk_disable_unprepare(ipctl->clk);
0924 
0925     return 0;
0926 }
0927 
0928 static const struct of_device_id rzn1_pinctrl_match[] = {
0929     { .compatible = "renesas,rzn1-pinctrl", },
0930     {}
0931 };
0932 MODULE_DEVICE_TABLE(of, rzn1_pinctrl_match);
0933 
0934 static struct platform_driver rzn1_pinctrl_driver = {
0935     .probe  = rzn1_pinctrl_probe,
0936     .remove = rzn1_pinctrl_remove,
0937     .driver = {
0938         .name       = "rzn1-pinctrl",
0939         .of_match_table = rzn1_pinctrl_match,
0940     },
0941 };
0942 
0943 static int __init _pinctrl_drv_register(void)
0944 {
0945     return platform_driver_register(&rzn1_pinctrl_driver);
0946 }
0947 subsys_initcall(_pinctrl_drv_register);
0948 
0949 MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
0950 MODULE_DESCRIPTION("Renesas RZ/N1 pinctrl driver");
0951 MODULE_LICENSE("GPL v2");
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