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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC
0004  *
0005  * Copyright (C) 2018 Chris Brandt
0006  */
0007 
0008 /*
0009  * This pin controller/gpio combined driver supports Renesas devices of RZ/A2
0010  * family.
0011  */
0012 
0013 #include <linux/bitops.h>
0014 #include <linux/gpio/driver.h>
0015 #include <linux/io.h>
0016 #include <linux/module.h>
0017 #include <linux/of_device.h>
0018 #include <linux/pinctrl/pinmux.h>
0019 
0020 #include "../core.h"
0021 #include "../pinmux.h"
0022 
0023 #define DRIVER_NAME     "pinctrl-rza2"
0024 
0025 #define RZA2_PINS_PER_PORT  8
0026 #define RZA2_PIN_ID_TO_PORT(id) ((id) / RZA2_PINS_PER_PORT)
0027 #define RZA2_PIN_ID_TO_PIN(id)  ((id) % RZA2_PINS_PER_PORT)
0028 
0029 /*
0030  * Use 16 lower bits [15:0] for pin identifier
0031  * Use 16 higher bits [31:16] for pin mux function
0032  */
0033 #define MUX_PIN_ID_MASK     GENMASK(15, 0)
0034 #define MUX_FUNC_MASK       GENMASK(31, 16)
0035 #define MUX_FUNC_OFFS       16
0036 #define MUX_FUNC(pinconf)   ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
0037 
0038 static const char port_names[] = "0123456789ABCDEFGHJKLM";
0039 
0040 struct rza2_pinctrl_priv {
0041     struct device *dev;
0042     void __iomem *base;
0043 
0044     struct pinctrl_pin_desc *pins;
0045     struct pinctrl_desc desc;
0046     struct pinctrl_dev *pctl;
0047     struct pinctrl_gpio_range gpio_range;
0048     int npins;
0049 };
0050 
0051 #define RZA2_PDR(port)      (0x0000 + (port) * 2)   /* Direction 16-bit */
0052 #define RZA2_PODR(port)     (0x0040 + (port))   /* Output Data 8-bit */
0053 #define RZA2_PIDR(port)     (0x0060 + (port))   /* Input Data 8-bit */
0054 #define RZA2_PMR(port)      (0x0080 + (port))   /* Mode 8-bit */
0055 #define RZA2_DSCR(port)     (0x0140 + (port) * 2)   /* Drive 16-bit */
0056 #define RZA2_PFS(port, pin) (0x0200 + ((port) * 8) + (pin)) /* Fnct 8-bit */
0057 
0058 #define RZA2_PWPR       0x02ff  /* Write Protect 8-bit */
0059 #define RZA2_PFENET     0x0820  /* Ethernet Pins 8-bit */
0060 #define RZA2_PPOC       0x0900  /* Dedicated Pins 32-bit */
0061 #define RZA2_PHMOMO     0x0980  /* Peripheral Pins 32-bit */
0062 #define RZA2_PCKIO      0x09d0  /* CKIO Drive 8-bit */
0063 
0064 #define RZA2_PDR_INPUT      0x02
0065 #define RZA2_PDR_OUTPUT     0x03
0066 #define RZA2_PDR_MASK       0x03
0067 
0068 #define PWPR_B0WI       BIT(7)  /* Bit Write Disable */
0069 #define PWPR_PFSWE      BIT(6)  /* PFS Register Write Enable */
0070 #define PFS_ISEL        BIT(6)  /* Interrupt Select */
0071 
0072 static void rza2_set_pin_function(void __iomem *pfc_base, u8 port, u8 pin,
0073                   u8 func)
0074 {
0075     u16 mask16;
0076     u16 reg16;
0077     u8 reg8;
0078 
0079     /* Set pin to 'Non-use (Hi-z input protection)'  */
0080     reg16 = readw(pfc_base + RZA2_PDR(port));
0081     mask16 = RZA2_PDR_MASK << (pin * 2);
0082     reg16 &= ~mask16;
0083     writew(reg16, pfc_base + RZA2_PDR(port));
0084 
0085     /* Temporarily switch to GPIO */
0086     reg8 = readb(pfc_base + RZA2_PMR(port));
0087     reg8 &= ~BIT(pin);
0088     writeb(reg8, pfc_base + RZA2_PMR(port));
0089 
0090     /* PFS Register Write Protect : OFF */
0091     writeb(0x00, pfc_base + RZA2_PWPR);     /* B0WI=0, PFSWE=0 */
0092     writeb(PWPR_PFSWE, pfc_base + RZA2_PWPR);   /* B0WI=0, PFSWE=1 */
0093 
0094     /* Set Pin function (interrupt disabled, ISEL=0) */
0095     writeb(func, pfc_base + RZA2_PFS(port, pin));
0096 
0097     /* PFS Register Write Protect : ON */
0098     writeb(0x00, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=0 */
0099     writeb(0x80, pfc_base + RZA2_PWPR); /* B0WI=1, PFSWE=0 */
0100 
0101     /* Port Mode  : Peripheral module pin functions */
0102     reg8 = readb(pfc_base + RZA2_PMR(port));
0103     reg8 |= BIT(pin);
0104     writeb(reg8, pfc_base + RZA2_PMR(port));
0105 }
0106 
0107 static void rza2_pin_to_gpio(void __iomem *pfc_base, unsigned int offset,
0108                  u8 dir)
0109 {
0110     u8 port = RZA2_PIN_ID_TO_PORT(offset);
0111     u8 pin = RZA2_PIN_ID_TO_PIN(offset);
0112     u16 mask16;
0113     u16 reg16;
0114 
0115     reg16 = readw(pfc_base + RZA2_PDR(port));
0116     mask16 = RZA2_PDR_MASK << (pin * 2);
0117     reg16 &= ~mask16;
0118 
0119     if (dir)
0120         reg16 |= RZA2_PDR_INPUT << (pin * 2);   /* pin as input */
0121     else
0122         reg16 |= RZA2_PDR_OUTPUT << (pin * 2);  /* pin as output */
0123 
0124     writew(reg16, pfc_base + RZA2_PDR(port));
0125 }
0126 
0127 static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset)
0128 {
0129     struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
0130     u8 port = RZA2_PIN_ID_TO_PORT(offset);
0131     u8 pin = RZA2_PIN_ID_TO_PIN(offset);
0132     u16 reg16;
0133 
0134     reg16 = readw(priv->base + RZA2_PDR(port));
0135     reg16 = (reg16 >> (pin * 2)) & RZA2_PDR_MASK;
0136 
0137     if (reg16 == RZA2_PDR_OUTPUT)
0138         return GPIO_LINE_DIRECTION_OUT;
0139 
0140     if (reg16 == RZA2_PDR_INPUT)
0141         return GPIO_LINE_DIRECTION_IN;
0142 
0143     /*
0144      * This GPIO controller has a default Hi-Z state that is not input or
0145      * output, so force the pin to input now.
0146      */
0147     rza2_pin_to_gpio(priv->base, offset, 1);
0148 
0149     return GPIO_LINE_DIRECTION_IN;
0150 }
0151 
0152 static int rza2_chip_direction_input(struct gpio_chip *chip,
0153                      unsigned int offset)
0154 {
0155     struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
0156 
0157     rza2_pin_to_gpio(priv->base, offset, 1);
0158 
0159     return 0;
0160 }
0161 
0162 static int rza2_chip_get(struct gpio_chip *chip, unsigned int offset)
0163 {
0164     struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
0165     u8 port = RZA2_PIN_ID_TO_PORT(offset);
0166     u8 pin = RZA2_PIN_ID_TO_PIN(offset);
0167 
0168     return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin));
0169 }
0170 
0171 static void rza2_chip_set(struct gpio_chip *chip, unsigned int offset,
0172               int value)
0173 {
0174     struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
0175     u8 port = RZA2_PIN_ID_TO_PORT(offset);
0176     u8 pin = RZA2_PIN_ID_TO_PIN(offset);
0177     u8 new_value;
0178 
0179     new_value = readb(priv->base + RZA2_PODR(port));
0180 
0181     if (value)
0182         new_value |= BIT(pin);
0183     else
0184         new_value &= ~BIT(pin);
0185 
0186     writeb(new_value, priv->base + RZA2_PODR(port));
0187 }
0188 
0189 static int rza2_chip_direction_output(struct gpio_chip *chip,
0190                       unsigned int offset, int val)
0191 {
0192     struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
0193 
0194     rza2_chip_set(chip, offset, val);
0195     rza2_pin_to_gpio(priv->base, offset, 0);
0196 
0197     return 0;
0198 }
0199 
0200 static const char * const rza2_gpio_names[] = {
0201     "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
0202     "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
0203     "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
0204     "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
0205     "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
0206     "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
0207     "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
0208     "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
0209     "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
0210     "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
0211     "PA_0", "PA_1", "PA_2", "PA_3", "PA_4", "PA_5", "PA_6", "PA_7",
0212     "PB_0", "PB_1", "PB_2", "PB_3", "PB_4", "PB_5", "PB_6", "PB_7",
0213     "PC_0", "PC_1", "PC_2", "PC_3", "PC_4", "PC_5", "PC_6", "PC_7",
0214     "PD_0", "PD_1", "PD_2", "PD_3", "PD_4", "PD_5", "PD_6", "PD_7",
0215     "PE_0", "PE_1", "PE_2", "PE_3", "PE_4", "PE_5", "PE_6", "PE_7",
0216     "PF_0", "PF_1", "PF_2", "PF_3", "PF_4", "PF_5", "PF_6", "PF_7",
0217     "PG_0", "PG_1", "PG_2", "PG_3", "PG_4", "PG_5", "PG_6", "PG_7",
0218     "PH_0", "PH_1", "PH_2", "PH_3", "PH_4", "PH_5", "PH_6", "PH_7",
0219     /* port I does not exist */
0220     "PJ_0", "PJ_1", "PJ_2", "PJ_3", "PJ_4", "PJ_5", "PJ_6", "PJ_7",
0221     "PK_0", "PK_1", "PK_2", "PK_3", "PK_4", "PK_5", "PK_6", "PK_7",
0222     "PL_0", "PL_1", "PL_2", "PL_3", "PL_4", "PL_5", "PL_6", "PL_7",
0223     "PM_0", "PM_1", "PM_2", "PM_3", "PM_4", "PM_5", "PM_6", "PM_7",
0224 };
0225 
0226 static struct gpio_chip chip = {
0227     .names = rza2_gpio_names,
0228     .base = -1,
0229     .get_direction = rza2_chip_get_direction,
0230     .direction_input = rza2_chip_direction_input,
0231     .direction_output = rza2_chip_direction_output,
0232     .get = rza2_chip_get,
0233     .set = rza2_chip_set,
0234 };
0235 
0236 static int rza2_gpio_register(struct rza2_pinctrl_priv *priv)
0237 {
0238     struct device_node *np = priv->dev->of_node;
0239     struct of_phandle_args of_args;
0240     int ret;
0241 
0242     chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np);
0243     chip.parent = priv->dev;
0244     chip.ngpio = priv->npins;
0245 
0246     ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
0247                            &of_args);
0248     if (ret) {
0249         dev_err(priv->dev, "Unable to parse gpio-ranges\n");
0250         return ret;
0251     }
0252 
0253     if ((of_args.args[0] != 0) ||
0254         (of_args.args[1] != 0) ||
0255         (of_args.args[2] != priv->npins)) {
0256         dev_err(priv->dev, "gpio-ranges does not match selected SOC\n");
0257         return -EINVAL;
0258     }
0259     priv->gpio_range.id = 0;
0260     priv->gpio_range.pin_base = priv->gpio_range.base = 0;
0261     priv->gpio_range.npins = priv->npins;
0262     priv->gpio_range.name = chip.label;
0263     priv->gpio_range.gc = &chip;
0264 
0265     /* Register our gpio chip with gpiolib */
0266     ret = devm_gpiochip_add_data(priv->dev, &chip, priv);
0267     if (ret)
0268         return ret;
0269 
0270     /* Register pin range with pinctrl core */
0271     pinctrl_add_gpio_range(priv->pctl, &priv->gpio_range);
0272 
0273     dev_dbg(priv->dev, "Registered gpio controller\n");
0274 
0275     return 0;
0276 }
0277 
0278 static int rza2_pinctrl_register(struct rza2_pinctrl_priv *priv)
0279 {
0280     struct pinctrl_pin_desc *pins;
0281     unsigned int i;
0282     int ret;
0283 
0284     pins = devm_kcalloc(priv->dev, priv->npins, sizeof(*pins), GFP_KERNEL);
0285     if (!pins)
0286         return -ENOMEM;
0287 
0288     priv->pins = pins;
0289     priv->desc.pins = pins;
0290     priv->desc.npins = priv->npins;
0291 
0292     for (i = 0; i < priv->npins; i++) {
0293         pins[i].number = i;
0294         pins[i].name = rza2_gpio_names[i];
0295     }
0296 
0297     ret = devm_pinctrl_register_and_init(priv->dev, &priv->desc, priv,
0298                          &priv->pctl);
0299     if (ret) {
0300         dev_err(priv->dev, "pinctrl registration failed\n");
0301         return ret;
0302     }
0303 
0304     ret = pinctrl_enable(priv->pctl);
0305     if (ret) {
0306         dev_err(priv->dev, "pinctrl enable failed\n");
0307         return ret;
0308     }
0309 
0310     ret = rza2_gpio_register(priv);
0311     if (ret) {
0312         dev_err(priv->dev, "GPIO registration failed\n");
0313         return ret;
0314     }
0315 
0316     return 0;
0317 }
0318 
0319 /*
0320  * For each DT node, create a single pin mapping. That pin mapping will only
0321  * contain a single group of pins, and that group of pins will only have a
0322  * single function that can be selected.
0323  */
0324 static int rza2_dt_node_to_map(struct pinctrl_dev *pctldev,
0325                    struct device_node *np,
0326                    struct pinctrl_map **map,
0327                    unsigned int *num_maps)
0328 {
0329     struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0330     unsigned int *pins, *psel_val;
0331     int i, ret, npins, gsel, fsel;
0332     struct property *of_pins;
0333     const char **pin_fn;
0334 
0335     /* Find out how many pins to map */
0336     of_pins = of_find_property(np, "pinmux", NULL);
0337     if (!of_pins) {
0338         dev_info(priv->dev, "Missing pinmux property\n");
0339         return -ENOENT;
0340     }
0341     npins = of_pins->length / sizeof(u32);
0342 
0343     pins = devm_kcalloc(priv->dev, npins, sizeof(*pins), GFP_KERNEL);
0344     psel_val = devm_kcalloc(priv->dev, npins, sizeof(*psel_val),
0345                 GFP_KERNEL);
0346     pin_fn = devm_kzalloc(priv->dev, sizeof(*pin_fn), GFP_KERNEL);
0347     if (!pins || !psel_val || !pin_fn)
0348         return -ENOMEM;
0349 
0350     /* Collect pin locations and mux settings from DT properties */
0351     for (i = 0; i < npins; ++i) {
0352         u32 value;
0353 
0354         ret = of_property_read_u32_index(np, "pinmux", i, &value);
0355         if (ret)
0356             return ret;
0357         pins[i] = value & MUX_PIN_ID_MASK;
0358         psel_val[i] = MUX_FUNC(value);
0359     }
0360 
0361     /* Register a single pin group listing all the pins we read from DT */
0362     gsel = pinctrl_generic_add_group(pctldev, np->name, pins, npins, NULL);
0363     if (gsel < 0)
0364         return gsel;
0365 
0366     /*
0367      * Register a single group function where the 'data' is an array PSEL
0368      * register values read from DT.
0369      */
0370     pin_fn[0] = np->name;
0371     fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
0372                        psel_val);
0373     if (fsel < 0) {
0374         ret = fsel;
0375         goto remove_group;
0376     }
0377 
0378     dev_dbg(priv->dev, "Parsed %pOF with %d pins\n", np, npins);
0379 
0380     /* Create map where to retrieve function and mux settings from */
0381     *num_maps = 0;
0382     *map = kzalloc(sizeof(**map), GFP_KERNEL);
0383     if (!*map) {
0384         ret = -ENOMEM;
0385         goto remove_function;
0386     }
0387 
0388     (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
0389     (*map)->data.mux.group = np->name;
0390     (*map)->data.mux.function = np->name;
0391     *num_maps = 1;
0392 
0393     return 0;
0394 
0395 remove_function:
0396     pinmux_generic_remove_function(pctldev, fsel);
0397 
0398 remove_group:
0399     pinctrl_generic_remove_group(pctldev, gsel);
0400 
0401     dev_err(priv->dev, "Unable to parse DT node %s\n", np->name);
0402 
0403     return ret;
0404 }
0405 
0406 static void rza2_dt_free_map(struct pinctrl_dev *pctldev,
0407                  struct pinctrl_map *map, unsigned int num_maps)
0408 {
0409     kfree(map);
0410 }
0411 
0412 static const struct pinctrl_ops rza2_pinctrl_ops = {
0413     .get_groups_count   = pinctrl_generic_get_group_count,
0414     .get_group_name     = pinctrl_generic_get_group_name,
0415     .get_group_pins     = pinctrl_generic_get_group_pins,
0416     .dt_node_to_map     = rza2_dt_node_to_map,
0417     .dt_free_map        = rza2_dt_free_map,
0418 };
0419 
0420 static int rza2_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
0421             unsigned int group)
0422 {
0423     struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
0424     struct function_desc *func;
0425     unsigned int i, *psel_val;
0426     struct group_desc *grp;
0427 
0428     grp = pinctrl_generic_get_group(pctldev, group);
0429     if (!grp)
0430         return -EINVAL;
0431 
0432     func = pinmux_generic_get_function(pctldev, selector);
0433     if (!func)
0434         return -EINVAL;
0435 
0436     psel_val = func->data;
0437 
0438     for (i = 0; i < grp->num_pins; ++i) {
0439         dev_dbg(priv->dev, "Setting P%c_%d to PSEL=%d\n",
0440             port_names[RZA2_PIN_ID_TO_PORT(grp->pins[i])],
0441             RZA2_PIN_ID_TO_PIN(grp->pins[i]),
0442             psel_val[i]);
0443         rza2_set_pin_function(
0444             priv->base,
0445             RZA2_PIN_ID_TO_PORT(grp->pins[i]),
0446             RZA2_PIN_ID_TO_PIN(grp->pins[i]),
0447             psel_val[i]);
0448     }
0449 
0450     return 0;
0451 }
0452 
0453 static const struct pinmux_ops rza2_pinmux_ops = {
0454     .get_functions_count    = pinmux_generic_get_function_count,
0455     .get_function_name  = pinmux_generic_get_function_name,
0456     .get_function_groups    = pinmux_generic_get_function_groups,
0457     .set_mux        = rza2_set_mux,
0458     .strict         = true,
0459 };
0460 
0461 static int rza2_pinctrl_probe(struct platform_device *pdev)
0462 {
0463     struct rza2_pinctrl_priv *priv;
0464     int ret;
0465 
0466     priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
0467     if (!priv)
0468         return -ENOMEM;
0469 
0470     priv->dev = &pdev->dev;
0471 
0472     priv->base = devm_platform_ioremap_resource(pdev, 0);
0473     if (IS_ERR(priv->base))
0474         return PTR_ERR(priv->base);
0475 
0476     platform_set_drvdata(pdev, priv);
0477 
0478     priv->npins = (int)(uintptr_t)of_device_get_match_data(&pdev->dev) *
0479               RZA2_PINS_PER_PORT;
0480 
0481     priv->desc.name     = DRIVER_NAME;
0482     priv->desc.pctlops  = &rza2_pinctrl_ops;
0483     priv->desc.pmxops   = &rza2_pinmux_ops;
0484     priv->desc.owner    = THIS_MODULE;
0485 
0486     ret = rza2_pinctrl_register(priv);
0487     if (ret)
0488         return ret;
0489 
0490     dev_info(&pdev->dev, "Registered ports P0 - P%c\n",
0491          port_names[priv->desc.npins / RZA2_PINS_PER_PORT - 1]);
0492 
0493     return 0;
0494 }
0495 
0496 static const struct of_device_id rza2_pinctrl_of_match[] = {
0497     { .compatible = "renesas,r7s9210-pinctrl", .data = (void *)22, },
0498     { /* sentinel */ }
0499 };
0500 
0501 static struct platform_driver rza2_pinctrl_driver = {
0502     .driver = {
0503         .name = DRIVER_NAME,
0504         .of_match_table = rza2_pinctrl_of_match,
0505     },
0506     .probe = rza2_pinctrl_probe,
0507 };
0508 
0509 static int __init rza2_pinctrl_init(void)
0510 {
0511     return platform_driver_register(&rza2_pinctrl_driver);
0512 }
0513 core_initcall(rza2_pinctrl_init);
0514 
0515 MODULE_AUTHOR("Chris Brandt <chris.brandt@renesas.com>");
0516 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/A2 SoC");
0517 MODULE_LICENSE("GPL v2");
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