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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
0004  *
0005  * Copyright (C) 2017 Jacopo Mondi
0006  */
0007 
0008 /*
0009  * This pin controller/gpio combined driver supports Renesas devices of RZ/A1
0010  * family.
0011  * This includes SoCs which are sub- or super- sets of this particular line,
0012  * as RZ/A1H (r7s721000), RZ/A1M (r7s721010) and RZ/A1L (r7s721020).
0013  */
0014 
0015 #include <linux/bitops.h>
0016 #include <linux/err.h>
0017 #include <linux/gpio/driver.h>
0018 #include <linux/init.h>
0019 #include <linux/ioport.h>
0020 #include <linux/module.h>
0021 #include <linux/of.h>
0022 #include <linux/of_address.h>
0023 #include <linux/of_device.h>
0024 #include <linux/pinctrl/pinconf-generic.h>
0025 #include <linux/pinctrl/pinctrl.h>
0026 #include <linux/pinctrl/pinmux.h>
0027 #include <linux/property.h>
0028 #include <linux/slab.h>
0029 
0030 #include "../core.h"
0031 #include "../devicetree.h"
0032 #include "../pinconf.h"
0033 #include "../pinmux.h"
0034 
0035 #define DRIVER_NAME         "pinctrl-rza1"
0036 
0037 #define RZA1_P_REG          0x0000
0038 #define RZA1_PPR_REG            0x0200
0039 #define RZA1_PM_REG         0x0300
0040 #define RZA1_PMC_REG            0x0400
0041 #define RZA1_PFC_REG            0x0500
0042 #define RZA1_PFCE_REG           0x0600
0043 #define RZA1_PFCEA_REG          0x0a00
0044 #define RZA1_PIBC_REG           0x4000
0045 #define RZA1_PBDC_REG           0x4100
0046 #define RZA1_PIPC_REG           0x4200
0047 
0048 #define RZA1_ADDR(mem, reg, port)   ((mem) + (reg) + ((port) * 4))
0049 
0050 #define RZA1_NPORTS         12
0051 #define RZA1_PINS_PER_PORT      16
0052 #define RZA1_NPINS          (RZA1_PINS_PER_PORT * RZA1_NPORTS)
0053 #define RZA1_PIN_ID_TO_PORT(id)     ((id) / RZA1_PINS_PER_PORT)
0054 #define RZA1_PIN_ID_TO_PIN(id)      ((id) % RZA1_PINS_PER_PORT)
0055 
0056 /*
0057  * Use 16 lower bits [15:0] for pin identifier
0058  * Use 16 higher bits [31:16] for pin mux function
0059  */
0060 #define MUX_PIN_ID_MASK         GENMASK(15, 0)
0061 #define MUX_FUNC_MASK           GENMASK(31, 16)
0062 
0063 #define MUX_FUNC_OFFS           16
0064 #define MUX_FUNC(pinconf)       \
0065     ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
0066 #define MUX_FUNC_PFC_MASK       BIT(0)
0067 #define MUX_FUNC_PFCE_MASK      BIT(1)
0068 #define MUX_FUNC_PFCEA_MASK     BIT(2)
0069 
0070 /* Pin mux flags */
0071 #define MUX_FLAGS_BIDIR         BIT(0)
0072 #define MUX_FLAGS_SWIO_INPUT        BIT(1)
0073 #define MUX_FLAGS_SWIO_OUTPUT       BIT(2)
0074 
0075 /* ----------------------------------------------------------------------------
0076  * RZ/A1 pinmux flags
0077  */
0078 
0079 /*
0080  * rza1_bidir_pin - describe a single pin that needs bidir flag applied.
0081  */
0082 struct rza1_bidir_pin {
0083     u8 pin: 4;
0084     u8 func: 4;
0085 };
0086 
0087 /*
0088  * rza1_bidir_entry - describe a list of pins that needs bidir flag applied.
0089  *            Each struct rza1_bidir_entry describes a port.
0090  */
0091 struct rza1_bidir_entry {
0092     const unsigned int npins;
0093     const struct rza1_bidir_pin *pins;
0094 };
0095 
0096 /*
0097  * rza1_swio_pin - describe a single pin that needs swio flag applied.
0098  */
0099 struct rza1_swio_pin {
0100     u16 pin: 4;
0101     u16 port: 4;
0102     u16 func: 4;
0103     u16 input: 1;
0104 };
0105 
0106 /*
0107  * rza1_swio_entry - describe a list of pins that needs swio flag applied
0108  */
0109 struct rza1_swio_entry {
0110     const unsigned int npins;
0111     const struct rza1_swio_pin *pins;
0112 };
0113 
0114 /*
0115  * rza1_pinmux_conf - group together bidir and swio pinmux flag tables
0116  */
0117 struct rza1_pinmux_conf {
0118     const struct rza1_bidir_entry *bidir_entries;
0119     const struct rza1_swio_entry *swio_entries;
0120 };
0121 
0122 /* ----------------------------------------------------------------------------
0123  * RZ/A1H (r7s72100) pinmux flags
0124  */
0125 
0126 static const struct rza1_bidir_pin rza1h_bidir_pins_p1[] = {
0127     { .pin = 0, .func = 1 },
0128     { .pin = 1, .func = 1 },
0129     { .pin = 2, .func = 1 },
0130     { .pin = 3, .func = 1 },
0131     { .pin = 4, .func = 1 },
0132     { .pin = 5, .func = 1 },
0133     { .pin = 6, .func = 1 },
0134     { .pin = 7, .func = 1 },
0135 };
0136 
0137 static const struct rza1_bidir_pin rza1h_bidir_pins_p2[] = {
0138     { .pin = 0, .func = 1 },
0139     { .pin = 1, .func = 1 },
0140     { .pin = 2, .func = 1 },
0141     { .pin = 3, .func = 1 },
0142     { .pin = 4, .func = 1 },
0143     { .pin = 0, .func = 4 },
0144     { .pin = 1, .func = 4 },
0145     { .pin = 2, .func = 4 },
0146     { .pin = 3, .func = 4 },
0147     { .pin = 5, .func = 1 },
0148     { .pin = 6, .func = 1 },
0149     { .pin = 7, .func = 1 },
0150     { .pin = 8, .func = 1 },
0151     { .pin = 9, .func = 1 },
0152     { .pin = 10, .func = 1 },
0153     { .pin = 11, .func = 1 },
0154     { .pin = 12, .func = 1 },
0155     { .pin = 13, .func = 1 },
0156     { .pin = 14, .func = 1 },
0157     { .pin = 15, .func = 1 },
0158     { .pin = 12, .func = 4 },
0159     { .pin = 13, .func = 4 },
0160     { .pin = 14, .func = 4 },
0161     { .pin = 15, .func = 4 },
0162 };
0163 
0164 static const struct rza1_bidir_pin rza1h_bidir_pins_p3[] = {
0165     { .pin = 3, .func = 2 },
0166     { .pin = 10, .func = 7 },
0167     { .pin = 11, .func = 7 },
0168     { .pin = 13, .func = 7 },
0169     { .pin = 14, .func = 7 },
0170     { .pin = 15, .func = 7 },
0171     { .pin = 10, .func = 8 },
0172     { .pin = 11, .func = 8 },
0173     { .pin = 13, .func = 8 },
0174     { .pin = 14, .func = 8 },
0175     { .pin = 15, .func = 8 },
0176 };
0177 
0178 static const struct rza1_bidir_pin rza1h_bidir_pins_p4[] = {
0179     { .pin = 0, .func = 8 },
0180     { .pin = 1, .func = 8 },
0181     { .pin = 2, .func = 8 },
0182     { .pin = 3, .func = 8 },
0183     { .pin = 10, .func = 3 },
0184     { .pin = 11, .func = 3 },
0185     { .pin = 13, .func = 3 },
0186     { .pin = 14, .func = 3 },
0187     { .pin = 15, .func = 3 },
0188     { .pin = 10, .func = 4 },
0189     { .pin = 11, .func = 4 },
0190     { .pin = 13, .func = 4 },
0191     { .pin = 14, .func = 4 },
0192     { .pin = 15, .func = 4 },
0193     { .pin = 12, .func = 5 },
0194     { .pin = 13, .func = 5 },
0195     { .pin = 14, .func = 5 },
0196     { .pin = 15, .func = 5 },
0197 };
0198 
0199 static const struct rza1_bidir_pin rza1h_bidir_pins_p6[] = {
0200     { .pin = 0, .func = 1 },
0201     { .pin = 1, .func = 1 },
0202     { .pin = 2, .func = 1 },
0203     { .pin = 3, .func = 1 },
0204     { .pin = 4, .func = 1 },
0205     { .pin = 5, .func = 1 },
0206     { .pin = 6, .func = 1 },
0207     { .pin = 7, .func = 1 },
0208     { .pin = 8, .func = 1 },
0209     { .pin = 9, .func = 1 },
0210     { .pin = 10, .func = 1 },
0211     { .pin = 11, .func = 1 },
0212     { .pin = 12, .func = 1 },
0213     { .pin = 13, .func = 1 },
0214     { .pin = 14, .func = 1 },
0215     { .pin = 15, .func = 1 },
0216 };
0217 
0218 static const struct rza1_bidir_pin rza1h_bidir_pins_p7[] = {
0219     { .pin = 13, .func = 3 },
0220 };
0221 
0222 static const struct rza1_bidir_pin rza1h_bidir_pins_p8[] = {
0223     { .pin = 8, .func = 3 },
0224     { .pin = 9, .func = 3 },
0225     { .pin = 10, .func = 3 },
0226     { .pin = 11, .func = 3 },
0227     { .pin = 14, .func = 2 },
0228     { .pin = 15, .func = 2 },
0229     { .pin = 14, .func = 3 },
0230     { .pin = 15, .func = 3 },
0231 };
0232 
0233 static const struct rza1_bidir_pin rza1h_bidir_pins_p9[] = {
0234     { .pin = 0, .func = 2 },
0235     { .pin = 1, .func = 2 },
0236     { .pin = 4, .func = 2 },
0237     { .pin = 5, .func = 2 },
0238     { .pin = 6, .func = 2 },
0239     { .pin = 7, .func = 2 },
0240 };
0241 
0242 static const struct rza1_bidir_pin rza1h_bidir_pins_p11[] = {
0243     { .pin = 6, .func = 2 },
0244     { .pin = 7, .func = 2 },
0245     { .pin = 9, .func = 2 },
0246     { .pin = 6, .func = 4 },
0247     { .pin = 7, .func = 4 },
0248     { .pin = 9, .func = 4 },
0249     { .pin = 10, .func = 2 },
0250     { .pin = 11, .func = 2 },
0251     { .pin = 10, .func = 4 },
0252     { .pin = 11, .func = 4 },
0253     { .pin = 12, .func = 4 },
0254     { .pin = 13, .func = 4 },
0255     { .pin = 14, .func = 4 },
0256     { .pin = 15, .func = 4 },
0257 };
0258 
0259 static const struct rza1_swio_pin rza1h_swio_pins[] = {
0260     { .port = 2, .pin = 7, .func = 4, .input = 0 },
0261     { .port = 2, .pin = 11, .func = 4, .input = 0 },
0262     { .port = 3, .pin = 7, .func = 3, .input = 0 },
0263     { .port = 3, .pin = 7, .func = 8, .input = 0 },
0264     { .port = 4, .pin = 7, .func = 5, .input = 0 },
0265     { .port = 4, .pin = 7, .func = 11, .input = 0 },
0266     { .port = 4, .pin = 15, .func = 6, .input = 0 },
0267     { .port = 5, .pin = 0, .func = 1, .input = 1 },
0268     { .port = 5, .pin = 1, .func = 1, .input = 1 },
0269     { .port = 5, .pin = 2, .func = 1, .input = 1 },
0270     { .port = 5, .pin = 3, .func = 1, .input = 1 },
0271     { .port = 5, .pin = 4, .func = 1, .input = 1 },
0272     { .port = 5, .pin = 5, .func = 1, .input = 1 },
0273     { .port = 5, .pin = 6, .func = 1, .input = 1 },
0274     { .port = 5, .pin = 7, .func = 1, .input = 1 },
0275     { .port = 7, .pin = 4, .func = 6, .input = 0 },
0276     { .port = 7, .pin = 11, .func = 2, .input = 0 },
0277     { .port = 8, .pin = 10, .func = 8, .input = 0 },
0278     { .port = 10, .pin = 15, .func = 2, .input = 0 },
0279 };
0280 
0281 static const struct rza1_bidir_entry rza1h_bidir_entries[RZA1_NPORTS] = {
0282     [1] = { ARRAY_SIZE(rza1h_bidir_pins_p1), rza1h_bidir_pins_p1 },
0283     [2] = { ARRAY_SIZE(rza1h_bidir_pins_p2), rza1h_bidir_pins_p2 },
0284     [3] = { ARRAY_SIZE(rza1h_bidir_pins_p3), rza1h_bidir_pins_p3 },
0285     [4] = { ARRAY_SIZE(rza1h_bidir_pins_p4), rza1h_bidir_pins_p4 },
0286     [6] = { ARRAY_SIZE(rza1h_bidir_pins_p6), rza1h_bidir_pins_p6 },
0287     [7] = { ARRAY_SIZE(rza1h_bidir_pins_p7), rza1h_bidir_pins_p7 },
0288     [8] = { ARRAY_SIZE(rza1h_bidir_pins_p8), rza1h_bidir_pins_p8 },
0289     [9] = { ARRAY_SIZE(rza1h_bidir_pins_p9), rza1h_bidir_pins_p9 },
0290     [11] = { ARRAY_SIZE(rza1h_bidir_pins_p11), rza1h_bidir_pins_p11 },
0291 };
0292 
0293 static const struct rza1_swio_entry rza1h_swio_entries[] = {
0294     [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },
0295 };
0296 
0297 /* RZ/A1H (r7s72100x) pinmux flags table */
0298 static const struct rza1_pinmux_conf rza1h_pmx_conf = {
0299     .bidir_entries  = rza1h_bidir_entries,
0300     .swio_entries   = rza1h_swio_entries,
0301 };
0302 
0303 /* ----------------------------------------------------------------------------
0304  * RZ/A1L (r7s72102) pinmux flags
0305  */
0306 
0307 static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = {
0308     { .pin = 0, .func = 1 },
0309     { .pin = 1, .func = 1 },
0310     { .pin = 2, .func = 1 },
0311     { .pin = 3, .func = 1 },
0312     { .pin = 4, .func = 1 },
0313     { .pin = 5, .func = 1 },
0314     { .pin = 6, .func = 1 },
0315     { .pin = 7, .func = 1 },
0316 };
0317 
0318 static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = {
0319     { .pin = 0, .func = 2 },
0320     { .pin = 1, .func = 2 },
0321     { .pin = 2, .func = 2 },
0322     { .pin = 4, .func = 2 },
0323     { .pin = 5, .func = 2 },
0324     { .pin = 10, .func = 2 },
0325     { .pin = 11, .func = 2 },
0326     { .pin = 12, .func = 2 },
0327     { .pin = 13, .func = 2 },
0328 };
0329 
0330 static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = {
0331     { .pin = 1, .func = 4 },
0332     { .pin = 2, .func = 2 },
0333     { .pin = 3, .func = 2 },
0334     { .pin = 6, .func = 2 },
0335     { .pin = 7, .func = 2 },
0336 };
0337 
0338 static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = {
0339     { .pin = 0, .func = 1 },
0340     { .pin = 1, .func = 1 },
0341     { .pin = 2, .func = 1 },
0342     { .pin = 3, .func = 1 },
0343     { .pin = 4, .func = 1 },
0344     { .pin = 5, .func = 1 },
0345     { .pin = 6, .func = 1 },
0346     { .pin = 7, .func = 1 },
0347     { .pin = 8, .func = 1 },
0348     { .pin = 9, .func = 1 },
0349     { .pin = 10, .func = 1 },
0350     { .pin = 11, .func = 1 },
0351     { .pin = 12, .func = 1 },
0352     { .pin = 13, .func = 1 },
0353     { .pin = 14, .func = 1 },
0354     { .pin = 15, .func = 1 },
0355     { .pin = 0, .func = 2 },
0356     { .pin = 1, .func = 2 },
0357     { .pin = 2, .func = 2 },
0358     { .pin = 3, .func = 2 },
0359 };
0360 
0361 static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = {
0362     { .pin = 0, .func = 1 },
0363     { .pin = 1, .func = 1 },
0364     { .pin = 2, .func = 1 },
0365     { .pin = 3, .func = 1 },
0366     { .pin = 4, .func = 1 },
0367     { .pin = 5, .func = 1 },
0368     { .pin = 6, .func = 1 },
0369     { .pin = 7, .func = 1 },
0370     { .pin = 8, .func = 1 },
0371     { .pin = 9, .func = 1 },
0372     { .pin = 10, .func = 1 },
0373     { .pin = 11, .func = 1 },
0374     { .pin = 12, .func = 1 },
0375     { .pin = 13, .func = 1 },
0376     { .pin = 14, .func = 1 },
0377     { .pin = 15, .func = 1 },
0378 };
0379 
0380 static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = {
0381     { .pin = 2, .func = 2 },
0382     { .pin = 3, .func = 2 },
0383     { .pin = 5, .func = 2 },
0384     { .pin = 6, .func = 2 },
0385     { .pin = 7, .func = 2 },
0386     { .pin = 2, .func = 3 },
0387     { .pin = 3, .func = 3 },
0388     { .pin = 5, .func = 3 },
0389     { .pin = 6, .func = 3 },
0390     { .pin = 7, .func = 3 },
0391 };
0392 
0393 static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = {
0394     { .pin = 1, .func = 2 },
0395     { .pin = 0, .func = 3 },
0396     { .pin = 1, .func = 3 },
0397     { .pin = 3, .func = 3 },
0398     { .pin = 4, .func = 3 },
0399     { .pin = 5, .func = 3 },
0400 };
0401 
0402 static const struct rza1_swio_pin rza1l_swio_pins[] = {
0403     { .port = 2, .pin = 8, .func = 2, .input = 0 },
0404     { .port = 5, .pin = 6, .func = 3, .input = 0 },
0405     { .port = 6, .pin = 6, .func = 3, .input = 0 },
0406     { .port = 6, .pin = 10, .func = 3, .input = 0 },
0407     { .port = 7, .pin = 10, .func = 2, .input = 0 },
0408     { .port = 8, .pin = 2, .func = 3, .input = 0 },
0409 };
0410 
0411 static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = {
0412     [1] = { ARRAY_SIZE(rza1l_bidir_pins_p1), rza1l_bidir_pins_p1 },
0413     [3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 },
0414     [4] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p4 },
0415     [5] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p5 },
0416     [6] = { ARRAY_SIZE(rza1l_bidir_pins_p6), rza1l_bidir_pins_p6 },
0417     [7] = { ARRAY_SIZE(rza1l_bidir_pins_p7), rza1l_bidir_pins_p7 },
0418     [9] = { ARRAY_SIZE(rza1l_bidir_pins_p9), rza1l_bidir_pins_p9 },
0419 };
0420 
0421 static const struct rza1_swio_entry rza1l_swio_entries[] = {
0422     [0] = { ARRAY_SIZE(rza1l_swio_pins), rza1l_swio_pins },
0423 };
0424 
0425 /* RZ/A1L (r7s72102x) pinmux flags table */
0426 static const struct rza1_pinmux_conf rza1l_pmx_conf = {
0427     .bidir_entries  = rza1l_bidir_entries,
0428     .swio_entries   = rza1l_swio_entries,
0429 };
0430 
0431 /* ----------------------------------------------------------------------------
0432  * RZ/A1 types
0433  */
0434 /**
0435  * struct rza1_mux_conf - describes a pin multiplexing operation
0436  *
0437  * @id: the pin identifier from 0 to RZA1_NPINS
0438  * @port: the port where pin sits on
0439  * @pin: pin id
0440  * @mux_func: alternate function id number
0441  * @mux_flags: alternate function flags
0442  * @value: output value to set the pin to
0443  */
0444 struct rza1_mux_conf {
0445     u16 id;
0446     u8 port;
0447     u8 pin;
0448     u8 mux_func;
0449     u8 mux_flags;
0450     u8 value;
0451 };
0452 
0453 /**
0454  * struct rza1_port - describes a pin port
0455  *
0456  * This is mostly useful to lock register writes per-bank and not globally.
0457  *
0458  * @lock: protect access to HW registers
0459  * @id: port number
0460  * @base: logical address base
0461  * @pins: pins sitting on this port
0462  */
0463 struct rza1_port {
0464     spinlock_t lock;
0465     unsigned int id;
0466     void __iomem *base;
0467     struct pinctrl_pin_desc *pins;
0468 };
0469 
0470 /**
0471  * struct rza1_pinctrl - RZ pincontroller device
0472  *
0473  * @dev: parent device structure
0474  * @mutex: protect [pinctrl|pinmux]_generic functions
0475  * @base: logical address base
0476  * @nport: number of pin controller ports
0477  * @ports: pin controller banks
0478  * @pins: pin array for pinctrl core
0479  * @desc: pincontroller desc for pinctrl core
0480  * @pctl: pinctrl device
0481  * @data: device specific data
0482  */
0483 struct rza1_pinctrl {
0484     struct device *dev;
0485 
0486     struct mutex mutex;
0487 
0488     void __iomem *base;
0489 
0490     unsigned int nport;
0491     struct rza1_port *ports;
0492 
0493     struct pinctrl_pin_desc *pins;
0494     struct pinctrl_desc desc;
0495     struct pinctrl_dev *pctl;
0496 
0497     const void *data;
0498 };
0499 
0500 /* ----------------------------------------------------------------------------
0501  * RZ/A1 pinmux flags
0502  */
0503 static inline bool rza1_pinmux_get_bidir(unsigned int port,
0504                      unsigned int pin,
0505                      unsigned int func,
0506                      const struct rza1_bidir_entry *table)
0507 {
0508     const struct rza1_bidir_entry *entry = &table[port];
0509     const struct rza1_bidir_pin *bidir_pin;
0510     unsigned int i;
0511 
0512     for (i = 0; i < entry->npins; ++i) {
0513         bidir_pin = &entry->pins[i];
0514         if (bidir_pin->pin == pin && bidir_pin->func == func)
0515             return true;
0516     }
0517 
0518     return false;
0519 }
0520 
0521 static inline int rza1_pinmux_get_swio(unsigned int port,
0522                        unsigned int pin,
0523                        unsigned int func,
0524                        const struct rza1_swio_entry *table)
0525 {
0526     const struct rza1_swio_pin *swio_pin;
0527     unsigned int i;
0528 
0529 
0530     for (i = 0; i < table->npins; ++i) {
0531         swio_pin = &table->pins[i];
0532         if (swio_pin->port == port && swio_pin->pin == pin &&
0533             swio_pin->func == func)
0534             return swio_pin->input;
0535     }
0536 
0537     return -ENOENT;
0538 }
0539 
0540 /*
0541  * rza1_pinmux_get_flags() - return pinmux flags associated to a pin
0542  */
0543 static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin,
0544                       unsigned int func,
0545                       struct rza1_pinctrl *rza1_pctl)
0546 
0547 {
0548     const struct rza1_pinmux_conf *pmx_conf = rza1_pctl->data;
0549     const struct rza1_bidir_entry *bidir_entries = pmx_conf->bidir_entries;
0550     const struct rza1_swio_entry *swio_entries = pmx_conf->swio_entries;
0551     unsigned int pmx_flags = 0;
0552     int ret;
0553 
0554     if (rza1_pinmux_get_bidir(port, pin, func, bidir_entries))
0555         pmx_flags |= MUX_FLAGS_BIDIR;
0556 
0557     ret = rza1_pinmux_get_swio(port, pin, func, swio_entries);
0558     if (ret == 0)
0559         pmx_flags |= MUX_FLAGS_SWIO_OUTPUT;
0560     else if (ret > 0)
0561         pmx_flags |= MUX_FLAGS_SWIO_INPUT;
0562 
0563     return pmx_flags;
0564 }
0565 
0566 /* ----------------------------------------------------------------------------
0567  * RZ/A1 SoC operations
0568  */
0569 
0570 /*
0571  * rza1_set_bit() - un-locked set/clear a single bit in pin configuration
0572  *          registers
0573  */
0574 static inline void rza1_set_bit(struct rza1_port *port, unsigned int reg,
0575                 unsigned int bit, bool set)
0576 {
0577     void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
0578     u16 val = ioread16(mem);
0579 
0580     if (set)
0581         val |= BIT(bit);
0582     else
0583         val &= ~BIT(bit);
0584 
0585     iowrite16(val, mem);
0586 }
0587 
0588 static inline unsigned int rza1_get_bit(struct rza1_port *port,
0589                     unsigned int reg, unsigned int bit)
0590 {
0591     void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
0592 
0593     return ioread16(mem) & BIT(bit);
0594 }
0595 
0596 /**
0597  * rza1_pin_reset() - reset a pin to default initial state
0598  *
0599  * Reset pin state disabling input buffer and bi-directional control,
0600  * and configure it as input port.
0601  * Note that pin is now configured with direction as input but with input
0602  * buffer disabled. This implies the pin value cannot be read in this state.
0603  *
0604  * @port: port where pin sits on
0605  * @pin: pin offset
0606  */
0607 static void rza1_pin_reset(struct rza1_port *port, unsigned int pin)
0608 {
0609     unsigned long irqflags;
0610 
0611     spin_lock_irqsave(&port->lock, irqflags);
0612     rza1_set_bit(port, RZA1_PIBC_REG, pin, 0);
0613     rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
0614 
0615     rza1_set_bit(port, RZA1_PM_REG, pin, 1);
0616     rza1_set_bit(port, RZA1_PMC_REG, pin, 0);
0617     rza1_set_bit(port, RZA1_PIPC_REG, pin, 0);
0618     spin_unlock_irqrestore(&port->lock, irqflags);
0619 }
0620 
0621 /**
0622  * rza1_pin_set_direction() - set I/O direction on a pin in port mode
0623  *
0624  * When running in output port mode keep PBDC enabled to allow reading the
0625  * pin value from PPR.
0626  *
0627  * @port: port where pin sits on
0628  * @pin: pin offset
0629  * @input: input enable/disable flag
0630  */
0631 static inline void rza1_pin_set_direction(struct rza1_port *port,
0632                       unsigned int pin, bool input)
0633 {
0634     unsigned long irqflags;
0635 
0636     spin_lock_irqsave(&port->lock, irqflags);
0637 
0638     rza1_set_bit(port, RZA1_PIBC_REG, pin, 1);
0639     if (input) {
0640         rza1_set_bit(port, RZA1_PM_REG, pin, 1);
0641         rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
0642     } else {
0643         rza1_set_bit(port, RZA1_PM_REG, pin, 0);
0644         rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
0645     }
0646 
0647     spin_unlock_irqrestore(&port->lock, irqflags);
0648 }
0649 
0650 static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin,
0651                 unsigned int value)
0652 {
0653     unsigned long irqflags;
0654 
0655     spin_lock_irqsave(&port->lock, irqflags);
0656     rza1_set_bit(port, RZA1_P_REG, pin, !!value);
0657     spin_unlock_irqrestore(&port->lock, irqflags);
0658 }
0659 
0660 static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin)
0661 {
0662     return rza1_get_bit(port, RZA1_PPR_REG, pin);
0663 }
0664 
0665 /**
0666  * rza1_pin_mux_single() - configure pin multiplexing on a single pin
0667  *
0668  * @rza1_pctl: RZ/A1 pin controller device
0669  * @mux_conf: pin multiplexing descriptor
0670  */
0671 static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl,
0672                    struct rza1_mux_conf *mux_conf)
0673 {
0674     struct rza1_port *port = &rza1_pctl->ports[mux_conf->port];
0675     unsigned int pin = mux_conf->pin;
0676     u8 mux_func = mux_conf->mux_func;
0677     u8 mux_flags = mux_conf->mux_flags;
0678     u8 mux_flags_from_table;
0679 
0680     rza1_pin_reset(port, pin);
0681 
0682     /* SWIO pinmux flags coming from DT are high precedence */
0683     mux_flags_from_table = rza1_pinmux_get_flags(port->id, pin, mux_func,
0684                              rza1_pctl);
0685     if (mux_flags)
0686         mux_flags |= (mux_flags_from_table & MUX_FLAGS_BIDIR);
0687     else
0688         mux_flags = mux_flags_from_table;
0689 
0690     if (mux_flags & MUX_FLAGS_BIDIR)
0691         rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
0692 
0693     /*
0694      * Enable alternate function mode and select it.
0695      *
0696      * Be careful here: the pin mux sub-nodes in device tree
0697      * enumerate alternate functions from 1 to 8;
0698      * subtract 1 before using macros to match registers configuration
0699      * which expects numbers from 0 to 7 instead.
0700      *
0701      * ----------------------------------------------------
0702      * Alternate mode selection table:
0703      *
0704      * PMC  PFC PFCE    PFCAE   (mux_func - 1)
0705      * 1    0   0   0   0
0706      * 1    1   0   0   1
0707      * 1    0   1   0   2
0708      * 1    1   1   0   3
0709      * 1    0   0   1   4
0710      * 1    1   0   1   5
0711      * 1    0   1   1   6
0712      * 1    1   1   1   7
0713      * ----------------------------------------------------
0714      */
0715     mux_func -= 1;
0716     rza1_set_bit(port, RZA1_PFC_REG, pin, mux_func & MUX_FUNC_PFC_MASK);
0717     rza1_set_bit(port, RZA1_PFCE_REG, pin, mux_func & MUX_FUNC_PFCE_MASK);
0718     rza1_set_bit(port, RZA1_PFCEA_REG, pin, mux_func & MUX_FUNC_PFCEA_MASK);
0719 
0720     /*
0721      * All alternate functions except a few need PIPCn = 1.
0722      * If PIPCn has to stay disabled (SW IO mode), configure PMn according
0723      * to I/O direction specified by pin configuration -after- PMC has been
0724      * set to one.
0725      */
0726     if (mux_flags & (MUX_FLAGS_SWIO_INPUT | MUX_FLAGS_SWIO_OUTPUT))
0727         rza1_set_bit(port, RZA1_PM_REG, pin,
0728                  mux_flags & MUX_FLAGS_SWIO_INPUT);
0729     else
0730         rza1_set_bit(port, RZA1_PIPC_REG, pin, 1);
0731 
0732     rza1_set_bit(port, RZA1_PMC_REG, pin, 1);
0733 
0734     return 0;
0735 }
0736 
0737 /* ----------------------------------------------------------------------------
0738  * gpio operations
0739  */
0740 
0741 /**
0742  * rza1_gpio_request() - configure pin in port mode
0743  *
0744  * Configure a pin as gpio (port mode).
0745  * After reset, the pin is in input mode with input buffer disabled.
0746  * To use the pin as input or output, set_direction shall be called first
0747  *
0748  * @chip: gpio chip where the gpio sits on
0749  * @gpio: gpio offset
0750  */
0751 static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio)
0752 {
0753     struct rza1_port *port = gpiochip_get_data(chip);
0754 
0755     rza1_pin_reset(port, gpio);
0756 
0757     return 0;
0758 }
0759 
0760 /**
0761  * rza1_gpio_free() - reset a pin
0762  *
0763  * Surprisingly, freeing a gpio is equivalent to requesting it.
0764  * Reset pin to port mode, with input buffer disabled. This overwrites all
0765  * port direction settings applied with set_direction
0766  *
0767  * @chip: gpio chip where the gpio sits on
0768  * @gpio: gpio offset
0769  */
0770 static void rza1_gpio_free(struct gpio_chip *chip, unsigned int gpio)
0771 {
0772     struct rza1_port *port = gpiochip_get_data(chip);
0773 
0774     rza1_pin_reset(port, gpio);
0775 }
0776 
0777 static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
0778 {
0779     struct rza1_port *port = gpiochip_get_data(chip);
0780 
0781     if (rza1_get_bit(port, RZA1_PM_REG, gpio))
0782         return GPIO_LINE_DIRECTION_IN;
0783 
0784     return GPIO_LINE_DIRECTION_OUT;
0785 }
0786 
0787 static int rza1_gpio_direction_input(struct gpio_chip *chip,
0788                      unsigned int gpio)
0789 {
0790     struct rza1_port *port = gpiochip_get_data(chip);
0791 
0792     rza1_pin_set_direction(port, gpio, true);
0793 
0794     return 0;
0795 }
0796 
0797 static int rza1_gpio_direction_output(struct gpio_chip *chip,
0798                       unsigned int gpio,
0799                       int value)
0800 {
0801     struct rza1_port *port = gpiochip_get_data(chip);
0802 
0803     /* Set value before driving pin direction */
0804     rza1_pin_set(port, gpio, value);
0805     rza1_pin_set_direction(port, gpio, false);
0806 
0807     return 0;
0808 }
0809 
0810 /**
0811  * rza1_gpio_get() - read a gpio pin value
0812  *
0813  * Read gpio pin value through PPR register.
0814  * Requires bi-directional mode to work when reading the value of a pin
0815  * in output mode
0816  *
0817  * @chip: gpio chip where the gpio sits on
0818  * @gpio: gpio offset
0819  */
0820 static int rza1_gpio_get(struct gpio_chip *chip, unsigned int gpio)
0821 {
0822     struct rza1_port *port = gpiochip_get_data(chip);
0823 
0824     return rza1_pin_get(port, gpio);
0825 }
0826 
0827 static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio,
0828               int value)
0829 {
0830     struct rza1_port *port = gpiochip_get_data(chip);
0831 
0832     rza1_pin_set(port, gpio, value);
0833 }
0834 
0835 static const struct gpio_chip rza1_gpiochip_template = {
0836     .request        = rza1_gpio_request,
0837     .free           = rza1_gpio_free,
0838     .get_direction      = rza1_gpio_get_direction,
0839     .direction_input    = rza1_gpio_direction_input,
0840     .direction_output   = rza1_gpio_direction_output,
0841     .get            = rza1_gpio_get,
0842     .set            = rza1_gpio_set,
0843 };
0844 /* ----------------------------------------------------------------------------
0845  * pinctrl operations
0846  */
0847 
0848 /**
0849  * rza1_dt_node_pin_count() - Count number of pins in a dt node or in all its
0850  *                children sub-nodes
0851  *
0852  * @np: device tree node to parse
0853  */
0854 static int rza1_dt_node_pin_count(struct device_node *np)
0855 {
0856     struct device_node *child;
0857     struct property *of_pins;
0858     unsigned int npins;
0859 
0860     of_pins = of_find_property(np, "pinmux", NULL);
0861     if (of_pins)
0862         return of_pins->length / sizeof(u32);
0863 
0864     npins = 0;
0865     for_each_child_of_node(np, child) {
0866         of_pins = of_find_property(child, "pinmux", NULL);
0867         if (!of_pins) {
0868             of_node_put(child);
0869             return -EINVAL;
0870         }
0871 
0872         npins += of_pins->length / sizeof(u32);
0873     }
0874 
0875     return npins;
0876 }
0877 
0878 /**
0879  * rza1_parse_pinmux_node() - parse a pin mux sub-node
0880  *
0881  * @rza1_pctl: RZ/A1 pin controller device
0882  * @np: of pmx sub-node
0883  * @mux_confs: array of pin mux configurations to fill with parsed info
0884  * @grpins: array of pin ids to mux
0885  */
0886 static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl,
0887                   struct device_node *np,
0888                   struct rza1_mux_conf *mux_confs,
0889                   unsigned int *grpins)
0890 {
0891     struct pinctrl_dev *pctldev = rza1_pctl->pctl;
0892     char const *prop_name = "pinmux";
0893     unsigned long *pin_configs;
0894     unsigned int npin_configs;
0895     struct property *of_pins;
0896     unsigned int npins;
0897     u8 pinmux_flags;
0898     unsigned int i;
0899     int ret;
0900 
0901     of_pins = of_find_property(np, prop_name, NULL);
0902     if (!of_pins) {
0903         dev_dbg(rza1_pctl->dev, "Missing %s property\n", prop_name);
0904         return -ENOENT;
0905     }
0906     npins = of_pins->length / sizeof(u32);
0907 
0908     /*
0909      * Collect pin configuration properties: they apply to all pins in
0910      * this sub-node
0911      */
0912     ret = pinconf_generic_parse_dt_config(np, pctldev, &pin_configs,
0913                           &npin_configs);
0914     if (ret) {
0915         dev_err(rza1_pctl->dev,
0916             "Unable to parse pin configuration options for %pOFn\n",
0917             np);
0918         return ret;
0919     }
0920 
0921     /*
0922      * Create a mask with pinmux flags from pin configuration;
0923      * very few pins (TIOC[0-4][A|B|C|D] require SWIO direction
0924      * specified in device tree.
0925      */
0926     pinmux_flags = 0;
0927     for (i = 0; i < npin_configs && pinmux_flags == 0; i++)
0928         switch (pinconf_to_config_param(pin_configs[i])) {
0929         case PIN_CONFIG_INPUT_ENABLE:
0930             pinmux_flags |= MUX_FLAGS_SWIO_INPUT;
0931             break;
0932         case PIN_CONFIG_OUTPUT: /* for DT backwards compatibility */
0933         case PIN_CONFIG_OUTPUT_ENABLE:
0934             pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT;
0935             break;
0936         default:
0937             break;
0938 
0939         }
0940 
0941     kfree(pin_configs);
0942 
0943     /* Collect pin positions and their mux settings. */
0944     for (i = 0; i < npins; ++i) {
0945         u32 of_pinconf;
0946         struct rza1_mux_conf *mux_conf = &mux_confs[i];
0947 
0948         ret = of_property_read_u32_index(np, prop_name, i, &of_pinconf);
0949         if (ret)
0950             return ret;
0951 
0952         mux_conf->id        = of_pinconf & MUX_PIN_ID_MASK;
0953         mux_conf->port      = RZA1_PIN_ID_TO_PORT(mux_conf->id);
0954         mux_conf->pin       = RZA1_PIN_ID_TO_PIN(mux_conf->id);
0955         mux_conf->mux_func  = MUX_FUNC(of_pinconf);
0956         mux_conf->mux_flags = pinmux_flags;
0957 
0958         if (mux_conf->port >= RZA1_NPORTS ||
0959             mux_conf->pin >= RZA1_PINS_PER_PORT) {
0960             dev_err(rza1_pctl->dev,
0961                 "Wrong port %u pin %u for %s property\n",
0962                 mux_conf->port, mux_conf->pin, prop_name);
0963             return -EINVAL;
0964         }
0965 
0966         grpins[i] = mux_conf->id;
0967     }
0968 
0969     return npins;
0970 }
0971 
0972 /**
0973  * rza1_dt_node_to_map() - map a pin mux node to a function/group
0974  *
0975  * Parse and register a pin mux function.
0976  *
0977  * @pctldev: pin controller device
0978  * @np: device tree node to parse
0979  * @map: pointer to pin map (output)
0980  * @num_maps: number of collected maps (output)
0981  */
0982 static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev,
0983                    struct device_node *np,
0984                    struct pinctrl_map **map,
0985                    unsigned int *num_maps)
0986 {
0987     struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
0988     struct rza1_mux_conf *mux_confs, *mux_conf;
0989     unsigned int *grpins, *grpin;
0990     struct device_node *child;
0991     const char *grpname;
0992     const char **fngrps;
0993     int ret, npins;
0994     int gsel, fsel;
0995 
0996     npins = rza1_dt_node_pin_count(np);
0997     if (npins < 0) {
0998         dev_err(rza1_pctl->dev, "invalid pinmux node structure\n");
0999         return -EINVAL;
1000     }
1001 
1002     /*
1003      * Functions are made of 1 group only;
1004      * in fact, functions and groups are identical for this pin controller
1005      * except that functions carry an array of per-pin mux configuration
1006      * settings.
1007      */
1008     mux_confs = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*mux_confs),
1009                  GFP_KERNEL);
1010     grpins = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*grpins),
1011                   GFP_KERNEL);
1012     fngrps = devm_kzalloc(rza1_pctl->dev, sizeof(*fngrps), GFP_KERNEL);
1013 
1014     if (!mux_confs || !grpins || !fngrps)
1015         return -ENOMEM;
1016 
1017     /*
1018      * Parse the pinmux node.
1019      * If the node does not contain "pinmux" property (-ENOENT)
1020      * that property shall be specified in all its children sub-nodes.
1021      */
1022     mux_conf = &mux_confs[0];
1023     grpin = &grpins[0];
1024 
1025     ret = rza1_parse_pinmux_node(rza1_pctl, np, mux_conf, grpin);
1026     if (ret == -ENOENT)
1027         for_each_child_of_node(np, child) {
1028             ret = rza1_parse_pinmux_node(rza1_pctl, child, mux_conf,
1029                              grpin);
1030             if (ret < 0) {
1031                 of_node_put(child);
1032                 return ret;
1033             }
1034 
1035             grpin += ret;
1036             mux_conf += ret;
1037         }
1038     else if (ret < 0)
1039         return ret;
1040 
1041     /* Register pin group and function name to pinctrl_generic */
1042     grpname = np->name;
1043     fngrps[0] = grpname;
1044 
1045     mutex_lock(&rza1_pctl->mutex);
1046     gsel = pinctrl_generic_add_group(pctldev, grpname, grpins, npins,
1047                      NULL);
1048     if (gsel < 0) {
1049         mutex_unlock(&rza1_pctl->mutex);
1050         return gsel;
1051     }
1052 
1053     fsel = pinmux_generic_add_function(pctldev, grpname, fngrps, 1,
1054                        mux_confs);
1055     if (fsel < 0) {
1056         ret = fsel;
1057         goto remove_group;
1058     }
1059 
1060     dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n",
1061                  grpname, npins);
1062 
1063     /* Create map where to retrieve function and mux settings from */
1064     *num_maps = 0;
1065     *map = kzalloc(sizeof(**map), GFP_KERNEL);
1066     if (!*map) {
1067         ret = -ENOMEM;
1068         goto remove_function;
1069     }
1070 
1071     (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1072     (*map)->data.mux.group = np->name;
1073     (*map)->data.mux.function = np->name;
1074     *num_maps = 1;
1075     mutex_unlock(&rza1_pctl->mutex);
1076 
1077     return 0;
1078 
1079 remove_function:
1080     pinmux_generic_remove_function(pctldev, fsel);
1081 
1082 remove_group:
1083     pinctrl_generic_remove_group(pctldev, gsel);
1084     mutex_unlock(&rza1_pctl->mutex);
1085 
1086     dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n",
1087                  grpname);
1088 
1089     return ret;
1090 }
1091 
1092 static void rza1_dt_free_map(struct pinctrl_dev *pctldev,
1093                  struct pinctrl_map *map, unsigned int num_maps)
1094 {
1095     kfree(map);
1096 }
1097 
1098 static const struct pinctrl_ops rza1_pinctrl_ops = {
1099     .get_groups_count   = pinctrl_generic_get_group_count,
1100     .get_group_name     = pinctrl_generic_get_group_name,
1101     .get_group_pins     = pinctrl_generic_get_group_pins,
1102     .dt_node_to_map     = rza1_dt_node_to_map,
1103     .dt_free_map        = rza1_dt_free_map,
1104 };
1105 
1106 /* ----------------------------------------------------------------------------
1107  * pinmux operations
1108  */
1109 
1110 /**
1111  * rza1_set_mux() - retrieve pins from a group and apply their mux settings
1112  *
1113  * @pctldev: pin controller device
1114  * @selector: function selector
1115  * @group: group selector
1116  */
1117 static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
1118                unsigned int group)
1119 {
1120     struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
1121     struct rza1_mux_conf *mux_confs;
1122     struct function_desc *func;
1123     struct group_desc *grp;
1124     int i;
1125 
1126     grp = pinctrl_generic_get_group(pctldev, group);
1127     if (!grp)
1128         return -EINVAL;
1129 
1130     func = pinmux_generic_get_function(pctldev, selector);
1131     if (!func)
1132         return -EINVAL;
1133 
1134     mux_confs = (struct rza1_mux_conf *)func->data;
1135     for (i = 0; i < grp->num_pins; ++i) {
1136         int ret;
1137 
1138         ret = rza1_pin_mux_single(rza1_pctl, &mux_confs[i]);
1139         if (ret)
1140             return ret;
1141     }
1142 
1143     return 0;
1144 }
1145 
1146 static const struct pinmux_ops rza1_pinmux_ops = {
1147     .get_functions_count    = pinmux_generic_get_function_count,
1148     .get_function_name  = pinmux_generic_get_function_name,
1149     .get_function_groups    = pinmux_generic_get_function_groups,
1150     .set_mux        = rza1_set_mux,
1151     .strict         = true,
1152 };
1153 
1154 /* ----------------------------------------------------------------------------
1155  * RZ/A1 pin controller driver operations
1156  */
1157 
1158 /**
1159  * rza1_parse_gpiochip() - parse and register a gpio chip and pin range
1160  *
1161  * The gpio controller subnode shall provide a "gpio-ranges" list property as
1162  * defined by gpio device tree binding documentation.
1163  *
1164  * @rza1_pctl: RZ/A1 pin controller device
1165  * @fwnode: gpio-controller firmware node
1166  * @chip: gpio chip to register to gpiolib
1167  * @range: pin range to register to pinctrl core
1168  */
1169 static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl,
1170                    struct fwnode_handle *fwnode,
1171                    struct gpio_chip *chip,
1172                    struct pinctrl_gpio_range *range)
1173 {
1174     const char *list_name = "gpio-ranges";
1175     struct fwnode_reference_args args;
1176     unsigned int gpioport;
1177     u32 pinctrl_base;
1178     int ret;
1179 
1180     ret = fwnode_property_get_reference_args(fwnode, list_name, NULL, 3, 0, &args);
1181     if (ret) {
1182         dev_err(rza1_pctl->dev, "Unable to parse %s list property\n",
1183             list_name);
1184         return ret;
1185     }
1186 
1187     /*
1188      * Find out on which port this gpio-chip maps to by inspecting the
1189      * second argument of the "gpio-ranges" property.
1190      */
1191     pinctrl_base = args.args[1];
1192     gpioport = RZA1_PIN_ID_TO_PORT(pinctrl_base);
1193     if (gpioport >= RZA1_NPORTS) {
1194         dev_err(rza1_pctl->dev,
1195             "Invalid values in property %s\n", list_name);
1196         return -EINVAL;
1197     }
1198 
1199     *chip       = rza1_gpiochip_template;
1200     chip->base  = -1;
1201     chip->ngpio = args.args[2];
1202     chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%pfwP", fwnode);
1203     if (!chip->label)
1204         return -ENOMEM;
1205 
1206     chip->fwnode    = fwnode;
1207     chip->parent    = rza1_pctl->dev;
1208 
1209     range->id   = gpioport;
1210     range->name = chip->label;
1211     range->pin_base = range->base = pinctrl_base;
1212     range->npins    = args.args[2];
1213     range->gc   = chip;
1214 
1215     ret = devm_gpiochip_add_data(rza1_pctl->dev, chip,
1216                      &rza1_pctl->ports[gpioport]);
1217     if (ret)
1218         return ret;
1219 
1220     pinctrl_add_gpio_range(rza1_pctl->pctl, range);
1221 
1222     dev_dbg(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n",
1223         chip->label, chip->ngpio);
1224 
1225     return 0;
1226 }
1227 
1228 /**
1229  * rza1_gpio_register() - parse DT to collect gpio-chips and gpio-ranges
1230  *
1231  * @rza1_pctl: RZ/A1 pin controller device
1232  */
1233 static int rza1_gpio_register(struct rza1_pinctrl *rza1_pctl)
1234 {
1235     struct pinctrl_gpio_range *gpio_ranges;
1236     struct gpio_chip *gpio_chips;
1237     struct fwnode_handle *child;
1238     unsigned int ngpiochips;
1239     unsigned int i;
1240     int ret;
1241 
1242     ngpiochips = gpiochip_node_count(rza1_pctl->dev);
1243     if (ngpiochips == 0) {
1244         dev_dbg(rza1_pctl->dev, "No gpiochip registered\n");
1245         return 0;
1246     }
1247 
1248     gpio_chips = devm_kcalloc(rza1_pctl->dev, ngpiochips,
1249                   sizeof(*gpio_chips), GFP_KERNEL);
1250     gpio_ranges = devm_kcalloc(rza1_pctl->dev, ngpiochips,
1251                    sizeof(*gpio_ranges), GFP_KERNEL);
1252     if (!gpio_chips || !gpio_ranges)
1253         return -ENOMEM;
1254 
1255     i = 0;
1256     for_each_gpiochip_node(rza1_pctl->dev, child) {
1257         ret = rza1_parse_gpiochip(rza1_pctl, child, &gpio_chips[i],
1258                       &gpio_ranges[i]);
1259         if (ret) {
1260             fwnode_handle_put(child);
1261             return ret;
1262         }
1263 
1264         ++i;
1265     }
1266 
1267     dev_info(rza1_pctl->dev, "Registered %u gpio controllers\n", i);
1268 
1269     return 0;
1270 }
1271 
1272 /**
1273  * rza1_pinctrl_register() - Enumerate pins, ports and gpiochips; register
1274  *               them to pinctrl and gpio cores.
1275  *
1276  * @rza1_pctl: RZ/A1 pin controller device
1277  */
1278 static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl)
1279 {
1280     struct pinctrl_pin_desc *pins;
1281     struct rza1_port *ports;
1282     unsigned int i;
1283     int ret;
1284 
1285     pins = devm_kcalloc(rza1_pctl->dev, RZA1_NPINS, sizeof(*pins),
1286                 GFP_KERNEL);
1287     ports = devm_kcalloc(rza1_pctl->dev, RZA1_NPORTS, sizeof(*ports),
1288                  GFP_KERNEL);
1289     if (!pins || !ports)
1290         return -ENOMEM;
1291 
1292     rza1_pctl->pins     = pins;
1293     rza1_pctl->desc.pins    = pins;
1294     rza1_pctl->desc.npins   = RZA1_NPINS;
1295     rza1_pctl->ports    = ports;
1296 
1297     for (i = 0; i < RZA1_NPINS; ++i) {
1298         unsigned int pin = RZA1_PIN_ID_TO_PIN(i);
1299         unsigned int port = RZA1_PIN_ID_TO_PORT(i);
1300 
1301         pins[i].number = i;
1302         pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL,
1303                           "P%u-%u", port, pin);
1304         if (!pins[i].name)
1305             return -ENOMEM;
1306 
1307         if (i % RZA1_PINS_PER_PORT == 0) {
1308             /*
1309              * Setup ports;
1310              * they provide per-port lock and logical base address.
1311              */
1312             unsigned int port_id = RZA1_PIN_ID_TO_PORT(i);
1313 
1314             ports[port_id].id   = port_id;
1315             ports[port_id].base = rza1_pctl->base;
1316             ports[port_id].pins = &pins[i];
1317             spin_lock_init(&ports[port_id].lock);
1318         }
1319     }
1320 
1321     ret = devm_pinctrl_register_and_init(rza1_pctl->dev, &rza1_pctl->desc,
1322                          rza1_pctl, &rza1_pctl->pctl);
1323     if (ret) {
1324         dev_err(rza1_pctl->dev,
1325             "RZ/A1 pin controller registration failed\n");
1326         return ret;
1327     }
1328 
1329     ret = pinctrl_enable(rza1_pctl->pctl);
1330     if (ret) {
1331         dev_err(rza1_pctl->dev,
1332             "RZ/A1 pin controller failed to start\n");
1333         return ret;
1334     }
1335 
1336     ret = rza1_gpio_register(rza1_pctl);
1337     if (ret) {
1338         dev_err(rza1_pctl->dev, "RZ/A1 GPIO registration failed\n");
1339         return ret;
1340     }
1341 
1342     return 0;
1343 }
1344 
1345 static int rza1_pinctrl_probe(struct platform_device *pdev)
1346 {
1347     struct rza1_pinctrl *rza1_pctl;
1348     int ret;
1349 
1350     rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL);
1351     if (!rza1_pctl)
1352         return -ENOMEM;
1353 
1354     rza1_pctl->dev = &pdev->dev;
1355 
1356     rza1_pctl->base = devm_platform_ioremap_resource(pdev, 0);
1357     if (IS_ERR(rza1_pctl->base))
1358         return PTR_ERR(rza1_pctl->base);
1359 
1360     mutex_init(&rza1_pctl->mutex);
1361 
1362     platform_set_drvdata(pdev, rza1_pctl);
1363 
1364     rza1_pctl->desc.name    = DRIVER_NAME;
1365     rza1_pctl->desc.pctlops = &rza1_pinctrl_ops;
1366     rza1_pctl->desc.pmxops  = &rza1_pinmux_ops;
1367     rza1_pctl->desc.owner   = THIS_MODULE;
1368     rza1_pctl->data     = of_device_get_match_data(&pdev->dev);
1369 
1370     ret = rza1_pinctrl_register(rza1_pctl);
1371     if (ret)
1372         return ret;
1373 
1374     dev_info(&pdev->dev,
1375          "RZ/A1 pin controller and gpio successfully registered\n");
1376 
1377     return 0;
1378 }
1379 
1380 static const struct of_device_id rza1_pinctrl_of_match[] = {
1381     {
1382         /* RZ/A1H, RZ/A1M */
1383         .compatible = "renesas,r7s72100-ports",
1384         .data       = &rza1h_pmx_conf,
1385     },
1386     {
1387         /* RZ/A1L */
1388         .compatible = "renesas,r7s72102-ports",
1389         .data       = &rza1l_pmx_conf,
1390     },
1391     { }
1392 };
1393 
1394 static struct platform_driver rza1_pinctrl_driver = {
1395     .driver = {
1396         .name = DRIVER_NAME,
1397         .of_match_table = rza1_pinctrl_of_match,
1398     },
1399     .probe = rza1_pinctrl_probe,
1400 };
1401 
1402 static int __init rza1_pinctrl_init(void)
1403 {
1404     return platform_driver_register(&rza1_pinctrl_driver);
1405 }
1406 core_initcall(rza1_pinctrl_init);
1407 
1408 MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org");
1409 MODULE_DESCRIPTION("Pin and gpio controller driver for Reneas RZ/A1 SoC");
1410 MODULE_LICENSE("GPL v2");
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