pinctrl/renesas/pfc-r8a77995.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * R8A77995 processor support - PFC hardware block.
0004  *
0005  * Copyright (C) 2017 Renesas Electronics Corp.
0006  *
0007  * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
0008  *
0009  * R-Car Gen3 processor support - PFC hardware block.
0010  *
0011  * Copyright (C) 2015  Renesas Electronics Corporation
0012  */
0013
0014 #include <linux/errno.h>
0015 #include <linux/kernel.h>
0016
0017 #include "core.h"
0018 #include "sh_pfc.h"
0019
0020 #define CPU_ALL_GP(fn, sfx)                     \
0021     PORT_GP_CFG_9(0,  fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
0022     PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
0023     PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
0024     PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
0025     PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
0026     PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
0027     PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
0028
0029 #define CPU_ALL_NOGP(fn)                        \
0030     PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, SH_PFC_PIN_CFG_PULL_DOWN),   \
0031     PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),   \
0032     PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),  \
0033     PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),   \
0034     PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP),       \
0035     PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP),       \
0036     PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP),       \
0037     PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
0038
0039 /*
0040  * F_() : just information
0041  * FM() : macro for FN_xxx / xxx_MARK
0042  */
0043
0044 /* GPSR0 */
0045 #define GPSR0_8     F_(MLB_SIG,     IP0_27_24)
0046 #define GPSR0_7     F_(MLB_DAT,     IP0_23_20)
0047 #define GPSR0_6     F_(MLB_CLK,     IP0_19_16)
0048 #define GPSR0_5     F_(MSIOF2_RXD,      IP0_15_12)
0049 #define GPSR0_4     F_(MSIOF2_TXD,      IP0_11_8)
0050 #define GPSR0_3     F_(MSIOF2_SCK,      IP0_7_4)
0051 #define GPSR0_2     F_(IRQ0_A,      IP0_3_0)
0052 #define GPSR0_1     FM(USB0_OVC)
0053 #define GPSR0_0     FM(USB0_PWEN)
0054
0055 /* GPSR1 */
0056 #define GPSR1_31    F_(QPOLB,       IP4_27_24)
0057 #define GPSR1_30    F_(QPOLA,       IP4_23_20)
0058 #define GPSR1_29    F_(DU_CDE,      IP4_19_16)
0059 #define GPSR1_28    F_(DU_DISP_CDE,     IP4_15_12)
0060 #define GPSR1_27    F_(DU_DISP,     IP4_11_8)
0061 #define GPSR1_26    F_(DU_VSYNC,        IP4_7_4)
0062 #define GPSR1_25    F_(DU_HSYNC,        IP4_3_0)
0063 #define GPSR1_24    F_(DU_DOTCLKOUT0,   IP3_31_28)
0064 #define GPSR1_23    F_(DU_DR7,      IP3_27_24)
0065 #define GPSR1_22    F_(DU_DR6,      IP3_23_20)
0066 #define GPSR1_21    F_(DU_DR5,      IP3_19_16)
0067 #define GPSR1_20    F_(DU_DR4,      IP3_15_12)
0068 #define GPSR1_19    F_(DU_DR3,      IP3_11_8)
0069 #define GPSR1_18    F_(DU_DR2,      IP3_7_4)
0070 #define GPSR1_17    F_(DU_DR1,      IP3_3_0)
0071 #define GPSR1_16    F_(DU_DR0,      IP2_31_28)
0072 #define GPSR1_15    F_(DU_DG7,      IP2_27_24)
0073 #define GPSR1_14    F_(DU_DG6,      IP2_23_20)
0074 #define GPSR1_13    F_(DU_DG5,      IP2_19_16)
0075 #define GPSR1_12    F_(DU_DG4,      IP2_15_12)
0076 #define GPSR1_11    F_(DU_DG3,      IP2_11_8)
0077 #define GPSR1_10    F_(DU_DG2,      IP2_7_4)
0078 #define GPSR1_9     F_(DU_DG1,      IP2_3_0)
0079 #define GPSR1_8     F_(DU_DG0,      IP1_31_28)
0080 #define GPSR1_7     F_(DU_DB7,      IP1_27_24)
0081 #define GPSR1_6     F_(DU_DB6,      IP1_23_20)
0082 #define GPSR1_5     F_(DU_DB5,      IP1_19_16)
0083 #define GPSR1_4     F_(DU_DB4,      IP1_15_12)
0084 #define GPSR1_3     F_(DU_DB3,      IP1_11_8)
0085 #define GPSR1_2     F_(DU_DB2,      IP1_7_4)
0086 #define GPSR1_1     F_(DU_DB1,      IP1_3_0)
0087 #define GPSR1_0     F_(DU_DB0,      IP0_31_28)
0088
0089 /* GPSR2 */
0090 #define GPSR2_31    F_(NFCE_N,      IP8_19_16)
0091 #define GPSR2_30    F_(NFCLE,       IP8_15_12)
0092 #define GPSR2_29    F_(NFALE,       IP8_11_8)
0093 #define GPSR2_28    F_(VI4_CLKENB,      IP8_7_4)
0094 #define GPSR2_27    F_(VI4_FIELD,       IP8_3_0)
0095 #define GPSR2_26    F_(VI4_HSYNC_N,     IP7_31_28)
0096 #define GPSR2_25    F_(VI4_VSYNC_N,     IP7_27_24)
0097 #define GPSR2_24    F_(VI4_DATA23,      IP7_23_20)
0098 #define GPSR2_23    F_(VI4_DATA22,      IP7_19_16)
0099 #define GPSR2_22    F_(VI4_DATA21,      IP7_15_12)
0100 #define GPSR2_21    F_(VI4_DATA20,      IP7_11_8)
0101 #define GPSR2_20    F_(VI4_DATA19,      IP7_7_4)
0102 #define GPSR2_19    F_(VI4_DATA18,      IP7_3_0)
0103 #define GPSR2_18    F_(VI4_DATA17,      IP6_31_28)
0104 #define GPSR2_17    F_(VI4_DATA16,      IP6_27_24)
0105 #define GPSR2_16    F_(VI4_DATA15,      IP6_23_20)
0106 #define GPSR2_15    F_(VI4_DATA14,      IP6_19_16)
0107 #define GPSR2_14    F_(VI4_DATA13,      IP6_15_12)
0108 #define GPSR2_13    F_(VI4_DATA12,      IP6_11_8)
0109 #define GPSR2_12    F_(VI4_DATA11,      IP6_7_4)
0110 #define GPSR2_11    F_(VI4_DATA10,      IP6_3_0)
0111 #define GPSR2_10    F_(VI4_DATA9,       IP5_31_28)
0112 #define GPSR2_9     F_(VI4_DATA8,       IP5_27_24)
0113 #define GPSR2_8     F_(VI4_DATA7,       IP5_23_20)
0114 #define GPSR2_7     F_(VI4_DATA6,       IP5_19_16)
0115 #define GPSR2_6     F_(VI4_DATA5,       IP5_15_12)
0116 #define GPSR2_5     FM(VI4_DATA4)
0117 #define GPSR2_4     F_(VI4_DATA3,       IP5_11_8)
0118 #define GPSR2_3     F_(VI4_DATA2,       IP5_7_4)
0119 #define GPSR2_2     F_(VI4_DATA1,       IP5_3_0)
0120 #define GPSR2_1     F_(VI4_DATA0,       IP4_31_28)
0121 #define GPSR2_0     FM(VI4_CLK)
0122
0123 /* GPSR3 */
0124 #define GPSR3_9     F_(NFDATA7,     IP9_31_28)
0125 #define GPSR3_8     F_(NFDATA6,     IP9_27_24)
0126 #define GPSR3_7     F_(NFDATA5,     IP9_23_20)
0127 #define GPSR3_6     F_(NFDATA4,     IP9_19_16)
0128 #define GPSR3_5     F_(NFDATA3,     IP9_15_12)
0129 #define GPSR3_4     F_(NFDATA2,     IP9_11_8)
0130 #define GPSR3_3     F_(NFDATA1,     IP9_7_4)
0131 #define GPSR3_2     F_(NFDATA0,     IP9_3_0)
0132 #define GPSR3_1     F_(NFWE_N,      IP8_31_28)
0133 #define GPSR3_0     F_(NFRE_N,      IP8_27_24)
0134
0135 /* GPSR4 */
0136 #define GPSR4_31    F_(CAN0_RX_A,       IP12_27_24)
0137 #define GPSR4_30    F_(CAN1_TX_A,       IP13_7_4)
0138 #define GPSR4_29    F_(CAN1_RX_A,       IP13_3_0)
0139 #define GPSR4_28    F_(CAN0_TX_A,       IP12_31_28)
0140 #define GPSR4_27    FM(TX2)
0141 #define GPSR4_26    FM(RX2)
0142 #define GPSR4_25    F_(SCK2,        IP12_11_8)
0143 #define GPSR4_24    F_(TX1_A,       IP12_7_4)
0144 #define GPSR4_23    F_(RX1_A,       IP12_3_0)
0145 #define GPSR4_22    F_(SCK1_A,      IP11_31_28)
0146 #define GPSR4_21    F_(TX0_A,       IP11_27_24)
0147 #define GPSR4_20    F_(RX0_A,       IP11_23_20)
0148 #define GPSR4_19    F_(SCK0_A,      IP11_19_16)
0149 #define GPSR4_18    F_(MSIOF1_RXD,      IP11_15_12)
0150 #define GPSR4_17    F_(MSIOF1_TXD,      IP11_11_8)
0151 #define GPSR4_16    F_(MSIOF1_SCK,      IP11_7_4)
0152 #define GPSR4_15    FM(MSIOF0_RXD)
0153 #define GPSR4_14    FM(MSIOF0_TXD)
0154 #define GPSR4_13    FM(MSIOF0_SYNC)
0155 #define GPSR4_12    FM(MSIOF0_SCK)
0156 #define GPSR4_11    F_(SDA1,        IP11_3_0)
0157 #define GPSR4_10    F_(SCL1,        IP10_31_28)
0158 #define GPSR4_9     FM(SDA0)
0159 #define GPSR4_8     FM(SCL0)
0160 #define GPSR4_7     F_(SSI_WS4_A,       IP10_27_24)
0161 #define GPSR4_6     F_(SSI_SDATA4_A,    IP10_23_20)
0162 #define GPSR4_5     F_(SSI_SCK4_A,      IP10_19_16)
0163 #define GPSR4_4     F_(SSI_WS34,        IP10_15_12)
0164 #define GPSR4_3     F_(SSI_SDATA3,      IP10_11_8)
0165 #define GPSR4_2     F_(SSI_SCK34,       IP10_7_4)
0166 #define GPSR4_1     F_(AUDIO_CLKA,      IP10_3_0)
0167 #define GPSR4_0     F_(NFRB_N,      IP8_23_20)
0168
0169 /* GPSR5 */
0170 #define GPSR5_20    FM(AVB0_LINK)
0171 #define GPSR5_19    FM(AVB0_PHY_INT)
0172 #define GPSR5_18    FM(AVB0_MAGIC)
0173 #define GPSR5_17    FM(AVB0_MDC)
0174 #define GPSR5_16    FM(AVB0_MDIO)
0175 #define GPSR5_15    FM(AVB0_TXCREFCLK)
0176 #define GPSR5_14    FM(AVB0_TD3)
0177 #define GPSR5_13    FM(AVB0_TD2)
0178 #define GPSR5_12    FM(AVB0_TD1)
0179 #define GPSR5_11    FM(AVB0_TD0)
0180 #define GPSR5_10    FM(AVB0_TXC)
0181 #define GPSR5_9     FM(AVB0_TX_CTL)
0182 #define GPSR5_8     FM(AVB0_RD3)
0183 #define GPSR5_7     FM(AVB0_RD2)
0184 #define GPSR5_6     FM(AVB0_RD1)
0185 #define GPSR5_5     FM(AVB0_RD0)
0186 #define GPSR5_4     FM(AVB0_RXC)
0187 #define GPSR5_3     FM(AVB0_RX_CTL)
0188 #define GPSR5_2     F_(CAN_CLK,     IP12_23_20)
0189 #define GPSR5_1     F_(TPU0TO1_A,       IP12_19_16)
0190 #define GPSR5_0     F_(TPU0TO0_A,       IP12_15_12)
0191
0192 /* GPSR6 */
0193 #define GPSR6_13    FM(RPC_INT_N)
0194 #define GPSR6_12    FM(RPC_RESET_N)
0195 #define GPSR6_11    FM(QSPI1_SSL)
0196 #define GPSR6_10    FM(QSPI1_IO3)
0197 #define GPSR6_9     FM(QSPI1_IO2)
0198 #define GPSR6_8     FM(QSPI1_MISO_IO1)
0199 #define GPSR6_7     FM(QSPI1_MOSI_IO0)
0200 #define GPSR6_6     FM(QSPI1_SPCLK)
0201 #define GPSR6_5     FM(QSPI0_SSL)
0202 #define GPSR6_4     FM(QSPI0_IO3)
0203 #define GPSR6_3     FM(QSPI0_IO2)
0204 #define GPSR6_2     FM(QSPI0_MISO_IO1)
0205 #define GPSR6_1     FM(QSPI0_MOSI_IO0)
0206 #define GPSR6_0     FM(QSPI0_SPCLK)
0207
0208 /* IPSRx */     /* 0 */         /* 1 */         /* 2 */         /* 3 */     /* 4 */         /* 5 */     /* 6  - F */
0209 #define IP0_3_0     FM(IRQ0_A)      FM(MSIOF2_SYNC_B)   F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0210 #define IP0_7_4     FM(MSIOF2_SCK)      F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0211 #define IP0_11_8    FM(MSIOF2_TXD)      FM(SCL3_A)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0212 #define IP0_15_12   FM(MSIOF2_RXD)      FM(SDA3_A)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0213 #define IP0_19_16   FM(MLB_CLK)     FM(MSIOF2_SYNC_A)   FM(SCK5_A)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0214 #define IP0_23_20   FM(MLB_DAT)     FM(MSIOF2_SS1)      FM(RX5_A)       FM(SCL3_B)  F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0215 #define IP0_27_24   FM(MLB_SIG)     FM(MSIOF2_SS2)      FM(TX5_A)       FM(SDA3_B)  F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0216 #define IP0_31_28   FM(DU_DB0)      FM(LCDOUT0)     FM(MSIOF3_TXD_B)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0217 #define IP1_3_0     FM(DU_DB1)      FM(LCDOUT1)     FM(MSIOF3_RXD_B)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0218 #define IP1_7_4     FM(DU_DB2)      FM(LCDOUT2)     FM(IRQ0_B)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0219 #define IP1_11_8    FM(DU_DB3)      FM(LCDOUT3)     FM(SCK5_B)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0220 #define IP1_15_12   FM(DU_DB4)      FM(LCDOUT4)     FM(RX5_B)       F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0221 #define IP1_19_16   FM(DU_DB5)      FM(LCDOUT5)     FM(TX5_B)       F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0222 #define IP1_23_20   FM(DU_DB6)      FM(LCDOUT6)     FM(MSIOF3_SS1_B)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0223 #define IP1_27_24   FM(DU_DB7)      FM(LCDOUT7)     FM(MSIOF3_SS2_B)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0224 #define IP1_31_28   FM(DU_DG0)      FM(LCDOUT8)     FM(MSIOF3_SCK_B)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0225 #define IP2_3_0     FM(DU_DG1)      FM(LCDOUT9)     FM(MSIOF3_SYNC_B)   F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0226 #define IP2_7_4     FM(DU_DG2)      FM(LCDOUT10)        F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0227 #define IP2_11_8    FM(DU_DG3)      FM(LCDOUT11)        FM(IRQ1_A)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0228 #define IP2_15_12   FM(DU_DG4)      FM(LCDOUT12)        FM(HSCK3_B)     F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0229 #define IP2_19_16   FM(DU_DG5)      FM(LCDOUT13)        FM(HTX3_B)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0230 #define IP2_23_20   FM(DU_DG6)      FM(LCDOUT14)        FM(HRX3_B)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0231 #define IP2_27_24   FM(DU_DG7)      FM(LCDOUT15)        FM(SCK4_B)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0232 #define IP2_31_28   FM(DU_DR0)      FM(LCDOUT16)        FM(RX4_B)       F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0233 #define IP3_3_0     FM(DU_DR1)      FM(LCDOUT17)        FM(TX4_B)       F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0234 #define IP3_7_4     FM(DU_DR2)      FM(LCDOUT18)        FM(PWM0_B)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0235 #define IP3_11_8    FM(DU_DR3)      FM(LCDOUT19)        FM(PWM1_B)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0236 #define IP3_15_12   FM(DU_DR4)      FM(LCDOUT20)        FM(TCLK2_B)     F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0237 #define IP3_19_16   FM(DU_DR5)      FM(LCDOUT21)        FM(NMI)         F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0238 #define IP3_23_20   FM(DU_DR6)      FM(LCDOUT22)        FM(PWM2_B)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0239 #define IP3_27_24   FM(DU_DR7)      FM(LCDOUT23)        FM(TCLK1_B)     F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0240 #define IP3_31_28   FM(DU_DOTCLKOUT0)   FM(QCLK)        F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0241
0242 /* IPSRx */     /* 0 */         /* 1 */         /* 2 */         /* 3 */     /* 4 */         /* 5 */     /* 6  - F */
0243 #define IP4_3_0     FM(DU_HSYNC)        FM(QSTH_QHS)        FM(IRQ3_A)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0244 #define IP4_7_4     FM(DU_VSYNC)        FM(QSTVA_QVS)       FM(IRQ4_A)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0245 #define IP4_11_8    FM(DU_DISP)     FM(QSTVB_QVE)       FM(PWM3_B)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0246 #define IP4_15_12   FM(DU_DISP_CDE)     FM(QCPV_QDE)        FM(IRQ2_B)      FM(DU_DOTCLKIN1)F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0247 #define IP4_19_16   FM(DU_CDE)      FM(QSTB_QHE)        FM(SCK3_B)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0248 #define IP4_23_20   FM(QPOLA)       F_(0, 0)        FM(RX3_B)       F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0249 #define IP4_27_24   FM(QPOLB)       F_(0, 0)        FM(TX3_B)       F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0250 #define IP4_31_28   FM(VI4_DATA0)       FM(PWM0_A)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0251 #define IP5_3_0     FM(VI4_DATA1)       FM(PWM1_A)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0252 #define IP5_7_4     FM(VI4_DATA2)       FM(PWM2_A)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0253 #define IP5_11_8    FM(VI4_DATA3)       FM(PWM3_A)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0254 #define IP5_15_12   FM(VI4_DATA5)       FM(SCK4_A)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0255 #define IP5_19_16   FM(VI4_DATA6)       FM(IRQ2_A)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0256 #define IP5_23_20   FM(VI4_DATA7)       FM(TCLK2_A)     F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0257 #define IP5_27_24   FM(VI4_DATA8)       F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0258 #define IP5_31_28   FM(VI4_DATA9)       FM(MSIOF3_SS2_A)    FM(IRQ1_B)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0259 #define IP6_3_0     FM(VI4_DATA10)      FM(RX4_A)       F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0260 #define IP6_7_4     FM(VI4_DATA11)      FM(TX4_A)       F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0261 #define IP6_11_8    FM(VI4_DATA12)      FM(TCLK1_A)     F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0262 #define IP6_15_12   FM(VI4_DATA13)      FM(MSIOF3_SS1_A)    FM(HCTS3_N)     F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0263 #define IP6_19_16   FM(VI4_DATA14)      FM(SSI_SCK4_B)      FM(HRTS3_N)     F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0264 #define IP6_23_20   FM(VI4_DATA15)      FM(SSI_SDATA4_B)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0265 #define IP6_27_24   FM(VI4_DATA16)      FM(HRX3_A)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0266 #define IP6_31_28   FM(VI4_DATA17)      FM(HTX3_A)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0267 #define IP7_3_0     FM(VI4_DATA18)      FM(HSCK3_A)     F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0268 #define IP7_7_4     FM(VI4_DATA19)      FM(SSI_WS4_B)       F_(0, 0)        F_(0, 0)    FM(NFDATA15)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0269 #define IP7_11_8    FM(VI4_DATA20)      FM(MSIOF3_SYNC_A)   F_(0, 0)        F_(0, 0)    FM(NFDATA14)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0270 #define IP7_15_12   FM(VI4_DATA21)      FM(MSIOF3_TXD_A)    F_(0, 0)        F_(0, 0)    FM(NFDATA13)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0271 #define IP7_19_16   FM(VI4_DATA22)      FM(MSIOF3_RXD_A)    F_(0, 0)        F_(0, 0)    FM(NFDATA12)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0272 #define IP7_23_20   FM(VI4_DATA23)      FM(MSIOF3_SCK_A)    F_(0, 0)        F_(0, 0)    FM(NFDATA11)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0273 #define IP7_27_24   FM(VI4_VSYNC_N)     FM(SCK1_B)      F_(0, 0)        F_(0, 0)    FM(NFDATA10)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0274 #define IP7_31_28   FM(VI4_HSYNC_N)     FM(RX1_B)       F_(0, 0)        F_(0, 0)    FM(NFDATA9)     F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0275
0276 /* IPSRx */     /* 0 */         /* 1 */         /* 2 */         /* 3 */     /* 4 */         /* 5 */     /* 6  - F */
0277 #define IP8_3_0     FM(VI4_FIELD)       FM(AUDIO_CLKB)      FM(IRQ5_A)      FM(SCIF_CLK)    FM(NFDATA8)     F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0278 #define IP8_7_4     FM(VI4_CLKENB)      FM(TX1_B)       F_(0, 0)        F_(0, 0)    FM(NFWP_N)      FM(DVC_MUTE_A)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0279 #define IP8_11_8    FM(NFALE)       FM(SCL2_B)      FM(IRQ3_B)      FM(PWM0_C)  F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0280 #define IP8_15_12   FM(NFCLE)       FM(SDA2_B)      FM(SCK3_A)      FM(PWM1_C)  F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0281 #define IP8_19_16   FM(NFCE_N)      F_(0, 0)        FM(RX3_A)       FM(PWM2_C)  F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0282 #define IP8_23_20   FM(NFRB_N)      F_(0, 0)        FM(TX3_A)       FM(PWM3_C)  F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0283 #define IP8_27_24   FM(NFRE_N)      FM(MMC_CMD)     F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0284 #define IP8_31_28   FM(NFWE_N)      FM(MMC_CLK)     F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0285 #define IP9_3_0     FM(NFDATA0)     FM(MMC_D0)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0286 #define IP9_7_4     FM(NFDATA1)     FM(MMC_D1)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0287 #define IP9_11_8    FM(NFDATA2)     FM(MMC_D2)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0288 #define IP9_15_12   FM(NFDATA3)     FM(MMC_D3)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0289 #define IP9_19_16   FM(NFDATA4)     FM(MMC_D4)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0290 #define IP9_23_20   FM(NFDATA5)     FM(MMC_D5)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0291 #define IP9_27_24   FM(NFDATA6)     FM(MMC_D6)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0292 #define IP9_31_28   FM(NFDATA7)     FM(MMC_D7)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0293 #define IP10_3_0    FM(AUDIO_CLKA)      F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)        FM(DVC_MUTE_B)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0294 #define IP10_7_4    FM(SSI_SCK34)       FM(FSO_CFE_0_N_A)   F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0295 #define IP10_11_8   FM(SSI_SDATA3)      FM(FSO_CFE_1_N_A)   F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0296 #define IP10_15_12  FM(SSI_WS34)        FM(FSO_TOE_N_A)     F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0297 #define IP10_19_16  FM(SSI_SCK4_A)      FM(HSCK0)       FM(AUDIO_CLKOUT)    FM(CAN0_RX_B)   FM(IRQ4_B)      F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0298 #define IP10_23_20  FM(SSI_SDATA4_A)    FM(HTX0)        FM(SCL2_A)      FM(CAN1_RX_B)   F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0299 #define IP10_27_24  FM(SSI_WS4_A)       FM(HRX0)        FM(SDA2_A)      FM(CAN1_TX_B)   F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0300 #define IP10_31_28  FM(SCL1)        FM(CTS1_N)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0301 #define IP11_3_0    FM(SDA1)        FM(RTS1_N)      F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0302 #define IP11_7_4    FM(MSIOF1_SCK)      FM(AVB0_AVTP_PPS_B) F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0303 #define IP11_11_8   FM(MSIOF1_TXD)      FM(AVB0_AVTP_CAPTURE_B) F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0304 #define IP11_15_12  FM(MSIOF1_RXD)      FM(AVB0_AVTP_MATCH_B)   F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0305 #define IP11_19_16  FM(SCK0_A)      FM(MSIOF1_SYNC)     FM(FSO_CFE_0_N_B)   F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0306 #define IP11_23_20  FM(RX0_A)       FM(MSIOF0_SS1)      FM(FSO_CFE_1_N_B)   F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0307 #define IP11_27_24  FM(TX0_A)       FM(MSIOF0_SS2)      FM(FSO_TOE_N_B)     F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0308 #define IP11_31_28  FM(SCK1_A)      FM(MSIOF1_SS2)      FM(TPU0TO2_B)       FM(CAN0_TX_B)   FM(AUDIO_CLKOUT1)   F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0309
0310 /* IPSRx */     /* 0 */         /* 1 */         /* 2 */         /* 3 */     /* 4 */         /* 5 */     /* 6  - F */
0311 #define IP12_3_0    FM(RX1_A)       FM(CTS0_N)      FM(TPU0TO0_B)       F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0312 #define IP12_7_4    FM(TX1_A)       FM(RTS0_N)      FM(TPU0TO1_B)       F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0313 #define IP12_11_8   FM(SCK2)        FM(MSIOF1_SS1)      FM(TPU0TO3_B)       F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0314 #define IP12_15_12  FM(TPU0TO0_A)       FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N)     F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0315 #define IP12_19_16  FM(TPU0TO1_A)       FM(AVB0_AVTP_MATCH_A)   FM(HRTS0_N)     F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0316 #define IP12_23_20  FM(CAN_CLK)     FM(AVB0_AVTP_PPS_A) FM(SCK0_B)      FM(IRQ5_B)  F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0317 #define IP12_27_24  FM(CAN0_RX_A)       FM(CANFD0_RX)       FM(RX0_B)       F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0318 #define IP12_31_28  FM(CAN0_TX_A)       FM(CANFD0_TX)       FM(TX0_B)       F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0319 #define IP13_3_0    FM(CAN1_RX_A)       FM(CANFD1_RX)       FM(TPU0TO2_A)       F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0320 #define IP13_7_4    FM(CAN1_TX_A)       FM(CANFD1_TX)       FM(TPU0TO3_A)       F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0321
0322 #define PINMUX_GPSR \
0323 \
0324         GPSR1_31    GPSR2_31            GPSR4_31         \
0325         GPSR1_30    GPSR2_30            GPSR4_30         \
0326         GPSR1_29    GPSR2_29            GPSR4_29         \
0327         GPSR1_28    GPSR2_28            GPSR4_28         \
0328         GPSR1_27    GPSR2_27            GPSR4_27         \
0329         GPSR1_26    GPSR2_26            GPSR4_26         \
0330         GPSR1_25    GPSR2_25            GPSR4_25         \
0331         GPSR1_24    GPSR2_24            GPSR4_24         \
0332         GPSR1_23    GPSR2_23            GPSR4_23         \
0333         GPSR1_22    GPSR2_22            GPSR4_22         \
0334         GPSR1_21    GPSR2_21            GPSR4_21         \
0335         GPSR1_20    GPSR2_20            GPSR4_20    GPSR5_20 \
0336         GPSR1_19    GPSR2_19            GPSR4_19    GPSR5_19 \
0337         GPSR1_18    GPSR2_18            GPSR4_18    GPSR5_18 \
0338         GPSR1_17    GPSR2_17            GPSR4_17    GPSR5_17 \
0339         GPSR1_16    GPSR2_16            GPSR4_16    GPSR5_16 \
0340         GPSR1_15    GPSR2_15            GPSR4_15    GPSR5_15 \
0341         GPSR1_14    GPSR2_14            GPSR4_14    GPSR5_14 \
0342         GPSR1_13    GPSR2_13            GPSR4_13    GPSR5_13    GPSR6_13 \
0343         GPSR1_12    GPSR2_12            GPSR4_12    GPSR5_12    GPSR6_12 \
0344         GPSR1_11    GPSR2_11            GPSR4_11    GPSR5_11    GPSR6_11 \
0345         GPSR1_10    GPSR2_10            GPSR4_10    GPSR5_10    GPSR6_10 \
0346         GPSR1_9     GPSR2_9     GPSR3_9     GPSR4_9     GPSR5_9     GPSR6_9 \
0347 GPSR0_8     GPSR1_8     GPSR2_8     GPSR3_8     GPSR4_8     GPSR5_8     GPSR6_8 \
0348 GPSR0_7     GPSR1_7     GPSR2_7     GPSR3_7     GPSR4_7     GPSR5_7     GPSR6_7 \
0349 GPSR0_6     GPSR1_6     GPSR2_6     GPSR3_6     GPSR4_6     GPSR5_6     GPSR6_6 \
0350 GPSR0_5     GPSR1_5     GPSR2_5     GPSR3_5     GPSR4_5     GPSR5_5     GPSR6_5 \
0351 GPSR0_4     GPSR1_4     GPSR2_4     GPSR3_4     GPSR4_4     GPSR5_4     GPSR6_4 \
0352 GPSR0_3     GPSR1_3     GPSR2_3     GPSR3_3     GPSR4_3     GPSR5_3     GPSR6_3 \
0353 GPSR0_2     GPSR1_2     GPSR2_2     GPSR3_2     GPSR4_2     GPSR5_2     GPSR6_2 \
0354 GPSR0_1     GPSR1_1     GPSR2_1     GPSR3_1     GPSR4_1     GPSR5_1     GPSR6_1 \
0355 GPSR0_0     GPSR1_0     GPSR2_0     GPSR3_0     GPSR4_0     GPSR5_0     GPSR6_0
0356
0357 #define PINMUX_IPSR             \
0358 \
0359 FM(IP0_3_0) IP0_3_0     FM(IP1_3_0) IP1_3_0     FM(IP2_3_0) IP2_3_0     FM(IP3_3_0) IP3_3_0 \
0360 FM(IP0_7_4) IP0_7_4     FM(IP1_7_4) IP1_7_4     FM(IP2_7_4) IP2_7_4     FM(IP3_7_4) IP3_7_4 \
0361 FM(IP0_11_8)    IP0_11_8    FM(IP1_11_8)    IP1_11_8    FM(IP2_11_8)    IP2_11_8    FM(IP3_11_8)    IP3_11_8 \
0362 FM(IP0_15_12)   IP0_15_12   FM(IP1_15_12)   IP1_15_12   FM(IP2_15_12)   IP2_15_12   FM(IP3_15_12)   IP3_15_12 \
0363 FM(IP0_19_16)   IP0_19_16   FM(IP1_19_16)   IP1_19_16   FM(IP2_19_16)   IP2_19_16   FM(IP3_19_16)   IP3_19_16 \
0364 FM(IP0_23_20)   IP0_23_20   FM(IP1_23_20)   IP1_23_20   FM(IP2_23_20)   IP2_23_20   FM(IP3_23_20)   IP3_23_20 \
0365 FM(IP0_27_24)   IP0_27_24   FM(IP1_27_24)   IP1_27_24   FM(IP2_27_24)   IP2_27_24   FM(IP3_27_24)   IP3_27_24 \
0366 FM(IP0_31_28)   IP0_31_28   FM(IP1_31_28)   IP1_31_28   FM(IP2_31_28)   IP2_31_28   FM(IP3_31_28)   IP3_31_28 \
0367 \
0368 FM(IP4_3_0) IP4_3_0     FM(IP5_3_0) IP5_3_0     FM(IP6_3_0) IP6_3_0     FM(IP7_3_0) IP7_3_0 \
0369 FM(IP4_7_4) IP4_7_4     FM(IP5_7_4) IP5_7_4     FM(IP6_7_4) IP6_7_4     FM(IP7_7_4) IP7_7_4 \
0370 FM(IP4_11_8)    IP4_11_8    FM(IP5_11_8)    IP5_11_8    FM(IP6_11_8)    IP6_11_8    FM(IP7_11_8)    IP7_11_8 \
0371 FM(IP4_15_12)   IP4_15_12   FM(IP5_15_12)   IP5_15_12   FM(IP6_15_12)   IP6_15_12   FM(IP7_15_12)   IP7_15_12 \
0372 FM(IP4_19_16)   IP4_19_16   FM(IP5_19_16)   IP5_19_16   FM(IP6_19_16)   IP6_19_16   FM(IP7_19_16)   IP7_19_16 \
0373 FM(IP4_23_20)   IP4_23_20   FM(IP5_23_20)   IP5_23_20   FM(IP6_23_20)   IP6_23_20   FM(IP7_23_20)   IP7_23_20 \
0374 FM(IP4_27_24)   IP4_27_24   FM(IP5_27_24)   IP5_27_24   FM(IP6_27_24)   IP6_27_24   FM(IP7_27_24)   IP7_27_24 \
0375 FM(IP4_31_28)   IP4_31_28   FM(IP5_31_28)   IP5_31_28   FM(IP6_31_28)   IP6_31_28   FM(IP7_31_28)   IP7_31_28 \
0376 \
0377 FM(IP8_3_0) IP8_3_0     FM(IP9_3_0) IP9_3_0     FM(IP10_3_0)    IP10_3_0    FM(IP11_3_0)    IP11_3_0 \
0378 FM(IP8_7_4) IP8_7_4     FM(IP9_7_4) IP9_7_4     FM(IP10_7_4)    IP10_7_4    FM(IP11_7_4)    IP11_7_4 \
0379 FM(IP8_11_8)    IP8_11_8    FM(IP9_11_8)    IP9_11_8    FM(IP10_11_8)   IP10_11_8   FM(IP11_11_8)   IP11_11_8 \
0380 FM(IP8_15_12)   IP8_15_12   FM(IP9_15_12)   IP9_15_12   FM(IP10_15_12)  IP10_15_12  FM(IP11_15_12)  IP11_15_12 \
0381 FM(IP8_19_16)   IP8_19_16   FM(IP9_19_16)   IP9_19_16   FM(IP10_19_16)  IP10_19_16  FM(IP11_19_16)  IP11_19_16 \
0382 FM(IP8_23_20)   IP8_23_20   FM(IP9_23_20)   IP9_23_20   FM(IP10_23_20)  IP10_23_20  FM(IP11_23_20)  IP11_23_20 \
0383 FM(IP8_27_24)   IP8_27_24   FM(IP9_27_24)   IP9_27_24   FM(IP10_27_24)  IP10_27_24  FM(IP11_27_24)  IP11_27_24 \
0384 FM(IP8_31_28)   IP8_31_28   FM(IP9_31_28)   IP9_31_28   FM(IP10_31_28)  IP10_31_28  FM(IP11_31_28)  IP11_31_28 \
0385 \
0386 FM(IP12_3_0)    IP12_3_0    FM(IP13_3_0)    IP13_3_0 \
0387 FM(IP12_7_4)    IP12_7_4    FM(IP13_7_4)    IP13_7_4 \
0388 FM(IP12_11_8)   IP12_11_8 \
0389 FM(IP12_15_12)  IP12_15_12 \
0390 FM(IP12_19_16)  IP12_19_16 \
0391 FM(IP12_23_20)  IP12_23_20 \
0392 FM(IP12_27_24)  IP12_27_24 \
0393 FM(IP12_31_28)  IP12_31_28 \
0394
0395 /* The bit numbering in MOD_SEL fields is reversed */
0396 #define REV4(f0, f1, f2, f3)            f0 f2 f1 f3
0397
0398 /* MOD_SEL0 */          /* 0 */         /* 1 */         /* 2 */         /* 3 */
0399 #define MOD_SEL0_30     FM(SEL_MSIOF2_0)    FM(SEL_MSIOF2_1)
0400 #define MOD_SEL0_29     FM(SEL_I2C3_0)      FM(SEL_I2C3_1)
0401 #define MOD_SEL0_28     FM(SEL_SCIF5_0)     FM(SEL_SCIF5_1)
0402 #define MOD_SEL0_27     FM(SEL_MSIOF3_0)    FM(SEL_MSIOF3_1)
0403 #define MOD_SEL0_26     FM(SEL_HSCIF3_0)    FM(SEL_HSCIF3_1)
0404 #define MOD_SEL0_25     FM(SEL_SCIF4_0)     FM(SEL_SCIF4_1)
0405 #define MOD_SEL0_24_23     REV4(FM(SEL_PWM0_0),     FM(SEL_PWM0_1),     FM(SEL_PWM0_2),     F_(0, 0))
0406 #define MOD_SEL0_22_21     REV4(FM(SEL_PWM1_0),     FM(SEL_PWM1_1),     FM(SEL_PWM1_2),     F_(0, 0))
0407 #define MOD_SEL0_20_19     REV4(FM(SEL_PWM2_0),     FM(SEL_PWM2_1),     FM(SEL_PWM2_2),     F_(0, 0))
0408 #define MOD_SEL0_18_17     REV4(FM(SEL_PWM3_0),     FM(SEL_PWM3_1),     FM(SEL_PWM3_2),     F_(0, 0))
0409 #define MOD_SEL0_15     FM(SEL_IRQ_0_0)     FM(SEL_IRQ_0_1)
0410 #define MOD_SEL0_14     FM(SEL_IRQ_1_0)     FM(SEL_IRQ_1_1)
0411 #define MOD_SEL0_13     FM(SEL_IRQ_2_0)     FM(SEL_IRQ_2_1)
0412 #define MOD_SEL0_12     FM(SEL_IRQ_3_0)     FM(SEL_IRQ_3_1)
0413 #define MOD_SEL0_11     FM(SEL_IRQ_4_0)     FM(SEL_IRQ_4_1)
0414 #define MOD_SEL0_10     FM(SEL_IRQ_5_0)     FM(SEL_IRQ_5_1)
0415 #define MOD_SEL0_5      FM(SEL_TMU_0_0)     FM(SEL_TMU_0_1)
0416 #define MOD_SEL0_4      FM(SEL_TMU_1_0)     FM(SEL_TMU_1_1)
0417 #define MOD_SEL0_3      FM(SEL_SCIF3_0)     FM(SEL_SCIF3_1)
0418 #define MOD_SEL0_2      FM(SEL_SCIF1_0)     FM(SEL_SCIF1_1)
0419 #define MOD_SEL0_1      FM(SEL_SCU_0)       FM(SEL_SCU_1)
0420 #define MOD_SEL0_0      FM(SEL_RFSO_0)      FM(SEL_RFSO_1)
0421
0422 #define MOD_SEL1_31     FM(SEL_CAN0_0)      FM(SEL_CAN0_1)
0423 #define MOD_SEL1_30     FM(SEL_CAN1_0)      FM(SEL_CAN1_1)
0424 #define MOD_SEL1_29     FM(SEL_I2C2_0)      FM(SEL_I2C2_1)
0425 #define MOD_SEL1_28     FM(SEL_ETHERAVB_0)  FM(SEL_ETHERAVB_1)
0426 #define MOD_SEL1_27     FM(SEL_SCIF0_0)     FM(SEL_SCIF0_1)
0427 #define MOD_SEL1_26     FM(SEL_SSIF4_0)     FM(SEL_SSIF4_1)
0428
0429
0430 #define PINMUX_MOD_SELS \
0431 \
0432         MOD_SEL1_31 \
0433 MOD_SEL0_30 MOD_SEL1_30 \
0434 MOD_SEL0_29 MOD_SEL1_29 \
0435 MOD_SEL0_28 MOD_SEL1_28 \
0436 MOD_SEL0_27 MOD_SEL1_27 \
0437 MOD_SEL0_26 MOD_SEL1_26 \
0438 MOD_SEL0_25 \
0439 MOD_SEL0_24_23 \
0440 MOD_SEL0_22_21 \
0441 MOD_SEL0_20_19 \
0442 MOD_SEL0_18_17 \
0443 MOD_SEL0_15 \
0444 MOD_SEL0_14 \
0445 MOD_SEL0_13 \
0446 MOD_SEL0_12 \
0447 MOD_SEL0_11 \
0448 MOD_SEL0_10 \
0449 MOD_SEL0_5 \
0450 MOD_SEL0_4 \
0451 MOD_SEL0_3 \
0452 MOD_SEL0_2 \
0453 MOD_SEL0_1 \
0454 MOD_SEL0_0
0455
0456 enum {
0457     PINMUX_RESERVED = 0,
0458
0459     PINMUX_DATA_BEGIN,
0460     GP_ALL(DATA),
0461     PINMUX_DATA_END,
0462
0463 #define F_(x, y)
0464 #define FM(x)   FN_##x,
0465     PINMUX_FUNCTION_BEGIN,
0466     GP_ALL(FN),
0467     PINMUX_GPSR
0468     PINMUX_IPSR
0469     PINMUX_MOD_SELS
0470     PINMUX_FUNCTION_END,
0471 #undef F_
0472 #undef FM
0473
0474 #define F_(x, y)
0475 #define FM(x)   x##_MARK,
0476     PINMUX_MARK_BEGIN,
0477     PINMUX_GPSR
0478     PINMUX_IPSR
0479     PINMUX_MOD_SELS
0480     PINMUX_MARK_END,
0481 #undef F_
0482 #undef FM
0483 };
0484
0485 static const u16 pinmux_data[] = {
0486     PINMUX_DATA_GP_ALL(),
0487
0488     PINMUX_SINGLE(USB0_OVC),
0489     PINMUX_SINGLE(USB0_PWEN),
0490     PINMUX_SINGLE(VI4_DATA4),
0491     PINMUX_SINGLE(VI4_CLK),
0492     PINMUX_SINGLE(TX2),
0493     PINMUX_SINGLE(RX2),
0494     PINMUX_SINGLE(AVB0_LINK),
0495     PINMUX_SINGLE(AVB0_PHY_INT),
0496     PINMUX_SINGLE(AVB0_MAGIC),
0497     PINMUX_SINGLE(AVB0_MDC),
0498     PINMUX_SINGLE(AVB0_MDIO),
0499     PINMUX_SINGLE(AVB0_TXCREFCLK),
0500     PINMUX_SINGLE(AVB0_TD3),
0501     PINMUX_SINGLE(AVB0_TD2),
0502     PINMUX_SINGLE(AVB0_TD1),
0503     PINMUX_SINGLE(AVB0_TD0),
0504     PINMUX_SINGLE(AVB0_TXC),
0505     PINMUX_SINGLE(AVB0_TX_CTL),
0506     PINMUX_SINGLE(AVB0_RD3),
0507     PINMUX_SINGLE(AVB0_RD2),
0508     PINMUX_SINGLE(AVB0_RD1),
0509     PINMUX_SINGLE(AVB0_RD0),
0510     PINMUX_SINGLE(AVB0_RXC),
0511     PINMUX_SINGLE(AVB0_RX_CTL),
0512     PINMUX_SINGLE(RPC_INT_N),
0513     PINMUX_SINGLE(RPC_RESET_N),
0514     PINMUX_SINGLE(QSPI1_SSL),
0515     PINMUX_SINGLE(QSPI1_IO3),
0516     PINMUX_SINGLE(QSPI1_IO2),
0517     PINMUX_SINGLE(QSPI1_MISO_IO1),
0518     PINMUX_SINGLE(QSPI1_MOSI_IO0),
0519     PINMUX_SINGLE(QSPI1_SPCLK),
0520     PINMUX_SINGLE(QSPI0_SSL),
0521     PINMUX_SINGLE(QSPI0_IO3),
0522     PINMUX_SINGLE(QSPI0_IO2),
0523     PINMUX_SINGLE(QSPI0_MISO_IO1),
0524     PINMUX_SINGLE(QSPI0_MOSI_IO0),
0525     PINMUX_SINGLE(QSPI0_SPCLK),
0526     PINMUX_SINGLE(SCL0),
0527     PINMUX_SINGLE(SDA0),
0528     PINMUX_SINGLE(MSIOF0_RXD),
0529     PINMUX_SINGLE(MSIOF0_TXD),
0530     PINMUX_SINGLE(MSIOF0_SYNC),
0531     PINMUX_SINGLE(MSIOF0_SCK),
0532
0533     /* IPSR0 */
0534     PINMUX_IPSR_MSEL(IP0_3_0,   IRQ0_A, SEL_IRQ_0_0),
0535     PINMUX_IPSR_MSEL(IP0_3_0,   MSIOF2_SYNC_B, SEL_MSIOF2_1),
0536
0537     PINMUX_IPSR_GPSR(IP0_7_4,   MSIOF2_SCK),
0538
0539     PINMUX_IPSR_GPSR(IP0_11_8,  MSIOF2_TXD),
0540     PINMUX_IPSR_MSEL(IP0_11_8,  SCL3_A, SEL_I2C3_0),
0541
0542     PINMUX_IPSR_GPSR(IP0_15_12, MSIOF2_RXD),
0543     PINMUX_IPSR_MSEL(IP0_15_12, SDA3_A, SEL_I2C3_0),
0544
0545     PINMUX_IPSR_GPSR(IP0_19_16, MLB_CLK),
0546     PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_SYNC_A, SEL_MSIOF2_0),
0547     PINMUX_IPSR_MSEL(IP0_19_16, SCK5_A, SEL_SCIF5_0),
0548
0549     PINMUX_IPSR_GPSR(IP0_23_20, MLB_DAT),
0550     PINMUX_IPSR_GPSR(IP0_23_20, MSIOF2_SS1),
0551     PINMUX_IPSR_MSEL(IP0_23_20, RX5_A, SEL_SCIF5_0),
0552     PINMUX_IPSR_MSEL(IP0_23_20, SCL3_B, SEL_I2C3_1),
0553
0554     PINMUX_IPSR_GPSR(IP0_27_24, MLB_SIG),
0555     PINMUX_IPSR_GPSR(IP0_27_24, MSIOF2_SS2),
0556     PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0),
0557     PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1),
0558
0559     PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0),
0560     PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0),
0561     PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1),
0562
0563     /* IPSR1 */
0564     PINMUX_IPSR_GPSR(IP1_3_0,   DU_DB1),
0565     PINMUX_IPSR_GPSR(IP1_3_0,   LCDOUT1),
0566     PINMUX_IPSR_MSEL(IP1_3_0,   MSIOF3_RXD_B, SEL_MSIOF3_1),
0567
0568     PINMUX_IPSR_GPSR(IP1_7_4,   DU_DB2),
0569     PINMUX_IPSR_GPSR(IP1_7_4,   LCDOUT2),
0570     PINMUX_IPSR_MSEL(IP1_7_4,   IRQ0_B, SEL_IRQ_0_1),
0571
0572     PINMUX_IPSR_GPSR(IP1_11_8,  DU_DB3),
0573     PINMUX_IPSR_GPSR(IP1_11_8,  LCDOUT3),
0574     PINMUX_IPSR_MSEL(IP1_11_8,  SCK5_B, SEL_SCIF5_1),
0575
0576     PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4),
0577     PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4),
0578     PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1),
0579
0580     PINMUX_IPSR_GPSR(IP1_19_16, DU_DB5),
0581     PINMUX_IPSR_GPSR(IP1_19_16, LCDOUT5),
0582     PINMUX_IPSR_MSEL(IP1_19_16, TX5_B, SEL_SCIF5_1),
0583
0584     PINMUX_IPSR_GPSR(IP1_23_20, DU_DB6),
0585     PINMUX_IPSR_GPSR(IP1_23_20, LCDOUT6),
0586     PINMUX_IPSR_MSEL(IP1_23_20, MSIOF3_SS1_B, SEL_MSIOF3_1),
0587
0588     PINMUX_IPSR_GPSR(IP1_27_24, DU_DB7),
0589     PINMUX_IPSR_GPSR(IP1_27_24, LCDOUT7),
0590     PINMUX_IPSR_MSEL(IP1_27_24, MSIOF3_SS2_B, SEL_MSIOF3_1),
0591
0592     PINMUX_IPSR_GPSR(IP1_31_28, DU_DG0),
0593     PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT8),
0594     PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SCK_B, SEL_MSIOF3_1),
0595
0596     /* IPSR2 */
0597     PINMUX_IPSR_GPSR(IP2_3_0,   DU_DG1),
0598     PINMUX_IPSR_GPSR(IP2_3_0,   LCDOUT9),
0599     PINMUX_IPSR_MSEL(IP2_3_0,   MSIOF3_SYNC_B, SEL_MSIOF3_1),
0600
0601     PINMUX_IPSR_GPSR(IP2_7_4,   DU_DG2),
0602     PINMUX_IPSR_GPSR(IP2_7_4,   LCDOUT10),
0603
0604     PINMUX_IPSR_GPSR(IP2_11_8,  DU_DG3),
0605     PINMUX_IPSR_GPSR(IP2_11_8,  LCDOUT11),
0606     PINMUX_IPSR_MSEL(IP2_11_8,  IRQ1_A, SEL_IRQ_1_0),
0607
0608     PINMUX_IPSR_GPSR(IP2_15_12, DU_DG4),
0609     PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT12),
0610     PINMUX_IPSR_MSEL(IP2_15_12, HSCK3_B, SEL_HSCIF3_1),
0611
0612     PINMUX_IPSR_GPSR(IP2_19_16, DU_DG5),
0613     PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT13),
0614     PINMUX_IPSR_MSEL(IP2_19_16, HTX3_B, SEL_HSCIF3_1),
0615
0616     PINMUX_IPSR_GPSR(IP2_23_20, DU_DG6),
0617     PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT14),
0618     PINMUX_IPSR_MSEL(IP2_23_20, HRX3_B, SEL_HSCIF3_1),
0619
0620     PINMUX_IPSR_GPSR(IP2_27_24, DU_DG7),
0621     PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT15),
0622     PINMUX_IPSR_MSEL(IP2_27_24, SCK4_B, SEL_SCIF4_1),
0623
0624     PINMUX_IPSR_GPSR(IP2_31_28, DU_DR0),
0625     PINMUX_IPSR_GPSR(IP2_31_28, LCDOUT16),
0626     PINMUX_IPSR_MSEL(IP2_31_28, RX4_B, SEL_SCIF4_1),
0627
0628     /* IPSR3 */
0629     PINMUX_IPSR_GPSR(IP3_3_0,   DU_DR1),
0630     PINMUX_IPSR_GPSR(IP3_3_0,   LCDOUT17),
0631     PINMUX_IPSR_MSEL(IP3_3_0,   TX4_B, SEL_SCIF4_1),
0632
0633     PINMUX_IPSR_GPSR(IP3_7_4,   DU_DR2),
0634     PINMUX_IPSR_GPSR(IP3_7_4,   LCDOUT18),
0635     PINMUX_IPSR_MSEL(IP3_7_4,   PWM0_B, SEL_PWM0_2),
0636
0637     PINMUX_IPSR_GPSR(IP3_11_8,  DU_DR3),
0638     PINMUX_IPSR_GPSR(IP3_11_8,  LCDOUT19),
0639     PINMUX_IPSR_MSEL(IP3_11_8,  PWM1_B, SEL_PWM1_2),
0640
0641     PINMUX_IPSR_GPSR(IP3_15_12, DU_DR4),
0642     PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT20),
0643     PINMUX_IPSR_MSEL(IP3_15_12, TCLK2_B, SEL_TMU_0_1),
0644
0645     PINMUX_IPSR_GPSR(IP3_19_16, DU_DR5),
0646     PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT21),
0647     PINMUX_IPSR_GPSR(IP3_19_16, NMI),
0648
0649     PINMUX_IPSR_GPSR(IP3_23_20, DU_DR6),
0650     PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT22),
0651     PINMUX_IPSR_MSEL(IP3_23_20, PWM2_B, SEL_PWM2_2),
0652
0653     PINMUX_IPSR_GPSR(IP3_27_24, DU_DR7),
0654     PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT23),
0655     PINMUX_IPSR_MSEL(IP3_27_24, TCLK1_B, SEL_TMU_1_1),
0656
0657     PINMUX_IPSR_GPSR(IP3_31_28, DU_DOTCLKOUT0),
0658     PINMUX_IPSR_GPSR(IP3_31_28, QCLK),
0659
0660     /* IPSR4 */
0661     PINMUX_IPSR_GPSR(IP4_3_0,   DU_HSYNC),
0662     PINMUX_IPSR_GPSR(IP4_3_0,   QSTH_QHS),
0663     PINMUX_IPSR_MSEL(IP4_3_0,   IRQ3_A, SEL_IRQ_3_0),
0664
0665     PINMUX_IPSR_GPSR(IP4_7_4,   DU_VSYNC),
0666     PINMUX_IPSR_GPSR(IP4_7_4,   QSTVA_QVS),
0667     PINMUX_IPSR_MSEL(IP4_7_4,   IRQ4_A, SEL_IRQ_4_0),
0668
0669     PINMUX_IPSR_GPSR(IP4_11_8,  DU_DISP),
0670     PINMUX_IPSR_GPSR(IP4_11_8,  QSTVB_QVE),
0671     PINMUX_IPSR_MSEL(IP4_11_8,  PWM3_B, SEL_PWM3_2),
0672
0673     PINMUX_IPSR_GPSR(IP4_15_12, DU_DISP_CDE),
0674     PINMUX_IPSR_GPSR(IP4_15_12, QCPV_QDE),
0675     PINMUX_IPSR_MSEL(IP4_15_12, IRQ2_B, SEL_IRQ_2_1),
0676     PINMUX_IPSR_GPSR(IP4_15_12, DU_DOTCLKIN1),
0677
0678     PINMUX_IPSR_GPSR(IP4_19_16, DU_CDE),
0679     PINMUX_IPSR_GPSR(IP4_19_16, QSTB_QHE),
0680     PINMUX_IPSR_MSEL(IP4_19_16, SCK3_B, SEL_SCIF3_1),
0681
0682     PINMUX_IPSR_GPSR(IP4_23_20, QPOLA),
0683     PINMUX_IPSR_MSEL(IP4_23_20, RX3_B, SEL_SCIF3_1),
0684
0685     PINMUX_IPSR_GPSR(IP4_27_24, QPOLB),
0686     PINMUX_IPSR_MSEL(IP4_27_24, TX3_B, SEL_SCIF3_1),
0687
0688     PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA0),
0689     PINMUX_IPSR_MSEL(IP4_31_28, PWM0_A, SEL_PWM0_0),
0690
0691     /* IPSR5 */
0692     PINMUX_IPSR_GPSR(IP5_3_0,   VI4_DATA1),
0693     PINMUX_IPSR_MSEL(IP5_3_0,   PWM1_A, SEL_PWM1_0),
0694
0695     PINMUX_IPSR_GPSR(IP5_7_4,   VI4_DATA2),
0696     PINMUX_IPSR_MSEL(IP5_7_4,   PWM2_A, SEL_PWM2_0),
0697
0698     PINMUX_IPSR_GPSR(IP5_11_8,  VI4_DATA3),
0699     PINMUX_IPSR_MSEL(IP5_11_8,  PWM3_A, SEL_PWM3_0),
0700
0701     PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA5),
0702     PINMUX_IPSR_MSEL(IP5_15_12, SCK4_A, SEL_SCIF4_0),
0703
0704     PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA6),
0705     PINMUX_IPSR_MSEL(IP5_19_16, IRQ2_A, SEL_IRQ_2_0),
0706
0707     PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA7),
0708     PINMUX_IPSR_MSEL(IP5_23_20, TCLK2_A, SEL_TMU_0_0),
0709
0710     PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8),
0711
0712     PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA9),
0713     PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_SS2_A, SEL_MSIOF3_0),
0714     PINMUX_IPSR_MSEL(IP5_31_28, IRQ1_B, SEL_IRQ_1_1),
0715
0716     /* IPSR6 */
0717     PINMUX_IPSR_GPSR(IP6_3_0,   VI4_DATA10),
0718     PINMUX_IPSR_MSEL(IP6_3_0,   RX4_A, SEL_SCIF4_0),
0719
0720     PINMUX_IPSR_GPSR(IP6_7_4,   VI4_DATA11),
0721     PINMUX_IPSR_MSEL(IP6_7_4,   TX4_A, SEL_SCIF4_0),
0722
0723     PINMUX_IPSR_GPSR(IP6_11_8,  VI4_DATA12),
0724     PINMUX_IPSR_MSEL(IP6_11_8,  TCLK1_A, SEL_TMU_1_0),
0725
0726     PINMUX_IPSR_GPSR(IP6_15_12, VI4_DATA13),
0727     PINMUX_IPSR_MSEL(IP6_15_12, MSIOF3_SS1_A, SEL_MSIOF3_0),
0728     PINMUX_IPSR_GPSR(IP6_15_12, HCTS3_N),
0729
0730     PINMUX_IPSR_GPSR(IP6_19_16, VI4_DATA14),
0731     PINMUX_IPSR_MSEL(IP6_19_16, SSI_SCK4_B, SEL_SSIF4_1),
0732     PINMUX_IPSR_GPSR(IP6_19_16, HRTS3_N),
0733
0734     PINMUX_IPSR_GPSR(IP6_23_20, VI4_DATA15),
0735     PINMUX_IPSR_MSEL(IP6_23_20, SSI_SDATA4_B, SEL_SSIF4_1),
0736
0737     PINMUX_IPSR_GPSR(IP6_27_24, VI4_DATA16),
0738     PINMUX_IPSR_MSEL(IP6_27_24, HRX3_A, SEL_HSCIF3_0),
0739
0740     PINMUX_IPSR_GPSR(IP6_31_28, VI4_DATA17),
0741     PINMUX_IPSR_MSEL(IP6_31_28, HTX3_A, SEL_HSCIF3_0),
0742
0743     /* IPSR7 */
0744     PINMUX_IPSR_GPSR(IP7_3_0,   VI4_DATA18),
0745     PINMUX_IPSR_MSEL(IP7_3_0,   HSCK3_A, SEL_HSCIF3_0),
0746
0747     PINMUX_IPSR_GPSR(IP7_7_4,   VI4_DATA19),
0748     PINMUX_IPSR_MSEL(IP7_7_4,   SSI_WS4_B, SEL_SSIF4_1),
0749     PINMUX_IPSR_GPSR(IP7_7_4,   NFDATA15),
0750
0751     PINMUX_IPSR_GPSR(IP7_11_8,  VI4_DATA20),
0752     PINMUX_IPSR_MSEL(IP7_11_8,  MSIOF3_SYNC_A, SEL_MSIOF3_0),
0753     PINMUX_IPSR_GPSR(IP7_11_8,  NFDATA14),
0754
0755     PINMUX_IPSR_GPSR(IP7_15_12, VI4_DATA21),
0756     PINMUX_IPSR_MSEL(IP7_15_12, MSIOF3_TXD_A, SEL_MSIOF3_0),
0757
0758     PINMUX_IPSR_GPSR(IP7_15_12, NFDATA13),
0759     PINMUX_IPSR_GPSR(IP7_19_16, VI4_DATA22),
0760     PINMUX_IPSR_MSEL(IP7_19_16, MSIOF3_RXD_A, SEL_MSIOF3_0),
0761
0762     PINMUX_IPSR_GPSR(IP7_19_16, NFDATA12),
0763     PINMUX_IPSR_GPSR(IP7_23_20, VI4_DATA23),
0764     PINMUX_IPSR_MSEL(IP7_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
0765
0766     PINMUX_IPSR_GPSR(IP7_23_20, NFDATA11),
0767
0768     PINMUX_IPSR_GPSR(IP7_27_24, VI4_VSYNC_N),
0769     PINMUX_IPSR_MSEL(IP7_27_24, SCK1_B, SEL_SCIF1_1),
0770     PINMUX_IPSR_GPSR(IP7_27_24, NFDATA10),
0771
0772     PINMUX_IPSR_GPSR(IP7_31_28, VI4_HSYNC_N),
0773     PINMUX_IPSR_MSEL(IP7_31_28, RX1_B, SEL_SCIF1_1),
0774     PINMUX_IPSR_GPSR(IP7_31_28, NFDATA9),
0775
0776     /* IPSR8 */
0777     PINMUX_IPSR_GPSR(IP8_3_0,   VI4_FIELD),
0778     PINMUX_IPSR_GPSR(IP8_3_0,   AUDIO_CLKB),
0779     PINMUX_IPSR_MSEL(IP8_3_0,   IRQ5_A, SEL_IRQ_5_0),
0780     PINMUX_IPSR_GPSR(IP8_3_0,   SCIF_CLK),
0781     PINMUX_IPSR_GPSR(IP8_3_0,   NFDATA8),
0782
0783     PINMUX_IPSR_GPSR(IP8_7_4,   VI4_CLKENB),
0784     PINMUX_IPSR_MSEL(IP8_7_4,   TX1_B, SEL_SCIF1_1),
0785     PINMUX_IPSR_GPSR(IP8_7_4,   NFWP_N),
0786     PINMUX_IPSR_MSEL(IP8_7_4,   DVC_MUTE_A, SEL_SCU_0),
0787
0788     PINMUX_IPSR_GPSR(IP8_11_8,  NFALE),
0789     PINMUX_IPSR_MSEL(IP8_11_8,  SCL2_B, SEL_I2C2_1),
0790     PINMUX_IPSR_MSEL(IP8_11_8,  IRQ3_B, SEL_IRQ_3_1),
0791     PINMUX_IPSR_MSEL(IP8_11_8,  PWM0_C, SEL_PWM0_1),
0792
0793     PINMUX_IPSR_GPSR(IP8_15_12, NFCLE),
0794     PINMUX_IPSR_MSEL(IP8_15_12, SDA2_B, SEL_I2C2_1),
0795     PINMUX_IPSR_MSEL(IP8_15_12, SCK3_A, SEL_SCIF3_0),
0796     PINMUX_IPSR_MSEL(IP8_15_12, PWM1_C, SEL_PWM1_1),
0797
0798     PINMUX_IPSR_GPSR(IP8_19_16, NFCE_N),
0799     PINMUX_IPSR_MSEL(IP8_19_16, RX3_A, SEL_SCIF3_0),
0800     PINMUX_IPSR_MSEL(IP8_19_16, PWM2_C, SEL_PWM2_1),
0801
0802     PINMUX_IPSR_GPSR(IP8_23_20, NFRB_N),
0803     PINMUX_IPSR_MSEL(IP8_23_20, TX3_A, SEL_SCIF3_0),
0804     PINMUX_IPSR_MSEL(IP8_23_20, PWM3_C, SEL_PWM3_1),
0805
0806     PINMUX_IPSR_GPSR(IP8_27_24, NFRE_N),
0807     PINMUX_IPSR_GPSR(IP8_27_24, MMC_CMD),
0808
0809     PINMUX_IPSR_GPSR(IP8_31_28, NFWE_N),
0810     PINMUX_IPSR_GPSR(IP8_31_28, MMC_CLK),
0811
0812     /* IPSR9 */
0813     PINMUX_IPSR_GPSR(IP9_3_0,   NFDATA0),
0814     PINMUX_IPSR_GPSR(IP9_3_0,   MMC_D0),
0815
0816     PINMUX_IPSR_GPSR(IP9_7_4,   NFDATA1),
0817     PINMUX_IPSR_GPSR(IP9_7_4,   MMC_D1),
0818
0819     PINMUX_IPSR_GPSR(IP9_11_8,  NFDATA2),
0820     PINMUX_IPSR_GPSR(IP9_11_8,  MMC_D2),
0821
0822     PINMUX_IPSR_GPSR(IP9_15_12, NFDATA3),
0823     PINMUX_IPSR_GPSR(IP9_15_12, MMC_D3),
0824
0825     PINMUX_IPSR_GPSR(IP9_19_16, NFDATA4),
0826     PINMUX_IPSR_GPSR(IP9_19_16, MMC_D4),
0827
0828     PINMUX_IPSR_GPSR(IP9_23_20, NFDATA5),
0829     PINMUX_IPSR_GPSR(IP9_23_20, MMC_D5),
0830
0831     PINMUX_IPSR_GPSR(IP9_27_24, NFDATA6),
0832     PINMUX_IPSR_GPSR(IP9_27_24, MMC_D6),
0833
0834     PINMUX_IPSR_GPSR(IP9_31_28, NFDATA7),
0835     PINMUX_IPSR_GPSR(IP9_31_28, MMC_D7),
0836
0837     /* IPSR10 */
0838     PINMUX_IPSR_GPSR(IP10_3_0,  AUDIO_CLKA),
0839     PINMUX_IPSR_MSEL(IP10_3_0,  DVC_MUTE_B, SEL_SCU_1),
0840
0841     PINMUX_IPSR_GPSR(IP10_7_4,  SSI_SCK34),
0842     PINMUX_IPSR_MSEL(IP10_7_4,  FSO_CFE_0_N_A, SEL_RFSO_0),
0843
0844     PINMUX_IPSR_GPSR(IP10_11_8, SSI_SDATA3),
0845     PINMUX_IPSR_MSEL(IP10_11_8, FSO_CFE_1_N_A, SEL_RFSO_0),
0846
0847     PINMUX_IPSR_GPSR(IP10_15_12,    SSI_WS34),
0848     PINMUX_IPSR_MSEL(IP10_15_12,    FSO_TOE_N_A, SEL_RFSO_0),
0849
0850     PINMUX_IPSR_MSEL(IP10_19_16,    SSI_SCK4_A, SEL_SSIF4_0),
0851     PINMUX_IPSR_GPSR(IP10_19_16,    HSCK0),
0852     PINMUX_IPSR_GPSR(IP10_19_16,    AUDIO_CLKOUT),
0853     PINMUX_IPSR_MSEL(IP10_19_16,    CAN0_RX_B, SEL_CAN0_1),
0854     PINMUX_IPSR_MSEL(IP10_19_16,    IRQ4_B, SEL_IRQ_4_1),
0855
0856     PINMUX_IPSR_MSEL(IP10_23_20,    SSI_SDATA4_A, SEL_SSIF4_0),
0857     PINMUX_IPSR_GPSR(IP10_23_20,    HTX0),
0858     PINMUX_IPSR_MSEL(IP10_23_20,    SCL2_A, SEL_I2C2_0),
0859     PINMUX_IPSR_MSEL(IP10_23_20,    CAN1_RX_B, SEL_CAN1_1),
0860
0861     PINMUX_IPSR_MSEL(IP10_27_24,    SSI_WS4_A, SEL_SSIF4_0),
0862     PINMUX_IPSR_GPSR(IP10_27_24,    HRX0),
0863     PINMUX_IPSR_MSEL(IP10_27_24,    SDA2_A, SEL_I2C2_0),
0864     PINMUX_IPSR_MSEL(IP10_27_24,    CAN1_TX_B, SEL_CAN1_1),
0865
0866     PINMUX_IPSR_GPSR(IP10_31_28,    SCL1),
0867     PINMUX_IPSR_GPSR(IP10_31_28,    CTS1_N),
0868
0869     /* IPSR11 */
0870     PINMUX_IPSR_GPSR(IP11_3_0,  SDA1),
0871     PINMUX_IPSR_GPSR(IP11_3_0,  RTS1_N),
0872
0873     PINMUX_IPSR_GPSR(IP11_7_4,  MSIOF1_SCK),
0874     PINMUX_IPSR_MSEL(IP11_7_4,  AVB0_AVTP_PPS_B, SEL_ETHERAVB_1),
0875
0876     PINMUX_IPSR_GPSR(IP11_11_8, MSIOF1_TXD),
0877     PINMUX_IPSR_MSEL(IP11_11_8, AVB0_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
0878
0879     PINMUX_IPSR_GPSR(IP11_15_12,    MSIOF1_RXD),
0880     PINMUX_IPSR_MSEL(IP11_15_12,    AVB0_AVTP_MATCH_B, SEL_ETHERAVB_1),
0881
0882     PINMUX_IPSR_MSEL(IP11_19_16,    SCK0_A, SEL_SCIF0_0),
0883     PINMUX_IPSR_GPSR(IP11_19_16,    MSIOF1_SYNC),
0884     PINMUX_IPSR_MSEL(IP11_19_16,    FSO_CFE_0_N_B, SEL_RFSO_1),
0885
0886     PINMUX_IPSR_MSEL(IP11_23_20,    RX0_A, SEL_SCIF0_0),
0887     PINMUX_IPSR_GPSR(IP11_23_20,    MSIOF0_SS1),
0888     PINMUX_IPSR_MSEL(IP11_23_20,    FSO_CFE_1_N_B, SEL_RFSO_1),
0889
0890     PINMUX_IPSR_MSEL(IP11_27_24,    TX0_A, SEL_SCIF0_0),
0891     PINMUX_IPSR_GPSR(IP11_27_24,    MSIOF0_SS2),
0892     PINMUX_IPSR_MSEL(IP11_27_24,    FSO_TOE_N_B, SEL_RFSO_1),
0893
0894     PINMUX_IPSR_MSEL(IP11_31_28,    SCK1_A, SEL_SCIF1_0),
0895     PINMUX_IPSR_GPSR(IP11_31_28,    MSIOF1_SS2),
0896     PINMUX_IPSR_GPSR(IP11_31_28,    TPU0TO2_B),
0897     PINMUX_IPSR_MSEL(IP11_31_28,    CAN0_TX_B, SEL_CAN0_1),
0898     PINMUX_IPSR_GPSR(IP11_31_28,    AUDIO_CLKOUT1),
0899
0900     /* IPSR12 */
0901     PINMUX_IPSR_MSEL(IP12_3_0,  RX1_A, SEL_SCIF1_0),
0902     PINMUX_IPSR_GPSR(IP12_3_0,  CTS0_N),
0903     PINMUX_IPSR_GPSR(IP12_3_0,  TPU0TO0_B),
0904
0905     PINMUX_IPSR_MSEL(IP12_7_4,  TX1_A, SEL_SCIF1_0),
0906     PINMUX_IPSR_GPSR(IP12_7_4,  RTS0_N),
0907     PINMUX_IPSR_GPSR(IP12_7_4,  TPU0TO1_B),
0908
0909     PINMUX_IPSR_GPSR(IP12_11_8, SCK2),
0910     PINMUX_IPSR_GPSR(IP12_11_8, MSIOF1_SS1),
0911     PINMUX_IPSR_GPSR(IP12_11_8, TPU0TO3_B),
0912
0913     PINMUX_IPSR_GPSR(IP12_15_12,    TPU0TO0_A),
0914     PINMUX_IPSR_MSEL(IP12_15_12,    AVB0_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
0915     PINMUX_IPSR_GPSR(IP12_15_12,    HCTS0_N),
0916
0917     PINMUX_IPSR_GPSR(IP12_19_16,    TPU0TO1_A),
0918     PINMUX_IPSR_MSEL(IP12_19_16,    AVB0_AVTP_MATCH_A, SEL_ETHERAVB_0),
0919     PINMUX_IPSR_GPSR(IP12_19_16,    HRTS0_N),
0920
0921     PINMUX_IPSR_GPSR(IP12_23_20,    CAN_CLK),
0922     PINMUX_IPSR_MSEL(IP12_23_20,    AVB0_AVTP_PPS_A, SEL_ETHERAVB_0),
0923     PINMUX_IPSR_MSEL(IP12_23_20,    SCK0_B, SEL_SCIF0_1),
0924     PINMUX_IPSR_MSEL(IP12_23_20,    IRQ5_B, SEL_IRQ_5_1),
0925
0926     PINMUX_IPSR_MSEL(IP12_27_24,    CAN0_RX_A, SEL_CAN0_0),
0927     PINMUX_IPSR_GPSR(IP12_27_24,    CANFD0_RX),
0928     PINMUX_IPSR_MSEL(IP12_27_24,    RX0_B, SEL_SCIF0_1),
0929
0930     PINMUX_IPSR_MSEL(IP12_31_28,    CAN0_TX_A, SEL_CAN0_0),
0931     PINMUX_IPSR_GPSR(IP12_31_28,    CANFD0_TX),
0932     PINMUX_IPSR_MSEL(IP12_31_28,    TX0_B, SEL_SCIF0_1),
0933
0934     /* IPSR13 */
0935     PINMUX_IPSR_MSEL(IP13_3_0,  CAN1_RX_A, SEL_CAN1_0),
0936     PINMUX_IPSR_GPSR(IP13_3_0,  CANFD1_RX),
0937     PINMUX_IPSR_GPSR(IP13_3_0,  TPU0TO2_A),
0938
0939     PINMUX_IPSR_MSEL(IP13_7_4,  CAN1_TX_A, SEL_CAN1_0),
0940     PINMUX_IPSR_GPSR(IP13_7_4,  CANFD1_TX),
0941     PINMUX_IPSR_GPSR(IP13_7_4,  TPU0TO3_A),
0942 };
0943
0944 /*
0945  * Pins not associated with a GPIO port.
0946  */
0947 enum {
0948     GP_ASSIGN_LAST(),
0949     NOGP_ALL(),
0950 };
0951
0952 static const struct sh_pfc_pin pinmux_pins[] = {
0953     PINMUX_GPIO_GP_ALL(),
0954     PINMUX_NOGP_ALL(),
0955 };
0956
0957 /* - AUDIO CLOCK ------------------------------------------------------------- */
0958 static const unsigned int audio_clk_a_pins[] = {
0959     /* CLK A */
0960     RCAR_GP_PIN(4, 1),
0961 };
0962 static const unsigned int audio_clk_a_mux[] = {
0963     AUDIO_CLKA_MARK,
0964 };
0965 static const unsigned int audio_clk_b_pins[] = {
0966     /* CLK B */
0967     RCAR_GP_PIN(2, 27),
0968 };
0969 static const unsigned int audio_clk_b_mux[] = {
0970     AUDIO_CLKB_MARK,
0971 };
0972 static const unsigned int audio_clkout_pins[] = {
0973     /* CLKOUT */
0974     RCAR_GP_PIN(4, 5),
0975 };
0976 static const unsigned int audio_clkout_mux[] = {
0977     AUDIO_CLKOUT_MARK,
0978 };
0979 static const unsigned int audio_clkout1_pins[] = {
0980     /* CLKOUT1 */
0981     RCAR_GP_PIN(4, 22),
0982 };
0983 static const unsigned int audio_clkout1_mux[] = {
0984     AUDIO_CLKOUT1_MARK,
0985 };
0986
0987 /* - EtherAVB --------------------------------------------------------------- */
0988 static const unsigned int avb0_link_pins[] = {
0989     /* AVB0_LINK */
0990     RCAR_GP_PIN(5, 20),
0991 };
0992 static const unsigned int avb0_link_mux[] = {
0993     AVB0_LINK_MARK,
0994 };
0995 static const unsigned int avb0_magic_pins[] = {
0996     /* AVB0_MAGIC */
0997     RCAR_GP_PIN(5, 18),
0998 };
0999 static const unsigned int avb0_magic_mux[] = {
1000     AVB0_MAGIC_MARK,
1001 };
1002 static const unsigned int avb0_phy_int_pins[] = {
1003     /* AVB0_PHY_INT */
1004     RCAR_GP_PIN(5, 19),
1005 };
1006 static const unsigned int avb0_phy_int_mux[] = {
1007     AVB0_PHY_INT_MARK,
1008 };
1009 static const unsigned int avb0_mdio_pins[] = {
1010     /* AVB0_MDC, AVB0_MDIO */
1011     RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16),
1012 };
1013 static const unsigned int avb0_mdio_mux[] = {
1014     AVB0_MDC_MARK, AVB0_MDIO_MARK,
1015 };
1016 static const unsigned int avb0_mii_pins[] = {
1017     /*
1018      * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0,
1019      * AVB0_TD1, AVB0_TD2, AVB0_TD3,
1020      * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0,
1021      * AVB0_RD1, AVB0_RD2, AVB0_RD3,
1022      * AVB0_TXCREFCLK
1023      */
1024     RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
1025     RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1026     RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1027     RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1028     RCAR_GP_PIN(5, 15),
1029 };
1030 static const unsigned int avb0_mii_mux[] = {
1031     AVB0_TX_CTL_MARK, AVB0_TXC_MARK, AVB0_TD0_MARK,
1032     AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
1033     AVB0_RX_CTL_MARK, AVB0_RXC_MARK, AVB0_RD0_MARK,
1034     AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
1035     AVB0_TXCREFCLK_MARK,
1036 };
1037 static const unsigned int avb0_avtp_pps_a_pins[] = {
1038     /* AVB0_AVTP_PPS_A */
1039     RCAR_GP_PIN(5, 2),
1040 };
1041 static const unsigned int avb0_avtp_pps_a_mux[] = {
1042     AVB0_AVTP_PPS_A_MARK,
1043 };
1044 static const unsigned int avb0_avtp_match_a_pins[] = {
1045     /* AVB0_AVTP_MATCH_A */
1046     RCAR_GP_PIN(5, 1),
1047 };
1048 static const unsigned int avb0_avtp_match_a_mux[] = {
1049     AVB0_AVTP_MATCH_A_MARK,
1050 };
1051 static const unsigned int avb0_avtp_capture_a_pins[] = {
1052     /* AVB0_AVTP_CAPTURE_A */
1053     RCAR_GP_PIN(5, 0),
1054 };
1055 static const unsigned int avb0_avtp_capture_a_mux[] = {
1056     AVB0_AVTP_CAPTURE_A_MARK,
1057 };
1058 static const unsigned int avb0_avtp_pps_b_pins[] = {
1059     /* AVB0_AVTP_PPS_B */
1060     RCAR_GP_PIN(4, 16),
1061 };
1062 static const unsigned int avb0_avtp_pps_b_mux[] = {
1063     AVB0_AVTP_PPS_B_MARK,
1064 };
1065 static const unsigned int avb0_avtp_match_b_pins[] = {
1066     /*  AVB0_AVTP_MATCH_B */
1067     RCAR_GP_PIN(4, 18),
1068 };
1069 static const unsigned int avb0_avtp_match_b_mux[] = {
1070     AVB0_AVTP_MATCH_B_MARK,
1071 };
1072 static const unsigned int avb0_avtp_capture_b_pins[] = {
1073     /* AVB0_AVTP_CAPTURE_B */
1074     RCAR_GP_PIN(4, 17),
1075 };
1076 static const unsigned int avb0_avtp_capture_b_mux[] = {
1077     AVB0_AVTP_CAPTURE_B_MARK,
1078 };
1079
1080 /* - CAN ------------------------------------------------------------------ */
1081 static const unsigned int can0_data_a_pins[] = {
1082     /* TX, RX */
1083     RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
1084 };
1085 static const unsigned int can0_data_a_mux[] = {
1086     CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1087 };
1088 static const unsigned int can0_data_b_pins[] = {
1089     /* TX, RX */
1090     RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 5),
1091 };
1092 static const unsigned int can0_data_b_mux[] = {
1093     CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1094 };
1095 static const unsigned int can1_data_a_pins[] = {
1096     /* TX, RX */
1097     RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
1098 };
1099 static const unsigned int can1_data_a_mux[] = {
1100     CAN1_TX_A_MARK, CAN1_RX_A_MARK,
1101 };
1102 static const unsigned int can1_data_b_pins[] = {
1103     /* TX, RX */
1104     RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6),
1105 };
1106 static const unsigned int can1_data_b_mux[] = {
1107     CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1108 };
1109
1110 /* - CAN Clock -------------------------------------------------------------- */
1111 static const unsigned int can_clk_pins[] = {
1112     /* CLK */
1113     RCAR_GP_PIN(5, 2),
1114 };
1115 static const unsigned int can_clk_mux[] = {
1116     CAN_CLK_MARK,
1117 };
1118
1119 /* - CAN FD ----------------------------------------------------------------- */
1120 static const unsigned int canfd0_data_pins[] = {
1121     /* TX, RX */
1122     RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
1123 };
1124 static const unsigned int canfd0_data_mux[] = {
1125     CANFD0_TX_MARK, CANFD0_RX_MARK,
1126 };
1127 static const unsigned int canfd1_data_pins[] = {
1128     /* TX, RX */
1129     RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
1130 };
1131 static const unsigned int canfd1_data_mux[] = {
1132     CANFD1_TX_MARK, CANFD1_RX_MARK,
1133 };
1134
1135 /* - DU --------------------------------------------------------------------- */
1136 static const unsigned int du_rgb666_pins[] = {
1137     /* R[7:2], G[7:2], B[7:2] */
1138     RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1139     RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1140     RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1141     RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
1142     RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
1143     RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
1144 };
1145 static const unsigned int du_rgb666_mux[] = {
1146     DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1147     DU_DR3_MARK, DU_DR2_MARK,
1148     DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1149     DU_DG3_MARK, DU_DG2_MARK,
1150     DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1151     DU_DB3_MARK, DU_DB2_MARK,
1152 };
1153 static const unsigned int du_rgb888_pins[] = {
1154     /* R[7:0], G[7:0], B[7:0] */
1155     RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1156     RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1157     RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1158     RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1159     RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
1160     RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),
1161     RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
1162     RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
1163     RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
1164 };
1165 static const unsigned int du_rgb888_mux[] = {
1166     DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1167     DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1168     DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1169     DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1170     DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1171     DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1172 };
1173 static const unsigned int du_clk_in_1_pins[] = {
1174     /* CLKIN */
1175     RCAR_GP_PIN(1, 28),
1176 };
1177 static const unsigned int du_clk_in_1_mux[] = {
1178     DU_DOTCLKIN1_MARK
1179 };
1180 static const unsigned int du_clk_out_0_pins[] = {
1181     /* CLKOUT */
1182     RCAR_GP_PIN(1, 24),
1183 };
1184 static const unsigned int du_clk_out_0_mux[] = {
1185     DU_DOTCLKOUT0_MARK
1186 };
1187 static const unsigned int du_sync_pins[] = {
1188     /* VSYNC, HSYNC */
1189     RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1190 };
1191 static const unsigned int du_sync_mux[] = {
1192     DU_VSYNC_MARK, DU_HSYNC_MARK
1193 };
1194 static const unsigned int du_disp_cde_pins[] = {
1195     /* DISP_CDE */
1196     RCAR_GP_PIN(1, 28),
1197 };
1198 static const unsigned int du_disp_cde_mux[] = {
1199     DU_DISP_CDE_MARK,
1200 };
1201 static const unsigned int du_cde_pins[] = {
1202     /* CDE */
1203     RCAR_GP_PIN(1, 29),
1204 };
1205 static const unsigned int du_cde_mux[] = {
1206     DU_CDE_MARK,
1207 };
1208 static const unsigned int du_disp_pins[] = {
1209     /* DISP */
1210     RCAR_GP_PIN(1, 27),
1211 };
1212 static const unsigned int du_disp_mux[] = {
1213     DU_DISP_MARK,
1214 };
1215
1216 /* - I2C -------------------------------------------------------------------- */
1217 static const unsigned int i2c0_pins[] = {
1218     /* SCL, SDA */
1219     RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1220 };
1221 static const unsigned int i2c0_mux[] = {
1222     SCL0_MARK, SDA0_MARK,
1223 };
1224 static const unsigned int i2c1_pins[] = {
1225     /* SCL, SDA */
1226     RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1227 };
1228 static const unsigned int i2c1_mux[] = {
1229     SCL1_MARK, SDA1_MARK,
1230 };
1231 static const unsigned int i2c2_a_pins[] = {
1232     /* SCL, SDA */
1233     RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1234 };
1235 static const unsigned int i2c2_a_mux[] = {
1236     SCL2_A_MARK, SDA2_A_MARK,
1237 };
1238 static const unsigned int i2c2_b_pins[] = {
1239     /* SCL, SDA */
1240     RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 30),
1241 };
1242 static const unsigned int i2c2_b_mux[] = {
1243     SCL2_B_MARK, SDA2_B_MARK,
1244 };
1245 static const unsigned int i2c3_a_pins[] = {
1246     /* SCL, SDA */
1247     RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1248 };
1249 static const unsigned int i2c3_a_mux[] = {
1250     SCL3_A_MARK, SDA3_A_MARK,
1251 };
1252 static const unsigned int i2c3_b_pins[] = {
1253     /* SCL, SDA */
1254     RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1255 };
1256 static const unsigned int i2c3_b_mux[] = {
1257     SCL3_B_MARK, SDA3_B_MARK,
1258 };
1259
1260 /* - MLB+ ------------------------------------------------------------------- */
1261 static const unsigned int mlb_3pin_pins[] = {
1262     RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7),
1263 };
1264 static const unsigned int mlb_3pin_mux[] = {
1265     MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
1266 };
1267
1268 /* - MMC ------------------------------------------------------------------- */
1269 static const unsigned int mmc_data_pins[] = {
1270     /* D[0:7] */
1271     RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
1272     RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1273     RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1274     RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1275 };
1276 static const unsigned int mmc_data_mux[] = {
1277     MMC_D0_MARK, MMC_D1_MARK,
1278     MMC_D2_MARK, MMC_D3_MARK,
1279     MMC_D4_MARK, MMC_D5_MARK,
1280     MMC_D6_MARK, MMC_D7_MARK,
1281 };
1282 static const unsigned int mmc_ctrl_pins[] = {
1283     /* CLK, CMD */
1284     RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1285 };
1286 static const unsigned int mmc_ctrl_mux[] = {
1287     MMC_CLK_MARK, MMC_CMD_MARK,
1288 };
1289
1290 /* - MSIOF0 ----------------------------------------------------------------- */
1291 static const unsigned int msiof0_clk_pins[] = {
1292     /* SCK */
1293     RCAR_GP_PIN(4, 12),
1294 };
1295
1296 static const unsigned int msiof0_clk_mux[] = {
1297     MSIOF0_SCK_MARK,
1298 };
1299
1300 static const unsigned int msiof0_sync_pins[] = {
1301     /* SYNC */
1302     RCAR_GP_PIN(4, 13),
1303 };
1304
1305 static const unsigned int msiof0_sync_mux[] = {
1306     MSIOF0_SYNC_MARK,
1307 };
1308
1309 static const unsigned int msiof0_ss1_pins[] = {
1310     /* SS1 */
1311     RCAR_GP_PIN(4, 20),
1312 };
1313
1314 static const unsigned int msiof0_ss1_mux[] = {
1315     MSIOF0_SS1_MARK,
1316 };
1317
1318 static const unsigned int msiof0_ss2_pins[] = {
1319     /* SS2 */
1320     RCAR_GP_PIN(4, 21),
1321 };
1322
1323 static const unsigned int msiof0_ss2_mux[] = {
1324     MSIOF0_SS2_MARK,
1325 };
1326
1327 static const unsigned int msiof0_txd_pins[] = {
1328     /* TXD */
1329     RCAR_GP_PIN(4, 14),
1330 };
1331
1332 static const unsigned int msiof0_txd_mux[] = {
1333     MSIOF0_TXD_MARK,
1334 };
1335
1336 static const unsigned int msiof0_rxd_pins[] = {
1337     /* RXD */
1338     RCAR_GP_PIN(4, 15),
1339 };
1340
1341 static const unsigned int msiof0_rxd_mux[] = {
1342     MSIOF0_RXD_MARK,
1343 };
1344
1345 /* - MSIOF1 ----------------------------------------------------------------- */
1346 static const unsigned int msiof1_clk_pins[] = {
1347     /* SCK */
1348     RCAR_GP_PIN(4, 16),
1349 };
1350
1351 static const unsigned int msiof1_clk_mux[] = {
1352     MSIOF1_SCK_MARK,
1353 };
1354
1355 static const unsigned int msiof1_sync_pins[] = {
1356     /* SYNC */
1357     RCAR_GP_PIN(4, 19),
1358 };
1359
1360 static const unsigned int msiof1_sync_mux[] = {
1361     MSIOF1_SYNC_MARK,
1362 };
1363
1364 static const unsigned int msiof1_ss1_pins[] = {
1365     /* SS1 */
1366     RCAR_GP_PIN(4, 25),
1367 };
1368
1369 static const unsigned int msiof1_ss1_mux[] = {
1370     MSIOF1_SS1_MARK,
1371 };
1372
1373 static const unsigned int msiof1_ss2_pins[] = {
1374     /* SS2 */
1375     RCAR_GP_PIN(4, 22),
1376 };
1377
1378 static const unsigned int msiof1_ss2_mux[] = {
1379     MSIOF1_SS2_MARK,
1380 };
1381
1382 static const unsigned int msiof1_txd_pins[] = {
1383     /* TXD */
1384     RCAR_GP_PIN(4, 17),
1385 };
1386
1387 static const unsigned int msiof1_txd_mux[] = {
1388     MSIOF1_TXD_MARK,
1389 };
1390
1391 static const unsigned int msiof1_rxd_pins[] = {
1392     /* RXD */
1393     RCAR_GP_PIN(4, 18),
1394 };
1395
1396 static const unsigned int msiof1_rxd_mux[] = {
1397     MSIOF1_RXD_MARK,
1398 };
1399
1400 /* - MSIOF2 ----------------------------------------------------------------- */
1401 static const unsigned int msiof2_clk_pins[] = {
1402     /* SCK */
1403     RCAR_GP_PIN(0, 3),
1404 };
1405
1406 static const unsigned int msiof2_clk_mux[] = {
1407     MSIOF2_SCK_MARK,
1408 };
1409
1410 static const unsigned int msiof2_sync_a_pins[] = {
1411     /* SYNC */
1412     RCAR_GP_PIN(0, 6),
1413 };
1414
1415 static const unsigned int msiof2_sync_a_mux[] = {
1416     MSIOF2_SYNC_A_MARK,
1417 };
1418
1419 static const unsigned int msiof2_sync_b_pins[] = {
1420     /* SYNC */
1421     RCAR_GP_PIN(0, 2),
1422 };
1423
1424 static const unsigned int msiof2_sync_b_mux[] = {
1425     MSIOF2_SYNC_B_MARK,
1426 };
1427
1428 static const unsigned int msiof2_ss1_pins[] = {
1429     /* SS1 */
1430     RCAR_GP_PIN(0, 7),
1431 };
1432
1433 static const unsigned int msiof2_ss1_mux[] = {
1434     MSIOF2_SS1_MARK,
1435 };
1436
1437 static const unsigned int msiof2_ss2_pins[] = {
1438     /* SS2 */
1439     RCAR_GP_PIN(0, 8),
1440 };
1441
1442 static const unsigned int msiof2_ss2_mux[] = {
1443     MSIOF2_SS2_MARK,
1444 };
1445
1446 static const unsigned int msiof2_txd_pins[] = {
1447     /* TXD */
1448     RCAR_GP_PIN(0, 4),
1449 };
1450
1451 static const unsigned int msiof2_txd_mux[] = {
1452     MSIOF2_TXD_MARK,
1453 };
1454
1455 static const unsigned int msiof2_rxd_pins[] = {
1456     /* RXD */
1457     RCAR_GP_PIN(0, 5),
1458 };
1459
1460 static const unsigned int msiof2_rxd_mux[] = {
1461     MSIOF2_RXD_MARK,
1462 };
1463
1464 /* - MSIOF3 ----------------------------------------------------------------- */
1465 static const unsigned int msiof3_clk_a_pins[] = {
1466     /* SCK */
1467     RCAR_GP_PIN(2, 24),
1468 };
1469
1470 static const unsigned int msiof3_clk_a_mux[] = {
1471     MSIOF3_SCK_A_MARK,
1472 };
1473
1474 static const unsigned int msiof3_sync_a_pins[] = {
1475     /* SYNC */
1476     RCAR_GP_PIN(2, 21),
1477 };
1478
1479 static const unsigned int msiof3_sync_a_mux[] = {
1480     MSIOF3_SYNC_A_MARK,
1481 };
1482
1483 static const unsigned int msiof3_ss1_a_pins[] = {
1484     /* SS1 */
1485     RCAR_GP_PIN(2, 14),
1486 };
1487
1488 static const unsigned int msiof3_ss1_a_mux[] = {
1489     MSIOF3_SS1_A_MARK,
1490 };
1491
1492 static const unsigned int msiof3_ss2_a_pins[] = {
1493     /* SS2 */
1494     RCAR_GP_PIN(2, 10),
1495 };
1496
1497 static const unsigned int msiof3_ss2_a_mux[] = {
1498     MSIOF3_SS2_A_MARK,
1499 };
1500
1501 static const unsigned int msiof3_txd_a_pins[] = {
1502     /* TXD */
1503     RCAR_GP_PIN(2, 22),
1504 };
1505
1506 static const unsigned int msiof3_txd_a_mux[] = {
1507     MSIOF3_TXD_A_MARK,
1508 };
1509
1510 static const unsigned int msiof3_rxd_a_pins[] = {
1511     /* RXD */
1512     RCAR_GP_PIN(2, 23),
1513 };
1514
1515 static const unsigned int msiof3_rxd_a_mux[] = {
1516     MSIOF3_RXD_A_MARK,
1517 };
1518
1519 static const unsigned int msiof3_clk_b_pins[] = {
1520     /* SCK */
1521     RCAR_GP_PIN(1, 8),
1522 };
1523
1524 static const unsigned int msiof3_clk_b_mux[] = {
1525     MSIOF3_SCK_B_MARK,
1526 };
1527
1528 static const unsigned int msiof3_sync_b_pins[] = {
1529     /* SYNC */
1530     RCAR_GP_PIN(1, 9),
1531 };
1532
1533 static const unsigned int msiof3_sync_b_mux[] = {
1534     MSIOF3_SYNC_B_MARK,
1535 };
1536
1537 static const unsigned int msiof3_ss1_b_pins[] = {
1538     /* SS1 */
1539     RCAR_GP_PIN(1, 6),
1540 };
1541
1542 static const unsigned int msiof3_ss1_b_mux[] = {
1543     MSIOF3_SS1_B_MARK,
1544 };
1545
1546 static const unsigned int msiof3_ss2_b_pins[] = {
1547     /* SS2 */
1548     RCAR_GP_PIN(1, 7),
1549 };
1550
1551 static const unsigned int msiof3_ss2_b_mux[] = {
1552     MSIOF3_SS2_B_MARK,
1553 };
1554
1555 static const unsigned int msiof3_txd_b_pins[] = {
1556     /* TXD */
1557     RCAR_GP_PIN(1, 0),
1558 };
1559
1560 static const unsigned int msiof3_txd_b_mux[] = {
1561     MSIOF3_TXD_B_MARK,
1562 };
1563
1564 static const unsigned int msiof3_rxd_b_pins[] = {
1565     /* RXD */
1566     RCAR_GP_PIN(1, 1),
1567 };
1568
1569 static const unsigned int msiof3_rxd_b_mux[] = {
1570     MSIOF3_RXD_B_MARK,
1571 };
1572
1573 /* - PWM0 ------------------------------------------------------------------ */
1574 static const unsigned int pwm0_a_pins[] = {
1575     /* PWM */
1576     RCAR_GP_PIN(2, 1),
1577 };
1578
1579 static const unsigned int pwm0_a_mux[] = {
1580     PWM0_A_MARK,
1581 };
1582
1583 static const unsigned int pwm0_b_pins[] = {
1584     /* PWM */
1585     RCAR_GP_PIN(1, 18),
1586 };
1587
1588 static const unsigned int pwm0_b_mux[] = {
1589     PWM0_B_MARK,
1590 };
1591
1592 static const unsigned int pwm0_c_pins[] = {
1593     /* PWM */
1594     RCAR_GP_PIN(2, 29),
1595 };
1596
1597 static const unsigned int pwm0_c_mux[] = {
1598     PWM0_C_MARK,
1599 };
1600
1601 /* - PWM1 ------------------------------------------------------------------ */
1602 static const unsigned int pwm1_a_pins[] = {
1603     /* PWM */
1604     RCAR_GP_PIN(2, 2),
1605 };
1606
1607 static const unsigned int pwm1_a_mux[] = {
1608     PWM1_A_MARK,
1609 };
1610
1611 static const unsigned int pwm1_b_pins[] = {
1612     /* PWM */
1613     RCAR_GP_PIN(1, 19),
1614 };
1615
1616 static const unsigned int pwm1_b_mux[] = {
1617     PWM1_B_MARK,
1618 };
1619
1620 static const unsigned int pwm1_c_pins[] = {
1621     /* PWM */
1622     RCAR_GP_PIN(2, 30),
1623 };
1624
1625 static const unsigned int pwm1_c_mux[] = {
1626     PWM1_C_MARK,
1627 };
1628
1629 /* - PWM2 ------------------------------------------------------------------ */
1630 static const unsigned int pwm2_a_pins[] = {
1631     /* PWM */
1632     RCAR_GP_PIN(2, 3),
1633 };
1634
1635 static const unsigned int pwm2_a_mux[] = {
1636     PWM2_A_MARK,
1637 };
1638
1639 static const unsigned int pwm2_b_pins[] = {
1640     /* PWM */
1641     RCAR_GP_PIN(1, 22),
1642 };
1643
1644 static const unsigned int pwm2_b_mux[] = {
1645     PWM2_B_MARK,
1646 };
1647
1648 static const unsigned int pwm2_c_pins[] = {
1649     /* PWM */
1650     RCAR_GP_PIN(2, 31),
1651 };
1652
1653 static const unsigned int pwm2_c_mux[] = {
1654     PWM2_C_MARK,
1655 };
1656
1657 /* - PWM3 ------------------------------------------------------------------ */
1658 static const unsigned int pwm3_a_pins[] = {
1659     /* PWM */
1660     RCAR_GP_PIN(2, 4),
1661 };
1662
1663 static const unsigned int pwm3_a_mux[] = {
1664     PWM3_A_MARK,
1665 };
1666
1667 static const unsigned int pwm3_b_pins[] = {
1668     /* PWM */
1669     RCAR_GP_PIN(1, 27),
1670 };
1671
1672 static const unsigned int pwm3_b_mux[] = {
1673     PWM3_B_MARK,
1674 };
1675
1676 static const unsigned int pwm3_c_pins[] = {
1677     /* PWM */
1678     RCAR_GP_PIN(4, 0),
1679 };
1680
1681 static const unsigned int pwm3_c_mux[] = {
1682     PWM3_C_MARK,
1683 };
1684
1685 /* - QSPI0 ------------------------------------------------------------------ */
1686 static const unsigned int qspi0_ctrl_pins[] = {
1687     /* QSPI0_SPCLK, QSPI0_SSL */
1688     RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
1689 };
1690 static const unsigned int qspi0_ctrl_mux[] = {
1691     QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1692 };
1693 /* - QSPI1 ------------------------------------------------------------------ */
1694 static const unsigned int qspi1_ctrl_pins[] = {
1695     /* QSPI1_SPCLK, QSPI1_SSL */
1696     RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 11),
1697 };
1698 static const unsigned int qspi1_ctrl_mux[] = {
1699     QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1700 };
1701
1702 /* - RPC -------------------------------------------------------------------- */
1703 static const unsigned int rpc_clk_pins[] = {
1704     /* Octal-SPI flash: C/SCLK */
1705     /* HyperFlash: CK, CK# */
1706     RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 6),
1707 };
1708 static const unsigned int rpc_clk_mux[] = {
1709     QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
1710 };
1711 static const unsigned int rpc_ctrl_pins[] = {
1712     /* Octal-SPI flash: S#/CS, DQS */
1713     /* HyperFlash: CS#, RDS */
1714     RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 11),
1715 };
1716 static const unsigned int rpc_ctrl_mux[] = {
1717     QSPI0_SSL_MARK, QSPI1_SSL_MARK,
1718 };
1719 static const unsigned int rpc_data_pins[] = {
1720     /* DQ[0:7] */
1721     RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
1722     RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4),
1723     RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 8),
1724     RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 10),
1725 };
1726 static const unsigned int rpc_data_mux[] = {
1727     QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1728     QSPI0_IO2_MARK, QSPI0_IO3_MARK,
1729     QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1730     QSPI1_IO2_MARK, QSPI1_IO3_MARK,
1731 };
1732 static const unsigned int rpc_reset_pins[] = {
1733     /* RPC_RESET# */
1734     RCAR_GP_PIN(6, 12),
1735 };
1736 static const unsigned int rpc_reset_mux[] = {
1737     RPC_RESET_N_MARK,
1738 };
1739 static const unsigned int rpc_int_pins[] = {
1740     /* RPC_INT# */
1741     RCAR_GP_PIN(6, 13),
1742 };
1743 static const unsigned int rpc_int_mux[] = {
1744     RPC_INT_N_MARK,
1745 };
1746
1747 /* - SCIF0 ------------------------------------------------------------------ */
1748 static const unsigned int scif0_data_a_pins[] = {
1749     /* RX, TX */
1750     RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
1751 };
1752 static const unsigned int scif0_data_a_mux[] = {
1753     RX0_A_MARK, TX0_A_MARK,
1754 };
1755 static const unsigned int scif0_clk_a_pins[] = {
1756     /* SCK */
1757     RCAR_GP_PIN(4, 19),
1758 };
1759 static const unsigned int scif0_clk_a_mux[] = {
1760     SCK0_A_MARK,
1761 };
1762 static const unsigned int scif0_data_b_pins[] = {
1763     /* RX, TX */
1764     RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 28),
1765 };
1766 static const unsigned int scif0_data_b_mux[] = {
1767     RX0_B_MARK, TX0_B_MARK,
1768 };
1769 static const unsigned int scif0_clk_b_pins[] = {
1770     /* SCK */
1771     RCAR_GP_PIN(5, 2),
1772 };
1773 static const unsigned int scif0_clk_b_mux[] = {
1774     SCK0_B_MARK,
1775 };
1776 static const unsigned int scif0_ctrl_pins[] = {
1777     /* RTS, CTS */
1778     RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
1779 };
1780 static const unsigned int scif0_ctrl_mux[] = {
1781     RTS0_N_MARK, CTS0_N_MARK,
1782 };
1783 /* - SCIF1 ------------------------------------------------------------------ */
1784 static const unsigned int scif1_data_a_pins[] = {
1785     /* RX, TX */
1786     RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
1787 };
1788 static const unsigned int scif1_data_a_mux[] = {
1789     RX1_A_MARK, TX1_A_MARK,
1790 };
1791 static const unsigned int scif1_clk_a_pins[] = {
1792     /* SCK */
1793     RCAR_GP_PIN(4, 22),
1794 };
1795 static const unsigned int scif1_clk_a_mux[] = {
1796     SCK1_A_MARK,
1797 };
1798 static const unsigned int scif1_data_b_pins[] = {
1799     /* RX, TX */
1800     RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 28),
1801 };
1802 static const unsigned int scif1_data_b_mux[] = {
1803     RX1_B_MARK, TX1_B_MARK,
1804 };
1805 static const unsigned int scif1_clk_b_pins[] = {
1806     /* SCK */
1807     RCAR_GP_PIN(2, 25),
1808 };
1809 static const unsigned int scif1_clk_b_mux[] = {
1810     SCK1_B_MARK,
1811 };
1812 static const unsigned int scif1_ctrl_pins[] = {
1813     /* RTS, CTS */
1814     RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
1815 };
1816 static const unsigned int scif1_ctrl_mux[] = {
1817     RTS1_N_MARK, CTS1_N_MARK,
1818 };
1819
1820 /* - SCIF2 ------------------------------------------------------------------ */
1821 static const unsigned int scif2_data_pins[] = {
1822     /* RX, TX */
1823     RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
1824 };
1825 static const unsigned int scif2_data_mux[] = {
1826     RX2_MARK, TX2_MARK,
1827 };
1828 static const unsigned int scif2_clk_pins[] = {
1829     /* SCK */
1830     RCAR_GP_PIN(4, 25),
1831 };
1832 static const unsigned int scif2_clk_mux[] = {
1833     SCK2_MARK,
1834 };
1835 /* - SCIF3 ------------------------------------------------------------------ */
1836 static const unsigned int scif3_data_a_pins[] = {
1837     /* RX, TX */
1838     RCAR_GP_PIN(2, 31), RCAR_GP_PIN(4, 00),
1839 };
1840 static const unsigned int scif3_data_a_mux[] = {
1841     RX3_A_MARK, TX3_A_MARK,
1842 };
1843 static const unsigned int scif3_clk_a_pins[] = {
1844     /* SCK */
1845     RCAR_GP_PIN(2, 30),
1846 };
1847 static const unsigned int scif3_clk_a_mux[] = {
1848     SCK3_A_MARK,
1849 };
1850 static const unsigned int scif3_data_b_pins[] = {
1851     /* RX, TX */
1852     RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31),
1853 };
1854 static const unsigned int scif3_data_b_mux[] = {
1855     RX3_B_MARK, TX3_B_MARK,
1856 };
1857 static const unsigned int scif3_clk_b_pins[] = {
1858     /* SCK */
1859     RCAR_GP_PIN(1, 29),
1860 };
1861 static const unsigned int scif3_clk_b_mux[] = {
1862     SCK3_B_MARK,
1863 };
1864 /* - SCIF4 ------------------------------------------------------------------ */
1865 static const unsigned int scif4_data_a_pins[] = {
1866     /* RX, TX */
1867     RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1868 };
1869 static const unsigned int scif4_data_a_mux[] = {
1870     RX4_A_MARK, TX4_A_MARK,
1871 };
1872 static const unsigned int scif4_clk_a_pins[] = {
1873     /* SCK */
1874     RCAR_GP_PIN(2, 6),
1875 };
1876 static const unsigned int scif4_clk_a_mux[] = {
1877     SCK4_A_MARK,
1878 };
1879 static const unsigned int scif4_data_b_pins[] = {
1880     /* RX, TX */
1881     RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
1882 };
1883 static const unsigned int scif4_data_b_mux[] = {
1884     RX4_B_MARK, TX4_B_MARK,
1885 };
1886 static const unsigned int scif4_clk_b_pins[] = {
1887     /* SCK */
1888     RCAR_GP_PIN(1, 15),
1889 };
1890 static const unsigned int scif4_clk_b_mux[] = {
1891     SCK4_B_MARK,
1892 };
1893 /* - SCIF5 ------------------------------------------------------------------ */
1894 static const unsigned int scif5_data_a_pins[] = {
1895     /* RX, TX */
1896     RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
1897 };
1898 static const unsigned int scif5_data_a_mux[] = {
1899     RX5_A_MARK, TX5_A_MARK,
1900 };
1901 static const unsigned int scif5_clk_a_pins[] = {
1902     /* SCK */
1903     RCAR_GP_PIN(0, 6),
1904 };
1905 static const unsigned int scif5_clk_a_mux[] = {
1906     SCK5_A_MARK,
1907 };
1908 static const unsigned int scif5_data_b_pins[] = {
1909     /* RX, TX */
1910     RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
1911 };
1912 static const unsigned int scif5_data_b_mux[] = {
1913     RX5_B_MARK, TX5_B_MARK,
1914 };
1915 static const unsigned int scif5_clk_b_pins[] = {
1916     /* SCK */
1917     RCAR_GP_PIN(1, 3),
1918 };
1919 static const unsigned int scif5_clk_b_mux[] = {
1920     SCK5_B_MARK,
1921 };
1922 /* - SCIF Clock ------------------------------------------------------------- */
1923 static const unsigned int scif_clk_pins[] = {
1924     /* SCIF_CLK */
1925     RCAR_GP_PIN(2, 27),
1926 };
1927 static const unsigned int scif_clk_mux[] = {
1928     SCIF_CLK_MARK,
1929 };
1930
1931 /* - SSI ---------------------------------------------------------------*/
1932 static const unsigned int ssi3_data_pins[] = {
1933     /* SDATA */
1934     RCAR_GP_PIN(4, 3),
1935 };
1936 static const unsigned int ssi3_data_mux[] = {
1937     SSI_SDATA3_MARK,
1938 };
1939 static const unsigned int ssi34_ctrl_pins[] = {
1940     /* SCK,  WS */
1941     RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 4),
1942 };
1943 static const unsigned int ssi34_ctrl_mux[] = {
1944     SSI_SCK34_MARK, SSI_WS34_MARK,
1945 };
1946 static const unsigned int ssi4_ctrl_a_pins[] = {
1947     /* SCK, WS */
1948     RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
1949 };
1950 static const unsigned int ssi4_ctrl_a_mux[] = {
1951     SSI_SCK4_A_MARK, SSI_WS4_A_MARK,
1952 };
1953 static const unsigned int ssi4_data_a_pins[] = {
1954     /* SDATA */
1955     RCAR_GP_PIN(4, 6),
1956 };
1957 static const unsigned int ssi4_data_a_mux[] = {
1958     SSI_SDATA4_A_MARK,
1959 };
1960 static const unsigned int ssi4_ctrl_b_pins[] = {
1961     /* SCK, WS */
1962     RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 20),
1963 };
1964 static const unsigned int ssi4_ctrl_b_mux[] = {
1965     SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
1966 };
1967 static const unsigned int ssi4_data_b_pins[] = {
1968     /* SDATA */
1969     RCAR_GP_PIN(2, 16),
1970 };
1971 static const unsigned int ssi4_data_b_mux[] = {
1972     SSI_SDATA4_B_MARK,
1973 };
1974
1975 /* - USB0 ------------------------------------------------------------------- */
1976 static const unsigned int usb0_pins[] = {
1977     /* PWEN, OVC */
1978     RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
1979 };
1980 static const unsigned int usb0_mux[] = {
1981     USB0_PWEN_MARK, USB0_OVC_MARK,
1982 };
1983
1984 /* - VIN4 ------------------------------------------------------------------- */
1985 static const unsigned int vin4_data18_pins[] = {
1986     RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1987     RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1988     RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1989     RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1990     RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
1991     RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
1992     RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1993     RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1994     RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1995 };
1996 static const unsigned int vin4_data18_mux[] = {
1997     VI4_DATA2_MARK, VI4_DATA3_MARK,
1998     VI4_DATA4_MARK, VI4_DATA5_MARK,
1999     VI4_DATA6_MARK, VI4_DATA7_MARK,
2000     VI4_DATA10_MARK, VI4_DATA11_MARK,
2001     VI4_DATA12_MARK, VI4_DATA13_MARK,
2002     VI4_DATA14_MARK, VI4_DATA15_MARK,
2003     VI4_DATA18_MARK, VI4_DATA19_MARK,
2004     VI4_DATA20_MARK, VI4_DATA21_MARK,
2005     VI4_DATA22_MARK, VI4_DATA23_MARK,
2006 };
2007 static const unsigned int vin4_data_pins[] = {
2008     RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
2009     RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
2010     RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
2011     RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2012     RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
2013     RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2014     RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2015     RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
2016     RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
2017     RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
2018     RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2019     RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
2020 };
2021 static const unsigned int vin4_data_mux[] = {
2022     VI4_DATA0_MARK, VI4_DATA1_MARK,
2023     VI4_DATA2_MARK, VI4_DATA3_MARK,
2024     VI4_DATA4_MARK, VI4_DATA5_MARK,
2025     VI4_DATA6_MARK, VI4_DATA7_MARK,
2026     VI4_DATA8_MARK,  VI4_DATA9_MARK,
2027     VI4_DATA10_MARK, VI4_DATA11_MARK,
2028     VI4_DATA12_MARK, VI4_DATA13_MARK,
2029     VI4_DATA14_MARK, VI4_DATA15_MARK,
2030     VI4_DATA16_MARK, VI4_DATA17_MARK,
2031     VI4_DATA18_MARK, VI4_DATA19_MARK,
2032     VI4_DATA20_MARK, VI4_DATA21_MARK,
2033     VI4_DATA22_MARK, VI4_DATA23_MARK,
2034 };
2035 static const unsigned int vin4_sync_pins[] = {
2036     /* HSYNC#, VSYNC# */
2037     RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
2038 };
2039 static const unsigned int vin4_sync_mux[] = {
2040     VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
2041 };
2042 static const unsigned int vin4_field_pins[] = {
2043     /* FIELD */
2044     RCAR_GP_PIN(2, 27),
2045 };
2046 static const unsigned int vin4_field_mux[] = {
2047     VI4_FIELD_MARK,
2048 };
2049 static const unsigned int vin4_clkenb_pins[] = {
2050     /* CLKENB */
2051     RCAR_GP_PIN(2, 28),
2052 };
2053 static const unsigned int vin4_clkenb_mux[] = {
2054     VI4_CLKENB_MARK,
2055 };
2056 static const unsigned int vin4_clk_pins[] = {
2057     /* CLK */
2058     RCAR_GP_PIN(2, 0),
2059 };
2060 static const unsigned int vin4_clk_mux[] = {
2061     VI4_CLK_MARK,
2062 };
2063
2064 static const struct sh_pfc_pin_group pinmux_groups[] = {
2065     SH_PFC_PIN_GROUP(audio_clk_a),
2066     SH_PFC_PIN_GROUP(audio_clk_b),
2067     SH_PFC_PIN_GROUP(audio_clkout),
2068     SH_PFC_PIN_GROUP(audio_clkout1),
2069     SH_PFC_PIN_GROUP(avb0_link),
2070     SH_PFC_PIN_GROUP(avb0_magic),
2071     SH_PFC_PIN_GROUP(avb0_phy_int),
2072     SH_PFC_PIN_GROUP_ALIAS(avb0_mdc, avb0_mdio),    /* Deprecated */
2073     SH_PFC_PIN_GROUP(avb0_mdio),
2074     SH_PFC_PIN_GROUP(avb0_mii),
2075     SH_PFC_PIN_GROUP(avb0_avtp_pps_a),
2076     SH_PFC_PIN_GROUP(avb0_avtp_match_a),
2077     SH_PFC_PIN_GROUP(avb0_avtp_capture_a),
2078     SH_PFC_PIN_GROUP(avb0_avtp_pps_b),
2079     SH_PFC_PIN_GROUP(avb0_avtp_match_b),
2080     SH_PFC_PIN_GROUP(avb0_avtp_capture_b),
2081     SH_PFC_PIN_GROUP(can0_data_a),
2082     SH_PFC_PIN_GROUP(can0_data_b),
2083     SH_PFC_PIN_GROUP(can1_data_a),
2084     SH_PFC_PIN_GROUP(can1_data_b),
2085     SH_PFC_PIN_GROUP(can_clk),
2086     SH_PFC_PIN_GROUP(canfd0_data),
2087     SH_PFC_PIN_GROUP(canfd1_data),
2088     SH_PFC_PIN_GROUP(du_rgb666),
2089     SH_PFC_PIN_GROUP(du_rgb888),
2090     SH_PFC_PIN_GROUP(du_clk_in_1),
2091     SH_PFC_PIN_GROUP(du_clk_out_0),
2092     SH_PFC_PIN_GROUP(du_sync),
2093     SH_PFC_PIN_GROUP(du_disp_cde),
2094     SH_PFC_PIN_GROUP(du_cde),
2095     SH_PFC_PIN_GROUP(du_disp),
2096     SH_PFC_PIN_GROUP(i2c0),
2097     SH_PFC_PIN_GROUP(i2c1),
2098     SH_PFC_PIN_GROUP(i2c2_a),
2099     SH_PFC_PIN_GROUP(i2c2_b),
2100     SH_PFC_PIN_GROUP(i2c3_a),
2101     SH_PFC_PIN_GROUP(i2c3_b),
2102     SH_PFC_PIN_GROUP(mlb_3pin),
2103     BUS_DATA_PIN_GROUP(mmc_data, 1),
2104     BUS_DATA_PIN_GROUP(mmc_data, 4),
2105     BUS_DATA_PIN_GROUP(mmc_data, 8),
2106     SH_PFC_PIN_GROUP(mmc_ctrl),
2107     SH_PFC_PIN_GROUP(msiof0_clk),
2108     SH_PFC_PIN_GROUP(msiof0_sync),
2109     SH_PFC_PIN_GROUP(msiof0_ss1),
2110     SH_PFC_PIN_GROUP(msiof0_ss2),
2111     SH_PFC_PIN_GROUP(msiof0_txd),
2112     SH_PFC_PIN_GROUP(msiof0_rxd),
2113     SH_PFC_PIN_GROUP(msiof1_clk),
2114     SH_PFC_PIN_GROUP(msiof1_sync),
2115     SH_PFC_PIN_GROUP(msiof1_ss1),
2116     SH_PFC_PIN_GROUP(msiof1_ss2),
2117     SH_PFC_PIN_GROUP(msiof1_txd),
2118     SH_PFC_PIN_GROUP(msiof1_rxd),
2119     SH_PFC_PIN_GROUP(msiof2_clk),
2120     SH_PFC_PIN_GROUP(msiof2_sync_a),
2121     SH_PFC_PIN_GROUP(msiof2_sync_b),
2122     SH_PFC_PIN_GROUP(msiof2_ss1),
2123     SH_PFC_PIN_GROUP(msiof2_ss2),
2124     SH_PFC_PIN_GROUP(msiof2_txd),
2125     SH_PFC_PIN_GROUP(msiof2_rxd),
2126     SH_PFC_PIN_GROUP(msiof3_clk_a),
2127     SH_PFC_PIN_GROUP(msiof3_sync_a),
2128     SH_PFC_PIN_GROUP(msiof3_ss1_a),
2129     SH_PFC_PIN_GROUP(msiof3_ss2_a),
2130     SH_PFC_PIN_GROUP(msiof3_txd_a),
2131     SH_PFC_PIN_GROUP(msiof3_rxd_a),
2132     SH_PFC_PIN_GROUP(msiof3_clk_b),
2133     SH_PFC_PIN_GROUP(msiof3_sync_b),
2134     SH_PFC_PIN_GROUP(msiof3_ss1_b),
2135     SH_PFC_PIN_GROUP(msiof3_ss2_b),
2136     SH_PFC_PIN_GROUP(msiof3_txd_b),
2137     SH_PFC_PIN_GROUP(msiof3_rxd_b),
2138     SH_PFC_PIN_GROUP(pwm0_a),
2139     SH_PFC_PIN_GROUP(pwm0_b),
2140     SH_PFC_PIN_GROUP(pwm0_c),
2141     SH_PFC_PIN_GROUP(pwm1_a),
2142     SH_PFC_PIN_GROUP(pwm1_b),
2143     SH_PFC_PIN_GROUP(pwm1_c),
2144     SH_PFC_PIN_GROUP(pwm2_a),
2145     SH_PFC_PIN_GROUP(pwm2_b),
2146     SH_PFC_PIN_GROUP(pwm2_c),
2147     SH_PFC_PIN_GROUP(pwm3_a),
2148     SH_PFC_PIN_GROUP(pwm3_b),
2149     SH_PFC_PIN_GROUP(pwm3_c),
2150     SH_PFC_PIN_GROUP(qspi0_ctrl),
2151     SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
2152     SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
2153     SH_PFC_PIN_GROUP(qspi1_ctrl),
2154     SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
2155     SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
2156     BUS_DATA_PIN_GROUP(rpc_clk, 1),
2157     BUS_DATA_PIN_GROUP(rpc_clk, 2),
2158     SH_PFC_PIN_GROUP(rpc_ctrl),
2159     SH_PFC_PIN_GROUP(rpc_data),
2160     SH_PFC_PIN_GROUP(rpc_reset),
2161     SH_PFC_PIN_GROUP(rpc_int),
2162     SH_PFC_PIN_GROUP(scif0_data_a),
2163     SH_PFC_PIN_GROUP(scif0_clk_a),
2164     SH_PFC_PIN_GROUP(scif0_data_b),
2165     SH_PFC_PIN_GROUP(scif0_clk_b),
2166     SH_PFC_PIN_GROUP(scif0_ctrl),
2167     SH_PFC_PIN_GROUP(scif1_data_a),
2168     SH_PFC_PIN_GROUP(scif1_clk_a),
2169     SH_PFC_PIN_GROUP(scif1_data_b),
2170     SH_PFC_PIN_GROUP(scif1_clk_b),
2171     SH_PFC_PIN_GROUP(scif1_ctrl),
2172     SH_PFC_PIN_GROUP(scif2_data),
2173     SH_PFC_PIN_GROUP(scif2_clk),
2174     SH_PFC_PIN_GROUP(scif3_data_a),
2175     SH_PFC_PIN_GROUP(scif3_clk_a),
2176     SH_PFC_PIN_GROUP(scif3_data_b),
2177     SH_PFC_PIN_GROUP(scif3_clk_b),
2178     SH_PFC_PIN_GROUP(scif4_data_a),
2179     SH_PFC_PIN_GROUP(scif4_clk_a),
2180     SH_PFC_PIN_GROUP(scif4_data_b),
2181     SH_PFC_PIN_GROUP(scif4_clk_b),
2182     SH_PFC_PIN_GROUP(scif5_data_a),
2183     SH_PFC_PIN_GROUP(scif5_clk_a),
2184     SH_PFC_PIN_GROUP(scif5_data_b),
2185     SH_PFC_PIN_GROUP(scif5_clk_b),
2186     SH_PFC_PIN_GROUP(scif_clk),
2187     SH_PFC_PIN_GROUP(ssi3_data),
2188     SH_PFC_PIN_GROUP(ssi34_ctrl),
2189     SH_PFC_PIN_GROUP(ssi4_ctrl_a),
2190     SH_PFC_PIN_GROUP(ssi4_data_a),
2191     SH_PFC_PIN_GROUP(ssi4_ctrl_b),
2192     SH_PFC_PIN_GROUP(ssi4_data_b),
2193     SH_PFC_PIN_GROUP(usb0),
2194     BUS_DATA_PIN_GROUP(vin4_data, 8),
2195     BUS_DATA_PIN_GROUP(vin4_data, 10),
2196     BUS_DATA_PIN_GROUP(vin4_data, 12),
2197     BUS_DATA_PIN_GROUP(vin4_data, 16),
2198     SH_PFC_PIN_GROUP(vin4_data18),
2199     BUS_DATA_PIN_GROUP(vin4_data, 20),
2200     BUS_DATA_PIN_GROUP(vin4_data, 24),
2201     SH_PFC_PIN_GROUP(vin4_sync),
2202     SH_PFC_PIN_GROUP(vin4_field),
2203     SH_PFC_PIN_GROUP(vin4_clkenb),
2204     SH_PFC_PIN_GROUP(vin4_clk),
2205 };
2206
2207 static const char * const audio_clk_groups[] = {
2208     "audio_clk_a",
2209     "audio_clk_b",
2210     "audio_clkout",
2211     "audio_clkout1",
2212 };
2213
2214 static const char * const avb0_groups[] = {
2215     "avb0_link",
2216     "avb0_magic",
2217     "avb0_phy_int",
2218     "avb0_mdc", /* Deprecated, please use "avb0_mdio" instead */
2219     "avb0_mdio",
2220     "avb0_mii",
2221     "avb0_avtp_pps_a",
2222     "avb0_avtp_match_a",
2223     "avb0_avtp_capture_a",
2224     "avb0_avtp_pps_b",
2225     "avb0_avtp_match_b",
2226     "avb0_avtp_capture_b",
2227 };
2228
2229 static const char * const can0_groups[] = {
2230     "can0_data_a",
2231     "can0_data_b",
2232 };
2233 static const char * const can1_groups[] = {
2234     "can1_data_a",
2235     "can1_data_b",
2236 };
2237 static const char * const can_clk_groups[] = {
2238     "can_clk",
2239 };
2240
2241 static const char * const canfd0_groups[] = {
2242     "canfd0_data",
2243 };
2244 static const char * const canfd1_groups[] = {
2245     "canfd1_data",
2246 };
2247
2248 static const char * const du_groups[] = {
2249     "du_rgb666",
2250     "du_rgb888",
2251     "du_clk_in_1",
2252     "du_clk_out_0",
2253     "du_sync",
2254     "du_disp_cde",
2255     "du_cde",
2256     "du_disp",
2257 };
2258
2259 static const char * const i2c0_groups[] = {
2260     "i2c0",
2261 };
2262 static const char * const i2c1_groups[] = {
2263     "i2c1",
2264 };
2265
2266 static const char * const i2c2_groups[] = {
2267     "i2c2_a",
2268     "i2c2_b",
2269 };
2270
2271 static const char * const i2c3_groups[] = {
2272     "i2c3_a",
2273     "i2c3_b",
2274 };
2275
2276 static const char * const mlb_3pin_groups[] = {
2277     "mlb_3pin",
2278 };
2279
2280 static const char * const mmc_groups[] = {
2281     "mmc_data1",
2282     "mmc_data4",
2283     "mmc_data8",
2284     "mmc_ctrl",
2285 };
2286
2287 static const char * const msiof0_groups[] = {
2288     "msiof0_clk",
2289     "msiof0_sync",
2290     "msiof0_ss1",
2291     "msiof0_ss2",
2292     "msiof0_txd",
2293     "msiof0_rxd",
2294 };
2295
2296 static const char * const msiof1_groups[] = {
2297     "msiof1_clk",
2298     "msiof1_sync",
2299     "msiof1_ss1",
2300     "msiof1_ss2",
2301     "msiof1_txd",
2302     "msiof1_rxd",
2303 };
2304
2305 static const char * const msiof2_groups[] = {
2306     "msiof2_clk",
2307     "msiof2_sync_a",
2308     "msiof2_sync_b",
2309     "msiof2_ss1",
2310     "msiof2_ss2",
2311     "msiof2_txd",
2312     "msiof2_rxd",
2313 };
2314
2315 static const char * const msiof3_groups[] = {
2316     "msiof3_clk_a",
2317     "msiof3_sync_a",
2318     "msiof3_ss1_a",
2319     "msiof3_ss2_a",
2320     "msiof3_txd_a",
2321     "msiof3_rxd_a",
2322     "msiof3_clk_b",
2323     "msiof3_sync_b",
2324     "msiof3_ss1_b",
2325     "msiof3_ss2_b",
2326     "msiof3_txd_b",
2327     "msiof3_rxd_b",
2328 };
2329
2330 static const char * const pwm0_groups[] = {
2331     "pwm0_a",
2332     "pwm0_b",
2333     "pwm0_c",
2334 };
2335
2336 static const char * const pwm1_groups[] = {
2337     "pwm1_a",
2338     "pwm1_b",
2339     "pwm1_c",
2340 };
2341
2342 static const char * const pwm2_groups[] = {
2343     "pwm2_a",
2344     "pwm2_b",
2345     "pwm2_c",
2346 };
2347
2348 static const char * const pwm3_groups[] = {
2349     "pwm3_a",
2350     "pwm3_b",
2351     "pwm3_c",
2352 };
2353
2354 static const char * const qspi0_groups[] = {
2355     "qspi0_ctrl",
2356     "qspi0_data2",
2357     "qspi0_data4",
2358 };
2359
2360 static const char * const qspi1_groups[] = {
2361     "qspi1_ctrl",
2362     "qspi1_data2",
2363     "qspi1_data4",
2364 };
2365
2366 static const char * const rpc_groups[] = {
2367     "rpc_clk1",
2368     "rpc_clk2",
2369     "rpc_ctrl",
2370     "rpc_data",
2371     "rpc_reset",
2372     "rpc_int",
2373 };
2374
2375 static const char * const scif0_groups[] = {
2376     "scif0_data_a",
2377     "scif0_clk_a",
2378     "scif0_data_b",
2379     "scif0_clk_b",
2380     "scif0_ctrl",
2381 };
2382
2383 static const char * const scif1_groups[] = {
2384     "scif1_data_a",
2385     "scif1_clk_a",
2386     "scif1_data_b",
2387     "scif1_clk_b",
2388     "scif1_ctrl",
2389 };
2390
2391 static const char * const scif2_groups[] = {
2392     "scif2_data",
2393     "scif2_clk",
2394 };
2395
2396 static const char * const scif3_groups[] = {
2397     "scif3_data_a",
2398     "scif3_clk_a",
2399     "scif3_data_b",
2400     "scif3_clk_b",
2401 };
2402
2403 static const char * const scif4_groups[] = {
2404     "scif4_data_a",
2405     "scif4_clk_a",
2406     "scif4_data_b",
2407     "scif4_clk_b",
2408 };
2409
2410 static const char * const scif5_groups[] = {
2411     "scif5_data_a",
2412     "scif5_clk_a",
2413     "scif5_data_b",
2414     "scif5_clk_b",
2415 };
2416
2417 static const char * const scif_clk_groups[] = {
2418     "scif_clk",
2419 };
2420
2421 static const char * const ssi_groups[] = {
2422     "ssi3_data",
2423     "ssi34_ctrl",
2424     "ssi4_ctrl_a",
2425     "ssi4_data_a",
2426     "ssi4_ctrl_b",
2427     "ssi4_data_b",
2428 };
2429
2430 static const char * const usb0_groups[] = {
2431     "usb0",
2432 };
2433
2434 static const char * const vin4_groups[] = {
2435     "vin4_data8",
2436     "vin4_data10",
2437     "vin4_data12",
2438     "vin4_data16",
2439     "vin4_data18",
2440     "vin4_data20",
2441     "vin4_data24",
2442     "vin4_sync",
2443     "vin4_field",
2444     "vin4_clkenb",
2445     "vin4_clk",
2446 };
2447
2448 static const struct sh_pfc_function pinmux_functions[] = {
2449     SH_PFC_FUNCTION(audio_clk),
2450     SH_PFC_FUNCTION(avb0),
2451     SH_PFC_FUNCTION(can0),
2452     SH_PFC_FUNCTION(can1),
2453     SH_PFC_FUNCTION(can_clk),
2454     SH_PFC_FUNCTION(canfd0),
2455     SH_PFC_FUNCTION(canfd1),
2456     SH_PFC_FUNCTION(du),
2457     SH_PFC_FUNCTION(i2c0),
2458     SH_PFC_FUNCTION(i2c1),
2459     SH_PFC_FUNCTION(i2c2),
2460     SH_PFC_FUNCTION(i2c3),
2461     SH_PFC_FUNCTION(mlb_3pin),
2462     SH_PFC_FUNCTION(mmc),
2463     SH_PFC_FUNCTION(msiof0),
2464     SH_PFC_FUNCTION(msiof1),
2465     SH_PFC_FUNCTION(msiof2),
2466     SH_PFC_FUNCTION(msiof3),
2467     SH_PFC_FUNCTION(pwm0),
2468     SH_PFC_FUNCTION(pwm1),
2469     SH_PFC_FUNCTION(pwm2),
2470     SH_PFC_FUNCTION(pwm3),
2471     SH_PFC_FUNCTION(qspi0),
2472     SH_PFC_FUNCTION(qspi1),
2473     SH_PFC_FUNCTION(rpc),
2474     SH_PFC_FUNCTION(scif0),
2475     SH_PFC_FUNCTION(scif1),
2476     SH_PFC_FUNCTION(scif2),
2477     SH_PFC_FUNCTION(scif3),
2478     SH_PFC_FUNCTION(scif4),
2479     SH_PFC_FUNCTION(scif5),
2480     SH_PFC_FUNCTION(scif_clk),
2481     SH_PFC_FUNCTION(ssi),
2482     SH_PFC_FUNCTION(usb0),
2483     SH_PFC_FUNCTION(vin4),
2484 };
2485
2486 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2487 #define F_(x, y)    FN_##y
2488 #define FM(x)       FN_##x
2489     { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
2490                  GROUP(-23, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2491                  GROUP(
2492         /* GP0_31_9 RESERVED */
2493         GP_0_8_FN,  GPSR0_8,
2494         GP_0_7_FN,  GPSR0_7,
2495         GP_0_6_FN,  GPSR0_6,
2496         GP_0_5_FN,  GPSR0_5,
2497         GP_0_4_FN,  GPSR0_4,
2498         GP_0_3_FN,  GPSR0_3,
2499         GP_0_2_FN,  GPSR0_2,
2500         GP_0_1_FN,  GPSR0_1,
2501         GP_0_0_FN,  GPSR0_0, ))
2502     },
2503     { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2504         GP_1_31_FN, GPSR1_31,
2505         GP_1_30_FN, GPSR1_30,
2506         GP_1_29_FN, GPSR1_29,
2507         GP_1_28_FN, GPSR1_28,
2508         GP_1_27_FN, GPSR1_27,
2509         GP_1_26_FN, GPSR1_26,
2510         GP_1_25_FN, GPSR1_25,
2511         GP_1_24_FN, GPSR1_24,
2512         GP_1_23_FN, GPSR1_23,
2513         GP_1_22_FN, GPSR1_22,
2514         GP_1_21_FN, GPSR1_21,
2515         GP_1_20_FN, GPSR1_20,
2516         GP_1_19_FN, GPSR1_19,
2517         GP_1_18_FN, GPSR1_18,
2518         GP_1_17_FN, GPSR1_17,
2519         GP_1_16_FN, GPSR1_16,
2520         GP_1_15_FN, GPSR1_15,
2521         GP_1_14_FN, GPSR1_14,
2522         GP_1_13_FN, GPSR1_13,
2523         GP_1_12_FN, GPSR1_12,
2524         GP_1_11_FN, GPSR1_11,
2525         GP_1_10_FN, GPSR1_10,
2526         GP_1_9_FN,  GPSR1_9,
2527         GP_1_8_FN,  GPSR1_8,
2528         GP_1_7_FN,  GPSR1_7,
2529         GP_1_6_FN,  GPSR1_6,
2530         GP_1_5_FN,  GPSR1_5,
2531         GP_1_4_FN,  GPSR1_4,
2532         GP_1_3_FN,  GPSR1_3,
2533         GP_1_2_FN,  GPSR1_2,
2534         GP_1_1_FN,  GPSR1_1,
2535         GP_1_0_FN,  GPSR1_0, ))
2536     },
2537     { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2538         GP_2_31_FN, GPSR2_31,
2539         GP_2_30_FN, GPSR2_30,
2540         GP_2_29_FN, GPSR2_29,
2541         GP_2_28_FN, GPSR2_28,
2542         GP_2_27_FN, GPSR2_27,
2543         GP_2_26_FN, GPSR2_26,
2544         GP_2_25_FN, GPSR2_25,
2545         GP_2_24_FN, GPSR2_24,
2546         GP_2_23_FN, GPSR2_23,
2547         GP_2_22_FN, GPSR2_22,
2548         GP_2_21_FN, GPSR2_21,
2549         GP_2_20_FN, GPSR2_20,
2550         GP_2_19_FN, GPSR2_19,
2551         GP_2_18_FN, GPSR2_18,
2552         GP_2_17_FN, GPSR2_17,
2553         GP_2_16_FN, GPSR2_16,
2554         GP_2_15_FN, GPSR2_15,
2555         GP_2_14_FN, GPSR2_14,
2556         GP_2_13_FN, GPSR2_13,
2557         GP_2_12_FN, GPSR2_12,
2558         GP_2_11_FN, GPSR2_11,
2559         GP_2_10_FN, GPSR2_10,
2560         GP_2_9_FN,  GPSR2_9,
2561         GP_2_8_FN,  GPSR2_8,
2562         GP_2_7_FN,  GPSR2_7,
2563         GP_2_6_FN,  GPSR2_6,
2564         GP_2_5_FN,  GPSR2_5,
2565         GP_2_4_FN,  GPSR2_4,
2566         GP_2_3_FN,  GPSR2_3,
2567         GP_2_2_FN,  GPSR2_2,
2568         GP_2_1_FN,  GPSR2_1,
2569         GP_2_0_FN,  GPSR2_0, ))
2570     },
2571     { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
2572                  GROUP(-22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2573                  GROUP(
2574         /* GP3_31_10 RESERVED */
2575         GP_3_9_FN,  GPSR3_9,
2576         GP_3_8_FN,  GPSR3_8,
2577         GP_3_7_FN,  GPSR3_7,
2578         GP_3_6_FN,  GPSR3_6,
2579         GP_3_5_FN,  GPSR3_5,
2580         GP_3_4_FN,  GPSR3_4,
2581         GP_3_3_FN,  GPSR3_3,
2582         GP_3_2_FN,  GPSR3_2,
2583         GP_3_1_FN,  GPSR3_1,
2584         GP_3_0_FN,  GPSR3_0, ))
2585     },
2586     { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
2587         GP_4_31_FN, GPSR4_31,
2588         GP_4_30_FN, GPSR4_30,
2589         GP_4_29_FN, GPSR4_29,
2590         GP_4_28_FN, GPSR4_28,
2591         GP_4_27_FN, GPSR4_27,
2592         GP_4_26_FN, GPSR4_26,
2593         GP_4_25_FN, GPSR4_25,
2594         GP_4_24_FN, GPSR4_24,
2595         GP_4_23_FN, GPSR4_23,
2596         GP_4_22_FN, GPSR4_22,
2597         GP_4_21_FN, GPSR4_21,
2598         GP_4_20_FN, GPSR4_20,
2599         GP_4_19_FN, GPSR4_19,
2600         GP_4_18_FN, GPSR4_18,
2601         GP_4_17_FN, GPSR4_17,
2602         GP_4_16_FN, GPSR4_16,
2603         GP_4_15_FN, GPSR4_15,
2604         GP_4_14_FN, GPSR4_14,
2605         GP_4_13_FN, GPSR4_13,
2606         GP_4_12_FN, GPSR4_12,
2607         GP_4_11_FN, GPSR4_11,
2608         GP_4_10_FN, GPSR4_10,
2609         GP_4_9_FN,  GPSR4_9,
2610         GP_4_8_FN,  GPSR4_8,
2611         GP_4_7_FN,  GPSR4_7,
2612         GP_4_6_FN,  GPSR4_6,
2613         GP_4_5_FN,  GPSR4_5,
2614         GP_4_4_FN,  GPSR4_4,
2615         GP_4_3_FN,  GPSR4_3,
2616         GP_4_2_FN,  GPSR4_2,
2617         GP_4_1_FN,  GPSR4_1,
2618         GP_4_0_FN,  GPSR4_0, ))
2619     },
2620     { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
2621                  GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2622                    1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2623                  GROUP(
2624         /* GP5_31_21 RESERVED */
2625         GP_5_20_FN, GPSR5_20,
2626         GP_5_19_FN, GPSR5_19,
2627         GP_5_18_FN, GPSR5_18,
2628         GP_5_17_FN, GPSR5_17,
2629         GP_5_16_FN, GPSR5_16,
2630         GP_5_15_FN, GPSR5_15,
2631         GP_5_14_FN, GPSR5_14,
2632         GP_5_13_FN, GPSR5_13,
2633         GP_5_12_FN, GPSR5_12,
2634         GP_5_11_FN, GPSR5_11,
2635         GP_5_10_FN, GPSR5_10,
2636         GP_5_9_FN,  GPSR5_9,
2637         GP_5_8_FN,  GPSR5_8,
2638         GP_5_7_FN,  GPSR5_7,
2639         GP_5_6_FN,  GPSR5_6,
2640         GP_5_5_FN,  GPSR5_5,
2641         GP_5_4_FN,  GPSR5_4,
2642         GP_5_3_FN,  GPSR5_3,
2643         GP_5_2_FN,  GPSR5_2,
2644         GP_5_1_FN,  GPSR5_1,
2645         GP_5_0_FN,  GPSR5_0, ))
2646     },
2647     { PINMUX_CFG_REG_VAR("GPSR6", 0xe6060118, 32,
2648                  GROUP(-18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2649                    1, 1, 1),
2650                  GROUP(
2651         /* GP6_31_14 RESERVED */
2652         GP_6_13_FN, GPSR6_13,
2653         GP_6_12_FN, GPSR6_12,
2654         GP_6_11_FN, GPSR6_11,
2655         GP_6_10_FN, GPSR6_10,
2656         GP_6_9_FN,  GPSR6_9,
2657         GP_6_8_FN,  GPSR6_8,
2658         GP_6_7_FN,  GPSR6_7,
2659         GP_6_6_FN,  GPSR6_6,
2660         GP_6_5_FN,  GPSR6_5,
2661         GP_6_4_FN,  GPSR6_4,
2662         GP_6_3_FN,  GPSR6_3,
2663         GP_6_2_FN,  GPSR6_2,
2664         GP_6_1_FN,  GPSR6_1,
2665         GP_6_0_FN,  GPSR6_0, ))
2666     },
2667 #undef F_
2668 #undef FM
2669
2670 #define F_(x, y)    x,
2671 #define FM(x)       FN_##x,
2672     { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2673         IP0_31_28
2674         IP0_27_24
2675         IP0_23_20
2676         IP0_19_16
2677         IP0_15_12
2678         IP0_11_8
2679         IP0_7_4
2680         IP0_3_0 ))
2681     },
2682     { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2683         IP1_31_28
2684         IP1_27_24
2685         IP1_23_20
2686         IP1_19_16
2687         IP1_15_12
2688         IP1_11_8
2689         IP1_7_4
2690         IP1_3_0 ))
2691     },
2692     { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2693         IP2_31_28
2694         IP2_27_24
2695         IP2_23_20
2696         IP2_19_16
2697         IP2_15_12
2698         IP2_11_8
2699         IP2_7_4
2700         IP2_3_0 ))
2701     },
2702     { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2703         IP3_31_28
2704         IP3_27_24
2705         IP3_23_20
2706         IP3_19_16
2707         IP3_15_12
2708         IP3_11_8
2709         IP3_7_4
2710         IP3_3_0 ))
2711     },
2712     { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2713         IP4_31_28
2714         IP4_27_24
2715         IP4_23_20
2716         IP4_19_16
2717         IP4_15_12
2718         IP4_11_8
2719         IP4_7_4
2720         IP4_3_0 ))
2721     },
2722     { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2723         IP5_31_28
2724         IP5_27_24
2725         IP5_23_20
2726         IP5_19_16
2727         IP5_15_12
2728         IP5_11_8
2729         IP5_7_4
2730         IP5_3_0 ))
2731     },
2732     { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2733         IP6_31_28
2734         IP6_27_24
2735         IP6_23_20
2736         IP6_19_16
2737         IP6_15_12
2738         IP6_11_8
2739         IP6_7_4
2740         IP6_3_0 ))
2741     },
2742     { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2743         IP7_31_28
2744         IP7_27_24
2745         IP7_23_20
2746         IP7_19_16
2747         IP7_15_12
2748         IP7_11_8
2749         IP7_7_4
2750         IP7_3_0 ))
2751     },
2752     { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2753         IP8_31_28
2754         IP8_27_24
2755         IP8_23_20
2756         IP8_19_16
2757         IP8_15_12
2758         IP8_11_8
2759         IP8_7_4
2760         IP8_3_0 ))
2761     },
2762     { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
2763         IP9_31_28
2764         IP9_27_24
2765         IP9_23_20
2766         IP9_19_16
2767         IP9_15_12
2768         IP9_11_8
2769         IP9_7_4
2770         IP9_3_0 ))
2771     },
2772     { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
2773         IP10_31_28
2774         IP10_27_24
2775         IP10_23_20
2776         IP10_19_16
2777         IP10_15_12
2778         IP10_11_8
2779         IP10_7_4
2780         IP10_3_0 ))
2781     },
2782     { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
2783         IP11_31_28
2784         IP11_27_24
2785         IP11_23_20
2786         IP11_19_16
2787         IP11_15_12
2788         IP11_11_8
2789         IP11_7_4
2790         IP11_3_0 ))
2791     },
2792     { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
2793         IP12_31_28
2794         IP12_27_24
2795         IP12_23_20
2796         IP12_19_16
2797         IP12_15_12
2798         IP12_11_8
2799         IP12_7_4
2800         IP12_3_0 ))
2801     },
2802     { PINMUX_CFG_REG_VAR("IPSR13", 0xe6060234, 32,
2803                  GROUP(-24, 4, 4),
2804                  GROUP(
2805         /* IP13_31_8 RESERVED */
2806         IP13_7_4
2807         IP13_3_0 ))
2808     },
2809 #undef F_
2810 #undef FM
2811
2812 #define F_(x, y)    x,
2813 #define FM(x)       FN_##x,
2814     { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2815                  GROUP(-1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, -1,
2816                    1, 1, 1, 1, 1, 1, -4, 1, 1, 1, 1, 1, 1),
2817                  GROUP(
2818         /* RESERVED 31 */
2819         MOD_SEL0_30
2820         MOD_SEL0_29
2821         MOD_SEL0_28
2822         MOD_SEL0_27
2823         MOD_SEL0_26
2824         MOD_SEL0_25
2825         MOD_SEL0_24_23
2826         MOD_SEL0_22_21
2827         MOD_SEL0_20_19
2828         MOD_SEL0_18_17
2829         /* RESERVED 16 */
2830         MOD_SEL0_15
2831         MOD_SEL0_14
2832         MOD_SEL0_13
2833         MOD_SEL0_12
2834         MOD_SEL0_11
2835         MOD_SEL0_10
2836         /* RESERVED 9, 8, 7, 6 */
2837         MOD_SEL0_5
2838         MOD_SEL0_4
2839         MOD_SEL0_3
2840         MOD_SEL0_2
2841         MOD_SEL0_1
2842         MOD_SEL0_0 ))
2843     },
2844     { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2845                  GROUP(1, 1, 1, 1, 1, 1, -26),
2846                  GROUP(
2847         MOD_SEL1_31
2848         MOD_SEL1_30
2849         MOD_SEL1_29
2850         MOD_SEL1_28
2851         MOD_SEL1_27
2852         MOD_SEL1_26
2853         /* RESERVED 25-0 */ ))
2854     },
2855     { },
2856 };
2857
2858 static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
2859 {
2860     int bit = -EINVAL;
2861
2862     *pocctrl = 0xe6060380;
2863
2864     if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9))
2865         bit = 29 - (pin - RCAR_GP_PIN(3, 0));
2866
2867     return bit;
2868 }
2869
2870 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2871     { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
2872         [ 0] = RCAR_GP_PIN(1, 9),   /* DU_DG1 */
2873         [ 1] = RCAR_GP_PIN(1, 8),   /* DU_DG0 */
2874         [ 2] = RCAR_GP_PIN(1, 7),   /* DU_DB7 */
2875         [ 3] = RCAR_GP_PIN(1, 6),   /* DU_DB6 */
2876         [ 4] = RCAR_GP_PIN(1, 5),   /* DU_DB5 */
2877         [ 5] = RCAR_GP_PIN(1, 4),   /* DU_DB4 */
2878         [ 6] = RCAR_GP_PIN(1, 3),   /* DU_DB3 */
2879         [ 7] = RCAR_GP_PIN(1, 2),   /* DU_DB2 */
2880         [ 8] = RCAR_GP_PIN(1, 1),   /* DU_DB1 */
2881         [ 9] = RCAR_GP_PIN(1, 0),   /* DU_DB0 */
2882         [10] = PIN_MLB_REF,     /* MLB_REF */
2883         [11] = RCAR_GP_PIN(0, 8),   /* MLB_SIG */
2884         [12] = RCAR_GP_PIN(0, 7),   /* MLB_DAT */
2885         [13] = RCAR_GP_PIN(0, 6),   /* MLB_CLK */
2886         [14] = RCAR_GP_PIN(0, 5),   /* MSIOF2_RXD */
2887         [15] = RCAR_GP_PIN(0, 4),   /* MSIOF2_TXD */
2888         [16] = RCAR_GP_PIN(0, 3),   /* MSIOF2_SCK */
2889         [17] = RCAR_GP_PIN(0, 2),   /* IRQ0_A */
2890         [18] = RCAR_GP_PIN(0, 1),   /* USB0_OVC */
2891         [19] = RCAR_GP_PIN(0, 0),   /* USB0_PWEN */
2892         [20] = PIN_PRESETOUT_N,     /* PRESETOUT# */
2893         [21] = PIN_DU_DOTCLKIN0,    /* DU_DOTCLKIN0 */
2894         [22] = PIN_FSCLKST_N,       /* FSCLKST# */
2895         [23] = SH_PFC_PIN_NONE,
2896         [24] = SH_PFC_PIN_NONE,
2897         [25] = SH_PFC_PIN_NONE,
2898         [26] = SH_PFC_PIN_NONE,
2899         [27] = SH_PFC_PIN_NONE,
2900         [28] = PIN_TDI,         /* TDI */
2901         [29] = PIN_TMS,         /* TMS */
2902         [30] = PIN_TCK,         /* TCK */
2903         [31] = PIN_TRST_N,      /* TRST# */
2904     } },
2905     { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
2906         [ 0] = RCAR_GP_PIN(2, 9),   /* VI4_DATA8 */
2907         [ 1] = RCAR_GP_PIN(2, 8),   /* VI4_DATA7 */
2908         [ 2] = RCAR_GP_PIN(2, 7),   /* VI4_DATA6 */
2909         [ 3] = RCAR_GP_PIN(2, 6),   /* VI4_DATA5 */
2910         [ 4] = RCAR_GP_PIN(2, 5),   /* VI4_DATA4 */
2911         [ 5] = RCAR_GP_PIN(2, 4),   /* VI4_DATA3 */
2912         [ 6] = RCAR_GP_PIN(2, 3),   /* VI4_DATA2 */
2913         [ 7] = RCAR_GP_PIN(2, 2),   /* VI4_DATA1 */
2914         [ 8] = RCAR_GP_PIN(2, 1),   /* VI4_DATA0 */
2915         [ 9] = RCAR_GP_PIN(2, 0),   /* VI4_CLK */
2916         [10] = RCAR_GP_PIN(1, 31),  /* QPOLB */
2917         [11] = RCAR_GP_PIN(1, 30),  /* QPOLA */
2918         [12] = RCAR_GP_PIN(1, 29),  /* DU_CDE */
2919         [13] = RCAR_GP_PIN(1, 28),  /* DU_DISP/CDE */
2920         [14] = RCAR_GP_PIN(1, 27),  /* DU_DISP */
2921         [15] = RCAR_GP_PIN(1, 26),  /* DU_VSYNC */
2922         [16] = RCAR_GP_PIN(1, 25),  /* DU_HSYNC */
2923         [17] = RCAR_GP_PIN(1, 24),  /* DU_DOTCLKOUT0 */
2924         [18] = RCAR_GP_PIN(1, 23),  /* DU_DR7 */
2925         [19] = RCAR_GP_PIN(1, 22),  /* DU_DR6 */
2926         [20] = RCAR_GP_PIN(1, 21),  /* DU_DR5 */
2927         [21] = RCAR_GP_PIN(1, 20),  /* DU_DR4 */
2928         [22] = RCAR_GP_PIN(1, 19),  /* DU_DR3 */
2929         [23] = RCAR_GP_PIN(1, 18),  /* DU_DR2 */
2930         [24] = RCAR_GP_PIN(1, 17),  /* DU_DR1 */
2931         [25] = RCAR_GP_PIN(1, 16),  /* DU_DR0 */
2932         [26] = RCAR_GP_PIN(1, 15),  /* DU_DG7 */
2933         [27] = RCAR_GP_PIN(1, 14),  /* DU_DG6 */
2934         [28] = RCAR_GP_PIN(1, 13),  /* DU_DG5 */
2935         [29] = RCAR_GP_PIN(1, 12),  /* DU_DG4 */
2936         [30] = RCAR_GP_PIN(1, 11),  /* DU_DG3 */
2937         [31] = RCAR_GP_PIN(1, 10),  /* DU_DG2 */
2938     } },
2939     { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
2940         [ 0] = RCAR_GP_PIN(3, 8),   /* NFDATA6 */
2941         [ 1] = RCAR_GP_PIN(3, 7),   /* NFDATA5 */
2942         [ 2] = RCAR_GP_PIN(3, 6),   /* NFDATA4 */
2943         [ 3] = RCAR_GP_PIN(3, 5),   /* NFDATA3 */
2944         [ 4] = RCAR_GP_PIN(3, 4),   /* NFDATA2 */
2945         [ 5] = RCAR_GP_PIN(3, 3),   /* NFDATA1 */
2946         [ 6] = RCAR_GP_PIN(3, 2),   /* NFDATA0 */
2947         [ 7] = RCAR_GP_PIN(3, 1),   /* NFWE# (PUEN) / NFRE# (PUD) */
2948         [ 8] = RCAR_GP_PIN(3, 0),   /* NFRE# (PUEN) / NFWE# (PUD) */
2949         [ 9] = RCAR_GP_PIN(4, 0),   /* NFRB# */
2950         [10] = RCAR_GP_PIN(2, 31),  /* NFCE# */
2951         [11] = RCAR_GP_PIN(2, 30),  /* NFCLE */
2952         [12] = RCAR_GP_PIN(2, 29),  /* NFALE */
2953         [13] = RCAR_GP_PIN(2, 28),  /* VI4_CLKENB */
2954         [14] = RCAR_GP_PIN(2, 27),  /* VI4_FIELD */
2955         [15] = RCAR_GP_PIN(2, 26),  /* VI4_HSYNC# */
2956         [16] = RCAR_GP_PIN(2, 25),  /* VI4_VSYNC# */
2957         [17] = RCAR_GP_PIN(2, 24),  /* VI4_DATA23 */
2958         [18] = RCAR_GP_PIN(2, 23),  /* VI4_DATA22 */
2959         [19] = RCAR_GP_PIN(2, 22),  /* VI4_DATA21 */
2960         [20] = RCAR_GP_PIN(2, 21),  /* VI4_DATA20 */
2961         [21] = RCAR_GP_PIN(2, 20),  /* VI4_DATA19 */
2962         [22] = RCAR_GP_PIN(2, 19),  /* VI4_DATA18 */
2963         [23] = RCAR_GP_PIN(2, 18),  /* VI4_DATA17 */
2964         [24] = RCAR_GP_PIN(2, 17),  /* VI4_DATA16 */
2965         [25] = RCAR_GP_PIN(2, 16),  /* VI4_DATA15 */
2966         [26] = RCAR_GP_PIN(2, 15),  /* VI4_DATA14 */
2967         [27] = RCAR_GP_PIN(2, 14),  /* VI4_DATA13 */
2968         [28] = RCAR_GP_PIN(2, 13),  /* VI4_DATA12 */
2969         [29] = RCAR_GP_PIN(2, 12),  /* VI4_DATA11 */
2970         [30] = RCAR_GP_PIN(2, 11),  /* VI4_DATA10 */
2971         [31] = RCAR_GP_PIN(2, 10),  /* VI4_DATA9 */
2972     } },
2973     { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
2974         [ 0] = RCAR_GP_PIN(4, 31),  /* CAN0_RX_A */
2975         [ 1] = RCAR_GP_PIN(5, 2),   /* CAN_CLK */
2976         [ 2] = RCAR_GP_PIN(5, 1),   /* TPU0TO1_A */
2977         [ 3] = RCAR_GP_PIN(5, 0),   /* TPU0TO0_A */
2978         [ 4] = RCAR_GP_PIN(4, 27),  /* TX2 */
2979         [ 5] = RCAR_GP_PIN(4, 26),  /* RX2 */
2980         [ 6] = RCAR_GP_PIN(4, 25),  /* SCK2 */
2981         [ 7] = RCAR_GP_PIN(4, 24),  /* TX1_A */
2982         [ 8] = RCAR_GP_PIN(4, 23),  /* RX1_A */
2983         [ 9] = RCAR_GP_PIN(4, 22),  /* SCK1_A */
2984         [10] = RCAR_GP_PIN(4, 21),  /* TX0_A */
2985         [11] = RCAR_GP_PIN(4, 20),  /* RX0_A */
2986         [12] = RCAR_GP_PIN(4, 19),  /* SCK0_A */
2987         [13] = RCAR_GP_PIN(4, 18),  /* MSIOF1_RXD */
2988         [14] = RCAR_GP_PIN(4, 17),  /* MSIOF1_TXD */
2989         [15] = RCAR_GP_PIN(4, 16),  /* MSIOF1_SCK */
2990         [16] = RCAR_GP_PIN(4, 15),  /* MSIOF0_RXD */
2991         [17] = RCAR_GP_PIN(4, 14),  /* MSIOF0_TXD */
2992         [18] = RCAR_GP_PIN(4, 13),  /* MSIOF0_SYNC */
2993         [19] = RCAR_GP_PIN(4, 12),  /* MSIOF0_SCK */
2994         [20] = RCAR_GP_PIN(4, 11),  /* SDA1 */
2995         [21] = RCAR_GP_PIN(4, 10),  /* SCL1 */
2996         [22] = RCAR_GP_PIN(4, 9),   /* SDA0 */
2997         [23] = RCAR_GP_PIN(4, 8),   /* SCL0 */
2998         [24] = RCAR_GP_PIN(4, 7),   /* SSI_WS4_A */
2999         [25] = RCAR_GP_PIN(4, 6),   /* SSI_SDATA4_A */
3000         [26] = RCAR_GP_PIN(4, 5),   /* SSI_SCK4_A */
3001         [27] = RCAR_GP_PIN(4, 4),   /* SSI_WS34 */
3002         [28] = RCAR_GP_PIN(4, 3),   /* SSI_SDATA3 */
3003         [29] = RCAR_GP_PIN(4, 2),   /* SSI_SCK34 */
3004         [30] = RCAR_GP_PIN(4, 1),   /* AUDIO_CLKA */
3005         [31] = RCAR_GP_PIN(3, 9),   /* NFDATA7 */
3006     } },
3007     { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
3008         [ 0] = RCAR_GP_PIN(6, 10),  /* QSPI1_IO3 */
3009         [ 1] = RCAR_GP_PIN(6, 9),   /* QSPI1_IO2 */
3010         [ 2] = RCAR_GP_PIN(6, 8),   /* QSPI1_MISO_IO1 */
3011         [ 3] = RCAR_GP_PIN(6, 7),   /* QSPI1_MOSI_IO0 */
3012         [ 4] = RCAR_GP_PIN(6, 6),   /* QSPI1_SPCLK */
3013         [ 5] = RCAR_GP_PIN(6, 5),   /* QSPI0_SSL */
3014         [ 6] = RCAR_GP_PIN(6, 4),   /* QSPI0_IO3 */
3015         [ 7] = RCAR_GP_PIN(6, 3),   /* QSPI0_IO2 */
3016         [ 8] = RCAR_GP_PIN(6, 2),   /* QSPI0_MISO_IO1 */
3017         [ 9] = RCAR_GP_PIN(6, 1),   /* QSPI0_MOSI_IO0 */
3018         [10] = RCAR_GP_PIN(6, 0),   /* QSPI0_SPCLK */
3019         [11] = RCAR_GP_PIN(5, 20),  /* AVB0_LINK */
3020         [12] = RCAR_GP_PIN(5, 19),  /* AVB0_PHY_INT */
3021         [13] = RCAR_GP_PIN(5, 18),  /* AVB0_MAGIC */
3022         [14] = RCAR_GP_PIN(5, 17),  /* AVB0_MDC */
3023         [15] = RCAR_GP_PIN(5, 16),  /* AVB0_MDIO */
3024         [16] = RCAR_GP_PIN(5, 15),  /* AVB0_TXCREFCLK */
3025         [17] = RCAR_GP_PIN(5, 14),  /* AVB0_TD3 */
3026         [18] = RCAR_GP_PIN(5, 13),  /* AVB0_TD2 */
3027         [19] = RCAR_GP_PIN(5, 12),  /* AVB0_TD1 */
3028         [20] = RCAR_GP_PIN(5, 11),  /* AVB0_TD0 */
3029         [21] = RCAR_GP_PIN(5, 10),  /* AVB0_TXC */
3030         [22] = RCAR_GP_PIN(5, 9),   /* AVB0_TX_CTL */
3031         [23] = RCAR_GP_PIN(5, 8),   /* AVB0_RD3 */
3032         [24] = RCAR_GP_PIN(5, 7),   /* AVB0_RD2 */
3033         [25] = RCAR_GP_PIN(5, 6),   /* AVB0_RD1 */
3034         [26] = RCAR_GP_PIN(5, 5),   /* AVB0_RD0 */
3035         [27] = RCAR_GP_PIN(5, 4),   /* AVB0_RXC */
3036         [28] = RCAR_GP_PIN(5, 3),   /* AVB0_RX_CTL */
3037         [29] = RCAR_GP_PIN(4, 30),  /* CAN1_TX_A */
3038         [30] = RCAR_GP_PIN(4, 29),  /* CAN1_RX_A */
3039         [31] = RCAR_GP_PIN(4, 28),  /* CAN0_TX_A */
3040     } },
3041     { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD4", 0xe6060454) {
3042         [ 0] = SH_PFC_PIN_NONE,
3043         [ 1] = SH_PFC_PIN_NONE,
3044         [ 2] = SH_PFC_PIN_NONE,
3045         [ 3] = SH_PFC_PIN_NONE,
3046         [ 4] = SH_PFC_PIN_NONE,
3047         [ 5] = SH_PFC_PIN_NONE,
3048         [ 6] = SH_PFC_PIN_NONE,
3049         [ 7] = SH_PFC_PIN_NONE,
3050         [ 8] = SH_PFC_PIN_NONE,
3051         [ 9] = SH_PFC_PIN_NONE,
3052         [10] = SH_PFC_PIN_NONE,
3053         [11] = SH_PFC_PIN_NONE,
3054         [12] = SH_PFC_PIN_NONE,
3055         [13] = SH_PFC_PIN_NONE,
3056         [14] = SH_PFC_PIN_NONE,
3057         [15] = SH_PFC_PIN_NONE,
3058         [16] = SH_PFC_PIN_NONE,
3059         [17] = SH_PFC_PIN_NONE,
3060         [18] = SH_PFC_PIN_NONE,
3061         [19] = SH_PFC_PIN_NONE,
3062         [20] = SH_PFC_PIN_NONE,
3063         [21] = SH_PFC_PIN_NONE,
3064         [22] = SH_PFC_PIN_NONE,
3065         [23] = SH_PFC_PIN_NONE,
3066         [24] = SH_PFC_PIN_NONE,
3067         [25] = SH_PFC_PIN_NONE,
3068         [26] = SH_PFC_PIN_NONE,
3069         [27] = SH_PFC_PIN_NONE,
3070         [28] = SH_PFC_PIN_NONE,
3071         [29] = RCAR_GP_PIN(6, 13),  /* RPC_INT# */
3072         [30] = RCAR_GP_PIN(6, 12),  /* RPC_RESET# */
3073         [31] = RCAR_GP_PIN(6, 11),  /* QSPI1_SSL */
3074     } },
3075     { /* sentinel */ }
3076 };
3077
3078 enum ioctrl_regs {
3079     TDSELCTRL,
3080 };
3081
3082 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
3083     [TDSELCTRL] = { 0xe60603c0, },
3084     { /* sentinel */ },
3085 };
3086
3087 static const struct pinmux_bias_reg *
3088 r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
3089              unsigned int *puen_bit, unsigned int *pud_bit)
3090 {
3091     const struct pinmux_bias_reg *reg;
3092     unsigned int bit;
3093
3094     reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit);
3095     if (!reg)
3096         return reg;
3097
3098     *puen_bit = bit;
3099
3100     /* NFWE# and NFRE# use different bit positions in PUD2 */
3101     switch (pin) {
3102     case RCAR_GP_PIN(3, 0): /* NFRE# */
3103         *pud_bit = 7;
3104         break;
3105
3106     case RCAR_GP_PIN(3, 1): /* NFWE# */
3107         *pud_bit = 8;
3108         break;
3109
3110     default:
3111         *pud_bit = bit;
3112         break;
3113     }
3114
3115     return reg;
3116 }
3117
3118 static unsigned int r8a77995_pinmux_get_bias(struct sh_pfc *pfc,
3119                          unsigned int pin)
3120 {
3121     const struct pinmux_bias_reg *reg;
3122     unsigned int puen_bit, pud_bit;
3123
3124     reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit);
3125     if (!reg)
3126         return PIN_CONFIG_BIAS_DISABLE;
3127
3128     if (!(sh_pfc_read(pfc, reg->puen) & BIT(puen_bit)))
3129         return PIN_CONFIG_BIAS_DISABLE;
3130     else if (sh_pfc_read(pfc, reg->pud) & BIT(pud_bit))
3131         return PIN_CONFIG_BIAS_PULL_UP;
3132     else
3133         return PIN_CONFIG_BIAS_PULL_DOWN;
3134 }
3135
3136 static void r8a77995_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3137                      unsigned int bias)
3138 {
3139     const struct pinmux_bias_reg *reg;
3140     unsigned int puen_bit, pud_bit;
3141     u32 enable, updown;
3142
3143     reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit);
3144     if (!reg)
3145         return;
3146
3147     enable = sh_pfc_read(pfc, reg->puen) & ~BIT(puen_bit);
3148     if (bias != PIN_CONFIG_BIAS_DISABLE) {
3149         enable |= BIT(puen_bit);
3150
3151         updown = sh_pfc_read(pfc, reg->pud) & ~BIT(pud_bit);
3152         if (bias == PIN_CONFIG_BIAS_PULL_UP)
3153             updown |= BIT(pud_bit);
3154
3155         sh_pfc_write(pfc, reg->pud, updown);
3156     }
3157     sh_pfc_write(pfc, reg->puen, enable);
3158 }
3159
3160 static const struct sh_pfc_soc_operations r8a77995_pfc_ops = {
3161     .pin_to_pocctrl = r8a77995_pin_to_pocctrl,
3162     .get_bias = r8a77995_pinmux_get_bias,
3163     .set_bias = r8a77995_pinmux_set_bias,
3164 };
3165
3166 const struct sh_pfc_soc_info r8a77995_pinmux_info = {
3167     .name = "r8a77995_pfc",
3168     .ops = &r8a77995_pfc_ops,
3169     .unlock_reg = 0xe6060000, /* PMMR */
3170
3171     .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3172
3173     .pins = pinmux_pins,
3174     .nr_pins = ARRAY_SIZE(pinmux_pins),
3175     .groups = pinmux_groups,
3176     .nr_groups = ARRAY_SIZE(pinmux_groups),
3177     .functions = pinmux_functions,
3178     .nr_functions = ARRAY_SIZE(pinmux_functions),
3179
3180     .cfg_regs = pinmux_config_regs,
3181     .bias_regs = pinmux_bias_regs,
3182     .ioctrl_regs = pinmux_ioctrl_regs,
3183
3184     .pinmux_data = pinmux_data,
3185     .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3186 };