pinctrl/renesas/pfc-r8a77990.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * R8A77990 processor support - PFC hardware block.
0004  *
0005  * Copyright (C) 2018-2019 Renesas Electronics Corp.
0006  *
0007  * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
0008  *
0009  * R8A7796 processor support - PFC hardware block.
0010  *
0011  * Copyright (C) 2016-2017 Renesas Electronics Corp.
0012  */
0013
0014 #include <linux/errno.h>
0015 #include <linux/kernel.h>
0016
0017 #include "sh_pfc.h"
0018
0019 #define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN)
0020
0021 #define CPU_ALL_GP(fn, sfx) \
0022     PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
0023     PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
0024     PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
0025     PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
0026     PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
0027     PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
0028     PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
0029     PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
0030     PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
0031     PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
0032     PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
0033     PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
0034     PORT_GP_CFG_1(6, 10, fn, sfx, CFG_FLAGS), \
0035     PORT_GP_CFG_1(6, 11, fn, sfx, CFG_FLAGS), \
0036     PORT_GP_CFG_1(6, 12, fn, sfx, CFG_FLAGS), \
0037     PORT_GP_CFG_1(6, 13, fn, sfx, CFG_FLAGS), \
0038     PORT_GP_CFG_1(6, 14, fn, sfx, CFG_FLAGS), \
0039     PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \
0040     PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \
0041     PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS)
0042
0043 #define CPU_ALL_NOGP(fn)                        \
0044     PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS),          \
0045     PIN_NOGP_CFG(AVB_MDC, "AVB_MDC", fn, CFG_FLAGS),        \
0046     PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS),      \
0047     PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS),        \
0048     PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS),        \
0049     PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS),        \
0050     PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS),        \
0051     PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS),        \
0052     PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS),      \
0053     PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS),        \
0054     PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS),        \
0055     PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS),    \
0056     PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP),       \
0057     PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP),       \
0058     PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP),       \
0059     PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP)
0060
0061 /*
0062  * F_() : just information
0063  * FM() : macro for FN_xxx / xxx_MARK
0064  */
0065
0066 /* GPSR0 */
0067 #define GPSR0_17    F_(SDA4,        IP7_27_24)
0068 #define GPSR0_16    F_(SCL4,        IP7_23_20)
0069 #define GPSR0_15    F_(D15,         IP7_19_16)
0070 #define GPSR0_14    F_(D14,         IP7_15_12)
0071 #define GPSR0_13    F_(D13,         IP7_11_8)
0072 #define GPSR0_12    F_(D12,         IP7_7_4)
0073 #define GPSR0_11    F_(D11,         IP7_3_0)
0074 #define GPSR0_10    F_(D10,         IP6_31_28)
0075 #define GPSR0_9     F_(D9,          IP6_27_24)
0076 #define GPSR0_8     F_(D8,          IP6_23_20)
0077 #define GPSR0_7     F_(D7,          IP6_19_16)
0078 #define GPSR0_6     F_(D6,          IP6_15_12)
0079 #define GPSR0_5     F_(D5,          IP6_11_8)
0080 #define GPSR0_4     F_(D4,          IP6_7_4)
0081 #define GPSR0_3     F_(D3,          IP6_3_0)
0082 #define GPSR0_2     F_(D2,          IP5_31_28)
0083 #define GPSR0_1     F_(D1,          IP5_27_24)
0084 #define GPSR0_0     F_(D0,          IP5_23_20)
0085
0086 /* GPSR1 */
0087 #define GPSR1_22    F_(WE0_N,       IP5_19_16)
0088 #define GPSR1_21    F_(CS0_N,       IP5_15_12)
0089 #define GPSR1_20    FM(CLKOUT)
0090 #define GPSR1_19    F_(A19,         IP5_11_8)
0091 #define GPSR1_18    F_(A18,         IP5_7_4)
0092 #define GPSR1_17    F_(A17,         IP5_3_0)
0093 #define GPSR1_16    F_(A16,         IP4_31_28)
0094 #define GPSR1_15    F_(A15,         IP4_27_24)
0095 #define GPSR1_14    F_(A14,         IP4_23_20)
0096 #define GPSR1_13    F_(A13,         IP4_19_16)
0097 #define GPSR1_12    F_(A12,         IP4_15_12)
0098 #define GPSR1_11    F_(A11,         IP4_11_8)
0099 #define GPSR1_10    F_(A10,         IP4_7_4)
0100 #define GPSR1_9     F_(A9,          IP4_3_0)
0101 #define GPSR1_8     F_(A8,          IP3_31_28)
0102 #define GPSR1_7     F_(A7,          IP3_27_24)
0103 #define GPSR1_6     F_(A6,          IP3_23_20)
0104 #define GPSR1_5     F_(A5,          IP3_19_16)
0105 #define GPSR1_4     F_(A4,          IP3_15_12)
0106 #define GPSR1_3     F_(A3,          IP3_11_8)
0107 #define GPSR1_2     F_(A2,          IP3_7_4)
0108 #define GPSR1_1     F_(A1,          IP3_3_0)
0109 #define GPSR1_0     F_(A0,          IP2_31_28)
0110
0111 /* GPSR2 */
0112 #define GPSR2_25    F_(EX_WAIT0,        IP2_27_24)
0113 #define GPSR2_24    F_(RD_WR_N,     IP2_23_20)
0114 #define GPSR2_23    F_(RD_N,        IP2_19_16)
0115 #define GPSR2_22    F_(BS_N,        IP2_15_12)
0116 #define GPSR2_21    FM(AVB_PHY_INT)
0117 #define GPSR2_20    F_(AVB_TXCREFCLK,   IP2_3_0)
0118 #define GPSR2_19    FM(AVB_RD3)
0119 #define GPSR2_18    F_(AVB_RD2,     IP1_31_28)
0120 #define GPSR2_17    F_(AVB_RD1,     IP1_27_24)
0121 #define GPSR2_16    F_(AVB_RD0,     IP1_23_20)
0122 #define GPSR2_15    FM(AVB_RXC)
0123 #define GPSR2_14    FM(AVB_RX_CTL)
0124 #define GPSR2_13    F_(RPC_RESET_N,     IP1_19_16)
0125 #define GPSR2_12    F_(RPC_INT_N,       IP1_15_12)
0126 #define GPSR2_11    F_(QSPI1_SSL,       IP1_11_8)
0127 #define GPSR2_10    F_(QSPI1_IO3,       IP1_7_4)
0128 #define GPSR2_9     F_(QSPI1_IO2,       IP1_3_0)
0129 #define GPSR2_8     F_(QSPI1_MISO_IO1,  IP0_31_28)
0130 #define GPSR2_7     F_(QSPI1_MOSI_IO0,  IP0_27_24)
0131 #define GPSR2_6     F_(QSPI1_SPCLK,     IP0_23_20)
0132 #define GPSR2_5     FM(QSPI0_SSL)
0133 #define GPSR2_4     F_(QSPI0_IO3,       IP0_19_16)
0134 #define GPSR2_3     F_(QSPI0_IO2,       IP0_15_12)
0135 #define GPSR2_2     F_(QSPI0_MISO_IO1,  IP0_11_8)
0136 #define GPSR2_1     F_(QSPI0_MOSI_IO0,  IP0_7_4)
0137 #define GPSR2_0     F_(QSPI0_SPCLK,     IP0_3_0)
0138
0139 /* GPSR3 */
0140 #define GPSR3_15    F_(SD1_WP,      IP11_7_4)
0141 #define GPSR3_14    F_(SD1_CD,      IP11_3_0)
0142 #define GPSR3_13    F_(SD0_WP,      IP10_31_28)
0143 #define GPSR3_12    F_(SD0_CD,      IP10_27_24)
0144 #define GPSR3_11    F_(SD1_DAT3,        IP9_11_8)
0145 #define GPSR3_10    F_(SD1_DAT2,        IP9_7_4)
0146 #define GPSR3_9     F_(SD1_DAT1,        IP9_3_0)
0147 #define GPSR3_8     F_(SD1_DAT0,        IP8_31_28)
0148 #define GPSR3_7     F_(SD1_CMD,     IP8_27_24)
0149 #define GPSR3_6     F_(SD1_CLK,     IP8_23_20)
0150 #define GPSR3_5     F_(SD0_DAT3,        IP8_19_16)
0151 #define GPSR3_4     F_(SD0_DAT2,        IP8_15_12)
0152 #define GPSR3_3     F_(SD0_DAT1,        IP8_11_8)
0153 #define GPSR3_2     F_(SD0_DAT0,        IP8_7_4)
0154 #define GPSR3_1     F_(SD0_CMD,     IP8_3_0)
0155 #define GPSR3_0     F_(SD0_CLK,     IP7_31_28)
0156
0157 /* GPSR4 */
0158 #define GPSR4_10    F_(SD3_DS,      IP10_23_20)
0159 #define GPSR4_9     F_(SD3_DAT7,        IP10_19_16)
0160 #define GPSR4_8     F_(SD3_DAT6,        IP10_15_12)
0161 #define GPSR4_7     F_(SD3_DAT5,        IP10_11_8)
0162 #define GPSR4_6     F_(SD3_DAT4,        IP10_7_4)
0163 #define GPSR4_5     F_(SD3_DAT3,        IP10_3_0)
0164 #define GPSR4_4     F_(SD3_DAT2,        IP9_31_28)
0165 #define GPSR4_3     F_(SD3_DAT1,        IP9_27_24)
0166 #define GPSR4_2     F_(SD3_DAT0,        IP9_23_20)
0167 #define GPSR4_1     F_(SD3_CMD,     IP9_19_16)
0168 #define GPSR4_0     F_(SD3_CLK,     IP9_15_12)
0169
0170 /* GPSR5 */
0171 #define GPSR5_19    F_(MLB_DAT,     IP13_23_20)
0172 #define GPSR5_18    F_(MLB_SIG,     IP13_19_16)
0173 #define GPSR5_17    F_(MLB_CLK,     IP13_15_12)
0174 #define GPSR5_16    F_(SSI_SDATA9,      IP13_11_8)
0175 #define GPSR5_15    F_(MSIOF0_SS2,      IP13_7_4)
0176 #define GPSR5_14    F_(MSIOF0_SS1,      IP13_3_0)
0177 #define GPSR5_13    F_(MSIOF0_SYNC,     IP12_31_28)
0178 #define GPSR5_12    F_(MSIOF0_TXD,      IP12_27_24)
0179 #define GPSR5_11    F_(MSIOF0_RXD,      IP12_23_20)
0180 #define GPSR5_10    F_(MSIOF0_SCK,      IP12_19_16)
0181 #define GPSR5_9     F_(RX2_A,       IP12_15_12)
0182 #define GPSR5_8     F_(TX2_A,       IP12_11_8)
0183 #define GPSR5_7     F_(SCK2_A,      IP12_7_4)
0184 #define GPSR5_6     F_(TX1,         IP12_3_0)
0185 #define GPSR5_5     F_(RX1,         IP11_31_28)
0186 #define GPSR5_4     F_(RTS0_N_A,        IP11_23_20)
0187 #define GPSR5_3     F_(CTS0_N_A,        IP11_19_16)
0188 #define GPSR5_2     F_(TX0_A,       IP11_15_12)
0189 #define GPSR5_1     F_(RX0_A,       IP11_11_8)
0190 #define GPSR5_0     F_(SCK0_A,      IP11_27_24)
0191
0192 /* GPSR6 */
0193 #define GPSR6_17    F_(USB30_PWEN,      IP15_27_24)
0194 #define GPSR6_16    F_(SSI_SDATA6,      IP15_19_16)
0195 #define GPSR6_15    F_(SSI_WS6,     IP15_15_12)
0196 #define GPSR6_14    F_(SSI_SCK6,        IP15_11_8)
0197 #define GPSR6_13    F_(SSI_SDATA5,      IP15_7_4)
0198 #define GPSR6_12    F_(SSI_WS5,     IP15_3_0)
0199 #define GPSR6_11    F_(SSI_SCK5,        IP14_31_28)
0200 #define GPSR6_10    F_(SSI_SDATA4,      IP14_27_24)
0201 #define GPSR6_9     F_(USB30_OVC,       IP15_31_28)
0202 #define GPSR6_8     F_(AUDIO_CLKA,      IP15_23_20)
0203 #define GPSR6_7     F_(SSI_SDATA3,      IP14_23_20)
0204 #define GPSR6_6     F_(SSI_WS349,       IP14_19_16)
0205 #define GPSR6_5     F_(SSI_SCK349,      IP14_15_12)
0206 #define GPSR6_4     F_(SSI_SDATA2,      IP14_11_8)
0207 #define GPSR6_3     F_(SSI_SDATA1,      IP14_7_4)
0208 #define GPSR6_2     F_(SSI_SDATA0,      IP14_3_0)
0209 #define GPSR6_1     F_(SSI_WS01239,     IP13_31_28)
0210 #define GPSR6_0     F_(SSI_SCK01239,    IP13_27_24)
0211
0212 /* IPSRx */     /* 0 */         /* 1 */         /* 2 */         /* 3 */         /* 4 */         /* 5 */     /* 6 */     /* 7 */     /* 8 */     /* 9 - F */
0213 #define IP0_3_0     FM(QSPI0_SPCLK)     FM(HSCK4_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0214 #define IP0_7_4     FM(QSPI0_MOSI_IO0)  FM(HCTS4_N_A)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0215 #define IP0_11_8    FM(QSPI0_MISO_IO1)  FM(HRTS4_N_A)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0216 #define IP0_15_12   FM(QSPI0_IO2)       FM(HTX4_A)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0217 #define IP0_19_16   FM(QSPI0_IO3)       FM(HRX4_A)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0218 #define IP0_23_20   FM(QSPI1_SPCLK)     FM(RIF2_CLK_A)      FM(HSCK4_B)     FM(VI4_DATA0_A)     F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0219 #define IP0_27_24   FM(QSPI1_MOSI_IO0)  FM(RIF2_SYNC_A)     FM(HTX4_B)      FM(VI4_DATA1_A)     F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0220 #define IP0_31_28   FM(QSPI1_MISO_IO1)  FM(RIF2_D0_A)       FM(HRX4_B)      FM(VI4_DATA2_A)     F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0221 #define IP1_3_0     FM(QSPI1_IO2)       FM(RIF2_D1_A)       FM(HTX3_C)      FM(VI4_DATA3_A)     F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0222 #define IP1_7_4     FM(QSPI1_IO3)       FM(RIF3_CLK_A)      FM(HRX3_C)      FM(VI4_DATA4_A)     F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0223 #define IP1_11_8    FM(QSPI1_SSL)       FM(RIF3_SYNC_A)     FM(HSCK3_C)     FM(VI4_DATA5_A)     F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0224 #define IP1_15_12   FM(RPC_INT_N)       FM(RIF3_D0_A)       FM(HCTS3_N_C)       FM(VI4_DATA6_A)     F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0225 #define IP1_19_16   FM(RPC_RESET_N)     FM(RIF3_D1_A)       FM(HRTS3_N_C)       FM(VI4_DATA7_A)     F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0226 #define IP1_23_20   FM(AVB_RD0)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0227 #define IP1_27_24   FM(AVB_RD1)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0228 #define IP1_31_28   FM(AVB_RD2)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0229 #define IP2_3_0     FM(AVB_TXCREFCLK)   F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0230 #define IP2_7_4     FM(AVB_MDIO)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0231 #define IP2_11_8    FM(AVB_MDC)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0232 #define IP2_15_12   FM(BS_N)        FM(PWM0_A)      FM(AVB_MAGIC)       FM(VI4_CLK)     F_(0, 0)        FM(TX3_C)   F_(0, 0)    FM(VI5_CLK_B)   F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0233 #define IP2_19_16   FM(RD_N)        FM(PWM1_A)      FM(AVB_LINK)        FM(VI4_FIELD)       F_(0, 0)        FM(RX3_C)   FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0234 #define IP2_23_20   FM(RD_WR_N)     FM(SCL7_A)      FM(AVB_AVTP_MATCH)  FM(VI4_VSYNC_N)     FM(TX5_B)       FM(SCK3_C)  FM(PWM5_A)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0235 #define IP2_27_24   FM(EX_WAIT0)        FM(SDA7_A)      FM(AVB_AVTP_CAPTURE)    FM(VI4_HSYNC_N)     FM(RX5_B)       FM(PWM6_A)  F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0236 #define IP2_31_28   FM(A0)          FM(IRQ0)        FM(PWM2_A)      FM(MSIOF3_SS1_B)    FM(VI5_CLK_A)       FM(DU_CDE)  FM(HRX3_D)  FM(IERX)    FM(QSTB_QHE)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0237 #define IP3_3_0     FM(A1)          FM(IRQ1)        FM(PWM3_A)      FM(DU_DOTCLKIN1)    FM(VI5_DATA0_A)     FM(DU_DISP_CDE) FM(SDA6_B)  FM(IETX)    FM(QCPV_QDE)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0238 #define IP3_7_4     FM(A2)          FM(IRQ2)        FM(AVB_AVTP_PPS)    FM(VI4_CLKENB)      FM(VI5_DATA1_A)     FM(DU_DISP) FM(SCL6_B)  F_(0, 0)    FM(QSTVB_QVE)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0239 #define IP3_11_8    FM(A3)          FM(CTS4_N_A)        FM(PWM4_A)      FM(VI4_DATA12)      F_(0, 0)        FM(DU_DOTCLKOUT0) FM(HTX3_D)    FM(IECLK)   FM(LCDOUT12)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0240 #define IP3_15_12   FM(A4)          FM(RTS4_N_A)        FM(MSIOF3_SYNC_B)   FM(VI4_DATA8)       FM(PWM2_B)      FM(DU_DG4)  FM(RIF2_CLK_B)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0241 #define IP3_19_16   FM(A5)          FM(SCK4_A)      FM(MSIOF3_SCK_B)    FM(VI4_DATA9)       FM(PWM3_B)      F_(0, 0)    FM(RIF2_SYNC_B) F_(0, 0)    FM(QPOLA)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0242 #define IP3_23_20   FM(A6)          FM(RX4_A)       FM(MSIOF3_RXD_B)    FM(VI4_DATA10)      F_(0, 0)        F_(0, 0)    FM(RIF2_D0_B)   F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0243 #define IP3_27_24   FM(A7)          FM(TX4_A)       FM(MSIOF3_TXD_B)    FM(VI4_DATA11)      F_(0, 0)        F_(0, 0)    FM(RIF2_D1_B)   F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0244 #define IP3_31_28   FM(A8)          FM(SDA6_A)      FM(RX3_B)       FM(HRX4_C)      FM(VI5_HSYNC_N_A)   FM(DU_HSYNC)    FM(VI4_DATA0_B) F_(0, 0)    FM(QSTH_QHS)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0245
0246 /* IPSRx */     /* 0 */         /* 1 */         /* 2 */         /* 3 */         /* 4 */         /* 5 */     /* 6 */     /* 7 */     /* 8 */     /* 9 - F */
0247 #define IP4_3_0     FM(A9)          FM(TX5_A)       FM(IRQ3)        FM(VI4_DATA16)      FM(VI5_VSYNC_N_A)   FM(DU_DG7)  F_(0, 0)    F_(0, 0)    FM(LCDOUT15)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0248 #define IP4_7_4     FM(A10)         FM(IRQ4)        FM(MSIOF2_SYNC_B)   FM(VI4_DATA13)      FM(VI5_FIELD_A)     FM(DU_DG5)  FM(FSCLKST2_N_B) F_(0, 0)   FM(LCDOUT13)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0249 #define IP4_11_8    FM(A11)         FM(SCL6_A)      FM(TX3_B)       FM(HTX4_C)      F_(0, 0)        FM(DU_VSYNC)    FM(VI4_DATA1_B) F_(0, 0)    FM(QSTVA_QVS)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0250 #define IP4_15_12   FM(A12)         FM(RX5_A)       FM(MSIOF2_SS2_B)    FM(VI4_DATA17)      FM(VI5_DATA3_A)     FM(DU_DG6)  F_(0, 0)    F_(0, 0)    FM(LCDOUT14)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0251 #define IP4_19_16   FM(A13)         FM(SCK5_A)      FM(MSIOF2_SCK_B)    FM(VI4_DATA14)      FM(HRX4_D)      FM(DU_DB2)  F_(0, 0)    F_(0, 0)    FM(LCDOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0252 #define IP4_23_20   FM(A14)         FM(MSIOF1_SS1)      FM(MSIOF2_RXD_B)    FM(VI4_DATA15)      FM(HTX4_D)      FM(DU_DB3)  F_(0, 0)    F_(0, 0)    FM(LCDOUT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0253 #define IP4_27_24   FM(A15)         FM(MSIOF1_SS2)      FM(MSIOF2_TXD_B)    FM(VI4_DATA18)      FM(VI5_DATA4_A)     FM(DU_DB4)  F_(0, 0)    F_(0, 0)    FM(LCDOUT4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0254 #define IP4_31_28   FM(A16)         FM(MSIOF1_SYNC)     FM(MSIOF2_SS1_B)    FM(VI4_DATA19)      FM(VI5_DATA5_A)     FM(DU_DB5)  F_(0, 0)    F_(0, 0)    FM(LCDOUT5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0255 #define IP5_3_0     FM(A17)         FM(MSIOF1_RXD)      F_(0, 0)        FM(VI4_DATA20)      FM(VI5_DATA6_A)     FM(DU_DB6)  F_(0, 0)    F_(0, 0)    FM(LCDOUT6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0256 #define IP5_7_4     FM(A18)         FM(MSIOF1_TXD)      F_(0, 0)        FM(VI4_DATA21)      FM(VI5_DATA7_A)     FM(DU_DB0)  F_(0, 0)    FM(HRX4_E)  FM(LCDOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0257 #define IP5_11_8    FM(A19)         FM(MSIOF1_SCK)      F_(0, 0)        FM(VI4_DATA22)      FM(VI5_DATA2_A)     FM(DU_DB1)  F_(0, 0)    FM(HTX4_E)  FM(LCDOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0258 #define IP5_15_12   FM(CS0_N)       FM(SCL5)        F_(0, 0)        F_(0, 0)        F_(0, 0)        FM(DU_DR0)  FM(VI4_DATA2_B) F_(0, 0)    FM(LCDOUT16)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0259 #define IP5_19_16   FM(WE0_N)       FM(SDA5)        F_(0, 0)        F_(0, 0)        F_(0, 0)        FM(DU_DR1)  FM(VI4_DATA3_B) F_(0, 0)    FM(LCDOUT17)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0260 #define IP5_23_20   FM(D0)          FM(MSIOF3_SCK_A)    F_(0, 0)        F_(0, 0)        F_(0, 0)        FM(DU_DR2)  FM(CTS4_N_C)    F_(0, 0)    FM(LCDOUT18)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0261 #define IP5_27_24   FM(D1)          FM(MSIOF3_SYNC_A)   FM(SCK3_A)      FM(VI4_DATA23)      FM(VI5_CLKENB_A)    FM(DU_DB7)  FM(RTS4_N_C)    F_(0, 0)    FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0262 #define IP5_31_28   FM(D2)          FM(MSIOF3_RXD_A)    FM(RX5_C)       F_(0, 0)        FM(VI5_DATA14_A)    FM(DU_DR3)  FM(RX4_C)   F_(0, 0)    FM(LCDOUT19)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0263 #define IP6_3_0     FM(D3)          FM(MSIOF3_TXD_A)    FM(TX5_C)       F_(0, 0)        FM(VI5_DATA15_A)    FM(DU_DR4)  FM(TX4_C)   F_(0, 0)    FM(LCDOUT20)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0264 #define IP6_7_4     FM(D4)          FM(CANFD1_TX)       FM(HSCK3_B)     FM(CAN1_TX)     FM(RTS3_N_A)        FM(MSIOF3_SS2_A) F_(0, 0)   FM(VI5_DATA1_B) F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0265 #define IP6_11_8    FM(D5)          FM(RX3_A)       FM(HRX3_B)      F_(0, 0)        F_(0, 0)        FM(DU_DR5)  FM(VI4_DATA4_B) F_(0, 0)    FM(LCDOUT21)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0266 #define IP6_15_12   FM(D6)          FM(TX3_A)       FM(HTX3_B)      F_(0, 0)        F_(0, 0)        FM(DU_DR6)  FM(VI4_DATA5_B) F_(0, 0)    FM(LCDOUT22)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0267 #define IP6_19_16   FM(D7)          FM(CANFD1_RX)       FM(IRQ5)        FM(CAN1_RX)     FM(CTS3_N_A)        F_(0, 0)    F_(0, 0)    FM(VI5_DATA2_B) F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0268 #define IP6_23_20   FM(D8)          FM(MSIOF2_SCK_A)    FM(SCK4_B)      F_(0, 0)        FM(VI5_DATA12_A)    FM(DU_DR7)  FM(RIF3_CLK_B)  FM(HCTS3_N_E)   FM(LCDOUT23)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0269 #define IP6_27_24   FM(D9)          FM(MSIOF2_SYNC_A)   F_(0, 0)        F_(0, 0)        FM(VI5_DATA10_A)    FM(DU_DG0)  FM(RIF3_SYNC_B) FM(HRX3_E)  FM(LCDOUT8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0270 #define IP6_31_28   FM(D10)         FM(MSIOF2_RXD_A)    F_(0, 0)        F_(0, 0)        FM(VI5_DATA13_A)    FM(DU_DG1)  FM(RIF3_D0_B)   FM(HTX3_E)  FM(LCDOUT9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0271 #define IP7_3_0     FM(D11)         FM(MSIOF2_TXD_A)    F_(0, 0)        F_(0, 0)        FM(VI5_DATA11_A)    FM(DU_DG2)  FM(RIF3_D1_B)   FM(HRTS3_N_E)   FM(LCDOUT10)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0272 #define IP7_7_4     FM(D12)         FM(CANFD0_TX)       FM(TX4_B)       FM(CAN0_TX)     FM(VI5_DATA8_A)     F_(0, 0)    F_(0, 0)    FM(VI5_DATA3_B) F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0273 #define IP7_11_8    FM(D13)         FM(CANFD0_RX)       FM(RX4_B)       FM(CAN0_RX)     FM(VI5_DATA9_A)     FM(SCL7_B)  F_(0, 0)    FM(VI5_DATA4_B) F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0274 #define IP7_15_12   FM(D14)         FM(CAN_CLK)     FM(HRX3_A)      FM(MSIOF2_SS2_A)    F_(0, 0)        FM(SDA7_B)  F_(0, 0)    FM(VI5_DATA5_B) F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0275 #define IP7_19_16   FM(D15)         FM(MSIOF2_SS1_A)    FM(HTX3_A)      FM(MSIOF3_SS1_A)    F_(0, 0)        FM(DU_DG3)  F_(0, 0)    F_(0, 0)    FM(LCDOUT11)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0276 #define IP7_23_20   FM(SCL4)        FM(CS1_N_A26)       F_(0, 0)        F_(0, 0)        F_(0, 0)        FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0277 #define IP7_27_24   FM(SDA4)        FM(WE1_N)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    FM(VI4_DATA7_B) FM(VI5_DATA7_B) FM(QPOLB)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0278 #define IP7_31_28   FM(SD0_CLK)     FM(NFDATA8)     FM(SCL1_C)      FM(HSCK1_B)     FM(SDA2_E)      FM(FMCLK_B) F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0279
0280 /* IPSRx */     /* 0 */         /* 1 */         /* 2 */         /* 3 */         /* 4 */         /* 5 */     /* 6 */     /* 7 */     /* 8 */     /* 9 - F */
0281 #define IP8_3_0     FM(SD0_CMD)     FM(NFDATA9)     F_(0, 0)        FM(HRX1_B)      F_(0, 0)        FM(SPEEDIN_B)   F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0282 #define IP8_7_4     FM(SD0_DAT0)        FM(NFDATA10)        F_(0, 0)        FM(HTX1_B)      F_(0, 0)        FM(REMOCON_B)   F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0283 #define IP8_11_8    FM(SD0_DAT1)        FM(NFDATA11)        FM(SDA2_C)      FM(HCTS1_N_B)       F_(0, 0)        FM(FMIN_B)  F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0284 #define IP8_15_12   FM(SD0_DAT2)        FM(NFDATA12)        FM(SCL2_C)      FM(HRTS1_N_B)       F_(0, 0)        FM(BPFCLK_B)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0285 #define IP8_19_16   FM(SD0_DAT3)        FM(NFDATA13)        FM(SDA1_C)      FM(SCL2_E)      FM(SPEEDIN_C)       FM(REMOCON_C)   F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0286 #define IP8_23_20   FM(SD1_CLK)     FM(NFDATA14_B)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0287 #define IP8_27_24   FM(SD1_CMD)     FM(NFDATA15_B)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0288 #define IP8_31_28   FM(SD1_DAT0)        FM(NFWP_N_B)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0289 #define IP9_3_0     FM(SD1_DAT1)        FM(NFCE_N_B)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0290 #define IP9_7_4     FM(SD1_DAT2)        FM(NFALE_B)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0291 #define IP9_11_8    FM(SD1_DAT3)        FM(NFRB_N_B)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0292 #define IP9_15_12   FM(SD3_CLK)     FM(NFWE_N)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0293 #define IP9_19_16   FM(SD3_CMD)     FM(NFRE_N)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0294 #define IP9_23_20   FM(SD3_DAT0)        FM(NFDATA0)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0295 #define IP9_27_24   FM(SD3_DAT1)        FM(NFDATA1)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0296 #define IP9_31_28   FM(SD3_DAT2)        FM(NFDATA2)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0297 #define IP10_3_0    FM(SD3_DAT3)        FM(NFDATA3)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0298 #define IP10_7_4    FM(SD3_DAT4)        FM(NFDATA4)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0299 #define IP10_11_8   FM(SD3_DAT5)        FM(NFDATA5)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0300 #define IP10_15_12  FM(SD3_DAT6)        FM(NFDATA6)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0301 #define IP10_19_16  FM(SD3_DAT7)        FM(NFDATA7)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0302 #define IP10_23_20  FM(SD3_DS)      FM(NFCLE)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0303 #define IP10_27_24  FM(SD0_CD)      FM(NFALE_A)     FM(SD3_CD)      FM(RIF0_CLK_B)      FM(SCL2_B)      FM(TCLK1_A) FM(SSI_SCK2_B)  FM(TS_SCK0) F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0304 #define IP10_31_28  FM(SD0_WP)      FM(NFRB_N_A)        FM(SD3_WP)      FM(RIF0_D0_B)       FM(SDA2_B)      FM(TCLK2_A) FM(SSI_WS2_B)   FM(TS_SDAT0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0305 #define IP11_3_0    FM(SD1_CD)      FM(NFCE_N_A)        FM(SSI_SCK1)        FM(RIF0_D1_B)       F_(0, 0)        F_(0, 0)    F_(0, 0)    FM(TS_SDEN0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0306 #define IP11_7_4    FM(SD1_WP)      FM(NFWP_N_A)        FM(SSI_WS1)     FM(RIF0_SYNC_B)     F_(0, 0)        F_(0, 0)    F_(0, 0)    FM(TS_SPSYNC0)  F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0307 #define IP11_11_8   FM(RX0_A)       FM(HRX1_A)      FM(SSI_SCK2_A)      FM(RIF1_SYNC)       F_(0, 0)        F_(0, 0)    F_(0, 0)    FM(TS_SCK1) F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0308 #define IP11_15_12  FM(TX0_A)       FM(HTX1_A)      FM(SSI_WS2_A)       FM(RIF1_D0)     F_(0, 0)        F_(0, 0)    F_(0, 0)    FM(TS_SDAT1)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0309 #define IP11_19_16  FM(CTS0_N_A)        FM(NFDATA14_A)      FM(AUDIO_CLKOUT_A)  FM(RIF1_D1)     FM(SCIF_CLK_A)      FM(FMCLK_A) F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0310 #define IP11_23_20  FM(RTS0_N_A)        FM(NFDATA15_A)      FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK)        FM(SCL2_A)      FM(FMIN_A)  F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0311 #define IP11_27_24  FM(SCK0_A)      FM(HSCK1_A)     FM(USB3HS0_ID)      FM(RTS1_N)      FM(SDA2_A)      FM(FMCLK_C) F_(0, 0)    F_(0, 0)    FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0312 #define IP11_31_28  FM(RX1)         FM(HRX2_B)      FM(SSI_SCK9_B)      FM(AUDIO_CLKOUT1_B) F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0313
0314 /* IPSRx */     /* 0 */         /* 1 */         /* 2 */         /* 3 */         /* 4 */         /* 5 */     /* 6 */     /* 7 */     /* 8 */     /* 9 - F */
0315 #define IP12_3_0    FM(TX1)         FM(HTX2_B)      FM(SSI_WS9_B)       FM(AUDIO_CLKOUT3_B) F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0316 #define IP12_7_4    FM(SCK2_A)      FM(HSCK0_A)     FM(AUDIO_CLKB_A)    FM(CTS1_N)      FM(RIF0_CLK_A)      FM(REMOCON_A)   FM(SCIF_CLK_B)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0317 #define IP12_11_8   FM(TX2_A)       FM(HRX0_A)      FM(AUDIO_CLKOUT2_A) F_(0, 0)        FM(SCL1_A)      F_(0, 0)    FM(FSO_CFE_0_N_A) FM(TS_SDEN1)  F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0318 #define IP12_15_12  FM(RX2_A)       FM(HTX0_A)      FM(AUDIO_CLKOUT3_A) F_(0, 0)        FM(SDA1_A)      F_(0, 0)    FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0319 #define IP12_19_16  FM(MSIOF0_SCK)      F_(0, 0)        FM(SSI_SCK78)       F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0320 #define IP12_23_20  FM(MSIOF0_RXD)      F_(0, 0)        FM(SSI_WS78)        F_(0, 0)        F_(0, 0)        FM(TX2_B)   F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0321 #define IP12_27_24  FM(MSIOF0_TXD)      F_(0, 0)        FM(SSI_SDATA7)      F_(0, 0)        F_(0, 0)        FM(RX2_B)   F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0322 #define IP12_31_28  FM(MSIOF0_SYNC)     FM(AUDIO_CLKOUT_B)  FM(SSI_SDATA8)      F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0323 #define IP13_3_0    FM(MSIOF0_SS1)      FM(HRX2_A)      FM(SSI_SCK4)        FM(HCTS0_N_A)       FM(BPFCLK_C)        FM(SPEEDIN_A)   F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0324 #define IP13_7_4    FM(MSIOF0_SS2)      FM(HTX2_A)      FM(SSI_WS4)     FM(HRTS0_N_A)       FM(FMIN_C)      FM(BPFCLK_A)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0325 #define IP13_11_8   FM(SSI_SDATA9)      F_(0, 0)        FM(AUDIO_CLKC_A)    FM(SCK1)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0326 #define IP13_15_12  FM(MLB_CLK)     FM(RX0_B)       F_(0, 0)        FM(RIF0_D0_A)       FM(SCL1_B)      FM(TCLK1_B) F_(0, 0)    F_(0, 0)    FM(SIM0_RST_A)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0327 #define IP13_19_16  FM(MLB_SIG)     FM(SCK0_B)      F_(0, 0)        FM(RIF0_D1_A)       FM(SDA1_B)      FM(TCLK2_B) F_(0, 0)    F_(0, 0)    FM(SIM0_D_A)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0328 #define IP13_23_20  FM(MLB_DAT)     FM(TX0_B)       F_(0, 0)        FM(RIF0_SYNC_A)     F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    FM(SIM0_CLK_A)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0329 #define IP13_27_24  FM(SSI_SCK01239)    F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0330 #define IP13_31_28  FM(SSI_WS01239)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0331 #define IP14_3_0    FM(SSI_SDATA0)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0332 #define IP14_7_4    FM(SSI_SDATA1)      FM(AUDIO_CLKC_B)    F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    FM(PWM0_B)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0333 #define IP14_11_8   FM(SSI_SDATA2)      FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_A)      F_(0, 0)        F_(0, 0)        F_(0, 0)    FM(PWM1_B)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0334 #define IP14_15_12  FM(SSI_SCK349)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    FM(PWM2_C)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0335 #define IP14_19_16  FM(SSI_WS349)       F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    FM(PWM3_C)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0336 #define IP14_23_20  FM(SSI_SDATA3)      FM(AUDIO_CLKOUT1_C) FM(AUDIO_CLKB_B)    F_(0, 0)        F_(0, 0)        F_(0, 0)    FM(PWM4_B)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0337 #define IP14_27_24  FM(SSI_SDATA4)      F_(0, 0)        FM(SSI_WS9_A)       F_(0, 0)        F_(0, 0)        F_(0, 0)    FM(PWM5_B)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0338 #define IP14_31_28  FM(SSI_SCK5)        FM(HRX0_B)      F_(0, 0)        FM(USB0_PWEN_B)     FM(SCL2_D)      F_(0, 0)    FM(PWM6_B)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0339 #define IP15_3_0    FM(SSI_WS5)     FM(HTX0_B)      F_(0, 0)        FM(USB0_OVC_B)      FM(SDA2_D)      F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0340 #define IP15_7_4    FM(SSI_SDATA5)      FM(HSCK0_B)     FM(AUDIO_CLKB_C)    FM(TPU0TO0)     F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0341 #define IP15_11_8   FM(SSI_SCK6)        FM(HSCK2_A)     FM(AUDIO_CLKC_C)    FM(TPU0TO1)     F_(0, 0)        F_(0, 0)    FM(FSO_CFE_0_N_B) F_(0, 0)  FM(SIM0_RST_B)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0342 #define IP15_15_12  FM(SSI_WS6)     FM(HCTS2_N_A)       FM(AUDIO_CLKOUT2_C) FM(TPU0TO2)     FM(SDA1_D)      F_(0, 0)    FM(FSO_CFE_1_N_B) F_(0, 0)  FM(SIM0_D_B)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0343 #define IP15_19_16  FM(SSI_SDATA6)      FM(HRTS2_N_A)       FM(AUDIO_CLKOUT3_C) FM(TPU0TO3)     FM(SCL1_D)      F_(0, 0)    FM(FSO_TOE_N_B) F_(0, 0)    FM(SIM0_CLK_B)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0344 #define IP15_23_20  FM(AUDIO_CLKA)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0345 #define IP15_27_24  FM(USB30_PWEN)      FM(USB0_PWEN_A)     F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0346 #define IP15_31_28  FM(USB30_OVC)       FM(USB0_OVC_A)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)    FM(FSO_TOE_N_A) F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0347
0348 #define PINMUX_GPSR \
0349 \
0350                                                      \
0351                                                      \
0352                                                      \
0353                                                      \
0354                                                      \
0355                                                      \
0356                 GPSR2_25                                 \
0357                 GPSR2_24                                 \
0358                 GPSR2_23                                 \
0359         GPSR1_22    GPSR2_22                                 \
0360         GPSR1_21    GPSR2_21                                 \
0361         GPSR1_20    GPSR2_20                                 \
0362         GPSR1_19    GPSR2_19                    GPSR5_19         \
0363         GPSR1_18    GPSR2_18                    GPSR5_18         \
0364 GPSR0_17    GPSR1_17    GPSR2_17                    GPSR5_17    GPSR6_17 \
0365 GPSR0_16    GPSR1_16    GPSR2_16                    GPSR5_16    GPSR6_16 \
0366 GPSR0_15    GPSR1_15    GPSR2_15    GPSR3_15            GPSR5_15    GPSR6_15 \
0367 GPSR0_14    GPSR1_14    GPSR2_14    GPSR3_14            GPSR5_14    GPSR6_14 \
0368 GPSR0_13    GPSR1_13    GPSR2_13    GPSR3_13            GPSR5_13    GPSR6_13 \
0369 GPSR0_12    GPSR1_12    GPSR2_12    GPSR3_12            GPSR5_12    GPSR6_12 \
0370 GPSR0_11    GPSR1_11    GPSR2_11    GPSR3_11            GPSR5_11    GPSR6_11 \
0371 GPSR0_10    GPSR1_10    GPSR2_10    GPSR3_10    GPSR4_10    GPSR5_10    GPSR6_10 \
0372 GPSR0_9     GPSR1_9     GPSR2_9     GPSR3_9     GPSR4_9     GPSR5_9     GPSR6_9 \
0373 GPSR0_8     GPSR1_8     GPSR2_8     GPSR3_8     GPSR4_8     GPSR5_8     GPSR6_8 \
0374 GPSR0_7     GPSR1_7     GPSR2_7     GPSR3_7     GPSR4_7     GPSR5_7     GPSR6_7 \
0375 GPSR0_6     GPSR1_6     GPSR2_6     GPSR3_6     GPSR4_6     GPSR5_6     GPSR6_6 \
0376 GPSR0_5     GPSR1_5     GPSR2_5     GPSR3_5     GPSR4_5     GPSR5_5     GPSR6_5 \
0377 GPSR0_4     GPSR1_4     GPSR2_4     GPSR3_4     GPSR4_4     GPSR5_4     GPSR6_4 \
0378 GPSR0_3     GPSR1_3     GPSR2_3     GPSR3_3     GPSR4_3     GPSR5_3     GPSR6_3 \
0379 GPSR0_2     GPSR1_2     GPSR2_2     GPSR3_2     GPSR4_2     GPSR5_2     GPSR6_2 \
0380 GPSR0_1     GPSR1_1     GPSR2_1     GPSR3_1     GPSR4_1     GPSR5_1     GPSR6_1 \
0381 GPSR0_0     GPSR1_0     GPSR2_0     GPSR3_0     GPSR4_0     GPSR5_0     GPSR6_0
0382
0383 #define PINMUX_IPSR             \
0384 \
0385 FM(IP0_3_0) IP0_3_0     FM(IP1_3_0) IP1_3_0     FM(IP2_3_0) IP2_3_0     FM(IP3_3_0) IP3_3_0 \
0386 FM(IP0_7_4) IP0_7_4     FM(IP1_7_4) IP1_7_4     FM(IP2_7_4) IP2_7_4     FM(IP3_7_4) IP3_7_4 \
0387 FM(IP0_11_8)    IP0_11_8    FM(IP1_11_8)    IP1_11_8    FM(IP2_11_8)    IP2_11_8    FM(IP3_11_8)    IP3_11_8 \
0388 FM(IP0_15_12)   IP0_15_12   FM(IP1_15_12)   IP1_15_12   FM(IP2_15_12)   IP2_15_12   FM(IP3_15_12)   IP3_15_12 \
0389 FM(IP0_19_16)   IP0_19_16   FM(IP1_19_16)   IP1_19_16   FM(IP2_19_16)   IP2_19_16   FM(IP3_19_16)   IP3_19_16 \
0390 FM(IP0_23_20)   IP0_23_20   FM(IP1_23_20)   IP1_23_20   FM(IP2_23_20)   IP2_23_20   FM(IP3_23_20)   IP3_23_20 \
0391 FM(IP0_27_24)   IP0_27_24   FM(IP1_27_24)   IP1_27_24   FM(IP2_27_24)   IP2_27_24   FM(IP3_27_24)   IP3_27_24 \
0392 FM(IP0_31_28)   IP0_31_28   FM(IP1_31_28)   IP1_31_28   FM(IP2_31_28)   IP2_31_28   FM(IP3_31_28)   IP3_31_28 \
0393 \
0394 FM(IP4_3_0) IP4_3_0     FM(IP5_3_0) IP5_3_0     FM(IP6_3_0) IP6_3_0     FM(IP7_3_0) IP7_3_0 \
0395 FM(IP4_7_4) IP4_7_4     FM(IP5_7_4) IP5_7_4     FM(IP6_7_4) IP6_7_4     FM(IP7_7_4) IP7_7_4 \
0396 FM(IP4_11_8)    IP4_11_8    FM(IP5_11_8)    IP5_11_8    FM(IP6_11_8)    IP6_11_8    FM(IP7_11_8)    IP7_11_8 \
0397 FM(IP4_15_12)   IP4_15_12   FM(IP5_15_12)   IP5_15_12   FM(IP6_15_12)   IP6_15_12   FM(IP7_15_12)   IP7_15_12 \
0398 FM(IP4_19_16)   IP4_19_16   FM(IP5_19_16)   IP5_19_16   FM(IP6_19_16)   IP6_19_16   FM(IP7_19_16)   IP7_19_16 \
0399 FM(IP4_23_20)   IP4_23_20   FM(IP5_23_20)   IP5_23_20   FM(IP6_23_20)   IP6_23_20   FM(IP7_23_20)   IP7_23_20 \
0400 FM(IP4_27_24)   IP4_27_24   FM(IP5_27_24)   IP5_27_24   FM(IP6_27_24)   IP6_27_24   FM(IP7_27_24)   IP7_27_24 \
0401 FM(IP4_31_28)   IP4_31_28   FM(IP5_31_28)   IP5_31_28   FM(IP6_31_28)   IP6_31_28   FM(IP7_31_28)   IP7_31_28 \
0402 \
0403 FM(IP8_3_0) IP8_3_0     FM(IP9_3_0) IP9_3_0     FM(IP10_3_0)    IP10_3_0    FM(IP11_3_0)    IP11_3_0 \
0404 FM(IP8_7_4) IP8_7_4     FM(IP9_7_4) IP9_7_4     FM(IP10_7_4)    IP10_7_4    FM(IP11_7_4)    IP11_7_4 \
0405 FM(IP8_11_8)    IP8_11_8    FM(IP9_11_8)    IP9_11_8    FM(IP10_11_8)   IP10_11_8   FM(IP11_11_8)   IP11_11_8 \
0406 FM(IP8_15_12)   IP8_15_12   FM(IP9_15_12)   IP9_15_12   FM(IP10_15_12)  IP10_15_12  FM(IP11_15_12)  IP11_15_12 \
0407 FM(IP8_19_16)   IP8_19_16   FM(IP9_19_16)   IP9_19_16   FM(IP10_19_16)  IP10_19_16  FM(IP11_19_16)  IP11_19_16 \
0408 FM(IP8_23_20)   IP8_23_20   FM(IP9_23_20)   IP9_23_20   FM(IP10_23_20)  IP10_23_20  FM(IP11_23_20)  IP11_23_20 \
0409 FM(IP8_27_24)   IP8_27_24   FM(IP9_27_24)   IP9_27_24   FM(IP10_27_24)  IP10_27_24  FM(IP11_27_24)  IP11_27_24 \
0410 FM(IP8_31_28)   IP8_31_28   FM(IP9_31_28)   IP9_31_28   FM(IP10_31_28)  IP10_31_28  FM(IP11_31_28)  IP11_31_28 \
0411 \
0412 FM(IP12_3_0)    IP12_3_0    FM(IP13_3_0)    IP13_3_0    FM(IP14_3_0)    IP14_3_0    FM(IP15_3_0)    IP15_3_0 \
0413 FM(IP12_7_4)    IP12_7_4    FM(IP13_7_4)    IP13_7_4    FM(IP14_7_4)    IP14_7_4    FM(IP15_7_4)    IP15_7_4 \
0414 FM(IP12_11_8)   IP12_11_8   FM(IP13_11_8)   IP13_11_8   FM(IP14_11_8)   IP14_11_8   FM(IP15_11_8)   IP15_11_8 \
0415 FM(IP12_15_12)  IP12_15_12  FM(IP13_15_12)  IP13_15_12  FM(IP14_15_12)  IP14_15_12  FM(IP15_15_12)  IP15_15_12 \
0416 FM(IP12_19_16)  IP12_19_16  FM(IP13_19_16)  IP13_19_16  FM(IP14_19_16)  IP14_19_16  FM(IP15_19_16)  IP15_19_16 \
0417 FM(IP12_23_20)  IP12_23_20  FM(IP13_23_20)  IP13_23_20  FM(IP14_23_20)  IP14_23_20  FM(IP15_23_20)  IP15_23_20 \
0418 FM(IP12_27_24)  IP12_27_24  FM(IP13_27_24)  IP13_27_24  FM(IP14_27_24)  IP14_27_24  FM(IP15_27_24)  IP15_27_24 \
0419 FM(IP12_31_28)  IP12_31_28  FM(IP13_31_28)  IP13_31_28  FM(IP14_31_28)  IP14_31_28  FM(IP15_31_28)  IP15_31_28
0420
0421 /* The bit numbering in MOD_SEL fields is reversed */
0422 #define REV4(f0, f1, f2, f3)            f0 f2 f1 f3
0423 #define REV8(f0, f1, f2, f3, f4, f5, f6, f7)    f0 f4 f2 f6 f1 f5 f3 f7
0424
0425 /* MOD_SEL0 */          /* 0 */             /* 1 */             /* 2 */             /* 3 */         /* 4 */         /* 5 */     /* 6 */     /* 7 */
0426 #define MOD_SEL0_30_29     REV4(FM(SEL_ADGB_0),         FM(SEL_ADGB_1),         FM(SEL_ADGB_2),         F_(0, 0))
0427 #define MOD_SEL0_28     FM(SEL_DRIF0_0)         FM(SEL_DRIF0_1)
0428 #define MOD_SEL0_27_26     REV4(FM(SEL_FM_0),           FM(SEL_FM_1),           FM(SEL_FM_2),           F_(0, 0))
0429 #define MOD_SEL0_25     FM(SEL_FSO_0)           FM(SEL_FSO_1)
0430 #define MOD_SEL0_24     FM(SEL_HSCIF0_0)        FM(SEL_HSCIF0_1)
0431 #define MOD_SEL0_23     FM(SEL_HSCIF1_0)        FM(SEL_HSCIF1_1)
0432 #define MOD_SEL0_22     FM(SEL_HSCIF2_0)        FM(SEL_HSCIF2_1)
0433 #define MOD_SEL0_21_20     REV4(FM(SEL_I2C1_0),         FM(SEL_I2C1_1),         FM(SEL_I2C1_2),         FM(SEL_I2C1_3))
0434 #define MOD_SEL0_19_18_17  REV8(FM(SEL_I2C2_0),         FM(SEL_I2C2_1),         FM(SEL_I2C2_2),         FM(SEL_I2C2_3),     FM(SEL_I2C2_4),     F_(0, 0),   F_(0, 0),   F_(0, 0))
0435 #define MOD_SEL0_16     FM(SEL_NDF_0)           FM(SEL_NDF_1)
0436 #define MOD_SEL0_15     FM(SEL_PWM0_0)          FM(SEL_PWM0_1)
0437 #define MOD_SEL0_14     FM(SEL_PWM1_0)          FM(SEL_PWM1_1)
0438 #define MOD_SEL0_13_12     REV4(FM(SEL_PWM2_0),         FM(SEL_PWM2_1),         FM(SEL_PWM2_2),         F_(0, 0))
0439 #define MOD_SEL0_11_10     REV4(FM(SEL_PWM3_0),         FM(SEL_PWM3_1),         FM(SEL_PWM3_2),         F_(0, 0))
0440 #define MOD_SEL0_9      FM(SEL_PWM4_0)          FM(SEL_PWM4_1)
0441 #define MOD_SEL0_8      FM(SEL_PWM5_0)          FM(SEL_PWM5_1)
0442 #define MOD_SEL0_7      FM(SEL_PWM6_0)          FM(SEL_PWM6_1)
0443 #define MOD_SEL0_6_5       REV4(FM(SEL_REMOCON_0),      FM(SEL_REMOCON_1),      FM(SEL_REMOCON_2),      F_(0, 0))
0444 #define MOD_SEL0_4      FM(SEL_SCIF_0)          FM(SEL_SCIF_1)
0445 #define MOD_SEL0_3      FM(SEL_SCIF0_0)         FM(SEL_SCIF0_1)
0446 #define MOD_SEL0_2      FM(SEL_SCIF2_0)         FM(SEL_SCIF2_1)
0447 #define MOD_SEL0_1_0       REV4(FM(SEL_SPEED_PULSE_IF_0),   FM(SEL_SPEED_PULSE_IF_1),   FM(SEL_SPEED_PULSE_IF_2),   F_(0, 0))
0448
0449 /* MOD_SEL1 */          /* 0 */             /* 1 */             /* 2 */             /* 3 */         /* 4 */         /* 5 */     /* 6 */     /* 7 */
0450 #define MOD_SEL1_31     FM(SEL_SIMCARD_0)       FM(SEL_SIMCARD_1)
0451 #define MOD_SEL1_30     FM(SEL_SSI2_0)          FM(SEL_SSI2_1)
0452 #define MOD_SEL1_29     FM(SEL_TIMER_TMU_0)     FM(SEL_TIMER_TMU_1)
0453 #define MOD_SEL1_28     FM(SEL_USB_20_CH0_0)        FM(SEL_USB_20_CH0_1)
0454 #define MOD_SEL1_26     FM(SEL_DRIF2_0)         FM(SEL_DRIF2_1)
0455 #define MOD_SEL1_25     FM(SEL_DRIF3_0)         FM(SEL_DRIF3_1)
0456 #define MOD_SEL1_24_23_22  REV8(FM(SEL_HSCIF3_0),       FM(SEL_HSCIF3_1),       FM(SEL_HSCIF3_2),       FM(SEL_HSCIF3_3),   FM(SEL_HSCIF3_4),   F_(0, 0),   F_(0, 0),   F_(0, 0))
0457 #define MOD_SEL1_21_20_19  REV8(FM(SEL_HSCIF4_0),       FM(SEL_HSCIF4_1),       FM(SEL_HSCIF4_2),       FM(SEL_HSCIF4_3),   FM(SEL_HSCIF4_4),   F_(0, 0),   F_(0, 0),   F_(0, 0))
0458 #define MOD_SEL1_18     FM(SEL_I2C6_0)          FM(SEL_I2C6_1)
0459 #define MOD_SEL1_17     FM(SEL_I2C7_0)          FM(SEL_I2C7_1)
0460 #define MOD_SEL1_16     FM(SEL_MSIOF2_0)        FM(SEL_MSIOF2_1)
0461 #define MOD_SEL1_15     FM(SEL_MSIOF3_0)        FM(SEL_MSIOF3_1)
0462 #define MOD_SEL1_14_13     REV4(FM(SEL_SCIF3_0),        FM(SEL_SCIF3_1),        FM(SEL_SCIF3_2),        F_(0, 0))
0463 #define MOD_SEL1_12_11     REV4(FM(SEL_SCIF4_0),        FM(SEL_SCIF4_1),        FM(SEL_SCIF4_2),        F_(0, 0))
0464 #define MOD_SEL1_10_9      REV4(FM(SEL_SCIF5_0),        FM(SEL_SCIF5_1),        FM(SEL_SCIF5_2),        F_(0, 0))
0465 #define MOD_SEL1_8      FM(SEL_VIN4_0)          FM(SEL_VIN4_1)
0466 #define MOD_SEL1_7      FM(SEL_VIN5_0)          FM(SEL_VIN5_1)
0467 #define MOD_SEL1_6_5       REV4(FM(SEL_ADGC_0),         FM(SEL_ADGC_1),         FM(SEL_ADGC_2),         F_(0, 0))
0468 #define MOD_SEL1_4      FM(SEL_SSI9_0)          FM(SEL_SSI9_1)
0469
0470 #define PINMUX_MOD_SELS \
0471 \
0472             MOD_SEL1_31 \
0473 MOD_SEL0_30_29      MOD_SEL1_30 \
0474             MOD_SEL1_29 \
0475 MOD_SEL0_28     MOD_SEL1_28 \
0476 MOD_SEL0_27_26 \
0477             MOD_SEL1_26 \
0478 MOD_SEL0_25     MOD_SEL1_25 \
0479 MOD_SEL0_24     MOD_SEL1_24_23_22 \
0480 MOD_SEL0_23 \
0481 MOD_SEL0_22 \
0482 MOD_SEL0_21_20      MOD_SEL1_21_20_19 \
0483 MOD_SEL0_19_18_17   MOD_SEL1_18 \
0484             MOD_SEL1_17 \
0485 MOD_SEL0_16     MOD_SEL1_16 \
0486 MOD_SEL0_15     MOD_SEL1_15 \
0487 MOD_SEL0_14     MOD_SEL1_14_13 \
0488 MOD_SEL0_13_12 \
0489             MOD_SEL1_12_11 \
0490 MOD_SEL0_11_10 \
0491             MOD_SEL1_10_9 \
0492 MOD_SEL0_9 \
0493 MOD_SEL0_8      MOD_SEL1_8 \
0494 MOD_SEL0_7      MOD_SEL1_7 \
0495 MOD_SEL0_6_5        MOD_SEL1_6_5 \
0496 MOD_SEL0_4      MOD_SEL1_4 \
0497 MOD_SEL0_3 \
0498 MOD_SEL0_2 \
0499 MOD_SEL0_1_0
0500
0501 /*
0502  * These pins are not able to be muxed but have other properties
0503  * that can be set, such as pull-up/pull-down enable.
0504  */
0505 #define PINMUX_STATIC \
0506     FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \
0507     FM(AVB_TD3) \
0508     FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
0509     FM(ASEBRK) \
0510     FM(MLB_REF)
0511
0512 enum {
0513     PINMUX_RESERVED = 0,
0514
0515     PINMUX_DATA_BEGIN,
0516     GP_ALL(DATA),
0517     PINMUX_DATA_END,
0518
0519 #define F_(x, y)
0520 #define FM(x)   FN_##x,
0521     PINMUX_FUNCTION_BEGIN,
0522     GP_ALL(FN),
0523     PINMUX_GPSR
0524     PINMUX_IPSR
0525     PINMUX_MOD_SELS
0526     PINMUX_FUNCTION_END,
0527 #undef F_
0528 #undef FM
0529
0530 #define F_(x, y)
0531 #define FM(x)   x##_MARK,
0532     PINMUX_MARK_BEGIN,
0533     PINMUX_GPSR
0534     PINMUX_IPSR
0535     PINMUX_MOD_SELS
0536     PINMUX_STATIC
0537     PINMUX_MARK_END,
0538 #undef F_
0539 #undef FM
0540 };
0541
0542 static const u16 pinmux_data[] = {
0543     PINMUX_DATA_GP_ALL(),
0544
0545     PINMUX_SINGLE(CLKOUT),
0546     PINMUX_SINGLE(AVB_PHY_INT),
0547     PINMUX_SINGLE(AVB_RD3),
0548     PINMUX_SINGLE(AVB_RXC),
0549     PINMUX_SINGLE(AVB_RX_CTL),
0550     PINMUX_SINGLE(QSPI0_SSL),
0551
0552     /* IPSR0 */
0553     PINMUX_IPSR_GPSR(IP0_3_0,       QSPI0_SPCLK),
0554     PINMUX_IPSR_MSEL(IP0_3_0,       HSCK4_A,    SEL_HSCIF4_0),
0555
0556     PINMUX_IPSR_GPSR(IP0_7_4,       QSPI0_MOSI_IO0),
0557     PINMUX_IPSR_MSEL(IP0_7_4,       HCTS4_N_A,  SEL_HSCIF4_0),
0558
0559     PINMUX_IPSR_GPSR(IP0_11_8,      QSPI0_MISO_IO1),
0560     PINMUX_IPSR_MSEL(IP0_11_8,      HRTS4_N_A,  SEL_HSCIF4_0),
0561
0562     PINMUX_IPSR_GPSR(IP0_15_12,     QSPI0_IO2),
0563     PINMUX_IPSR_GPSR(IP0_15_12,     HTX4_A),
0564
0565     PINMUX_IPSR_GPSR(IP0_19_16,     QSPI0_IO3),
0566     PINMUX_IPSR_MSEL(IP0_19_16,     HRX4_A,     SEL_HSCIF4_0),
0567
0568     PINMUX_IPSR_GPSR(IP0_23_20,     QSPI1_SPCLK),
0569     PINMUX_IPSR_MSEL(IP0_23_20,     RIF2_CLK_A, SEL_DRIF2_0),
0570     PINMUX_IPSR_MSEL(IP0_23_20,     HSCK4_B,    SEL_HSCIF4_1),
0571     PINMUX_IPSR_MSEL(IP0_23_20,     VI4_DATA0_A,    SEL_VIN4_0),
0572
0573     PINMUX_IPSR_GPSR(IP0_27_24,     QSPI1_MOSI_IO0),
0574     PINMUX_IPSR_MSEL(IP0_27_24,     RIF2_SYNC_A,    SEL_DRIF2_0),
0575     PINMUX_IPSR_GPSR(IP0_27_24,     HTX4_B),
0576     PINMUX_IPSR_MSEL(IP0_27_24,     VI4_DATA1_A,    SEL_VIN4_0),
0577
0578     PINMUX_IPSR_GPSR(IP0_31_28,     QSPI1_MISO_IO1),
0579     PINMUX_IPSR_MSEL(IP0_31_28,     RIF2_D0_A,  SEL_DRIF2_0),
0580     PINMUX_IPSR_MSEL(IP0_31_28,     HRX4_B,     SEL_HSCIF4_1),
0581     PINMUX_IPSR_MSEL(IP0_31_28,     VI4_DATA2_A,    SEL_VIN4_0),
0582
0583     /* IPSR1 */
0584     PINMUX_IPSR_GPSR(IP1_3_0,       QSPI1_IO2),
0585     PINMUX_IPSR_MSEL(IP1_3_0,       RIF2_D1_A,  SEL_DRIF2_0),
0586     PINMUX_IPSR_GPSR(IP1_3_0,       HTX3_C),
0587     PINMUX_IPSR_MSEL(IP1_3_0,       VI4_DATA3_A,    SEL_VIN4_0),
0588
0589     PINMUX_IPSR_GPSR(IP1_7_4,       QSPI1_IO3),
0590     PINMUX_IPSR_MSEL(IP1_7_4,       RIF3_CLK_A, SEL_DRIF3_0),
0591     PINMUX_IPSR_MSEL(IP1_7_4,       HRX3_C,     SEL_HSCIF3_2),
0592     PINMUX_IPSR_MSEL(IP1_7_4,       VI4_DATA4_A,    SEL_VIN4_0),
0593
0594     PINMUX_IPSR_GPSR(IP1_11_8,      QSPI1_SSL),
0595     PINMUX_IPSR_MSEL(IP1_11_8,      RIF3_SYNC_A,    SEL_DRIF3_0),
0596     PINMUX_IPSR_MSEL(IP1_11_8,      HSCK3_C,    SEL_HSCIF3_2),
0597     PINMUX_IPSR_MSEL(IP1_11_8,      VI4_DATA5_A,    SEL_VIN4_0),
0598
0599     PINMUX_IPSR_GPSR(IP1_15_12,     RPC_INT_N),
0600     PINMUX_IPSR_MSEL(IP1_15_12,     RIF3_D0_A,  SEL_DRIF3_0),
0601     PINMUX_IPSR_MSEL(IP1_15_12,     HCTS3_N_C,  SEL_HSCIF3_2),
0602     PINMUX_IPSR_MSEL(IP1_15_12,     VI4_DATA6_A,    SEL_VIN4_0),
0603
0604     PINMUX_IPSR_GPSR(IP1_19_16,     RPC_RESET_N),
0605     PINMUX_IPSR_MSEL(IP1_19_16,     RIF3_D1_A,  SEL_DRIF3_0),
0606     PINMUX_IPSR_MSEL(IP1_19_16,     HRTS3_N_C,  SEL_HSCIF3_2),
0607     PINMUX_IPSR_MSEL(IP1_19_16,     VI4_DATA7_A,    SEL_VIN4_0),
0608
0609     PINMUX_IPSR_GPSR(IP1_23_20,     AVB_RD0),
0610
0611     PINMUX_IPSR_GPSR(IP1_27_24,     AVB_RD1),
0612
0613     PINMUX_IPSR_GPSR(IP1_31_28,     AVB_RD2),
0614
0615     /* IPSR2 */
0616     PINMUX_IPSR_GPSR(IP2_3_0,       AVB_TXCREFCLK),
0617
0618     PINMUX_IPSR_GPSR(IP2_7_4,       AVB_MDIO),
0619
0620     PINMUX_IPSR_GPSR(IP2_11_8,      AVB_MDC),
0621
0622     PINMUX_IPSR_GPSR(IP2_15_12,     BS_N),
0623     PINMUX_IPSR_MSEL(IP2_15_12,     PWM0_A,     SEL_PWM0_0),
0624     PINMUX_IPSR_GPSR(IP2_15_12,     AVB_MAGIC),
0625     PINMUX_IPSR_GPSR(IP2_15_12,     VI4_CLK),
0626     PINMUX_IPSR_GPSR(IP2_15_12,     TX3_C),
0627     PINMUX_IPSR_MSEL(IP2_15_12,     VI5_CLK_B,  SEL_VIN5_1),
0628
0629     PINMUX_IPSR_GPSR(IP2_19_16,     RD_N),
0630     PINMUX_IPSR_MSEL(IP2_19_16,     PWM1_A,     SEL_PWM1_0),
0631     PINMUX_IPSR_GPSR(IP2_19_16,     AVB_LINK),
0632     PINMUX_IPSR_GPSR(IP2_19_16,     VI4_FIELD),
0633     PINMUX_IPSR_MSEL(IP2_19_16,     RX3_C,      SEL_SCIF3_2),
0634     PINMUX_IPSR_GPSR(IP2_19_16,     FSCLKST2_N_A),
0635     PINMUX_IPSR_MSEL(IP2_19_16,     VI5_DATA0_B,    SEL_VIN5_1),
0636
0637     PINMUX_IPSR_GPSR(IP2_23_20,     RD_WR_N),
0638     PINMUX_IPSR_MSEL(IP2_23_20,     SCL7_A,     SEL_I2C7_0),
0639     PINMUX_IPSR_GPSR(IP2_23_20,     AVB_AVTP_MATCH),
0640     PINMUX_IPSR_GPSR(IP2_23_20,     VI4_VSYNC_N),
0641     PINMUX_IPSR_GPSR(IP2_23_20,     TX5_B),
0642     PINMUX_IPSR_MSEL(IP2_23_20,     SCK3_C,     SEL_SCIF3_2),
0643     PINMUX_IPSR_MSEL(IP2_23_20,     PWM5_A,     SEL_PWM5_0),
0644
0645     PINMUX_IPSR_GPSR(IP2_27_24,     EX_WAIT0),
0646     PINMUX_IPSR_MSEL(IP2_27_24,     SDA7_A,     SEL_I2C7_0),
0647     PINMUX_IPSR_GPSR(IP2_27_24,     AVB_AVTP_CAPTURE),
0648     PINMUX_IPSR_GPSR(IP2_27_24,     VI4_HSYNC_N),
0649     PINMUX_IPSR_MSEL(IP2_27_24,     RX5_B,      SEL_SCIF5_1),
0650     PINMUX_IPSR_MSEL(IP2_27_24,     PWM6_A,     SEL_PWM6_0),
0651
0652     PINMUX_IPSR_GPSR(IP2_31_28,     A0),
0653     PINMUX_IPSR_GPSR(IP2_31_28,     IRQ0),
0654     PINMUX_IPSR_MSEL(IP2_31_28,     PWM2_A,     SEL_PWM2_0),
0655     PINMUX_IPSR_MSEL(IP2_31_28,     MSIOF3_SS1_B,   SEL_MSIOF3_1),
0656     PINMUX_IPSR_MSEL(IP2_31_28,     VI5_CLK_A,  SEL_VIN5_0),
0657     PINMUX_IPSR_GPSR(IP2_31_28,     DU_CDE),
0658     PINMUX_IPSR_MSEL(IP2_31_28,     HRX3_D,     SEL_HSCIF3_3),
0659     PINMUX_IPSR_GPSR(IP2_31_28,     IERX),
0660     PINMUX_IPSR_GPSR(IP2_31_28,     QSTB_QHE),
0661
0662     /* IPSR3 */
0663     PINMUX_IPSR_GPSR(IP3_3_0,       A1),
0664     PINMUX_IPSR_GPSR(IP3_3_0,       IRQ1),
0665     PINMUX_IPSR_MSEL(IP3_3_0,       PWM3_A,     SEL_PWM3_0),
0666     PINMUX_IPSR_GPSR(IP3_3_0,       DU_DOTCLKIN1),
0667     PINMUX_IPSR_MSEL(IP3_3_0,       VI5_DATA0_A,    SEL_VIN5_0),
0668     PINMUX_IPSR_GPSR(IP3_3_0,       DU_DISP_CDE),
0669     PINMUX_IPSR_MSEL(IP3_3_0,       SDA6_B,     SEL_I2C6_1),
0670     PINMUX_IPSR_GPSR(IP3_3_0,       IETX),
0671     PINMUX_IPSR_GPSR(IP3_3_0,       QCPV_QDE),
0672
0673     PINMUX_IPSR_GPSR(IP3_7_4,       A2),
0674     PINMUX_IPSR_GPSR(IP3_7_4,       IRQ2),
0675     PINMUX_IPSR_GPSR(IP3_7_4,       AVB_AVTP_PPS),
0676     PINMUX_IPSR_GPSR(IP3_7_4,       VI4_CLKENB),
0677     PINMUX_IPSR_MSEL(IP3_7_4,       VI5_DATA1_A,    SEL_VIN5_0),
0678     PINMUX_IPSR_GPSR(IP3_7_4,       DU_DISP),
0679     PINMUX_IPSR_MSEL(IP3_7_4,       SCL6_B,     SEL_I2C6_1),
0680     PINMUX_IPSR_GPSR(IP3_7_4,       QSTVB_QVE),
0681
0682     PINMUX_IPSR_GPSR(IP3_11_8,      A3),
0683     PINMUX_IPSR_MSEL(IP3_11_8,      CTS4_N_A,   SEL_SCIF4_0),
0684     PINMUX_IPSR_MSEL(IP3_11_8,      PWM4_A,     SEL_PWM4_0),
0685     PINMUX_IPSR_GPSR(IP3_11_8,      VI4_DATA12),
0686     PINMUX_IPSR_GPSR(IP3_11_8,      DU_DOTCLKOUT0),
0687     PINMUX_IPSR_GPSR(IP3_11_8,      HTX3_D),
0688     PINMUX_IPSR_GPSR(IP3_11_8,      IECLK),
0689     PINMUX_IPSR_GPSR(IP3_11_8,      LCDOUT12),
0690
0691     PINMUX_IPSR_GPSR(IP3_15_12,     A4),
0692     PINMUX_IPSR_MSEL(IP3_15_12,     RTS4_N_A,   SEL_SCIF4_0),
0693     PINMUX_IPSR_MSEL(IP3_15_12,     MSIOF3_SYNC_B,  SEL_MSIOF3_1),
0694     PINMUX_IPSR_GPSR(IP3_15_12,     VI4_DATA8),
0695     PINMUX_IPSR_MSEL(IP3_15_12,     PWM2_B,     SEL_PWM2_1),
0696     PINMUX_IPSR_GPSR(IP3_15_12,     DU_DG4),
0697     PINMUX_IPSR_MSEL(IP3_15_12,     RIF2_CLK_B, SEL_DRIF2_1),
0698
0699     PINMUX_IPSR_GPSR(IP3_19_16,     A5),
0700     PINMUX_IPSR_MSEL(IP3_19_16,     SCK4_A,     SEL_SCIF4_0),
0701     PINMUX_IPSR_MSEL(IP3_19_16,     MSIOF3_SCK_B,   SEL_MSIOF3_1),
0702     PINMUX_IPSR_GPSR(IP3_19_16,     VI4_DATA9),
0703     PINMUX_IPSR_MSEL(IP3_19_16,     PWM3_B,     SEL_PWM3_1),
0704     PINMUX_IPSR_MSEL(IP3_19_16,     RIF2_SYNC_B,    SEL_DRIF2_1),
0705     PINMUX_IPSR_GPSR(IP3_19_16,     QPOLA),
0706
0707     PINMUX_IPSR_GPSR(IP3_23_20,     A6),
0708     PINMUX_IPSR_MSEL(IP3_23_20,     RX4_A,      SEL_SCIF4_0),
0709     PINMUX_IPSR_MSEL(IP3_23_20,     MSIOF3_RXD_B,   SEL_MSIOF3_1),
0710     PINMUX_IPSR_GPSR(IP3_23_20,     VI4_DATA10),
0711     PINMUX_IPSR_MSEL(IP3_23_20,     RIF2_D0_B,  SEL_DRIF2_1),
0712
0713     PINMUX_IPSR_GPSR(IP3_27_24,     A7),
0714     PINMUX_IPSR_GPSR(IP3_27_24,     TX4_A),
0715     PINMUX_IPSR_GPSR(IP3_27_24,     MSIOF3_TXD_B),
0716     PINMUX_IPSR_GPSR(IP3_27_24,     VI4_DATA11),
0717     PINMUX_IPSR_MSEL(IP3_27_24,     RIF2_D1_B,  SEL_DRIF2_1),
0718
0719     PINMUX_IPSR_GPSR(IP3_31_28,     A8),
0720     PINMUX_IPSR_MSEL(IP3_31_28,     SDA6_A,     SEL_I2C6_0),
0721     PINMUX_IPSR_MSEL(IP3_31_28,     RX3_B,      SEL_SCIF3_1),
0722     PINMUX_IPSR_MSEL(IP3_31_28,     HRX4_C,     SEL_HSCIF4_2),
0723     PINMUX_IPSR_MSEL(IP3_31_28,     VI5_HSYNC_N_A,  SEL_VIN5_0),
0724     PINMUX_IPSR_GPSR(IP3_31_28,     DU_HSYNC),
0725     PINMUX_IPSR_MSEL(IP3_31_28,     VI4_DATA0_B,    SEL_VIN4_1),
0726     PINMUX_IPSR_GPSR(IP3_31_28,     QSTH_QHS),
0727
0728     /* IPSR4 */
0729     PINMUX_IPSR_GPSR(IP4_3_0,       A9),
0730     PINMUX_IPSR_GPSR(IP4_3_0,       TX5_A),
0731     PINMUX_IPSR_GPSR(IP4_3_0,       IRQ3),
0732     PINMUX_IPSR_GPSR(IP4_3_0,       VI4_DATA16),
0733     PINMUX_IPSR_MSEL(IP4_3_0,       VI5_VSYNC_N_A,  SEL_VIN5_0),
0734     PINMUX_IPSR_GPSR(IP4_3_0,       DU_DG7),
0735     PINMUX_IPSR_GPSR(IP4_3_0,       LCDOUT15),
0736
0737     PINMUX_IPSR_GPSR(IP4_7_4,       A10),
0738     PINMUX_IPSR_GPSR(IP4_7_4,       IRQ4),
0739     PINMUX_IPSR_MSEL(IP4_7_4,       MSIOF2_SYNC_B,  SEL_MSIOF2_1),
0740     PINMUX_IPSR_GPSR(IP4_7_4,       VI4_DATA13),
0741     PINMUX_IPSR_MSEL(IP4_7_4,       VI5_FIELD_A,    SEL_VIN5_0),
0742     PINMUX_IPSR_GPSR(IP4_7_4,       DU_DG5),
0743     PINMUX_IPSR_GPSR(IP4_7_4,       FSCLKST2_N_B),
0744     PINMUX_IPSR_GPSR(IP4_7_4,       LCDOUT13),
0745
0746     PINMUX_IPSR_GPSR(IP4_11_8,      A11),
0747     PINMUX_IPSR_MSEL(IP4_11_8,      SCL6_A,     SEL_I2C6_0),
0748     PINMUX_IPSR_GPSR(IP4_11_8,      TX3_B),
0749     PINMUX_IPSR_GPSR(IP4_11_8,      HTX4_C),
0750     PINMUX_IPSR_GPSR(IP4_11_8,      DU_VSYNC),
0751     PINMUX_IPSR_MSEL(IP4_11_8,      VI4_DATA1_B,    SEL_VIN4_1),
0752     PINMUX_IPSR_GPSR(IP4_11_8,      QSTVA_QVS),
0753
0754     PINMUX_IPSR_GPSR(IP4_15_12,     A12),
0755     PINMUX_IPSR_MSEL(IP4_15_12,     RX5_A,      SEL_SCIF5_0),
0756     PINMUX_IPSR_GPSR(IP4_15_12,     MSIOF2_SS2_B),
0757     PINMUX_IPSR_GPSR(IP4_15_12,     VI4_DATA17),
0758     PINMUX_IPSR_MSEL(IP4_15_12,     VI5_DATA3_A,    SEL_VIN5_0),
0759     PINMUX_IPSR_GPSR(IP4_15_12,     DU_DG6),
0760     PINMUX_IPSR_GPSR(IP4_15_12,     LCDOUT14),
0761
0762     PINMUX_IPSR_GPSR(IP4_19_16,     A13),
0763     PINMUX_IPSR_MSEL(IP4_19_16,     SCK5_A,     SEL_SCIF5_0),
0764     PINMUX_IPSR_MSEL(IP4_19_16,     MSIOF2_SCK_B,   SEL_MSIOF2_1),
0765     PINMUX_IPSR_GPSR(IP4_19_16,     VI4_DATA14),
0766     PINMUX_IPSR_MSEL(IP4_19_16,     HRX4_D,     SEL_HSCIF4_3),
0767     PINMUX_IPSR_GPSR(IP4_19_16,     DU_DB2),
0768     PINMUX_IPSR_GPSR(IP4_19_16,     LCDOUT2),
0769
0770     PINMUX_IPSR_GPSR(IP4_23_20,     A14),
0771     PINMUX_IPSR_GPSR(IP4_23_20,     MSIOF1_SS1),
0772     PINMUX_IPSR_MSEL(IP4_23_20,     MSIOF2_RXD_B,   SEL_MSIOF2_1),
0773     PINMUX_IPSR_GPSR(IP4_23_20,     VI4_DATA15),
0774     PINMUX_IPSR_GPSR(IP4_23_20,     HTX4_D),
0775     PINMUX_IPSR_GPSR(IP4_23_20,     DU_DB3),
0776     PINMUX_IPSR_GPSR(IP4_23_20,     LCDOUT3),
0777
0778     PINMUX_IPSR_GPSR(IP4_27_24,     A15),
0779     PINMUX_IPSR_GPSR(IP4_27_24,     MSIOF1_SS2),
0780     PINMUX_IPSR_GPSR(IP4_27_24,     MSIOF2_TXD_B),
0781     PINMUX_IPSR_GPSR(IP4_27_24,     VI4_DATA18),
0782     PINMUX_IPSR_MSEL(IP4_27_24,     VI5_DATA4_A,    SEL_VIN5_0),
0783     PINMUX_IPSR_GPSR(IP4_27_24,     DU_DB4),
0784     PINMUX_IPSR_GPSR(IP4_27_24,     LCDOUT4),
0785
0786     PINMUX_IPSR_GPSR(IP4_31_28,     A16),
0787     PINMUX_IPSR_GPSR(IP4_31_28,     MSIOF1_SYNC),
0788     PINMUX_IPSR_GPSR(IP4_31_28,     MSIOF2_SS1_B),
0789     PINMUX_IPSR_GPSR(IP4_31_28,     VI4_DATA19),
0790     PINMUX_IPSR_MSEL(IP4_31_28,     VI5_DATA5_A,    SEL_VIN5_0),
0791     PINMUX_IPSR_GPSR(IP4_31_28,     DU_DB5),
0792     PINMUX_IPSR_GPSR(IP4_31_28,     LCDOUT5),
0793
0794     /* IPSR5 */
0795     PINMUX_IPSR_GPSR(IP5_3_0,       A17),
0796     PINMUX_IPSR_GPSR(IP5_3_0,       MSIOF1_RXD),
0797     PINMUX_IPSR_GPSR(IP5_3_0,       VI4_DATA20),
0798     PINMUX_IPSR_MSEL(IP5_3_0,       VI5_DATA6_A,    SEL_VIN5_0),
0799     PINMUX_IPSR_GPSR(IP5_3_0,       DU_DB6),
0800     PINMUX_IPSR_GPSR(IP5_3_0,       LCDOUT6),
0801
0802     PINMUX_IPSR_GPSR(IP5_7_4,       A18),
0803     PINMUX_IPSR_GPSR(IP5_7_4,       MSIOF1_TXD),
0804     PINMUX_IPSR_GPSR(IP5_7_4,       VI4_DATA21),
0805     PINMUX_IPSR_MSEL(IP5_7_4,       VI5_DATA7_A,    SEL_VIN5_0),
0806     PINMUX_IPSR_GPSR(IP5_7_4,       DU_DB0),
0807     PINMUX_IPSR_MSEL(IP5_7_4,       HRX4_E,     SEL_HSCIF4_4),
0808     PINMUX_IPSR_GPSR(IP5_7_4,       LCDOUT0),
0809
0810     PINMUX_IPSR_GPSR(IP5_11_8,      A19),
0811     PINMUX_IPSR_GPSR(IP5_11_8,      MSIOF1_SCK),
0812     PINMUX_IPSR_GPSR(IP5_11_8,      VI4_DATA22),
0813     PINMUX_IPSR_MSEL(IP5_11_8,      VI5_DATA2_A,    SEL_VIN5_0),
0814     PINMUX_IPSR_GPSR(IP5_11_8,      DU_DB1),
0815     PINMUX_IPSR_GPSR(IP5_11_8,      HTX4_E),
0816     PINMUX_IPSR_GPSR(IP5_11_8,      LCDOUT1),
0817
0818     PINMUX_IPSR_GPSR(IP5_15_12,     CS0_N),
0819     PINMUX_IPSR_GPSR(IP5_15_12,     SCL5),
0820     PINMUX_IPSR_GPSR(IP5_15_12,     DU_DR0),
0821     PINMUX_IPSR_MSEL(IP5_15_12,     VI4_DATA2_B,    SEL_VIN4_1),
0822     PINMUX_IPSR_GPSR(IP5_15_12,     LCDOUT16),
0823
0824     PINMUX_IPSR_GPSR(IP5_19_16,     WE0_N),
0825     PINMUX_IPSR_GPSR(IP5_19_16,     SDA5),
0826     PINMUX_IPSR_GPSR(IP5_19_16,     DU_DR1),
0827     PINMUX_IPSR_MSEL(IP5_19_16,     VI4_DATA3_B,    SEL_VIN4_1),
0828     PINMUX_IPSR_GPSR(IP5_19_16,     LCDOUT17),
0829
0830     PINMUX_IPSR_GPSR(IP5_23_20,     D0),
0831     PINMUX_IPSR_MSEL(IP5_23_20,     MSIOF3_SCK_A,   SEL_MSIOF3_0),
0832     PINMUX_IPSR_GPSR(IP5_23_20,     DU_DR2),
0833     PINMUX_IPSR_MSEL(IP5_23_20,     CTS4_N_C,   SEL_SCIF4_2),
0834     PINMUX_IPSR_GPSR(IP5_23_20,     LCDOUT18),
0835
0836     PINMUX_IPSR_GPSR(IP5_27_24,     D1),
0837     PINMUX_IPSR_MSEL(IP5_27_24,     MSIOF3_SYNC_A,  SEL_MSIOF3_0),
0838     PINMUX_IPSR_MSEL(IP5_27_24,     SCK3_A,     SEL_SCIF3_0),
0839     PINMUX_IPSR_GPSR(IP5_27_24,     VI4_DATA23),
0840     PINMUX_IPSR_MSEL(IP5_27_24,     VI5_CLKENB_A,   SEL_VIN5_0),
0841     PINMUX_IPSR_GPSR(IP5_27_24,     DU_DB7),
0842     PINMUX_IPSR_MSEL(IP5_27_24,     RTS4_N_C,   SEL_SCIF4_2),
0843     PINMUX_IPSR_GPSR(IP5_27_24,     LCDOUT7),
0844
0845     PINMUX_IPSR_GPSR(IP5_31_28,     D2),
0846     PINMUX_IPSR_MSEL(IP5_31_28,     MSIOF3_RXD_A,   SEL_MSIOF3_0),
0847     PINMUX_IPSR_MSEL(IP5_31_28,     RX5_C,      SEL_SCIF5_2),
0848     PINMUX_IPSR_MSEL(IP5_31_28,     VI5_DATA14_A,   SEL_VIN5_0),
0849     PINMUX_IPSR_GPSR(IP5_31_28,     DU_DR3),
0850     PINMUX_IPSR_MSEL(IP5_31_28,     RX4_C,      SEL_SCIF4_2),
0851     PINMUX_IPSR_GPSR(IP5_31_28,     LCDOUT19),
0852
0853     /* IPSR6 */
0854     PINMUX_IPSR_GPSR(IP6_3_0,       D3),
0855     PINMUX_IPSR_GPSR(IP6_3_0,       MSIOF3_TXD_A),
0856     PINMUX_IPSR_GPSR(IP6_3_0,       TX5_C),
0857     PINMUX_IPSR_MSEL(IP6_3_0,       VI5_DATA15_A,   SEL_VIN5_0),
0858     PINMUX_IPSR_GPSR(IP6_3_0,       DU_DR4),
0859     PINMUX_IPSR_GPSR(IP6_3_0,       TX4_C),
0860     PINMUX_IPSR_GPSR(IP6_3_0,       LCDOUT20),
0861
0862     PINMUX_IPSR_GPSR(IP6_7_4,       D4),
0863     PINMUX_IPSR_GPSR(IP6_7_4,       CANFD1_TX),
0864     PINMUX_IPSR_MSEL(IP6_7_4,       HSCK3_B,    SEL_HSCIF3_1),
0865     PINMUX_IPSR_GPSR(IP6_7_4,       CAN1_TX),
0866     PINMUX_IPSR_MSEL(IP6_7_4,       RTS3_N_A,   SEL_SCIF3_0),
0867     PINMUX_IPSR_GPSR(IP6_7_4,       MSIOF3_SS2_A),
0868     PINMUX_IPSR_MSEL(IP6_7_4,       VI5_DATA1_B,    SEL_VIN5_1),
0869
0870     PINMUX_IPSR_GPSR(IP6_11_8,      D5),
0871     PINMUX_IPSR_MSEL(IP6_11_8,      RX3_A,      SEL_SCIF3_0),
0872     PINMUX_IPSR_MSEL(IP6_11_8,      HRX3_B,     SEL_HSCIF3_1),
0873     PINMUX_IPSR_GPSR(IP6_11_8,      DU_DR5),
0874     PINMUX_IPSR_MSEL(IP6_11_8,      VI4_DATA4_B,    SEL_VIN4_1),
0875     PINMUX_IPSR_GPSR(IP6_11_8,      LCDOUT21),
0876
0877     PINMUX_IPSR_GPSR(IP6_15_12,     D6),
0878     PINMUX_IPSR_GPSR(IP6_15_12,     TX3_A),
0879     PINMUX_IPSR_GPSR(IP6_15_12,     HTX3_B),
0880     PINMUX_IPSR_GPSR(IP6_15_12,     DU_DR6),
0881     PINMUX_IPSR_MSEL(IP6_15_12,     VI4_DATA5_B,    SEL_VIN4_1),
0882     PINMUX_IPSR_GPSR(IP6_15_12,     LCDOUT22),
0883
0884     PINMUX_IPSR_GPSR(IP6_19_16,     D7),
0885     PINMUX_IPSR_GPSR(IP6_19_16,     CANFD1_RX),
0886     PINMUX_IPSR_GPSR(IP6_19_16,     IRQ5),
0887     PINMUX_IPSR_GPSR(IP6_19_16,     CAN1_RX),
0888     PINMUX_IPSR_MSEL(IP6_19_16,     CTS3_N_A,   SEL_SCIF3_0),
0889     PINMUX_IPSR_MSEL(IP6_19_16,     VI5_DATA2_B,    SEL_VIN5_1),
0890
0891     PINMUX_IPSR_GPSR(IP6_23_20,     D8),
0892     PINMUX_IPSR_MSEL(IP6_23_20,     MSIOF2_SCK_A,   SEL_MSIOF2_0),
0893     PINMUX_IPSR_MSEL(IP6_23_20,     SCK4_B,     SEL_SCIF4_1),
0894     PINMUX_IPSR_MSEL(IP6_23_20,     VI5_DATA12_A,   SEL_VIN5_0),
0895     PINMUX_IPSR_GPSR(IP6_23_20,     DU_DR7),
0896     PINMUX_IPSR_MSEL(IP6_23_20,     RIF3_CLK_B, SEL_DRIF3_1),
0897     PINMUX_IPSR_MSEL(IP6_23_20,     HCTS3_N_E,  SEL_HSCIF3_4),
0898     PINMUX_IPSR_GPSR(IP6_23_20,     LCDOUT23),
0899
0900     PINMUX_IPSR_GPSR(IP6_27_24,     D9),
0901     PINMUX_IPSR_MSEL(IP6_27_24,     MSIOF2_SYNC_A,  SEL_MSIOF2_0),
0902     PINMUX_IPSR_MSEL(IP6_27_24,     VI5_DATA10_A,   SEL_VIN5_0),
0903     PINMUX_IPSR_GPSR(IP6_27_24,     DU_DG0),
0904     PINMUX_IPSR_MSEL(IP6_27_24,     RIF3_SYNC_B,    SEL_DRIF3_1),
0905     PINMUX_IPSR_MSEL(IP6_27_24,     HRX3_E,     SEL_HSCIF3_4),
0906     PINMUX_IPSR_GPSR(IP6_27_24,     LCDOUT8),
0907
0908     PINMUX_IPSR_GPSR(IP6_31_28,     D10),
0909     PINMUX_IPSR_MSEL(IP6_31_28,     MSIOF2_RXD_A,   SEL_MSIOF2_0),
0910     PINMUX_IPSR_MSEL(IP6_31_28,     VI5_DATA13_A,   SEL_VIN5_0),
0911     PINMUX_IPSR_GPSR(IP6_31_28,     DU_DG1),
0912     PINMUX_IPSR_MSEL(IP6_31_28,     RIF3_D0_B,  SEL_DRIF3_1),
0913     PINMUX_IPSR_GPSR(IP6_31_28,     HTX3_E),
0914     PINMUX_IPSR_GPSR(IP6_31_28,     LCDOUT9),
0915
0916     /* IPSR7 */
0917     PINMUX_IPSR_GPSR(IP7_3_0,       D11),
0918     PINMUX_IPSR_GPSR(IP7_3_0,       MSIOF2_TXD_A),
0919     PINMUX_IPSR_MSEL(IP7_3_0,       VI5_DATA11_A,   SEL_VIN5_0),
0920     PINMUX_IPSR_GPSR(IP7_3_0,       DU_DG2),
0921     PINMUX_IPSR_MSEL(IP7_3_0,       RIF3_D1_B,  SEL_DRIF3_1),
0922     PINMUX_IPSR_MSEL(IP7_3_0,       HRTS3_N_E,  SEL_HSCIF3_4),
0923     PINMUX_IPSR_GPSR(IP7_3_0,       LCDOUT10),
0924
0925     PINMUX_IPSR_GPSR(IP7_7_4,       D12),
0926     PINMUX_IPSR_GPSR(IP7_7_4,       CANFD0_TX),
0927     PINMUX_IPSR_GPSR(IP7_7_4,       TX4_B),
0928     PINMUX_IPSR_GPSR(IP7_7_4,       CAN0_TX),
0929     PINMUX_IPSR_MSEL(IP7_7_4,       VI5_DATA8_A,    SEL_VIN5_0),
0930     PINMUX_IPSR_MSEL(IP7_7_4,       VI5_DATA3_B,    SEL_VIN5_1),
0931
0932     PINMUX_IPSR_GPSR(IP7_11_8,      D13),
0933     PINMUX_IPSR_GPSR(IP7_11_8,      CANFD0_RX),
0934     PINMUX_IPSR_MSEL(IP7_11_8,      RX4_B,      SEL_SCIF4_1),
0935     PINMUX_IPSR_GPSR(IP7_11_8,      CAN0_RX),
0936     PINMUX_IPSR_MSEL(IP7_11_8,      VI5_DATA9_A,    SEL_VIN5_0),
0937     PINMUX_IPSR_MSEL(IP7_11_8,      SCL7_B,     SEL_I2C7_1),
0938     PINMUX_IPSR_MSEL(IP7_11_8,      VI5_DATA4_B,    SEL_VIN5_1),
0939
0940     PINMUX_IPSR_GPSR(IP7_15_12,     D14),
0941     PINMUX_IPSR_GPSR(IP7_15_12,     CAN_CLK),
0942     PINMUX_IPSR_MSEL(IP7_15_12,     HRX3_A,     SEL_HSCIF3_0),
0943     PINMUX_IPSR_GPSR(IP7_15_12,     MSIOF2_SS2_A),
0944     PINMUX_IPSR_MSEL(IP7_15_12,     SDA7_B,     SEL_I2C7_1),
0945     PINMUX_IPSR_MSEL(IP7_15_12,     VI5_DATA5_B,    SEL_VIN5_1),
0946
0947     PINMUX_IPSR_GPSR(IP7_19_16,     D15),
0948     PINMUX_IPSR_GPSR(IP7_19_16,     MSIOF2_SS1_A),
0949     PINMUX_IPSR_GPSR(IP7_19_16,     HTX3_A),
0950     PINMUX_IPSR_GPSR(IP7_19_16,     MSIOF3_SS1_A),
0951     PINMUX_IPSR_GPSR(IP7_19_16,     DU_DG3),
0952     PINMUX_IPSR_GPSR(IP7_19_16,     LCDOUT11),
0953
0954     PINMUX_IPSR_GPSR(IP7_23_20,     SCL4),
0955     PINMUX_IPSR_GPSR(IP7_23_20,     CS1_N_A26),
0956     PINMUX_IPSR_GPSR(IP7_23_20,     DU_DOTCLKIN0),
0957     PINMUX_IPSR_MSEL(IP7_23_20,     VI4_DATA6_B,    SEL_VIN4_1),
0958     PINMUX_IPSR_MSEL(IP7_23_20,     VI5_DATA6_B,    SEL_VIN5_1),
0959     PINMUX_IPSR_GPSR(IP7_23_20,     QCLK),
0960
0961     PINMUX_IPSR_GPSR(IP7_27_24,     SDA4),
0962     PINMUX_IPSR_GPSR(IP7_27_24,     WE1_N),
0963     PINMUX_IPSR_MSEL(IP7_27_24,     VI4_DATA7_B,    SEL_VIN4_1),
0964     PINMUX_IPSR_MSEL(IP7_27_24,     VI5_DATA7_B,    SEL_VIN5_1),
0965     PINMUX_IPSR_GPSR(IP7_27_24,     QPOLB),
0966
0967     PINMUX_IPSR_GPSR(IP7_31_28,     SD0_CLK),
0968     PINMUX_IPSR_GPSR(IP7_31_28,     NFDATA8),
0969     PINMUX_IPSR_MSEL(IP7_31_28,     SCL1_C,     SEL_I2C1_2),
0970     PINMUX_IPSR_MSEL(IP7_31_28,     HSCK1_B,    SEL_HSCIF1_1),
0971     PINMUX_IPSR_MSEL(IP7_31_28,     SDA2_E,     SEL_I2C2_4),
0972     PINMUX_IPSR_MSEL(IP7_31_28,     FMCLK_B,    SEL_FM_1),
0973
0974     /* IPSR8 */
0975     PINMUX_IPSR_GPSR(IP8_3_0,       SD0_CMD),
0976     PINMUX_IPSR_GPSR(IP8_3_0,       NFDATA9),
0977     PINMUX_IPSR_MSEL(IP8_3_0,       HRX1_B,     SEL_HSCIF1_1),
0978     PINMUX_IPSR_MSEL(IP8_3_0,       SPEEDIN_B,  SEL_SPEED_PULSE_IF_1),
0979
0980     PINMUX_IPSR_GPSR(IP8_7_4,       SD0_DAT0),
0981     PINMUX_IPSR_GPSR(IP8_7_4,       NFDATA10),
0982     PINMUX_IPSR_GPSR(IP8_7_4,       HTX1_B),
0983     PINMUX_IPSR_MSEL(IP8_7_4,       REMOCON_B,  SEL_REMOCON_1),
0984
0985     PINMUX_IPSR_GPSR(IP8_11_8,      SD0_DAT1),
0986     PINMUX_IPSR_GPSR(IP8_11_8,      NFDATA11),
0987     PINMUX_IPSR_MSEL(IP8_11_8,      SDA2_C,     SEL_I2C2_2),
0988     PINMUX_IPSR_MSEL(IP8_11_8,      HCTS1_N_B,  SEL_HSCIF1_1),
0989     PINMUX_IPSR_MSEL(IP8_11_8,      FMIN_B,     SEL_FM_1),
0990
0991     PINMUX_IPSR_GPSR(IP8_15_12,     SD0_DAT2),
0992     PINMUX_IPSR_GPSR(IP8_15_12,     NFDATA12),
0993     PINMUX_IPSR_MSEL(IP8_15_12,     SCL2_C,     SEL_I2C2_2),
0994     PINMUX_IPSR_MSEL(IP8_15_12,     HRTS1_N_B,  SEL_HSCIF1_1),
0995     PINMUX_IPSR_GPSR(IP8_15_12,     BPFCLK_B),
0996
0997     PINMUX_IPSR_GPSR(IP8_19_16,     SD0_DAT3),
0998     PINMUX_IPSR_GPSR(IP8_19_16,     NFDATA13),
0999     PINMUX_IPSR_MSEL(IP8_19_16,     SDA1_C,     SEL_I2C1_2),
1000     PINMUX_IPSR_MSEL(IP8_19_16,     SCL2_E,     SEL_I2C2_4),
1001     PINMUX_IPSR_MSEL(IP8_19_16,     SPEEDIN_C,  SEL_SPEED_PULSE_IF_2),
1002     PINMUX_IPSR_MSEL(IP8_19_16,     REMOCON_C,  SEL_REMOCON_2),
1003
1004     PINMUX_IPSR_GPSR(IP8_23_20,     SD1_CLK),
1005     PINMUX_IPSR_MSEL(IP8_23_20,     NFDATA14_B, SEL_NDF_1),
1006
1007     PINMUX_IPSR_GPSR(IP8_27_24,     SD1_CMD),
1008     PINMUX_IPSR_MSEL(IP8_27_24,     NFDATA15_B, SEL_NDF_1),
1009
1010     PINMUX_IPSR_GPSR(IP8_31_28,     SD1_DAT0),
1011     PINMUX_IPSR_MSEL(IP8_31_28,     NFWP_N_B,   SEL_NDF_1),
1012
1013     /* IPSR9 */
1014     PINMUX_IPSR_GPSR(IP9_3_0,       SD1_DAT1),
1015     PINMUX_IPSR_MSEL(IP9_3_0,       NFCE_N_B,   SEL_NDF_1),
1016
1017     PINMUX_IPSR_GPSR(IP9_7_4,       SD1_DAT2),
1018     PINMUX_IPSR_MSEL(IP9_7_4,       NFALE_B,    SEL_NDF_1),
1019
1020     PINMUX_IPSR_GPSR(IP9_11_8,      SD1_DAT3),
1021     PINMUX_IPSR_MSEL(IP9_11_8,      NFRB_N_B,   SEL_NDF_1),
1022
1023     PINMUX_IPSR_GPSR(IP9_15_12,     SD3_CLK),
1024     PINMUX_IPSR_GPSR(IP9_15_12,     NFWE_N),
1025
1026     PINMUX_IPSR_GPSR(IP9_19_16,     SD3_CMD),
1027     PINMUX_IPSR_GPSR(IP9_19_16,     NFRE_N),
1028
1029     PINMUX_IPSR_GPSR(IP9_23_20,     SD3_DAT0),
1030     PINMUX_IPSR_GPSR(IP9_23_20,     NFDATA0),
1031
1032     PINMUX_IPSR_GPSR(IP9_27_24,     SD3_DAT1),
1033     PINMUX_IPSR_GPSR(IP9_27_24,     NFDATA1),
1034
1035     PINMUX_IPSR_GPSR(IP9_31_28,     SD3_DAT2),
1036     PINMUX_IPSR_GPSR(IP9_31_28,     NFDATA2),
1037
1038     /* IPSR10 */
1039     PINMUX_IPSR_GPSR(IP10_3_0,      SD3_DAT3),
1040     PINMUX_IPSR_GPSR(IP10_3_0,      NFDATA3),
1041
1042     PINMUX_IPSR_GPSR(IP10_7_4,      SD3_DAT4),
1043     PINMUX_IPSR_GPSR(IP10_7_4,      NFDATA4),
1044
1045     PINMUX_IPSR_GPSR(IP10_11_8,     SD3_DAT5),
1046     PINMUX_IPSR_GPSR(IP10_11_8,     NFDATA5),
1047
1048     PINMUX_IPSR_GPSR(IP10_15_12,        SD3_DAT6),
1049     PINMUX_IPSR_GPSR(IP10_15_12,        NFDATA6),
1050
1051     PINMUX_IPSR_GPSR(IP10_19_16,        SD3_DAT7),
1052     PINMUX_IPSR_GPSR(IP10_19_16,        NFDATA7),
1053
1054     PINMUX_IPSR_GPSR(IP10_23_20,        SD3_DS),
1055     PINMUX_IPSR_GPSR(IP10_23_20,        NFCLE),
1056
1057     PINMUX_IPSR_GPSR(IP10_27_24,        SD0_CD),
1058     PINMUX_IPSR_MSEL(IP10_27_24,        NFALE_A,    SEL_NDF_0),
1059     PINMUX_IPSR_GPSR(IP10_27_24,        SD3_CD),
1060     PINMUX_IPSR_MSEL(IP10_27_24,        RIF0_CLK_B, SEL_DRIF0_1),
1061     PINMUX_IPSR_MSEL(IP10_27_24,        SCL2_B,     SEL_I2C2_1),
1062     PINMUX_IPSR_MSEL(IP10_27_24,        TCLK1_A,    SEL_TIMER_TMU_0),
1063     PINMUX_IPSR_MSEL(IP10_27_24,        SSI_SCK2_B, SEL_SSI2_1),
1064     PINMUX_IPSR_GPSR(IP10_27_24,        TS_SCK0),
1065
1066     PINMUX_IPSR_GPSR(IP10_31_28,        SD0_WP),
1067     PINMUX_IPSR_MSEL(IP10_31_28,        NFRB_N_A,   SEL_NDF_0),
1068     PINMUX_IPSR_GPSR(IP10_31_28,        SD3_WP),
1069     PINMUX_IPSR_MSEL(IP10_31_28,        RIF0_D0_B,  SEL_DRIF0_1),
1070     PINMUX_IPSR_MSEL(IP10_31_28,        SDA2_B,     SEL_I2C2_1),
1071     PINMUX_IPSR_MSEL(IP10_31_28,        TCLK2_A,    SEL_TIMER_TMU_0),
1072     PINMUX_IPSR_MSEL(IP10_31_28,        SSI_WS2_B,  SEL_SSI2_1),
1073     PINMUX_IPSR_GPSR(IP10_31_28,        TS_SDAT0),
1074
1075     /* IPSR11 */
1076     PINMUX_IPSR_GPSR(IP11_3_0,      SD1_CD),
1077     PINMUX_IPSR_MSEL(IP11_3_0,      NFCE_N_A,   SEL_NDF_0),
1078     PINMUX_IPSR_GPSR(IP11_3_0,      SSI_SCK1),
1079     PINMUX_IPSR_MSEL(IP11_3_0,      RIF0_D1_B,  SEL_DRIF0_1),
1080     PINMUX_IPSR_GPSR(IP11_3_0,      TS_SDEN0),
1081
1082     PINMUX_IPSR_GPSR(IP11_7_4,      SD1_WP),
1083     PINMUX_IPSR_MSEL(IP11_7_4,      NFWP_N_A,   SEL_NDF_0),
1084     PINMUX_IPSR_GPSR(IP11_7_4,      SSI_WS1),
1085     PINMUX_IPSR_MSEL(IP11_7_4,      RIF0_SYNC_B,    SEL_DRIF0_1),
1086     PINMUX_IPSR_GPSR(IP11_7_4,      TS_SPSYNC0),
1087
1088     PINMUX_IPSR_MSEL(IP11_11_8,     RX0_A,      SEL_SCIF0_0),
1089     PINMUX_IPSR_MSEL(IP11_11_8,     HRX1_A,     SEL_HSCIF1_0),
1090     PINMUX_IPSR_MSEL(IP11_11_8,     SSI_SCK2_A, SEL_SSI2_0),
1091     PINMUX_IPSR_GPSR(IP11_11_8,     RIF1_SYNC),
1092     PINMUX_IPSR_GPSR(IP11_11_8,     TS_SCK1),
1093
1094     PINMUX_IPSR_MSEL(IP11_15_12,        TX0_A,      SEL_SCIF0_0),
1095     PINMUX_IPSR_GPSR(IP11_15_12,        HTX1_A),
1096     PINMUX_IPSR_MSEL(IP11_15_12,        SSI_WS2_A,  SEL_SSI2_0),
1097     PINMUX_IPSR_GPSR(IP11_15_12,        RIF1_D0),
1098     PINMUX_IPSR_GPSR(IP11_15_12,        TS_SDAT1),
1099
1100     PINMUX_IPSR_MSEL(IP11_19_16,        CTS0_N_A,   SEL_SCIF0_0),
1101     PINMUX_IPSR_MSEL(IP11_19_16,        NFDATA14_A, SEL_NDF_0),
1102     PINMUX_IPSR_GPSR(IP11_19_16,        AUDIO_CLKOUT_A),
1103     PINMUX_IPSR_GPSR(IP11_19_16,        RIF1_D1),
1104     PINMUX_IPSR_MSEL(IP11_19_16,        SCIF_CLK_A, SEL_SCIF_0),
1105     PINMUX_IPSR_MSEL(IP11_19_16,        FMCLK_A,    SEL_FM_0),
1106
1107     PINMUX_IPSR_MSEL(IP11_23_20,        RTS0_N_A,   SEL_SCIF0_0),
1108     PINMUX_IPSR_MSEL(IP11_23_20,        NFDATA15_A, SEL_NDF_0),
1109     PINMUX_IPSR_GPSR(IP11_23_20,        AUDIO_CLKOUT1_A),
1110     PINMUX_IPSR_GPSR(IP11_23_20,        RIF1_CLK),
1111     PINMUX_IPSR_MSEL(IP11_23_20,        SCL2_A,     SEL_I2C2_0),
1112     PINMUX_IPSR_MSEL(IP11_23_20,        FMIN_A,     SEL_FM_0),
1113
1114     PINMUX_IPSR_MSEL(IP11_27_24,        SCK0_A,     SEL_SCIF0_0),
1115     PINMUX_IPSR_MSEL(IP11_27_24,        HSCK1_A,    SEL_HSCIF1_0),
1116     PINMUX_IPSR_GPSR(IP11_27_24,        USB3HS0_ID),
1117     PINMUX_IPSR_GPSR(IP11_27_24,        RTS1_N),
1118     PINMUX_IPSR_MSEL(IP11_27_24,        SDA2_A,     SEL_I2C2_0),
1119     PINMUX_IPSR_MSEL(IP11_27_24,        FMCLK_C,    SEL_FM_2),
1120     PINMUX_IPSR_GPSR(IP11_27_24,        USB0_ID),
1121
1122     PINMUX_IPSR_GPSR(IP11_31_28,        RX1),
1123     PINMUX_IPSR_MSEL(IP11_31_28,        HRX2_B,     SEL_HSCIF2_1),
1124     PINMUX_IPSR_MSEL(IP11_31_28,        SSI_SCK9_B, SEL_SSI9_1),
1125     PINMUX_IPSR_GPSR(IP11_31_28,        AUDIO_CLKOUT1_B),
1126
1127     /* IPSR12 */
1128     PINMUX_IPSR_GPSR(IP12_3_0,      TX1),
1129     PINMUX_IPSR_GPSR(IP12_3_0,      HTX2_B),
1130     PINMUX_IPSR_MSEL(IP12_3_0,      SSI_WS9_B,  SEL_SSI9_1),
1131     PINMUX_IPSR_GPSR(IP12_3_0,      AUDIO_CLKOUT3_B),
1132
1133     PINMUX_IPSR_MSEL(IP12_7_4,      SCK2_A,     SEL_SCIF2_0),
1134     PINMUX_IPSR_MSEL(IP12_7_4,      HSCK0_A,    SEL_HSCIF0_0),
1135     PINMUX_IPSR_MSEL(IP12_7_4,      AUDIO_CLKB_A,   SEL_ADGB_0),
1136     PINMUX_IPSR_GPSR(IP12_7_4,      CTS1_N),
1137     PINMUX_IPSR_MSEL(IP12_7_4,      RIF0_CLK_A, SEL_DRIF0_0),
1138     PINMUX_IPSR_MSEL(IP12_7_4,      REMOCON_A,  SEL_REMOCON_0),
1139     PINMUX_IPSR_MSEL(IP12_7_4,      SCIF_CLK_B, SEL_SCIF_1),
1140
1141     PINMUX_IPSR_MSEL(IP12_11_8,     TX2_A,      SEL_SCIF2_0),
1142     PINMUX_IPSR_MSEL(IP12_11_8,     HRX0_A,     SEL_HSCIF0_0),
1143     PINMUX_IPSR_GPSR(IP12_11_8,     AUDIO_CLKOUT2_A),
1144     PINMUX_IPSR_MSEL(IP12_11_8,     SCL1_A,     SEL_I2C1_0),
1145     PINMUX_IPSR_MSEL(IP12_11_8,     FSO_CFE_0_N_A,  SEL_FSO_0),
1146     PINMUX_IPSR_GPSR(IP12_11_8,     TS_SDEN1),
1147
1148     PINMUX_IPSR_MSEL(IP12_15_12,        RX2_A,      SEL_SCIF2_0),
1149     PINMUX_IPSR_GPSR(IP12_15_12,        HTX0_A),
1150     PINMUX_IPSR_GPSR(IP12_15_12,        AUDIO_CLKOUT3_A),
1151     PINMUX_IPSR_MSEL(IP12_15_12,        SDA1_A,     SEL_I2C1_0),
1152     PINMUX_IPSR_MSEL(IP12_15_12,        FSO_CFE_1_N_A,  SEL_FSO_0),
1153     PINMUX_IPSR_GPSR(IP12_15_12,        TS_SPSYNC1),
1154
1155     PINMUX_IPSR_GPSR(IP12_19_16,        MSIOF0_SCK),
1156     PINMUX_IPSR_GPSR(IP12_19_16,        SSI_SCK78),
1157
1158     PINMUX_IPSR_GPSR(IP12_23_20,        MSIOF0_RXD),
1159     PINMUX_IPSR_GPSR(IP12_23_20,        SSI_WS78),
1160     PINMUX_IPSR_MSEL(IP12_23_20,        TX2_B,      SEL_SCIF2_1),
1161
1162     PINMUX_IPSR_GPSR(IP12_27_24,        MSIOF0_TXD),
1163     PINMUX_IPSR_GPSR(IP12_27_24,        SSI_SDATA7),
1164     PINMUX_IPSR_MSEL(IP12_27_24,        RX2_B,      SEL_SCIF2_1),
1165
1166     PINMUX_IPSR_GPSR(IP12_31_28,        MSIOF0_SYNC),
1167     PINMUX_IPSR_GPSR(IP12_31_28,        AUDIO_CLKOUT_B),
1168     PINMUX_IPSR_GPSR(IP12_31_28,        SSI_SDATA8),
1169
1170     /* IPSR13 */
1171     PINMUX_IPSR_GPSR(IP13_3_0,      MSIOF0_SS1),
1172     PINMUX_IPSR_MSEL(IP13_3_0,      HRX2_A,     SEL_HSCIF2_0),
1173     PINMUX_IPSR_GPSR(IP13_3_0,      SSI_SCK4),
1174     PINMUX_IPSR_MSEL(IP13_3_0,      HCTS0_N_A,  SEL_HSCIF0_0),
1175     PINMUX_IPSR_GPSR(IP13_3_0,      BPFCLK_C),
1176     PINMUX_IPSR_MSEL(IP13_3_0,      SPEEDIN_A,  SEL_SPEED_PULSE_IF_0),
1177
1178     PINMUX_IPSR_GPSR(IP13_7_4,      MSIOF0_SS2),
1179     PINMUX_IPSR_GPSR(IP13_7_4,      HTX2_A),
1180     PINMUX_IPSR_GPSR(IP13_7_4,      SSI_WS4),
1181     PINMUX_IPSR_MSEL(IP13_7_4,      HRTS0_N_A,  SEL_HSCIF0_0),
1182     PINMUX_IPSR_MSEL(IP13_7_4,      FMIN_C,     SEL_FM_2),
1183     PINMUX_IPSR_GPSR(IP13_7_4,      BPFCLK_A),
1184
1185     PINMUX_IPSR_GPSR(IP13_11_8,     SSI_SDATA9),
1186     PINMUX_IPSR_MSEL(IP13_11_8,     AUDIO_CLKC_A,   SEL_ADGC_0),
1187     PINMUX_IPSR_GPSR(IP13_11_8,     SCK1),
1188
1189     PINMUX_IPSR_GPSR(IP13_15_12,        MLB_CLK),
1190     PINMUX_IPSR_MSEL(IP13_15_12,        RX0_B,      SEL_SCIF0_1),
1191     PINMUX_IPSR_MSEL(IP13_15_12,        RIF0_D0_A,  SEL_DRIF0_0),
1192     PINMUX_IPSR_MSEL(IP13_15_12,        SCL1_B,     SEL_I2C1_1),
1193     PINMUX_IPSR_MSEL(IP13_15_12,        TCLK1_B,    SEL_TIMER_TMU_1),
1194     PINMUX_IPSR_GPSR(IP13_15_12,        SIM0_RST_A),
1195
1196     PINMUX_IPSR_GPSR(IP13_19_16,        MLB_SIG),
1197     PINMUX_IPSR_MSEL(IP13_19_16,        SCK0_B,     SEL_SCIF0_1),
1198     PINMUX_IPSR_MSEL(IP13_19_16,        RIF0_D1_A,  SEL_DRIF0_0),
1199     PINMUX_IPSR_MSEL(IP13_19_16,        SDA1_B,     SEL_I2C1_1),
1200     PINMUX_IPSR_MSEL(IP13_19_16,        TCLK2_B,    SEL_TIMER_TMU_1),
1201     PINMUX_IPSR_MSEL(IP13_19_16,        SIM0_D_A,   SEL_SIMCARD_0),
1202
1203     PINMUX_IPSR_GPSR(IP13_23_20,        MLB_DAT),
1204     PINMUX_IPSR_MSEL(IP13_23_20,        TX0_B,      SEL_SCIF0_1),
1205     PINMUX_IPSR_MSEL(IP13_23_20,        RIF0_SYNC_A,    SEL_DRIF0_0),
1206     PINMUX_IPSR_GPSR(IP13_23_20,        SIM0_CLK_A),
1207
1208     PINMUX_IPSR_GPSR(IP13_27_24,        SSI_SCK01239),
1209
1210     PINMUX_IPSR_GPSR(IP13_31_28,        SSI_WS01239),
1211
1212     /* IPSR14 */
1213     PINMUX_IPSR_GPSR(IP14_3_0,      SSI_SDATA0),
1214
1215     PINMUX_IPSR_GPSR(IP14_7_4,      SSI_SDATA1),
1216     PINMUX_IPSR_MSEL(IP14_7_4,      AUDIO_CLKC_B,   SEL_ADGC_1),
1217     PINMUX_IPSR_MSEL(IP14_7_4,      PWM0_B,     SEL_PWM0_1),
1218
1219     PINMUX_IPSR_GPSR(IP14_11_8,     SSI_SDATA2),
1220     PINMUX_IPSR_GPSR(IP14_11_8,     AUDIO_CLKOUT2_B),
1221     PINMUX_IPSR_MSEL(IP14_11_8,     SSI_SCK9_A, SEL_SSI9_0),
1222     PINMUX_IPSR_MSEL(IP14_11_8,     PWM1_B,     SEL_PWM1_1),
1223
1224     PINMUX_IPSR_GPSR(IP14_15_12,        SSI_SCK349),
1225     PINMUX_IPSR_MSEL(IP14_15_12,        PWM2_C,     SEL_PWM2_2),
1226
1227     PINMUX_IPSR_GPSR(IP14_19_16,        SSI_WS349),
1228     PINMUX_IPSR_MSEL(IP14_19_16,        PWM3_C,     SEL_PWM3_2),
1229
1230     PINMUX_IPSR_GPSR(IP14_23_20,        SSI_SDATA3),
1231     PINMUX_IPSR_GPSR(IP14_23_20,        AUDIO_CLKOUT1_C),
1232     PINMUX_IPSR_MSEL(IP14_23_20,        AUDIO_CLKB_B,   SEL_ADGB_1),
1233     PINMUX_IPSR_MSEL(IP14_23_20,        PWM4_B,     SEL_PWM4_1),
1234
1235     PINMUX_IPSR_GPSR(IP14_27_24,        SSI_SDATA4),
1236     PINMUX_IPSR_MSEL(IP14_27_24,        SSI_WS9_A,  SEL_SSI9_0),
1237     PINMUX_IPSR_MSEL(IP14_27_24,        PWM5_B,     SEL_PWM5_1),
1238
1239     PINMUX_IPSR_GPSR(IP14_31_28,        SSI_SCK5),
1240     PINMUX_IPSR_MSEL(IP14_31_28,        HRX0_B,     SEL_HSCIF0_1),
1241     PINMUX_IPSR_GPSR(IP14_31_28,        USB0_PWEN_B),
1242     PINMUX_IPSR_MSEL(IP14_31_28,        SCL2_D,     SEL_I2C2_3),
1243     PINMUX_IPSR_MSEL(IP14_31_28,        PWM6_B,     SEL_PWM6_1),
1244
1245     /* IPSR15 */
1246     PINMUX_IPSR_GPSR(IP15_3_0,      SSI_WS5),
1247     PINMUX_IPSR_GPSR(IP15_3_0,      HTX0_B),
1248     PINMUX_IPSR_MSEL(IP15_3_0,      USB0_OVC_B, SEL_USB_20_CH0_1),
1249     PINMUX_IPSR_MSEL(IP15_3_0,      SDA2_D,     SEL_I2C2_3),
1250
1251     PINMUX_IPSR_GPSR(IP15_7_4,      SSI_SDATA5),
1252     PINMUX_IPSR_MSEL(IP15_7_4,      HSCK0_B,    SEL_HSCIF0_1),
1253     PINMUX_IPSR_MSEL(IP15_7_4,      AUDIO_CLKB_C,   SEL_ADGB_2),
1254     PINMUX_IPSR_GPSR(IP15_7_4,      TPU0TO0),
1255
1256     PINMUX_IPSR_GPSR(IP15_11_8,     SSI_SCK6),
1257     PINMUX_IPSR_MSEL(IP15_11_8,     HSCK2_A,    SEL_HSCIF2_0),
1258     PINMUX_IPSR_MSEL(IP15_11_8,     AUDIO_CLKC_C,   SEL_ADGC_2),
1259     PINMUX_IPSR_GPSR(IP15_11_8,     TPU0TO1),
1260     PINMUX_IPSR_MSEL(IP15_11_8,     FSO_CFE_0_N_B,  SEL_FSO_1),
1261     PINMUX_IPSR_GPSR(IP15_11_8,     SIM0_RST_B),
1262
1263     PINMUX_IPSR_GPSR(IP15_15_12,        SSI_WS6),
1264     PINMUX_IPSR_MSEL(IP15_15_12,        HCTS2_N_A,  SEL_HSCIF2_0),
1265     PINMUX_IPSR_GPSR(IP15_15_12,        AUDIO_CLKOUT2_C),
1266     PINMUX_IPSR_GPSR(IP15_15_12,        TPU0TO2),
1267     PINMUX_IPSR_MSEL(IP15_15_12,        SDA1_D,     SEL_I2C1_3),
1268     PINMUX_IPSR_MSEL(IP15_15_12,        FSO_CFE_1_N_B,  SEL_FSO_1),
1269     PINMUX_IPSR_MSEL(IP15_15_12,        SIM0_D_B,   SEL_SIMCARD_1),
1270
1271     PINMUX_IPSR_GPSR(IP15_19_16,        SSI_SDATA6),
1272     PINMUX_IPSR_MSEL(IP15_19_16,        HRTS2_N_A,  SEL_HSCIF2_0),
1273     PINMUX_IPSR_GPSR(IP15_19_16,        AUDIO_CLKOUT3_C),
1274     PINMUX_IPSR_GPSR(IP15_19_16,        TPU0TO3),
1275     PINMUX_IPSR_MSEL(IP15_19_16,        SCL1_D,     SEL_I2C1_3),
1276     PINMUX_IPSR_MSEL(IP15_19_16,        FSO_TOE_N_B,    SEL_FSO_1),
1277     PINMUX_IPSR_GPSR(IP15_19_16,        SIM0_CLK_B),
1278
1279     PINMUX_IPSR_GPSR(IP15_23_20,        AUDIO_CLKA),
1280
1281     PINMUX_IPSR_GPSR(IP15_27_24,        USB30_PWEN),
1282     PINMUX_IPSR_GPSR(IP15_27_24,        USB0_PWEN_A),
1283
1284     PINMUX_IPSR_GPSR(IP15_31_28,        USB30_OVC),
1285     PINMUX_IPSR_MSEL(IP15_31_28,        USB0_OVC_A, SEL_USB_20_CH0_0),
1286
1287 /*
1288  * Static pins can not be muxed between different functions but
1289  * still need mark entries in the pinmux list. Add each static
1290  * pin to the list without an associated function. The sh-pfc
1291  * core will do the right thing and skip trying to mux the pin
1292  * while still applying configuration to it.
1293  */
1294 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1295     PINMUX_STATIC
1296 #undef FM
1297 };
1298
1299 /*
1300  * Pins not associated with a GPIO port.
1301  */
1302 enum {
1303     GP_ASSIGN_LAST(),
1304     NOGP_ALL(),
1305 };
1306
1307 static const struct sh_pfc_pin pinmux_pins[] = {
1308     PINMUX_GPIO_GP_ALL(),
1309     PINMUX_NOGP_ALL(),
1310 };
1311
1312 /* - AUDIO CLOCK ------------------------------------------------------------ */
1313 static const unsigned int audio_clk_a_pins[] = {
1314     /* CLK A */
1315     RCAR_GP_PIN(6, 8),
1316 };
1317
1318 static const unsigned int audio_clk_a_mux[] = {
1319     AUDIO_CLKA_MARK,
1320 };
1321
1322 static const unsigned int audio_clk_b_a_pins[] = {
1323     /* CLK B_A */
1324     RCAR_GP_PIN(5, 7),
1325 };
1326
1327 static const unsigned int audio_clk_b_a_mux[] = {
1328     AUDIO_CLKB_A_MARK,
1329 };
1330
1331 static const unsigned int audio_clk_b_b_pins[] = {
1332     /* CLK B_B */
1333     RCAR_GP_PIN(6, 7),
1334 };
1335
1336 static const unsigned int audio_clk_b_b_mux[] = {
1337     AUDIO_CLKB_B_MARK,
1338 };
1339
1340 static const unsigned int audio_clk_b_c_pins[] = {
1341     /* CLK B_C */
1342     RCAR_GP_PIN(6, 13),
1343 };
1344
1345 static const unsigned int audio_clk_b_c_mux[] = {
1346     AUDIO_CLKB_C_MARK,
1347 };
1348
1349 static const unsigned int audio_clk_c_a_pins[] = {
1350     /* CLK C_A */
1351     RCAR_GP_PIN(5, 16),
1352 };
1353
1354 static const unsigned int audio_clk_c_a_mux[] = {
1355     AUDIO_CLKC_A_MARK,
1356 };
1357
1358 static const unsigned int audio_clk_c_b_pins[] = {
1359     /* CLK C_B */
1360     RCAR_GP_PIN(6, 3),
1361 };
1362
1363 static const unsigned int audio_clk_c_b_mux[] = {
1364     AUDIO_CLKC_B_MARK,
1365 };
1366
1367 static const unsigned int audio_clk_c_c_pins[] = {
1368     /* CLK C_C */
1369     RCAR_GP_PIN(6, 14),
1370 };
1371
1372 static const unsigned int audio_clk_c_c_mux[] = {
1373     AUDIO_CLKC_C_MARK,
1374 };
1375
1376 static const unsigned int audio_clkout_a_pins[] = {
1377     /* CLKOUT_A */
1378     RCAR_GP_PIN(5, 3),
1379 };
1380
1381 static const unsigned int audio_clkout_a_mux[] = {
1382     AUDIO_CLKOUT_A_MARK,
1383 };
1384
1385 static const unsigned int audio_clkout_b_pins[] = {
1386     /* CLKOUT_B */
1387     RCAR_GP_PIN(5, 13),
1388 };
1389
1390 static const unsigned int audio_clkout_b_mux[] = {
1391     AUDIO_CLKOUT_B_MARK,
1392 };
1393
1394 static const unsigned int audio_clkout1_a_pins[] = {
1395     /* CLKOUT1_A */
1396     RCAR_GP_PIN(5, 4),
1397 };
1398
1399 static const unsigned int audio_clkout1_a_mux[] = {
1400     AUDIO_CLKOUT1_A_MARK,
1401 };
1402
1403 static const unsigned int audio_clkout1_b_pins[] = {
1404     /* CLKOUT1_B */
1405     RCAR_GP_PIN(5, 5),
1406 };
1407
1408 static const unsigned int audio_clkout1_b_mux[] = {
1409     AUDIO_CLKOUT1_B_MARK,
1410 };
1411
1412 static const unsigned int audio_clkout1_c_pins[] = {
1413     /* CLKOUT1_C */
1414     RCAR_GP_PIN(6, 7),
1415 };
1416
1417 static const unsigned int audio_clkout1_c_mux[] = {
1418     AUDIO_CLKOUT1_C_MARK,
1419 };
1420
1421 static const unsigned int audio_clkout2_a_pins[] = {
1422     /* CLKOUT2_A */
1423     RCAR_GP_PIN(5, 8),
1424 };
1425
1426 static const unsigned int audio_clkout2_a_mux[] = {
1427     AUDIO_CLKOUT2_A_MARK,
1428 };
1429
1430 static const unsigned int audio_clkout2_b_pins[] = {
1431     /* CLKOUT2_B */
1432     RCAR_GP_PIN(6, 4),
1433 };
1434
1435 static const unsigned int audio_clkout2_b_mux[] = {
1436     AUDIO_CLKOUT2_B_MARK,
1437 };
1438
1439 static const unsigned int audio_clkout2_c_pins[] = {
1440     /* CLKOUT2_C */
1441     RCAR_GP_PIN(6, 15),
1442 };
1443
1444 static const unsigned int audio_clkout2_c_mux[] = {
1445     AUDIO_CLKOUT2_C_MARK,
1446 };
1447
1448 static const unsigned int audio_clkout3_a_pins[] = {
1449     /* CLKOUT3_A */
1450     RCAR_GP_PIN(5, 9),
1451 };
1452
1453 static const unsigned int audio_clkout3_a_mux[] = {
1454     AUDIO_CLKOUT3_A_MARK,
1455 };
1456
1457 static const unsigned int audio_clkout3_b_pins[] = {
1458     /* CLKOUT3_B */
1459     RCAR_GP_PIN(5, 6),
1460 };
1461
1462 static const unsigned int audio_clkout3_b_mux[] = {
1463     AUDIO_CLKOUT3_B_MARK,
1464 };
1465
1466 static const unsigned int audio_clkout3_c_pins[] = {
1467     /* CLKOUT3_C */
1468     RCAR_GP_PIN(6, 16),
1469 };
1470
1471 static const unsigned int audio_clkout3_c_mux[] = {
1472     AUDIO_CLKOUT3_C_MARK,
1473 };
1474
1475 /* - EtherAVB --------------------------------------------------------------- */
1476 static const unsigned int avb_link_pins[] = {
1477     /* AVB_LINK */
1478     RCAR_GP_PIN(2, 23),
1479 };
1480
1481 static const unsigned int avb_link_mux[] = {
1482     AVB_LINK_MARK,
1483 };
1484
1485 static const unsigned int avb_magic_pins[] = {
1486     /* AVB_MAGIC */
1487     RCAR_GP_PIN(2, 22),
1488 };
1489
1490 static const unsigned int avb_magic_mux[] = {
1491     AVB_MAGIC_MARK,
1492 };
1493
1494 static const unsigned int avb_phy_int_pins[] = {
1495     /* AVB_PHY_INT */
1496     RCAR_GP_PIN(2, 21),
1497 };
1498
1499 static const unsigned int avb_phy_int_mux[] = {
1500     AVB_PHY_INT_MARK,
1501 };
1502
1503 static const unsigned int avb_mii_pins[] = {
1504     /*
1505      * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1506      * AVB_RD1, AVB_RD2, AVB_RD3,
1507      * AVB_TXCREFCLK
1508      */
1509     RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
1510     RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
1511     RCAR_GP_PIN(2, 20),
1512 };
1513
1514 static const unsigned int avb_mii_mux[] = {
1515     AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1516     AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1517     AVB_TXCREFCLK_MARK,
1518 };
1519
1520 static const unsigned int avb_avtp_pps_pins[] = {
1521     /* AVB_AVTP_PPS */
1522     RCAR_GP_PIN(1, 2),
1523 };
1524
1525 static const unsigned int avb_avtp_pps_mux[] = {
1526     AVB_AVTP_PPS_MARK,
1527 };
1528
1529 static const unsigned int avb_avtp_match_pins[] = {
1530     /* AVB_AVTP_MATCH */
1531     RCAR_GP_PIN(2, 24),
1532 };
1533
1534 static const unsigned int avb_avtp_match_mux[] = {
1535     AVB_AVTP_MATCH_MARK,
1536 };
1537
1538 static const unsigned int avb_avtp_capture_pins[] = {
1539     /* AVB_AVTP_CAPTURE */
1540     RCAR_GP_PIN(2, 25),
1541 };
1542
1543 static const unsigned int avb_avtp_capture_mux[] = {
1544     AVB_AVTP_CAPTURE_MARK,
1545 };
1546
1547 /* - CAN ------------------------------------------------------------------ */
1548 static const unsigned int can0_data_pins[] = {
1549     /* TX, RX */
1550     RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1551 };
1552
1553 static const unsigned int can0_data_mux[] = {
1554     CAN0_TX_MARK, CAN0_RX_MARK,
1555 };
1556
1557 static const unsigned int can1_data_pins[] = {
1558     /* TX, RX */
1559     RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
1560 };
1561
1562 static const unsigned int can1_data_mux[] = {
1563     CAN1_TX_MARK, CAN1_RX_MARK,
1564 };
1565
1566 /* - CAN Clock -------------------------------------------------------------- */
1567 static const unsigned int can_clk_pins[] = {
1568     /* CLK */
1569     RCAR_GP_PIN(0, 14),
1570 };
1571
1572 static const unsigned int can_clk_mux[] = {
1573     CAN_CLK_MARK,
1574 };
1575
1576 /* - CAN FD --------------------------------------------------------------- */
1577 static const unsigned int canfd0_data_pins[] = {
1578     /* TX, RX */
1579     RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1580 };
1581
1582 static const unsigned int canfd0_data_mux[] = {
1583     CANFD0_TX_MARK, CANFD0_RX_MARK,
1584 };
1585
1586 static const unsigned int canfd1_data_pins[] = {
1587     /* TX, RX */
1588     RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
1589 };
1590
1591 static const unsigned int canfd1_data_mux[] = {
1592     CANFD1_TX_MARK, CANFD1_RX_MARK,
1593 };
1594
1595 #ifdef CONFIG_PINCTRL_PFC_R8A77990
1596 /* - DRIF0 --------------------------------------------------------------- */
1597 static const unsigned int drif0_ctrl_a_pins[] = {
1598     /* CLK, SYNC */
1599     RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 19),
1600 };
1601
1602 static const unsigned int drif0_ctrl_a_mux[] = {
1603     RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1604 };
1605
1606 static const unsigned int drif0_data0_a_pins[] = {
1607     /* D0 */
1608     RCAR_GP_PIN(5, 17),
1609 };
1610
1611 static const unsigned int drif0_data0_a_mux[] = {
1612     RIF0_D0_A_MARK,
1613 };
1614
1615 static const unsigned int drif0_data1_a_pins[] = {
1616     /* D1 */
1617     RCAR_GP_PIN(5, 18),
1618 };
1619
1620 static const unsigned int drif0_data1_a_mux[] = {
1621     RIF0_D1_A_MARK,
1622 };
1623
1624 static const unsigned int drif0_ctrl_b_pins[] = {
1625     /* CLK, SYNC */
1626     RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
1627 };
1628
1629 static const unsigned int drif0_ctrl_b_mux[] = {
1630     RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1631 };
1632
1633 static const unsigned int drif0_data0_b_pins[] = {
1634     /* D0 */
1635     RCAR_GP_PIN(3, 13),
1636 };
1637
1638 static const unsigned int drif0_data0_b_mux[] = {
1639     RIF0_D0_B_MARK,
1640 };
1641
1642 static const unsigned int drif0_data1_b_pins[] = {
1643     /* D1 */
1644     RCAR_GP_PIN(3, 14),
1645 };
1646
1647 static const unsigned int drif0_data1_b_mux[] = {
1648     RIF0_D1_B_MARK,
1649 };
1650
1651 /* - DRIF1 --------------------------------------------------------------- */
1652 static const unsigned int drif1_ctrl_pins[] = {
1653     /* CLK, SYNC */
1654     RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 1),
1655 };
1656
1657 static const unsigned int drif1_ctrl_mux[] = {
1658     RIF1_CLK_MARK, RIF1_SYNC_MARK,
1659 };
1660
1661 static const unsigned int drif1_data0_pins[] = {
1662     /* D0 */
1663     RCAR_GP_PIN(5, 2),
1664 };
1665
1666 static const unsigned int drif1_data0_mux[] = {
1667     RIF1_D0_MARK,
1668 };
1669
1670 static const unsigned int drif1_data1_pins[] = {
1671     /* D1 */
1672     RCAR_GP_PIN(5, 3),
1673 };
1674
1675 static const unsigned int drif1_data1_mux[] = {
1676     RIF1_D1_MARK,
1677 };
1678
1679 /* - DRIF2 --------------------------------------------------------------- */
1680 static const unsigned int drif2_ctrl_a_pins[] = {
1681     /* CLK, SYNC */
1682     RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1683 };
1684
1685 static const unsigned int drif2_ctrl_a_mux[] = {
1686     RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1687 };
1688
1689 static const unsigned int drif2_data0_a_pins[] = {
1690     /* D0 */
1691     RCAR_GP_PIN(2, 8),
1692 };
1693
1694 static const unsigned int drif2_data0_a_mux[] = {
1695     RIF2_D0_A_MARK,
1696 };
1697
1698 static const unsigned int drif2_data1_a_pins[] = {
1699     /* D1 */
1700     RCAR_GP_PIN(2, 9),
1701 };
1702
1703 static const unsigned int drif2_data1_a_mux[] = {
1704     RIF2_D1_A_MARK,
1705 };
1706
1707 static const unsigned int drif2_ctrl_b_pins[] = {
1708     /* CLK, SYNC */
1709     RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
1710 };
1711
1712 static const unsigned int drif2_ctrl_b_mux[] = {
1713     RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1714 };
1715
1716 static const unsigned int drif2_data0_b_pins[] = {
1717     /* D0 */
1718     RCAR_GP_PIN(1, 6),
1719 };
1720
1721 static const unsigned int drif2_data0_b_mux[] = {
1722     RIF2_D0_B_MARK,
1723 };
1724
1725 static const unsigned int drif2_data1_b_pins[] = {
1726     /* D1 */
1727     RCAR_GP_PIN(1, 7),
1728 };
1729
1730 static const unsigned int drif2_data1_b_mux[] = {
1731     RIF2_D1_B_MARK,
1732 };
1733
1734 /* - DRIF3 --------------------------------------------------------------- */
1735 static const unsigned int drif3_ctrl_a_pins[] = {
1736     /* CLK, SYNC */
1737     RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1738 };
1739
1740 static const unsigned int drif3_ctrl_a_mux[] = {
1741     RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1742 };
1743
1744 static const unsigned int drif3_data0_a_pins[] = {
1745     /* D0 */
1746     RCAR_GP_PIN(2, 12),
1747 };
1748
1749 static const unsigned int drif3_data0_a_mux[] = {
1750     RIF3_D0_A_MARK,
1751 };
1752
1753 static const unsigned int drif3_data1_a_pins[] = {
1754     /* D1 */
1755     RCAR_GP_PIN(2, 13),
1756 };
1757
1758 static const unsigned int drif3_data1_a_mux[] = {
1759     RIF3_D1_A_MARK,
1760 };
1761
1762 static const unsigned int drif3_ctrl_b_pins[] = {
1763     /* CLK, SYNC */
1764     RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1765 };
1766
1767 static const unsigned int drif3_ctrl_b_mux[] = {
1768     RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1769 };
1770
1771 static const unsigned int drif3_data0_b_pins[] = {
1772     /* D0 */
1773     RCAR_GP_PIN(0, 10),
1774 };
1775
1776 static const unsigned int drif3_data0_b_mux[] = {
1777     RIF3_D0_B_MARK,
1778 };
1779
1780 static const unsigned int drif3_data1_b_pins[] = {
1781     /* D1 */
1782     RCAR_GP_PIN(0, 11),
1783 };
1784
1785 static const unsigned int drif3_data1_b_mux[] = {
1786     RIF3_D1_B_MARK,
1787 };
1788 #endif /* CONFIG_PINCTRL_PFC_R8A77990 */
1789
1790 /* - DU --------------------------------------------------------------------- */
1791 static const unsigned int du_rgb666_pins[] = {
1792     /* R[7:2], G[7:2], B[7:2] */
1793     RCAR_GP_PIN(0, 8),  RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 5),
1794     RCAR_GP_PIN(0, 3),  RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 0),
1795     RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
1796     RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1797     RCAR_GP_PIN(0, 1),  RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1798     RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1799 };
1800 static const unsigned int du_rgb666_mux[] = {
1801     DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1802     DU_DR3_MARK, DU_DR2_MARK,
1803     DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1804     DU_DG3_MARK, DU_DG2_MARK,
1805     DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1806     DU_DB3_MARK, DU_DB2_MARK,
1807 };
1808 static const unsigned int du_rgb888_pins[] = {
1809     /* R[7:0], G[7:0], B[7:0] */
1810     RCAR_GP_PIN(0, 8),  RCAR_GP_PIN(0, 6),  RCAR_GP_PIN(0, 5),
1811     RCAR_GP_PIN(0, 3),  RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 0),
1812     RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1813     RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
1814     RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
1815     RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
1816     RCAR_GP_PIN(0, 1),  RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1817     RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1818     RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1819 };
1820 static const unsigned int du_rgb888_mux[] = {
1821     DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1822     DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1823     DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1824     DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1825     DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1826     DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1827 };
1828 static const unsigned int du_clk_in_0_pins[] = {
1829     /* CLKIN0 */
1830     RCAR_GP_PIN(0, 16),
1831 };
1832 static const unsigned int du_clk_in_0_mux[] = {
1833     DU_DOTCLKIN0_MARK
1834 };
1835 static const unsigned int du_clk_in_1_pins[] = {
1836     /* CLKIN1 */
1837     RCAR_GP_PIN(1, 1),
1838 };
1839 static const unsigned int du_clk_in_1_mux[] = {
1840     DU_DOTCLKIN1_MARK
1841 };
1842 static const unsigned int du_clk_out_0_pins[] = {
1843     /* CLKOUT */
1844     RCAR_GP_PIN(1, 3),
1845 };
1846 static const unsigned int du_clk_out_0_mux[] = {
1847     DU_DOTCLKOUT0_MARK
1848 };
1849 static const unsigned int du_sync_pins[] = {
1850     /* VSYNC, HSYNC */
1851     RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
1852 };
1853 static const unsigned int du_sync_mux[] = {
1854     DU_VSYNC_MARK, DU_HSYNC_MARK
1855 };
1856 static const unsigned int du_disp_cde_pins[] = {
1857     /* DISP_CDE */
1858     RCAR_GP_PIN(1, 1),
1859 };
1860 static const unsigned int du_disp_cde_mux[] = {
1861     DU_DISP_CDE_MARK,
1862 };
1863 static const unsigned int du_cde_pins[] = {
1864     /* CDE */
1865     RCAR_GP_PIN(1, 0),
1866 };
1867 static const unsigned int du_cde_mux[] = {
1868     DU_CDE_MARK,
1869 };
1870 static const unsigned int du_disp_pins[] = {
1871     /* DISP */
1872     RCAR_GP_PIN(1, 2),
1873 };
1874 static const unsigned int du_disp_mux[] = {
1875     DU_DISP_MARK,
1876 };
1877
1878 /* - HSCIF0 --------------------------------------------------*/
1879 static const unsigned int hscif0_data_a_pins[] = {
1880     /* RX, TX */
1881     RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
1882 };
1883
1884 static const unsigned int hscif0_data_a_mux[] = {
1885     HRX0_A_MARK, HTX0_A_MARK,
1886 };
1887
1888 static const unsigned int hscif0_clk_a_pins[] = {
1889     /* SCK */
1890     RCAR_GP_PIN(5, 7),
1891 };
1892
1893 static const unsigned int hscif0_clk_a_mux[] = {
1894     HSCK0_A_MARK,
1895 };
1896
1897 static const unsigned int hscif0_ctrl_a_pins[] = {
1898     /* RTS, CTS */
1899     RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1900 };
1901
1902 static const unsigned int hscif0_ctrl_a_mux[] = {
1903     HRTS0_N_A_MARK, HCTS0_N_A_MARK,
1904 };
1905
1906 static const unsigned int hscif0_data_b_pins[] = {
1907     /* RX, TX */
1908     RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
1909 };
1910
1911 static const unsigned int hscif0_data_b_mux[] = {
1912     HRX0_B_MARK, HTX0_B_MARK,
1913 };
1914
1915 static const unsigned int hscif0_clk_b_pins[] = {
1916     /* SCK */
1917     RCAR_GP_PIN(6, 13),
1918 };
1919
1920 static const unsigned int hscif0_clk_b_mux[] = {
1921     HSCK0_B_MARK,
1922 };
1923
1924 /* - HSCIF1 ------------------------------------------------- */
1925 static const unsigned int hscif1_data_a_pins[] = {
1926     /* RX, TX */
1927     RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1928 };
1929
1930 static const unsigned int hscif1_data_a_mux[] = {
1931     HRX1_A_MARK, HTX1_A_MARK,
1932 };
1933
1934 static const unsigned int hscif1_clk_a_pins[] = {
1935     /* SCK */
1936     RCAR_GP_PIN(5, 0),
1937 };
1938
1939 static const unsigned int hscif1_clk_a_mux[] = {
1940     HSCK1_A_MARK,
1941 };
1942
1943 static const unsigned int hscif1_data_b_pins[] = {
1944     /* RX, TX */
1945     RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
1946 };
1947
1948 static const unsigned int hscif1_data_b_mux[] = {
1949     HRX1_B_MARK, HTX1_B_MARK,
1950 };
1951
1952 static const unsigned int hscif1_clk_b_pins[] = {
1953     /* SCK */
1954     RCAR_GP_PIN(3, 0),
1955 };
1956
1957 static const unsigned int hscif1_clk_b_mux[] = {
1958     HSCK1_B_MARK,
1959 };
1960
1961 static const unsigned int hscif1_ctrl_b_pins[] = {
1962     /* RTS, CTS */
1963     RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
1964 };
1965
1966 static const unsigned int hscif1_ctrl_b_mux[] = {
1967     HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1968 };
1969
1970 /* - HSCIF2 ------------------------------------------------- */
1971 static const unsigned int hscif2_data_a_pins[] = {
1972     /* RX, TX */
1973     RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
1974 };
1975
1976 static const unsigned int hscif2_data_a_mux[] = {
1977     HRX2_A_MARK, HTX2_A_MARK,
1978 };
1979
1980 static const unsigned int hscif2_clk_a_pins[] = {
1981     /* SCK */
1982     RCAR_GP_PIN(6, 14),
1983 };
1984
1985 static const unsigned int hscif2_clk_a_mux[] = {
1986     HSCK2_A_MARK,
1987 };
1988
1989 static const unsigned int hscif2_ctrl_a_pins[] = {
1990     /* RTS, CTS */
1991     RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
1992 };
1993
1994 static const unsigned int hscif2_ctrl_a_mux[] = {
1995     HRTS2_N_A_MARK, HCTS2_N_A_MARK,
1996 };
1997
1998 static const unsigned int hscif2_data_b_pins[] = {
1999     /* RX, TX */
2000     RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2001 };
2002
2003 static const unsigned int hscif2_data_b_mux[] = {
2004     HRX2_B_MARK, HTX2_B_MARK,
2005 };
2006
2007 /* - HSCIF3 ------------------------------------------------*/
2008 static const unsigned int hscif3_data_a_pins[] = {
2009     /* RX, TX */
2010     RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2011 };
2012
2013 static const unsigned int hscif3_data_a_mux[] = {
2014     HRX3_A_MARK, HTX3_A_MARK,
2015 };
2016
2017 static const unsigned int hscif3_data_b_pins[] = {
2018     /* RX, TX */
2019     RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2020 };
2021
2022 static const unsigned int hscif3_data_b_mux[] = {
2023     HRX3_B_MARK, HTX3_B_MARK,
2024 };
2025
2026 static const unsigned int hscif3_clk_b_pins[] = {
2027     /* SCK */
2028     RCAR_GP_PIN(0, 4),
2029 };
2030
2031 static const unsigned int hscif3_clk_b_mux[] = {
2032     HSCK3_B_MARK,
2033 };
2034
2035 static const unsigned int hscif3_data_c_pins[] = {
2036     /* RX, TX */
2037     RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9),
2038 };
2039
2040 static const unsigned int hscif3_data_c_mux[] = {
2041     HRX3_C_MARK, HTX3_C_MARK,
2042 };
2043
2044 static const unsigned int hscif3_clk_c_pins[] = {
2045     /* SCK */
2046     RCAR_GP_PIN(2, 11),
2047 };
2048
2049 static const unsigned int hscif3_clk_c_mux[] = {
2050     HSCK3_C_MARK,
2051 };
2052
2053 static const unsigned int hscif3_ctrl_c_pins[] = {
2054     /* RTS, CTS */
2055     RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
2056 };
2057
2058 static const unsigned int hscif3_ctrl_c_mux[] = {
2059     HRTS3_N_C_MARK, HCTS3_N_C_MARK,
2060 };
2061
2062 static const unsigned int hscif3_data_d_pins[] = {
2063     /* RX, TX */
2064     RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3),
2065 };
2066
2067 static const unsigned int hscif3_data_d_mux[] = {
2068     HRX3_D_MARK, HTX3_D_MARK,
2069 };
2070
2071 static const unsigned int hscif3_data_e_pins[] = {
2072     /* RX, TX */
2073     RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2074 };
2075
2076 static const unsigned int hscif3_data_e_mux[] = {
2077     HRX3_E_MARK, HTX3_E_MARK,
2078 };
2079
2080 static const unsigned int hscif3_ctrl_e_pins[] = {
2081     /* RTS, CTS */
2082     RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8),
2083 };
2084
2085 static const unsigned int hscif3_ctrl_e_mux[] = {
2086     HRTS3_N_E_MARK, HCTS3_N_E_MARK,
2087 };
2088
2089 /* - HSCIF4 -------------------------------------------------- */
2090 static const unsigned int hscif4_data_a_pins[] = {
2091     /* RX, TX */
2092     RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
2093 };
2094
2095 static const unsigned int hscif4_data_a_mux[] = {
2096     HRX4_A_MARK, HTX4_A_MARK,
2097 };
2098
2099 static const unsigned int hscif4_clk_a_pins[] = {
2100     /* SCK */
2101     RCAR_GP_PIN(2, 0),
2102 };
2103
2104 static const unsigned int hscif4_clk_a_mux[] = {
2105     HSCK4_A_MARK,
2106 };
2107
2108 static const unsigned int hscif4_ctrl_a_pins[] = {
2109     /* RTS, CTS */
2110     RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
2111 };
2112
2113 static const unsigned int hscif4_ctrl_a_mux[] = {
2114     HRTS4_N_A_MARK, HCTS4_N_A_MARK,
2115 };
2116
2117 static const unsigned int hscif4_data_b_pins[] = {
2118     /* RX, TX */
2119     RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2120 };
2121
2122 static const unsigned int hscif4_data_b_mux[] = {
2123     HRX4_B_MARK, HTX4_B_MARK,
2124 };
2125
2126 static const unsigned int hscif4_clk_b_pins[] = {
2127     /* SCK */
2128     RCAR_GP_PIN(2, 6),
2129 };
2130
2131 static const unsigned int hscif4_clk_b_mux[] = {
2132     HSCK4_B_MARK,
2133 };
2134
2135 static const unsigned int hscif4_data_c_pins[] = {
2136     /* RX, TX */
2137     RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2138 };
2139
2140 static const unsigned int hscif4_data_c_mux[] = {
2141     HRX4_C_MARK, HTX4_C_MARK,
2142 };
2143
2144 static const unsigned int hscif4_data_d_pins[] = {
2145     /* RX, TX */
2146     RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
2147 };
2148
2149 static const unsigned int hscif4_data_d_mux[] = {
2150     HRX4_D_MARK, HTX4_D_MARK,
2151 };
2152
2153 static const unsigned int hscif4_data_e_pins[] = {
2154     /* RX, TX */
2155     RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2156 };
2157
2158 static const unsigned int hscif4_data_e_mux[] = {
2159     HRX4_E_MARK, HTX4_E_MARK,
2160 };
2161
2162 /* - I2C -------------------------------------------------------------------- */
2163 static const unsigned int i2c1_a_pins[] = {
2164     /* SCL, SDA */
2165     RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2166 };
2167
2168 static const unsigned int i2c1_a_mux[] = {
2169     SCL1_A_MARK, SDA1_A_MARK,
2170 };
2171
2172 static const unsigned int i2c1_b_pins[] = {
2173     /* SCL, SDA */
2174     RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2175 };
2176
2177 static const unsigned int i2c1_b_mux[] = {
2178     SCL1_B_MARK, SDA1_B_MARK,
2179 };
2180
2181 static const unsigned int i2c1_c_pins[] = {
2182     /* SCL, SDA */
2183     RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5),
2184 };
2185
2186 static const unsigned int i2c1_c_mux[] = {
2187     SCL1_C_MARK, SDA1_C_MARK,
2188 };
2189
2190 static const unsigned int i2c1_d_pins[] = {
2191     /* SCL, SDA */
2192     RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
2193 };
2194
2195 static const unsigned int i2c1_d_mux[] = {
2196     SCL1_D_MARK, SDA1_D_MARK,
2197 };
2198
2199 static const unsigned int i2c2_a_pins[] = {
2200     /* SCL, SDA */
2201     RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0),
2202 };
2203
2204 static const unsigned int i2c2_a_mux[] = {
2205     SCL2_A_MARK, SDA2_A_MARK,
2206 };
2207
2208 static const unsigned int i2c2_b_pins[] = {
2209     /* SCL, SDA */
2210     RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2211 };
2212
2213 static const unsigned int i2c2_b_mux[] = {
2214     SCL2_B_MARK, SDA2_B_MARK,
2215 };
2216
2217 static const unsigned int i2c2_c_pins[] = {
2218     /* SCL, SDA */
2219     RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
2220 };
2221
2222 static const unsigned int i2c2_c_mux[] = {
2223     SCL2_C_MARK, SDA2_C_MARK,
2224 };
2225
2226 static const unsigned int i2c2_d_pins[] = {
2227     /* SCL, SDA */
2228     RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
2229 };
2230
2231 static const unsigned int i2c2_d_mux[] = {
2232     SCL2_D_MARK, SDA2_D_MARK,
2233 };
2234
2235 static const unsigned int i2c2_e_pins[] = {
2236     /* SCL, SDA */
2237     RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
2238 };
2239
2240 static const unsigned int i2c2_e_mux[] = {
2241     SCL2_E_MARK, SDA2_E_MARK,
2242 };
2243
2244 static const unsigned int i2c4_pins[] = {
2245     /* SCL, SDA */
2246     RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
2247 };
2248
2249 static const unsigned int i2c4_mux[] = {
2250     SCL4_MARK, SDA4_MARK,
2251 };
2252
2253 static const unsigned int i2c5_pins[] = {
2254     /* SCL, SDA */
2255     RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
2256 };
2257
2258 static const unsigned int i2c5_mux[] = {
2259     SCL5_MARK, SDA5_MARK,
2260 };
2261
2262 static const unsigned int i2c6_a_pins[] = {
2263     /* SCL, SDA */
2264     RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
2265 };
2266
2267 static const unsigned int i2c6_a_mux[] = {
2268     SCL6_A_MARK, SDA6_A_MARK,
2269 };
2270
2271 static const unsigned int i2c6_b_pins[] = {
2272     /* SCL, SDA */
2273     RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
2274 };
2275
2276 static const unsigned int i2c6_b_mux[] = {
2277     SCL6_B_MARK, SDA6_B_MARK,
2278 };
2279
2280 static const unsigned int i2c7_a_pins[] = {
2281     /* SCL, SDA */
2282     RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25),
2283 };
2284
2285 static const unsigned int i2c7_a_mux[] = {
2286     SCL7_A_MARK, SDA7_A_MARK,
2287 };
2288
2289 static const unsigned int i2c7_b_pins[] = {
2290     /* SCL, SDA */
2291     RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
2292 };
2293
2294 static const unsigned int i2c7_b_mux[] = {
2295     SCL7_B_MARK, SDA7_B_MARK,
2296 };
2297
2298 /* - INTC-EX ---------------------------------------------------------------- */
2299 static const unsigned int intc_ex_irq0_pins[] = {
2300     /* IRQ0 */
2301     RCAR_GP_PIN(1, 0),
2302 };
2303 static const unsigned int intc_ex_irq0_mux[] = {
2304     IRQ0_MARK,
2305 };
2306 static const unsigned int intc_ex_irq1_pins[] = {
2307     /* IRQ1 */
2308     RCAR_GP_PIN(1, 1),
2309 };
2310 static const unsigned int intc_ex_irq1_mux[] = {
2311     IRQ1_MARK,
2312 };
2313 static const unsigned int intc_ex_irq2_pins[] = {
2314     /* IRQ2 */
2315     RCAR_GP_PIN(1, 2),
2316 };
2317 static const unsigned int intc_ex_irq2_mux[] = {
2318     IRQ2_MARK,
2319 };
2320 static const unsigned int intc_ex_irq3_pins[] = {
2321     /* IRQ3 */
2322     RCAR_GP_PIN(1, 9),
2323 };
2324 static const unsigned int intc_ex_irq3_mux[] = {
2325     IRQ3_MARK,
2326 };
2327 static const unsigned int intc_ex_irq4_pins[] = {
2328     /* IRQ4 */
2329     RCAR_GP_PIN(1, 10),
2330 };
2331 static const unsigned int intc_ex_irq4_mux[] = {
2332     IRQ4_MARK,
2333 };
2334 static const unsigned int intc_ex_irq5_pins[] = {
2335     /* IRQ5 */
2336     RCAR_GP_PIN(0, 7),
2337 };
2338 static const unsigned int intc_ex_irq5_mux[] = {
2339     IRQ5_MARK,
2340 };
2341
2342 #ifdef CONFIG_PINCTRL_PFC_R8A77990
2343 /* - MLB+ ------------------------------------------------------------------- */
2344 static const unsigned int mlb_3pin_pins[] = {
2345     RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2346 };
2347 static const unsigned int mlb_3pin_mux[] = {
2348     MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2349 };
2350 #endif /* CONFIG_PINCTRL_PFC_R8A77990 */
2351
2352 /* - MSIOF0 ----------------------------------------------------------------- */
2353 static const unsigned int msiof0_clk_pins[] = {
2354     /* SCK */
2355     RCAR_GP_PIN(5, 10),
2356 };
2357
2358 static const unsigned int msiof0_clk_mux[] = {
2359     MSIOF0_SCK_MARK,
2360 };
2361
2362 static const unsigned int msiof0_sync_pins[] = {
2363     /* SYNC */
2364     RCAR_GP_PIN(5, 13),
2365 };
2366
2367 static const unsigned int msiof0_sync_mux[] = {
2368     MSIOF0_SYNC_MARK,
2369 };
2370
2371 static const unsigned int msiof0_ss1_pins[] = {
2372     /* SS1 */
2373     RCAR_GP_PIN(5, 14),
2374 };
2375
2376 static const unsigned int msiof0_ss1_mux[] = {
2377     MSIOF0_SS1_MARK,
2378 };
2379
2380 static const unsigned int msiof0_ss2_pins[] = {
2381     /* SS2 */
2382     RCAR_GP_PIN(5, 15),
2383 };
2384
2385 static const unsigned int msiof0_ss2_mux[] = {
2386     MSIOF0_SS2_MARK,
2387 };
2388
2389 static const unsigned int msiof0_txd_pins[] = {
2390     /* TXD */
2391     RCAR_GP_PIN(5, 12),
2392 };
2393
2394 static const unsigned int msiof0_txd_mux[] = {
2395     MSIOF0_TXD_MARK,
2396 };
2397
2398 static const unsigned int msiof0_rxd_pins[] = {
2399     /* RXD */
2400     RCAR_GP_PIN(5, 11),
2401 };
2402
2403 static const unsigned int msiof0_rxd_mux[] = {
2404     MSIOF0_RXD_MARK,
2405 };
2406
2407 /* - MSIOF1 ----------------------------------------------------------------- */
2408 static const unsigned int msiof1_clk_pins[] = {
2409     /* SCK */
2410     RCAR_GP_PIN(1, 19),
2411 };
2412
2413 static const unsigned int msiof1_clk_mux[] = {
2414     MSIOF1_SCK_MARK,
2415 };
2416
2417 static const unsigned int msiof1_sync_pins[] = {
2418     /* SYNC */
2419     RCAR_GP_PIN(1, 16),
2420 };
2421
2422 static const unsigned int msiof1_sync_mux[] = {
2423     MSIOF1_SYNC_MARK,
2424 };
2425
2426 static const unsigned int msiof1_ss1_pins[] = {
2427     /* SS1 */
2428     RCAR_GP_PIN(1, 14),
2429 };
2430
2431 static const unsigned int msiof1_ss1_mux[] = {
2432     MSIOF1_SS1_MARK,
2433 };
2434
2435 static const unsigned int msiof1_ss2_pins[] = {
2436     /* SS2 */
2437     RCAR_GP_PIN(1, 15),
2438 };
2439
2440 static const unsigned int msiof1_ss2_mux[] = {
2441     MSIOF1_SS2_MARK,
2442 };
2443
2444 static const unsigned int msiof1_txd_pins[] = {
2445     /* TXD */
2446     RCAR_GP_PIN(1, 18),
2447 };
2448
2449 static const unsigned int msiof1_txd_mux[] = {
2450     MSIOF1_TXD_MARK,
2451 };
2452
2453 static const unsigned int msiof1_rxd_pins[] = {
2454     /* RXD */
2455     RCAR_GP_PIN(1, 17),
2456 };
2457
2458 static const unsigned int msiof1_rxd_mux[] = {
2459     MSIOF1_RXD_MARK,
2460 };
2461
2462 /* - MSIOF2 ----------------------------------------------------------------- */
2463 static const unsigned int msiof2_clk_a_pins[] = {
2464     /* SCK */
2465     RCAR_GP_PIN(0, 8),
2466 };
2467
2468 static const unsigned int msiof2_clk_a_mux[] = {
2469     MSIOF2_SCK_A_MARK,
2470 };
2471
2472 static const unsigned int msiof2_sync_a_pins[] = {
2473     /* SYNC */
2474     RCAR_GP_PIN(0, 9),
2475 };
2476
2477 static const unsigned int msiof2_sync_a_mux[] = {
2478     MSIOF2_SYNC_A_MARK,
2479 };
2480
2481 static const unsigned int msiof2_ss1_a_pins[] = {
2482     /* SS1 */
2483     RCAR_GP_PIN(0, 15),
2484 };
2485
2486 static const unsigned int msiof2_ss1_a_mux[] = {
2487     MSIOF2_SS1_A_MARK,
2488 };
2489
2490 static const unsigned int msiof2_ss2_a_pins[] = {
2491     /* SS2 */
2492     RCAR_GP_PIN(0, 14),
2493 };
2494
2495 static const unsigned int msiof2_ss2_a_mux[] = {
2496     MSIOF2_SS2_A_MARK,
2497 };
2498
2499 static const unsigned int msiof2_txd_a_pins[] = {
2500     /* TXD */
2501     RCAR_GP_PIN(0, 11),
2502 };
2503
2504 static const unsigned int msiof2_txd_a_mux[] = {
2505     MSIOF2_TXD_A_MARK,
2506 };
2507
2508 static const unsigned int msiof2_rxd_a_pins[] = {
2509     /* RXD */
2510     RCAR_GP_PIN(0, 10),
2511 };
2512
2513 static const unsigned int msiof2_rxd_a_mux[] = {
2514     MSIOF2_RXD_A_MARK,
2515 };
2516
2517 static const unsigned int msiof2_clk_b_pins[] = {
2518     /* SCK */
2519     RCAR_GP_PIN(1, 13),
2520 };
2521
2522 static const unsigned int msiof2_clk_b_mux[] = {
2523     MSIOF2_SCK_B_MARK,
2524 };
2525
2526 static const unsigned int msiof2_sync_b_pins[] = {
2527     /* SYNC */
2528     RCAR_GP_PIN(1, 10),
2529 };
2530
2531 static const unsigned int msiof2_sync_b_mux[] = {
2532     MSIOF2_SYNC_B_MARK,
2533 };
2534
2535 static const unsigned int msiof2_ss1_b_pins[] = {
2536     /* SS1 */
2537     RCAR_GP_PIN(1, 16),
2538 };
2539
2540 static const unsigned int msiof2_ss1_b_mux[] = {
2541     MSIOF2_SS1_B_MARK,
2542 };
2543
2544 static const unsigned int msiof2_ss2_b_pins[] = {
2545     /* SS2 */
2546     RCAR_GP_PIN(1, 12),
2547 };
2548
2549 static const unsigned int msiof2_ss2_b_mux[] = {
2550     MSIOF2_SS2_B_MARK,
2551 };
2552
2553 static const unsigned int msiof2_txd_b_pins[] = {
2554     /* TXD */
2555     RCAR_GP_PIN(1, 15),
2556 };
2557
2558 static const unsigned int msiof2_txd_b_mux[] = {
2559     MSIOF2_TXD_B_MARK,
2560 };
2561
2562 static const unsigned int msiof2_rxd_b_pins[] = {
2563     /* RXD */
2564     RCAR_GP_PIN(1, 14),
2565 };
2566
2567 static const unsigned int msiof2_rxd_b_mux[] = {
2568     MSIOF2_RXD_B_MARK,
2569 };
2570
2571 /* - MSIOF3 ----------------------------------------------------------------- */
2572 static const unsigned int msiof3_clk_a_pins[] = {
2573     /* SCK */
2574     RCAR_GP_PIN(0, 0),
2575 };
2576
2577 static const unsigned int msiof3_clk_a_mux[] = {
2578     MSIOF3_SCK_A_MARK,
2579 };
2580
2581 static const unsigned int msiof3_sync_a_pins[] = {
2582     /* SYNC */
2583     RCAR_GP_PIN(0, 1),
2584 };
2585
2586 static const unsigned int msiof3_sync_a_mux[] = {
2587     MSIOF3_SYNC_A_MARK,
2588 };
2589
2590 static const unsigned int msiof3_ss1_a_pins[] = {
2591     /* SS1 */
2592     RCAR_GP_PIN(0, 15),
2593 };
2594
2595 static const unsigned int msiof3_ss1_a_mux[] = {
2596     MSIOF3_SS1_A_MARK,
2597 };
2598
2599 static const unsigned int msiof3_ss2_a_pins[] = {
2600     /* SS2 */
2601     RCAR_GP_PIN(0, 4),
2602 };
2603
2604 static const unsigned int msiof3_ss2_a_mux[] = {
2605     MSIOF3_SS2_A_MARK,
2606 };
2607
2608 static const unsigned int msiof3_txd_a_pins[] = {
2609     /* TXD */
2610     RCAR_GP_PIN(0, 3),
2611 };
2612
2613 static const unsigned int msiof3_txd_a_mux[] = {
2614     MSIOF3_TXD_A_MARK,
2615 };
2616
2617 static const unsigned int msiof3_rxd_a_pins[] = {
2618     /* RXD */
2619     RCAR_GP_PIN(0, 2),
2620 };
2621
2622 static const unsigned int msiof3_rxd_a_mux[] = {
2623     MSIOF3_RXD_A_MARK,
2624 };
2625
2626 static const unsigned int msiof3_clk_b_pins[] = {
2627     /* SCK */
2628     RCAR_GP_PIN(1, 5),
2629 };
2630
2631 static const unsigned int msiof3_clk_b_mux[] = {
2632     MSIOF3_SCK_B_MARK,
2633 };
2634
2635 static const unsigned int msiof3_sync_b_pins[] = {
2636     /* SYNC */
2637     RCAR_GP_PIN(1, 4),
2638 };
2639
2640 static const unsigned int msiof3_sync_b_mux[] = {
2641     MSIOF3_SYNC_B_MARK,
2642 };
2643
2644 static const unsigned int msiof3_ss1_b_pins[] = {
2645     /* SS1 */
2646     RCAR_GP_PIN(1, 0),
2647 };
2648
2649 static const unsigned int msiof3_ss1_b_mux[] = {
2650     MSIOF3_SS1_B_MARK,
2651 };
2652
2653 static const unsigned int msiof3_txd_b_pins[] = {
2654     /* TXD */
2655     RCAR_GP_PIN(1, 7),
2656 };
2657
2658 static const unsigned int msiof3_txd_b_mux[] = {
2659     MSIOF3_TXD_B_MARK,
2660 };
2661
2662 static const unsigned int msiof3_rxd_b_pins[] = {
2663     /* RXD */
2664     RCAR_GP_PIN(1, 6),
2665 };
2666
2667 static const unsigned int msiof3_rxd_b_mux[] = {
2668     MSIOF3_RXD_B_MARK,
2669 };
2670
2671 /* - PWM0 --------------------------------------------------------------------*/
2672 static const unsigned int pwm0_a_pins[] = {
2673     /* PWM */
2674     RCAR_GP_PIN(2, 22),
2675 };
2676
2677 static const unsigned int pwm0_a_mux[] = {
2678     PWM0_A_MARK,
2679 };
2680
2681 static const unsigned int pwm0_b_pins[] = {
2682     /* PWM */
2683     RCAR_GP_PIN(6, 3),
2684 };
2685
2686 static const unsigned int pwm0_b_mux[] = {
2687     PWM0_B_MARK,
2688 };
2689
2690 /* - PWM1 --------------------------------------------------------------------*/
2691 static const unsigned int pwm1_a_pins[] = {
2692     /* PWM */
2693     RCAR_GP_PIN(2, 23),
2694 };
2695
2696 static const unsigned int pwm1_a_mux[] = {
2697     PWM1_A_MARK,
2698 };
2699
2700 static const unsigned int pwm1_b_pins[] = {
2701     /* PWM */
2702     RCAR_GP_PIN(6, 4),
2703 };
2704
2705 static const unsigned int pwm1_b_mux[] = {
2706     PWM1_B_MARK,
2707 };
2708
2709 /* - PWM2 --------------------------------------------------------------------*/
2710 static const unsigned int pwm2_a_pins[] = {
2711     /* PWM */
2712     RCAR_GP_PIN(1, 0),
2713 };
2714
2715 static const unsigned int pwm2_a_mux[] = {
2716     PWM2_A_MARK,
2717 };
2718
2719 static const unsigned int pwm2_b_pins[] = {
2720     /* PWM */
2721     RCAR_GP_PIN(1, 4),
2722 };
2723
2724 static const unsigned int pwm2_b_mux[] = {
2725     PWM2_B_MARK,
2726 };
2727
2728 static const unsigned int pwm2_c_pins[] = {
2729     /* PWM */
2730     RCAR_GP_PIN(6, 5),
2731 };
2732
2733 static const unsigned int pwm2_c_mux[] = {
2734     PWM2_C_MARK,
2735 };
2736
2737 /* - PWM3 --------------------------------------------------------------------*/
2738 static const unsigned int pwm3_a_pins[] = {
2739     /* PWM */
2740     RCAR_GP_PIN(1, 1),
2741 };
2742
2743 static const unsigned int pwm3_a_mux[] = {
2744     PWM3_A_MARK,
2745 };
2746
2747 static const unsigned int pwm3_b_pins[] = {
2748     /* PWM */
2749     RCAR_GP_PIN(1, 5),
2750 };
2751
2752 static const unsigned int pwm3_b_mux[] = {
2753     PWM3_B_MARK,
2754 };
2755
2756 static const unsigned int pwm3_c_pins[] = {
2757     /* PWM */
2758     RCAR_GP_PIN(6, 6),
2759 };
2760
2761 static const unsigned int pwm3_c_mux[] = {
2762     PWM3_C_MARK,
2763 };
2764
2765 /* - PWM4 --------------------------------------------------------------------*/
2766 static const unsigned int pwm4_a_pins[] = {
2767     /* PWM */
2768     RCAR_GP_PIN(1, 3),
2769 };
2770
2771 static const unsigned int pwm4_a_mux[] = {
2772     PWM4_A_MARK,
2773 };
2774
2775 static const unsigned int pwm4_b_pins[] = {
2776     /* PWM */
2777     RCAR_GP_PIN(6, 7),
2778 };
2779
2780 static const unsigned int pwm4_b_mux[] = {
2781     PWM4_B_MARK,
2782 };
2783
2784 /* - PWM5 --------------------------------------------------------------------*/
2785 static const unsigned int pwm5_a_pins[] = {
2786     /* PWM */
2787     RCAR_GP_PIN(2, 24),
2788 };
2789
2790 static const unsigned int pwm5_a_mux[] = {
2791     PWM5_A_MARK,
2792 };
2793
2794 static const unsigned int pwm5_b_pins[] = {
2795     /* PWM */
2796     RCAR_GP_PIN(6, 10),
2797 };
2798
2799 static const unsigned int pwm5_b_mux[] = {
2800     PWM5_B_MARK,
2801 };
2802
2803 /* - PWM6 --------------------------------------------------------------------*/
2804 static const unsigned int pwm6_a_pins[] = {
2805     /* PWM */
2806     RCAR_GP_PIN(2, 25),
2807 };
2808
2809 static const unsigned int pwm6_a_mux[] = {
2810     PWM6_A_MARK,
2811 };
2812
2813 static const unsigned int pwm6_b_pins[] = {
2814     /* PWM */
2815     RCAR_GP_PIN(6, 11),
2816 };
2817
2818 static const unsigned int pwm6_b_mux[] = {
2819     PWM6_B_MARK,
2820 };
2821
2822 /* - QSPI0 ------------------------------------------------------------------ */
2823 static const unsigned int qspi0_ctrl_pins[] = {
2824     /* QSPI0_SPCLK, QSPI0_SSL */
2825     RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 5),
2826 };
2827 static const unsigned int qspi0_ctrl_mux[] = {
2828     QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
2829 };
2830 /* - QSPI1 ------------------------------------------------------------------ */
2831 static const unsigned int qspi1_ctrl_pins[] = {
2832     /* QSPI1_SPCLK, QSPI1_SSL */
2833     RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 11),
2834 };
2835 static const unsigned int qspi1_ctrl_mux[] = {
2836     QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
2837 };
2838
2839 /* - RPC -------------------------------------------------------------------- */
2840 static const unsigned int rpc_clk_pins[] = {
2841     /* Octal-SPI flash: C/SCLK */
2842     /* HyperFlash: CK, CK# */
2843     RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 6),
2844 };
2845 static const unsigned int rpc_clk_mux[] = {
2846     QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
2847 };
2848 static const unsigned int rpc_ctrl_pins[] = {
2849     /* Octal-SPI flash: S#/CS, DQS */
2850     /* HyperFlash: CS#, RDS */
2851     RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 11),
2852 };
2853 static const unsigned int rpc_ctrl_mux[] = {
2854     QSPI0_SSL_MARK, QSPI1_SSL_MARK,
2855 };
2856 static const unsigned int rpc_data_pins[] = {
2857     /* DQ[0:7] */
2858     RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
2859     RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
2860     RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2861     RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
2862 };
2863 static const unsigned int rpc_data_mux[] = {
2864     QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
2865     QSPI0_IO2_MARK, QSPI0_IO3_MARK,
2866     QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
2867     QSPI1_IO2_MARK, QSPI1_IO3_MARK,
2868 };
2869 static const unsigned int rpc_reset_pins[] = {
2870     /* RPC_RESET# */
2871     RCAR_GP_PIN(2, 13),
2872 };
2873 static const unsigned int rpc_reset_mux[] = {
2874     RPC_RESET_N_MARK,
2875 };
2876 static const unsigned int rpc_int_pins[] = {
2877     /* RPC_INT# */
2878     RCAR_GP_PIN(2, 12),
2879 };
2880 static const unsigned int rpc_int_mux[] = {
2881     RPC_INT_N_MARK,
2882 };
2883
2884 /* - SCIF0 ------------------------------------------------------------------ */
2885 static const unsigned int scif0_data_a_pins[] = {
2886     /* RX, TX */
2887     RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2888 };
2889
2890 static const unsigned int scif0_data_a_mux[] = {
2891     RX0_A_MARK, TX0_A_MARK,
2892 };
2893
2894 static const unsigned int scif0_clk_a_pins[] = {
2895     /* SCK */
2896     RCAR_GP_PIN(5, 0),
2897 };
2898
2899 static const unsigned int scif0_clk_a_mux[] = {
2900     SCK0_A_MARK,
2901 };
2902
2903 static const unsigned int scif0_ctrl_a_pins[] = {
2904     /* RTS, CTS */
2905     RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2906 };
2907
2908 static const unsigned int scif0_ctrl_a_mux[] = {
2909     RTS0_N_A_MARK, CTS0_N_A_MARK,
2910 };
2911
2912 static const unsigned int scif0_data_b_pins[] = {
2913     /* RX, TX */
2914     RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
2915 };
2916
2917 static const unsigned int scif0_data_b_mux[] = {
2918     RX0_B_MARK, TX0_B_MARK,
2919 };
2920
2921 static const unsigned int scif0_clk_b_pins[] = {
2922     /* SCK */
2923     RCAR_GP_PIN(5, 18),
2924 };
2925
2926 static const unsigned int scif0_clk_b_mux[] = {
2927     SCK0_B_MARK,
2928 };
2929
2930 /* - SCIF1 ------------------------------------------------------------------ */
2931 static const unsigned int scif1_data_pins[] = {
2932     /* RX, TX */
2933     RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2934 };
2935
2936 static const unsigned int scif1_data_mux[] = {
2937     RX1_MARK, TX1_MARK,
2938 };
2939
2940 static const unsigned int scif1_clk_pins[] = {
2941     /* SCK */
2942     RCAR_GP_PIN(5, 16),
2943 };
2944
2945 static const unsigned int scif1_clk_mux[] = {
2946     SCK1_MARK,
2947 };
2948
2949 static const unsigned int scif1_ctrl_pins[] = {
2950     /* RTS, CTS */
2951     RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7),
2952 };
2953
2954 static const unsigned int scif1_ctrl_mux[] = {
2955     RTS1_N_MARK, CTS1_N_MARK,
2956 };
2957
2958 /* - SCIF2 ------------------------------------------------------------------ */
2959 static const unsigned int scif2_data_a_pins[] = {
2960     /* RX, TX */
2961     RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
2962 };
2963
2964 static const unsigned int scif2_data_a_mux[] = {
2965     RX2_A_MARK, TX2_A_MARK,
2966 };
2967
2968 static const unsigned int scif2_clk_a_pins[] = {
2969     /* SCK */
2970     RCAR_GP_PIN(5, 7),
2971 };
2972
2973 static const unsigned int scif2_clk_a_mux[] = {
2974     SCK2_A_MARK,
2975 };
2976
2977 static const unsigned int scif2_data_b_pins[] = {
2978     /* RX, TX */
2979     RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
2980 };
2981
2982 static const unsigned int scif2_data_b_mux[] = {
2983     RX2_B_MARK, TX2_B_MARK,
2984 };
2985
2986 /* - SCIF3 ------------------------------------------------------------------ */
2987 static const unsigned int scif3_data_a_pins[] = {
2988     /* RX, TX */
2989     RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2990 };
2991
2992 static const unsigned int scif3_data_a_mux[] = {
2993     RX3_A_MARK, TX3_A_MARK,
2994 };
2995
2996 static const unsigned int scif3_clk_a_pins[] = {
2997     /* SCK */
2998     RCAR_GP_PIN(0, 1),
2999 };
3000
3001 static const unsigned int scif3_clk_a_mux[] = {
3002     SCK3_A_MARK,
3003 };
3004
3005 static const unsigned int scif3_ctrl_a_pins[] = {
3006     /* RTS, CTS */
3007     RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
3008 };
3009
3010 static const unsigned int scif3_ctrl_a_mux[] = {
3011     RTS3_N_A_MARK, CTS3_N_A_MARK,
3012 };
3013
3014 static const unsigned int scif3_data_b_pins[] = {
3015     /* RX, TX */
3016     RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3017 };
3018
3019 static const unsigned int scif3_data_b_mux[] = {
3020     RX3_B_MARK, TX3_B_MARK,
3021 };
3022
3023 static const unsigned int scif3_data_c_pins[] = {
3024     /* RX, TX */
3025     RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
3026 };
3027
3028 static const unsigned int scif3_data_c_mux[] = {
3029     RX3_C_MARK, TX3_C_MARK,
3030 };
3031
3032 static const unsigned int scif3_clk_c_pins[] = {
3033     /* SCK */
3034     RCAR_GP_PIN(2, 24),
3035 };
3036
3037 static const unsigned int scif3_clk_c_mux[] = {
3038     SCK3_C_MARK,
3039 };
3040
3041 /* - SCIF4 ------------------------------------------------------------------ */
3042 static const unsigned int scif4_data_a_pins[] = {
3043     /* RX, TX */
3044     RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3045 };
3046
3047 static const unsigned int scif4_data_a_mux[] = {
3048     RX4_A_MARK, TX4_A_MARK,
3049 };
3050
3051 static const unsigned int scif4_clk_a_pins[] = {
3052     /* SCK */
3053     RCAR_GP_PIN(1, 5),
3054 };
3055
3056 static const unsigned int scif4_clk_a_mux[] = {
3057     SCK4_A_MARK,
3058 };
3059
3060 static const unsigned int scif4_ctrl_a_pins[] = {
3061     /* RTS, CTS */
3062     RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
3063 };
3064
3065 static const unsigned int scif4_ctrl_a_mux[] = {
3066     RTS4_N_A_MARK, CTS4_N_A_MARK,
3067 };
3068
3069 static const unsigned int scif4_data_b_pins[] = {
3070     /* RX, TX */
3071     RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
3072 };
3073
3074 static const unsigned int scif4_data_b_mux[] = {
3075     RX4_B_MARK, TX4_B_MARK,
3076 };
3077
3078 static const unsigned int scif4_clk_b_pins[] = {
3079     /* SCK */
3080     RCAR_GP_PIN(0, 8),
3081 };
3082
3083 static const unsigned int scif4_clk_b_mux[] = {
3084     SCK4_B_MARK,
3085 };
3086
3087 static const unsigned int scif4_data_c_pins[] = {
3088     /* RX, TX */
3089     RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3090 };
3091
3092 static const unsigned int scif4_data_c_mux[] = {
3093     RX4_C_MARK, TX4_C_MARK,
3094 };
3095
3096 static const unsigned int scif4_ctrl_c_pins[] = {
3097     /* RTS, CTS */
3098     RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
3099 };
3100
3101 static const unsigned int scif4_ctrl_c_mux[] = {
3102     RTS4_N_C_MARK, CTS4_N_C_MARK,
3103 };
3104
3105 /* - SCIF5 ------------------------------------------------------------------ */
3106 static const unsigned int scif5_data_a_pins[] = {
3107     /* RX, TX */
3108     RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9),
3109 };
3110
3111 static const unsigned int scif5_data_a_mux[] = {
3112     RX5_A_MARK, TX5_A_MARK,
3113 };
3114
3115 static const unsigned int scif5_clk_a_pins[] = {
3116     /* SCK */
3117     RCAR_GP_PIN(1, 13),
3118 };
3119
3120 static const unsigned int scif5_clk_a_mux[] = {
3121     SCK5_A_MARK,
3122 };
3123
3124 static const unsigned int scif5_data_b_pins[] = {
3125     /* RX, TX */
3126     RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3127 };
3128
3129 static const unsigned int scif5_data_b_mux[] = {
3130     RX5_B_MARK, TX5_B_MARK,
3131 };
3132
3133 static const unsigned int scif5_data_c_pins[] = {
3134     /* RX, TX */
3135     RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3136 };
3137
3138 static const unsigned int scif5_data_c_mux[] = {
3139     RX5_C_MARK, TX5_C_MARK,
3140 };
3141
3142 /* - SCIF Clock ------------------------------------------------------------- */
3143 static const unsigned int scif_clk_a_pins[] = {
3144     /* SCIF_CLK */
3145     RCAR_GP_PIN(5, 3),
3146 };
3147
3148 static const unsigned int scif_clk_a_mux[] = {
3149     SCIF_CLK_A_MARK,
3150 };
3151
3152 static const unsigned int scif_clk_b_pins[] = {
3153     /* SCIF_CLK */
3154     RCAR_GP_PIN(5, 7),
3155 };
3156
3157 static const unsigned int scif_clk_b_mux[] = {
3158     SCIF_CLK_B_MARK,
3159 };
3160
3161 /* - SDHI0 ------------------------------------------------------------------ */
3162 static const unsigned int sdhi0_data_pins[] = {
3163     /* D[0:3] */
3164     RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3165     RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3166 };
3167
3168 static const unsigned int sdhi0_data_mux[] = {
3169     SD0_DAT0_MARK, SD0_DAT1_MARK,
3170     SD0_DAT2_MARK, SD0_DAT3_MARK,
3171 };
3172
3173 static const unsigned int sdhi0_ctrl_pins[] = {
3174     /* CLK, CMD */
3175     RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3176 };
3177
3178 static const unsigned int sdhi0_ctrl_mux[] = {
3179     SD0_CLK_MARK, SD0_CMD_MARK,
3180 };
3181
3182 static const unsigned int sdhi0_cd_pins[] = {
3183     /* CD */
3184     RCAR_GP_PIN(3, 12),
3185 };
3186
3187 static const unsigned int sdhi0_cd_mux[] = {
3188     SD0_CD_MARK,
3189 };
3190
3191 static const unsigned int sdhi0_wp_pins[] = {
3192     /* WP */
3193     RCAR_GP_PIN(3, 13),
3194 };
3195
3196 static const unsigned int sdhi0_wp_mux[] = {
3197     SD0_WP_MARK,
3198 };
3199
3200 /* - SDHI1 ------------------------------------------------------------------ */
3201 static const unsigned int sdhi1_data_pins[] = {
3202     /* D[0:3] */
3203     RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3204     RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3205 };
3206
3207 static const unsigned int sdhi1_data_mux[] = {
3208     SD1_DAT0_MARK, SD1_DAT1_MARK,
3209     SD1_DAT2_MARK, SD1_DAT3_MARK,
3210 };
3211
3212 static const unsigned int sdhi1_ctrl_pins[] = {
3213     /* CLK, CMD */
3214     RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3215 };
3216
3217 static const unsigned int sdhi1_ctrl_mux[] = {
3218     SD1_CLK_MARK, SD1_CMD_MARK,
3219 };
3220
3221 static const unsigned int sdhi1_cd_pins[] = {
3222     /* CD */
3223     RCAR_GP_PIN(3, 14),
3224 };
3225
3226 static const unsigned int sdhi1_cd_mux[] = {
3227     SD1_CD_MARK,
3228 };
3229
3230 static const unsigned int sdhi1_wp_pins[] = {
3231     /* WP */
3232     RCAR_GP_PIN(3, 15),
3233 };
3234
3235 static const unsigned int sdhi1_wp_mux[] = {
3236     SD1_WP_MARK,
3237 };
3238
3239 /* - SDHI3 ------------------------------------------------------------------ */
3240 static const unsigned int sdhi3_data_pins[] = {
3241     /* D[0:7] */
3242     RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3243     RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3244     RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
3245     RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3246 };
3247
3248 static const unsigned int sdhi3_data_mux[] = {
3249     SD3_DAT0_MARK, SD3_DAT1_MARK,
3250     SD3_DAT2_MARK, SD3_DAT3_MARK,
3251     SD3_DAT4_MARK, SD3_DAT5_MARK,
3252     SD3_DAT6_MARK, SD3_DAT7_MARK,
3253 };
3254
3255 static const unsigned int sdhi3_ctrl_pins[] = {
3256     /* CLK, CMD */
3257     RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3258 };
3259
3260 static const unsigned int sdhi3_ctrl_mux[] = {
3261     SD3_CLK_MARK, SD3_CMD_MARK,
3262 };
3263
3264 static const unsigned int sdhi3_cd_pins[] = {
3265     /* CD */
3266     RCAR_GP_PIN(3, 12),
3267 };
3268
3269 static const unsigned int sdhi3_cd_mux[] = {
3270     SD3_CD_MARK,
3271 };
3272
3273 static const unsigned int sdhi3_wp_pins[] = {
3274     /* WP */
3275     RCAR_GP_PIN(3, 13),
3276 };
3277
3278 static const unsigned int sdhi3_wp_mux[] = {
3279     SD3_WP_MARK,
3280 };
3281
3282 static const unsigned int sdhi3_ds_pins[] = {
3283     /* DS */
3284     RCAR_GP_PIN(4, 10),
3285 };
3286
3287 static const unsigned int sdhi3_ds_mux[] = {
3288     SD3_DS_MARK,
3289 };
3290
3291 /* - SSI -------------------------------------------------------------------- */
3292 static const unsigned int ssi0_data_pins[] = {
3293     /* SDATA */
3294     RCAR_GP_PIN(6, 2),
3295 };
3296
3297 static const unsigned int ssi0_data_mux[] = {
3298     SSI_SDATA0_MARK,
3299 };
3300
3301 static const unsigned int ssi01239_ctrl_pins[] = {
3302     /* SCK, WS */
3303     RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3304 };
3305
3306 static const unsigned int ssi01239_ctrl_mux[] = {
3307     SSI_SCK01239_MARK, SSI_WS01239_MARK,
3308 };
3309
3310 static const unsigned int ssi1_data_pins[] = {
3311     /* SDATA */
3312     RCAR_GP_PIN(6, 3),
3313 };
3314
3315 static const unsigned int ssi1_data_mux[] = {
3316     SSI_SDATA1_MARK,
3317 };
3318
3319 static const unsigned int ssi1_ctrl_pins[] = {
3320     /* SCK, WS */
3321     RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
3322 };
3323
3324 static const unsigned int ssi1_ctrl_mux[] = {
3325     SSI_SCK1_MARK, SSI_WS1_MARK,
3326 };
3327
3328 static const unsigned int ssi2_data_pins[] = {
3329     /* SDATA */
3330     RCAR_GP_PIN(6, 4),
3331 };
3332
3333 static const unsigned int ssi2_data_mux[] = {
3334     SSI_SDATA2_MARK,
3335 };
3336
3337 static const unsigned int ssi2_ctrl_a_pins[] = {
3338     /* SCK, WS */
3339     RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3340 };
3341
3342 static const unsigned int ssi2_ctrl_a_mux[] = {
3343     SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3344 };
3345
3346 static const unsigned int ssi2_ctrl_b_pins[] = {
3347     /* SCK, WS */
3348     RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3349 };
3350
3351 static const unsigned int ssi2_ctrl_b_mux[] = {
3352     SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3353 };
3354
3355 static const unsigned int ssi3_data_pins[] = {
3356     /* SDATA */
3357     RCAR_GP_PIN(6, 7),
3358 };
3359
3360 static const unsigned int ssi3_data_mux[] = {
3361     SSI_SDATA3_MARK,
3362 };
3363
3364 static const unsigned int ssi349_ctrl_pins[] = {
3365     /* SCK, WS */
3366     RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3367 };
3368
3369 static const unsigned int ssi349_ctrl_mux[] = {
3370     SSI_SCK349_MARK, SSI_WS349_MARK,
3371 };
3372
3373 static const unsigned int ssi4_data_pins[] = {
3374     /* SDATA */
3375     RCAR_GP_PIN(6, 10),
3376 };
3377
3378 static const unsigned int ssi4_data_mux[] = {
3379     SSI_SDATA4_MARK,
3380 };
3381
3382 static const unsigned int ssi4_ctrl_pins[] = {
3383     /* SCK, WS */
3384     RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3385 };
3386
3387 static const unsigned int ssi4_ctrl_mux[] = {
3388     SSI_SCK4_MARK, SSI_WS4_MARK,
3389 };
3390
3391 static const unsigned int ssi5_data_pins[] = {
3392     /* SDATA */
3393     RCAR_GP_PIN(6, 13),
3394 };
3395
3396 static const unsigned int ssi5_data_mux[] = {
3397     SSI_SDATA5_MARK,
3398 };
3399
3400 static const unsigned int ssi5_ctrl_pins[] = {
3401     /* SCK, WS */
3402     RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3403 };
3404
3405 static const unsigned int ssi5_ctrl_mux[] = {
3406     SSI_SCK5_MARK, SSI_WS5_MARK,
3407 };
3408
3409 static const unsigned int ssi6_data_pins[] = {
3410     /* SDATA */
3411     RCAR_GP_PIN(6, 16),
3412 };
3413
3414 static const unsigned int ssi6_data_mux[] = {
3415     SSI_SDATA6_MARK,
3416 };
3417
3418 static const unsigned int ssi6_ctrl_pins[] = {
3419     /* SCK, WS */
3420     RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3421 };
3422
3423 static const unsigned int ssi6_ctrl_mux[] = {
3424     SSI_SCK6_MARK, SSI_WS6_MARK,
3425 };
3426
3427 static const unsigned int ssi7_data_pins[] = {
3428     /* SDATA */
3429     RCAR_GP_PIN(5, 12),
3430 };
3431
3432 static const unsigned int ssi7_data_mux[] = {
3433     SSI_SDATA7_MARK,
3434 };
3435
3436 static const unsigned int ssi78_ctrl_pins[] = {
3437     /* SCK, WS */
3438     RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3439 };
3440
3441 static const unsigned int ssi78_ctrl_mux[] = {
3442     SSI_SCK78_MARK, SSI_WS78_MARK,
3443 };
3444
3445 static const unsigned int ssi8_data_pins[] = {
3446     /* SDATA */
3447     RCAR_GP_PIN(5, 13),
3448 };
3449
3450 static const unsigned int ssi8_data_mux[] = {
3451     SSI_SDATA8_MARK,
3452 };
3453
3454 static const unsigned int ssi9_data_pins[] = {
3455     /* SDATA */
3456     RCAR_GP_PIN(5, 16),
3457 };
3458
3459 static const unsigned int ssi9_data_mux[] = {
3460     SSI_SDATA9_MARK,
3461 };
3462
3463 static const unsigned int ssi9_ctrl_a_pins[] = {
3464     /* SCK, WS */
3465     RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 10),
3466 };
3467
3468 static const unsigned int ssi9_ctrl_a_mux[] = {
3469     SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3470 };
3471
3472 static const unsigned int ssi9_ctrl_b_pins[] = {
3473     /* SCK, WS */
3474     RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3475 };
3476
3477 static const unsigned int ssi9_ctrl_b_mux[] = {
3478     SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3479 };
3480
3481 /* - TMU -------------------------------------------------------------------- */
3482 static const unsigned int tmu_tclk1_a_pins[] = {
3483     /* TCLK */
3484     RCAR_GP_PIN(3, 12),
3485 };
3486
3487 static const unsigned int tmu_tclk1_a_mux[] = {
3488     TCLK1_A_MARK,
3489 };
3490
3491 static const unsigned int tmu_tclk1_b_pins[] = {
3492     /* TCLK */
3493     RCAR_GP_PIN(5, 17),
3494 };
3495
3496 static const unsigned int tmu_tclk1_b_mux[] = {
3497     TCLK1_B_MARK,
3498 };
3499
3500 static const unsigned int tmu_tclk2_a_pins[] = {
3501     /* TCLK */
3502     RCAR_GP_PIN(3, 13),
3503 };
3504
3505 static const unsigned int tmu_tclk2_a_mux[] = {
3506     TCLK2_A_MARK,
3507 };
3508
3509 static const unsigned int tmu_tclk2_b_pins[] = {
3510     /* TCLK */
3511     RCAR_GP_PIN(5, 18),
3512 };
3513
3514 static const unsigned int tmu_tclk2_b_mux[] = {
3515     TCLK2_B_MARK,
3516 };
3517
3518 /* - USB0 ------------------------------------------------------------------- */
3519 static const unsigned int usb0_a_pins[] = {
3520     /* PWEN, OVC */
3521     RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
3522 };
3523
3524 static const unsigned int usb0_a_mux[] = {
3525     USB0_PWEN_A_MARK, USB0_OVC_A_MARK,
3526 };
3527
3528 static const unsigned int usb0_b_pins[] = {
3529     /* PWEN, OVC */
3530     RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3531 };
3532
3533 static const unsigned int usb0_b_mux[] = {
3534     USB0_PWEN_B_MARK, USB0_OVC_B_MARK,
3535 };
3536
3537 static const unsigned int usb0_id_pins[] = {
3538     /* ID */
3539     RCAR_GP_PIN(5, 0)
3540 };
3541
3542 static const unsigned int usb0_id_mux[] = {
3543     USB0_ID_MARK,
3544 };
3545
3546 /* - USB30 ------------------------------------------------------------------ */
3547 static const unsigned int usb30_pins[] = {
3548     /* PWEN, OVC */
3549     RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
3550 };
3551
3552 static const unsigned int usb30_mux[] = {
3553     USB30_PWEN_MARK, USB30_OVC_MARK,
3554 };
3555
3556 static const unsigned int usb30_id_pins[] = {
3557     /* ID */
3558     RCAR_GP_PIN(5, 0),
3559 };
3560
3561 static const unsigned int usb30_id_mux[] = {
3562     USB3HS0_ID_MARK,
3563 };
3564
3565 /* - VIN4 ------------------------------------------------------------------- */
3566 static const unsigned int vin4_data18_a_pins[] = {
3567     RCAR_GP_PIN(2, 8),  RCAR_GP_PIN(2, 9),
3568     RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3569     RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3570     RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
3571     RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
3572     RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3573     RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3574     RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3575     RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3576 };
3577
3578 static const unsigned int vin4_data18_a_mux[] = {
3579     VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3580     VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3581     VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3582     VI4_DATA10_MARK,  VI4_DATA11_MARK,
3583     VI4_DATA12_MARK,  VI4_DATA13_MARK,
3584     VI4_DATA14_MARK,  VI4_DATA15_MARK,
3585     VI4_DATA18_MARK,  VI4_DATA19_MARK,
3586     VI4_DATA20_MARK,  VI4_DATA21_MARK,
3587     VI4_DATA22_MARK,  VI4_DATA23_MARK,
3588 };
3589
3590 static const unsigned int vin4_data_a_pins[] = {
3591     RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 7),
3592     RCAR_GP_PIN(2, 8),  RCAR_GP_PIN(2, 9),
3593     RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3594     RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3595     RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
3596     RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
3597     RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
3598     RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3599     RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 12),
3600     RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3601     RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3602     RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3603 };
3604
3605 static const unsigned int vin4_data_a_mux[] = {
3606     VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3607     VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3608     VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3609     VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3610     VI4_DATA8_MARK,   VI4_DATA9_MARK,
3611     VI4_DATA10_MARK,  VI4_DATA11_MARK,
3612     VI4_DATA12_MARK,  VI4_DATA13_MARK,
3613     VI4_DATA14_MARK,  VI4_DATA15_MARK,
3614     VI4_DATA16_MARK,  VI4_DATA17_MARK,
3615     VI4_DATA18_MARK,  VI4_DATA19_MARK,
3616     VI4_DATA20_MARK,  VI4_DATA21_MARK,
3617     VI4_DATA22_MARK,  VI4_DATA23_MARK,
3618 };
3619
3620 static const unsigned int vin4_data18_b_pins[] = {
3621     RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3622     RCAR_GP_PIN(0, 5),  RCAR_GP_PIN(0, 6),
3623     RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3624     RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
3625     RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
3626     RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3627     RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3628     RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3629     RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3630 };
3631
3632 static const unsigned int vin4_data18_b_mux[] = {
3633     VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3634     VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3635     VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3636     VI4_DATA10_MARK,  VI4_DATA11_MARK,
3637     VI4_DATA12_MARK,  VI4_DATA13_MARK,
3638     VI4_DATA14_MARK,  VI4_DATA15_MARK,
3639     VI4_DATA18_MARK,  VI4_DATA19_MARK,
3640     VI4_DATA20_MARK,  VI4_DATA21_MARK,
3641     VI4_DATA22_MARK,  VI4_DATA23_MARK,
3642 };
3643
3644 static const unsigned int vin4_data_b_pins[] = {
3645     RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 11),
3646     RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
3647     RCAR_GP_PIN(0, 5),  RCAR_GP_PIN(0, 6),
3648     RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3649     RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 5),
3650     RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 7),
3651     RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
3652     RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
3653     RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 12),
3654     RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3655     RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3656     RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
3657 };
3658
3659 static const unsigned int vin4_data_b_mux[] = {
3660     VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
3661     VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3662     VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3663     VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3664     VI4_DATA8_MARK,   VI4_DATA9_MARK,
3665     VI4_DATA10_MARK,  VI4_DATA11_MARK,
3666     VI4_DATA12_MARK,  VI4_DATA13_MARK,
3667     VI4_DATA14_MARK,  VI4_DATA15_MARK,
3668     VI4_DATA16_MARK,  VI4_DATA17_MARK,
3669     VI4_DATA18_MARK,  VI4_DATA19_MARK,
3670     VI4_DATA20_MARK,  VI4_DATA21_MARK,
3671     VI4_DATA22_MARK,  VI4_DATA23_MARK,
3672 };
3673
3674 static const unsigned int vin4_sync_pins[] = {
3675     /* HSYNC, VSYNC */
3676     RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3677 };
3678
3679 static const unsigned int vin4_sync_mux[] = {
3680     VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
3681 };
3682
3683 static const unsigned int vin4_field_pins[] = {
3684     RCAR_GP_PIN(2, 23),
3685 };
3686
3687 static const unsigned int vin4_field_mux[] = {
3688     VI4_FIELD_MARK,
3689 };
3690
3691 static const unsigned int vin4_clkenb_pins[] = {
3692     RCAR_GP_PIN(1, 2),
3693 };
3694
3695 static const unsigned int vin4_clkenb_mux[] = {
3696     VI4_CLKENB_MARK,
3697 };
3698
3699 static const unsigned int vin4_clk_pins[] = {
3700     RCAR_GP_PIN(2, 22),
3701 };
3702
3703 static const unsigned int vin4_clk_mux[] = {
3704     VI4_CLK_MARK,
3705 };
3706
3707 /* - VIN5 ------------------------------------------------------------------- */
3708 static const unsigned int vin5_data_a_pins[] = {
3709     RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 2),
3710     RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
3711     RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
3712     RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3713     RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3714     RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 11),
3715     RCAR_GP_PIN(0, 8),  RCAR_GP_PIN(0, 10),
3716     RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 3),
3717 };
3718
3719 static const unsigned int vin5_data_a_mux[] = {
3720     VI5_DATA0_A_MARK,  VI5_DATA1_A_MARK,
3721     VI5_DATA2_A_MARK,  VI5_DATA3_A_MARK,
3722     VI5_DATA4_A_MARK,  VI5_DATA5_A_MARK,
3723     VI5_DATA6_A_MARK,  VI5_DATA7_A_MARK,
3724     VI5_DATA8_A_MARK,  VI5_DATA9_A_MARK,
3725     VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
3726     VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
3727     VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
3728 };
3729
3730 static const unsigned int vin5_data8_b_pins[] = {
3731     RCAR_GP_PIN(2, 23), RCAR_GP_PIN(0, 4),
3732     RCAR_GP_PIN(0, 7),  RCAR_GP_PIN(0, 12),
3733     RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
3734     RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
3735 };
3736
3737 static const unsigned int vin5_data8_b_mux[] = {
3738     VI5_DATA0_B_MARK,  VI5_DATA1_B_MARK,
3739     VI5_DATA2_B_MARK,  VI5_DATA3_B_MARK,
3740     VI5_DATA4_B_MARK,  VI5_DATA5_B_MARK,
3741     VI5_DATA6_B_MARK,  VI5_DATA7_B_MARK,
3742 };
3743
3744 static const unsigned int vin5_sync_a_pins[] = {
3745     /* HSYNC_N, VSYNC_N */
3746     RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
3747 };
3748
3749 static const unsigned int vin5_sync_a_mux[] = {
3750     VI5_HSYNC_N_A_MARK, VI5_VSYNC_N_A_MARK,
3751 };
3752
3753 static const unsigned int vin5_field_a_pins[] = {
3754     RCAR_GP_PIN(1, 10),
3755 };
3756
3757 static const unsigned int vin5_field_a_mux[] = {
3758     VI5_FIELD_A_MARK,
3759 };
3760
3761 static const unsigned int vin5_clkenb_a_pins[] = {
3762     RCAR_GP_PIN(0, 1),
3763 };
3764
3765 static const unsigned int vin5_clkenb_a_mux[] = {
3766     VI5_CLKENB_A_MARK,
3767 };
3768
3769 static const unsigned int vin5_clk_a_pins[] = {
3770     RCAR_GP_PIN(1, 0),
3771 };
3772
3773 static const unsigned int vin5_clk_a_mux[] = {
3774     VI5_CLK_A_MARK,
3775 };
3776
3777 static const unsigned int vin5_clk_b_pins[] = {
3778     RCAR_GP_PIN(2, 22),
3779 };
3780
3781 static const unsigned int vin5_clk_b_mux[] = {
3782     VI5_CLK_B_MARK,
3783 };
3784
3785 static const struct {
3786     struct sh_pfc_pin_group common[261];
3787 #ifdef CONFIG_PINCTRL_PFC_R8A77990
3788     struct sh_pfc_pin_group automotive[22];
3789 #endif
3790 } pinmux_groups = {
3791     .common = {
3792         SH_PFC_PIN_GROUP(audio_clk_a),
3793         SH_PFC_PIN_GROUP(audio_clk_b_a),
3794         SH_PFC_PIN_GROUP(audio_clk_b_b),
3795         SH_PFC_PIN_GROUP(audio_clk_b_c),
3796         SH_PFC_PIN_GROUP(audio_clk_c_a),
3797         SH_PFC_PIN_GROUP(audio_clk_c_b),
3798         SH_PFC_PIN_GROUP(audio_clk_c_c),
3799         SH_PFC_PIN_GROUP(audio_clkout_a),
3800         SH_PFC_PIN_GROUP(audio_clkout_b),
3801         SH_PFC_PIN_GROUP(audio_clkout1_a),
3802         SH_PFC_PIN_GROUP(audio_clkout1_b),
3803         SH_PFC_PIN_GROUP(audio_clkout1_c),
3804         SH_PFC_PIN_GROUP(audio_clkout2_a),
3805         SH_PFC_PIN_GROUP(audio_clkout2_b),
3806         SH_PFC_PIN_GROUP(audio_clkout2_c),
3807         SH_PFC_PIN_GROUP(audio_clkout3_a),
3808         SH_PFC_PIN_GROUP(audio_clkout3_b),
3809         SH_PFC_PIN_GROUP(audio_clkout3_c),
3810         SH_PFC_PIN_GROUP(avb_link),
3811         SH_PFC_PIN_GROUP(avb_magic),
3812         SH_PFC_PIN_GROUP(avb_phy_int),
3813         SH_PFC_PIN_GROUP(avb_mii),
3814         SH_PFC_PIN_GROUP(avb_avtp_pps),
3815         SH_PFC_PIN_GROUP(avb_avtp_match),
3816         SH_PFC_PIN_GROUP(avb_avtp_capture),
3817         SH_PFC_PIN_GROUP(can0_data),
3818         SH_PFC_PIN_GROUP(can1_data),
3819         SH_PFC_PIN_GROUP(can_clk),
3820         SH_PFC_PIN_GROUP(canfd0_data),
3821         SH_PFC_PIN_GROUP(canfd1_data),
3822         SH_PFC_PIN_GROUP(du_rgb666),
3823         SH_PFC_PIN_GROUP(du_rgb888),
3824         SH_PFC_PIN_GROUP(du_clk_in_0),
3825         SH_PFC_PIN_GROUP(du_clk_in_1),
3826         SH_PFC_PIN_GROUP(du_clk_out_0),
3827         SH_PFC_PIN_GROUP(du_sync),
3828         SH_PFC_PIN_GROUP(du_disp_cde),
3829         SH_PFC_PIN_GROUP(du_cde),
3830         SH_PFC_PIN_GROUP(du_disp),
3831         SH_PFC_PIN_GROUP(hscif0_data_a),
3832         SH_PFC_PIN_GROUP(hscif0_clk_a),
3833         SH_PFC_PIN_GROUP(hscif0_ctrl_a),
3834         SH_PFC_PIN_GROUP(hscif0_data_b),
3835         SH_PFC_PIN_GROUP(hscif0_clk_b),
3836         SH_PFC_PIN_GROUP(hscif1_data_a),
3837         SH_PFC_PIN_GROUP(hscif1_clk_a),
3838         SH_PFC_PIN_GROUP(hscif1_data_b),
3839         SH_PFC_PIN_GROUP(hscif1_clk_b),
3840         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3841         SH_PFC_PIN_GROUP(hscif2_data_a),
3842         SH_PFC_PIN_GROUP(hscif2_clk_a),
3843         SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3844         SH_PFC_PIN_GROUP(hscif2_data_b),
3845         SH_PFC_PIN_GROUP(hscif3_data_a),
3846         SH_PFC_PIN_GROUP(hscif3_data_b),
3847         SH_PFC_PIN_GROUP(hscif3_clk_b),
3848         SH_PFC_PIN_GROUP(hscif3_data_c),
3849         SH_PFC_PIN_GROUP(hscif3_clk_c),
3850         SH_PFC_PIN_GROUP(hscif3_ctrl_c),
3851         SH_PFC_PIN_GROUP(hscif3_data_d),
3852         SH_PFC_PIN_GROUP(hscif3_data_e),
3853         SH_PFC_PIN_GROUP(hscif3_ctrl_e),
3854         SH_PFC_PIN_GROUP(hscif4_data_a),
3855         SH_PFC_PIN_GROUP(hscif4_clk_a),
3856         SH_PFC_PIN_GROUP(hscif4_ctrl_a),
3857         SH_PFC_PIN_GROUP(hscif4_data_b),
3858         SH_PFC_PIN_GROUP(hscif4_clk_b),
3859         SH_PFC_PIN_GROUP(hscif4_data_c),
3860         SH_PFC_PIN_GROUP(hscif4_data_d),
3861         SH_PFC_PIN_GROUP(hscif4_data_e),
3862         SH_PFC_PIN_GROUP(i2c1_a),
3863         SH_PFC_PIN_GROUP(i2c1_b),
3864         SH_PFC_PIN_GROUP(i2c1_c),
3865         SH_PFC_PIN_GROUP(i2c1_d),
3866         SH_PFC_PIN_GROUP(i2c2_a),
3867         SH_PFC_PIN_GROUP(i2c2_b),
3868         SH_PFC_PIN_GROUP(i2c2_c),
3869         SH_PFC_PIN_GROUP(i2c2_d),
3870         SH_PFC_PIN_GROUP(i2c2_e),
3871         SH_PFC_PIN_GROUP(i2c4),
3872         SH_PFC_PIN_GROUP(i2c5),
3873         SH_PFC_PIN_GROUP(i2c6_a),
3874         SH_PFC_PIN_GROUP(i2c6_b),
3875         SH_PFC_PIN_GROUP(i2c7_a),
3876         SH_PFC_PIN_GROUP(i2c7_b),
3877         SH_PFC_PIN_GROUP(intc_ex_irq0),
3878         SH_PFC_PIN_GROUP(intc_ex_irq1),
3879         SH_PFC_PIN_GROUP(intc_ex_irq2),
3880         SH_PFC_PIN_GROUP(intc_ex_irq3),
3881         SH_PFC_PIN_GROUP(intc_ex_irq4),
3882         SH_PFC_PIN_GROUP(intc_ex_irq5),
3883         SH_PFC_PIN_GROUP(msiof0_clk),
3884         SH_PFC_PIN_GROUP(msiof0_sync),
3885         SH_PFC_PIN_GROUP(msiof0_ss1),
3886         SH_PFC_PIN_GROUP(msiof0_ss2),
3887         SH_PFC_PIN_GROUP(msiof0_txd),
3888         SH_PFC_PIN_GROUP(msiof0_rxd),
3889         SH_PFC_PIN_GROUP(msiof1_clk),
3890         SH_PFC_PIN_GROUP(msiof1_sync),
3891         SH_PFC_PIN_GROUP(msiof1_ss1),
3892         SH_PFC_PIN_GROUP(msiof1_ss2),
3893         SH_PFC_PIN_GROUP(msiof1_txd),
3894         SH_PFC_PIN_GROUP(msiof1_rxd),
3895         SH_PFC_PIN_GROUP(msiof2_clk_a),
3896         SH_PFC_PIN_GROUP(msiof2_sync_a),
3897         SH_PFC_PIN_GROUP(msiof2_ss1_a),
3898         SH_PFC_PIN_GROUP(msiof2_ss2_a),
3899         SH_PFC_PIN_GROUP(msiof2_txd_a),
3900         SH_PFC_PIN_GROUP(msiof2_rxd_a),
3901         SH_PFC_PIN_GROUP(msiof2_clk_b),
3902         SH_PFC_PIN_GROUP(msiof2_sync_b),
3903         SH_PFC_PIN_GROUP(msiof2_ss1_b),
3904         SH_PFC_PIN_GROUP(msiof2_ss2_b),
3905         SH_PFC_PIN_GROUP(msiof2_txd_b),
3906         SH_PFC_PIN_GROUP(msiof2_rxd_b),
3907         SH_PFC_PIN_GROUP(msiof3_clk_a),
3908         SH_PFC_PIN_GROUP(msiof3_sync_a),
3909         SH_PFC_PIN_GROUP(msiof3_ss1_a),
3910         SH_PFC_PIN_GROUP(msiof3_ss2_a),
3911         SH_PFC_PIN_GROUP(msiof3_txd_a),
3912         SH_PFC_PIN_GROUP(msiof3_rxd_a),
3913         SH_PFC_PIN_GROUP(msiof3_clk_b),
3914         SH_PFC_PIN_GROUP(msiof3_sync_b),
3915         SH_PFC_PIN_GROUP(msiof3_ss1_b),
3916         SH_PFC_PIN_GROUP(msiof3_txd_b),
3917         SH_PFC_PIN_GROUP(msiof3_rxd_b),
3918         SH_PFC_PIN_GROUP(pwm0_a),
3919         SH_PFC_PIN_GROUP(pwm0_b),
3920         SH_PFC_PIN_GROUP(pwm1_a),
3921         SH_PFC_PIN_GROUP(pwm1_b),
3922         SH_PFC_PIN_GROUP(pwm2_a),
3923         SH_PFC_PIN_GROUP(pwm2_b),
3924         SH_PFC_PIN_GROUP(pwm2_c),
3925         SH_PFC_PIN_GROUP(pwm3_a),
3926         SH_PFC_PIN_GROUP(pwm3_b),
3927         SH_PFC_PIN_GROUP(pwm3_c),
3928         SH_PFC_PIN_GROUP(pwm4_a),
3929         SH_PFC_PIN_GROUP(pwm4_b),
3930         SH_PFC_PIN_GROUP(pwm5_a),
3931         SH_PFC_PIN_GROUP(pwm5_b),
3932         SH_PFC_PIN_GROUP(pwm6_a),
3933         SH_PFC_PIN_GROUP(pwm6_b),
3934         SH_PFC_PIN_GROUP(qspi0_ctrl),
3935         SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
3936         SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
3937         SH_PFC_PIN_GROUP(qspi1_ctrl),
3938         SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
3939         SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
3940         BUS_DATA_PIN_GROUP(rpc_clk, 1),
3941         BUS_DATA_PIN_GROUP(rpc_clk, 2),
3942         SH_PFC_PIN_GROUP(rpc_ctrl),
3943         SH_PFC_PIN_GROUP(rpc_data),
3944         SH_PFC_PIN_GROUP(rpc_reset),
3945         SH_PFC_PIN_GROUP(rpc_int),
3946         SH_PFC_PIN_GROUP(scif0_data_a),
3947         SH_PFC_PIN_GROUP(scif0_clk_a),
3948         SH_PFC_PIN_GROUP(scif0_ctrl_a),
3949         SH_PFC_PIN_GROUP(scif0_data_b),
3950         SH_PFC_PIN_GROUP(scif0_clk_b),
3951         SH_PFC_PIN_GROUP(scif1_data),
3952         SH_PFC_PIN_GROUP(scif1_clk),
3953         SH_PFC_PIN_GROUP(scif1_ctrl),
3954         SH_PFC_PIN_GROUP(scif2_data_a),
3955         SH_PFC_PIN_GROUP(scif2_clk_a),
3956         SH_PFC_PIN_GROUP(scif2_data_b),
3957         SH_PFC_PIN_GROUP(scif3_data_a),
3958         SH_PFC_PIN_GROUP(scif3_clk_a),
3959         SH_PFC_PIN_GROUP(scif3_ctrl_a),
3960         SH_PFC_PIN_GROUP(scif3_data_b),
3961         SH_PFC_PIN_GROUP(scif3_data_c),
3962         SH_PFC_PIN_GROUP(scif3_clk_c),
3963         SH_PFC_PIN_GROUP(scif4_data_a),
3964         SH_PFC_PIN_GROUP(scif4_clk_a),
3965         SH_PFC_PIN_GROUP(scif4_ctrl_a),
3966         SH_PFC_PIN_GROUP(scif4_data_b),
3967         SH_PFC_PIN_GROUP(scif4_clk_b),
3968         SH_PFC_PIN_GROUP(scif4_data_c),
3969         SH_PFC_PIN_GROUP(scif4_ctrl_c),
3970         SH_PFC_PIN_GROUP(scif5_data_a),
3971         SH_PFC_PIN_GROUP(scif5_clk_a),
3972         SH_PFC_PIN_GROUP(scif5_data_b),
3973         SH_PFC_PIN_GROUP(scif5_data_c),
3974         SH_PFC_PIN_GROUP(scif_clk_a),
3975         SH_PFC_PIN_GROUP(scif_clk_b),
3976         BUS_DATA_PIN_GROUP(sdhi0_data, 1),
3977         BUS_DATA_PIN_GROUP(sdhi0_data, 4),
3978         SH_PFC_PIN_GROUP(sdhi0_ctrl),
3979         SH_PFC_PIN_GROUP(sdhi0_cd),
3980         SH_PFC_PIN_GROUP(sdhi0_wp),
3981         BUS_DATA_PIN_GROUP(sdhi1_data, 1),
3982         BUS_DATA_PIN_GROUP(sdhi1_data, 4),
3983         SH_PFC_PIN_GROUP(sdhi1_ctrl),
3984         SH_PFC_PIN_GROUP(sdhi1_cd),
3985         SH_PFC_PIN_GROUP(sdhi1_wp),
3986         BUS_DATA_PIN_GROUP(sdhi3_data, 1),
3987         BUS_DATA_PIN_GROUP(sdhi3_data, 4),
3988         BUS_DATA_PIN_GROUP(sdhi3_data, 8),
3989         SH_PFC_PIN_GROUP(sdhi3_ctrl),
3990         SH_PFC_PIN_GROUP(sdhi3_cd),
3991         SH_PFC_PIN_GROUP(sdhi3_wp),
3992         SH_PFC_PIN_GROUP(sdhi3_ds),
3993         SH_PFC_PIN_GROUP(ssi0_data),
3994         SH_PFC_PIN_GROUP(ssi01239_ctrl),
3995         SH_PFC_PIN_GROUP(ssi1_data),
3996         SH_PFC_PIN_GROUP(ssi1_ctrl),
3997         SH_PFC_PIN_GROUP(ssi2_data),
3998         SH_PFC_PIN_GROUP(ssi2_ctrl_a),
3999         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4000         SH_PFC_PIN_GROUP(ssi3_data),
4001         SH_PFC_PIN_GROUP(ssi349_ctrl),
4002         SH_PFC_PIN_GROUP(ssi4_data),
4003         SH_PFC_PIN_GROUP(ssi4_ctrl),
4004         SH_PFC_PIN_GROUP(ssi5_data),
4005         SH_PFC_PIN_GROUP(ssi5_ctrl),
4006         SH_PFC_PIN_GROUP(ssi6_data),
4007         SH_PFC_PIN_GROUP(ssi6_ctrl),
4008         SH_PFC_PIN_GROUP(ssi7_data),
4009         SH_PFC_PIN_GROUP(ssi78_ctrl),
4010         SH_PFC_PIN_GROUP(ssi8_data),
4011         SH_PFC_PIN_GROUP(ssi9_data),
4012         SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4013         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4014         SH_PFC_PIN_GROUP(tmu_tclk1_a),
4015         SH_PFC_PIN_GROUP(tmu_tclk1_b),
4016         SH_PFC_PIN_GROUP(tmu_tclk2_a),
4017         SH_PFC_PIN_GROUP(tmu_tclk2_b),
4018         SH_PFC_PIN_GROUP(usb0_a),
4019         SH_PFC_PIN_GROUP(usb0_b),
4020         SH_PFC_PIN_GROUP(usb0_id),
4021         SH_PFC_PIN_GROUP(usb30),
4022         SH_PFC_PIN_GROUP(usb30_id),
4023         BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
4024         BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
4025         BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
4026         BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
4027         SH_PFC_PIN_GROUP(vin4_data18_a),
4028         BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
4029         BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
4030         BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
4031         BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
4032         BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
4033         BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
4034         SH_PFC_PIN_GROUP(vin4_data18_b),
4035         BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
4036         BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
4037         SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
4038         SH_PFC_PIN_GROUP(vin4_sync),
4039         SH_PFC_PIN_GROUP(vin4_field),
4040         SH_PFC_PIN_GROUP(vin4_clkenb),
4041         SH_PFC_PIN_GROUP(vin4_clk),
4042         BUS_DATA_PIN_GROUP(vin5_data, 8, _a),
4043         BUS_DATA_PIN_GROUP(vin5_data, 10, _a),
4044         BUS_DATA_PIN_GROUP(vin5_data, 12, _a),
4045         BUS_DATA_PIN_GROUP(vin5_data, 16, _a),
4046         SH_PFC_PIN_GROUP(vin5_data8_b),
4047         SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data_a, 8, 8),
4048         SH_PFC_PIN_GROUP(vin5_sync_a),
4049         SH_PFC_PIN_GROUP(vin5_field_a),
4050         SH_PFC_PIN_GROUP(vin5_clkenb_a),
4051         SH_PFC_PIN_GROUP(vin5_clk_a),
4052         SH_PFC_PIN_GROUP(vin5_clk_b),
4053     },
4054 #ifdef CONFIG_PINCTRL_PFC_R8A77990
4055     .automotive = {
4056         SH_PFC_PIN_GROUP(drif0_ctrl_a),
4057         SH_PFC_PIN_GROUP(drif0_data0_a),
4058         SH_PFC_PIN_GROUP(drif0_data1_a),
4059         SH_PFC_PIN_GROUP(drif0_ctrl_b),
4060         SH_PFC_PIN_GROUP(drif0_data0_b),
4061         SH_PFC_PIN_GROUP(drif0_data1_b),
4062         SH_PFC_PIN_GROUP(drif1_ctrl),
4063         SH_PFC_PIN_GROUP(drif1_data0),
4064         SH_PFC_PIN_GROUP(drif1_data1),
4065         SH_PFC_PIN_GROUP(drif2_ctrl_a),
4066         SH_PFC_PIN_GROUP(drif2_data0_a),
4067         SH_PFC_PIN_GROUP(drif2_data1_a),
4068         SH_PFC_PIN_GROUP(drif2_ctrl_b),
4069         SH_PFC_PIN_GROUP(drif2_data0_b),
4070         SH_PFC_PIN_GROUP(drif2_data1_b),
4071         SH_PFC_PIN_GROUP(drif3_ctrl_a),
4072         SH_PFC_PIN_GROUP(drif3_data0_a),
4073         SH_PFC_PIN_GROUP(drif3_data1_a),
4074         SH_PFC_PIN_GROUP(drif3_ctrl_b),
4075         SH_PFC_PIN_GROUP(drif3_data0_b),
4076         SH_PFC_PIN_GROUP(drif3_data1_b),
4077         SH_PFC_PIN_GROUP(mlb_3pin),
4078     }
4079 #endif /* CONFIG_PINCTRL_PFC_R8A77990 */
4080 };
4081
4082 static const char * const audio_clk_groups[] = {
4083     "audio_clk_a",
4084     "audio_clk_b_a",
4085     "audio_clk_b_b",
4086     "audio_clk_b_c",
4087     "audio_clk_c_a",
4088     "audio_clk_c_b",
4089     "audio_clk_c_c",
4090     "audio_clkout_a",
4091     "audio_clkout_b",
4092     "audio_clkout1_a",
4093     "audio_clkout1_b",
4094     "audio_clkout1_c",
4095     "audio_clkout2_a",
4096     "audio_clkout2_b",
4097     "audio_clkout2_c",
4098     "audio_clkout3_a",
4099     "audio_clkout3_b",
4100     "audio_clkout3_c",
4101 };
4102
4103 static const char * const avb_groups[] = {
4104     "avb_link",
4105     "avb_magic",
4106     "avb_phy_int",
4107     "avb_mii",
4108     "avb_avtp_pps",
4109     "avb_avtp_match",
4110     "avb_avtp_capture",
4111 };
4112
4113 static const char * const can0_groups[] = {
4114     "can0_data",
4115 };
4116
4117 static const char * const can1_groups[] = {
4118     "can1_data",
4119 };
4120
4121 static const char * const can_clk_groups[] = {
4122     "can_clk",
4123 };
4124
4125 static const char * const canfd0_groups[] = {
4126     "canfd0_data",
4127 };
4128
4129 static const char * const canfd1_groups[] = {
4130     "canfd1_data",
4131 };
4132
4133 #ifdef CONFIG_PINCTRL_PFC_R8A77990
4134 static const char * const drif0_groups[] = {
4135     "drif0_ctrl_a",
4136     "drif0_data0_a",
4137     "drif0_data1_a",
4138     "drif0_ctrl_b",
4139     "drif0_data0_b",
4140     "drif0_data1_b",
4141 };
4142
4143 static const char * const drif1_groups[] = {
4144     "drif1_ctrl",
4145     "drif1_data0",
4146     "drif1_data1",
4147 };
4148
4149 static const char * const drif2_groups[] = {
4150     "drif2_ctrl_a",
4151     "drif2_data0_a",
4152     "drif2_data1_a",
4153     "drif2_ctrl_b",
4154     "drif2_data0_b",
4155     "drif2_data1_b",
4156 };
4157
4158 static const char * const drif3_groups[] = {
4159     "drif3_ctrl_a",
4160     "drif3_data0_a",
4161     "drif3_data1_a",
4162     "drif3_ctrl_b",
4163     "drif3_data0_b",
4164     "drif3_data1_b",
4165 };
4166 #endif /* CONFIG_PINCTRL_PFC_R8A77990 */
4167
4168 static const char * const du_groups[] = {
4169     "du_rgb666",
4170     "du_rgb888",
4171     "du_clk_in_0",
4172     "du_clk_in_1",
4173     "du_clk_out_0",
4174     "du_sync",
4175     "du_disp_cde",
4176     "du_cde",
4177     "du_disp",
4178 };
4179
4180 static const char * const hscif0_groups[] = {
4181     "hscif0_data_a",
4182     "hscif0_clk_a",
4183     "hscif0_ctrl_a",
4184     "hscif0_data_b",
4185     "hscif0_clk_b",
4186 };
4187
4188 static const char * const hscif1_groups[] = {
4189     "hscif1_data_a",
4190     "hscif1_clk_a",
4191     "hscif1_data_b",
4192     "hscif1_clk_b",
4193     "hscif1_ctrl_b",
4194 };
4195
4196 static const char * const hscif2_groups[] = {
4197     "hscif2_data_a",
4198     "hscif2_clk_a",
4199     "hscif2_ctrl_a",
4200     "hscif2_data_b",
4201 };
4202
4203 static const char * const hscif3_groups[] = {
4204     "hscif3_data_a",
4205     "hscif3_data_b",
4206     "hscif3_clk_b",
4207     "hscif3_data_c",
4208     "hscif3_clk_c",
4209     "hscif3_ctrl_c",
4210     "hscif3_data_d",
4211     "hscif3_data_e",
4212     "hscif3_ctrl_e",
4213 };
4214
4215 static const char * const hscif4_groups[] = {
4216     "hscif4_data_a",
4217     "hscif4_clk_a",
4218     "hscif4_ctrl_a",
4219     "hscif4_data_b",
4220     "hscif4_clk_b",
4221     "hscif4_data_c",
4222     "hscif4_data_d",
4223     "hscif4_data_e",
4224 };
4225
4226 static const char * const i2c1_groups[] = {
4227     "i2c1_a",
4228     "i2c1_b",
4229     "i2c1_c",
4230     "i2c1_d",
4231 };
4232
4233 static const char * const i2c2_groups[] = {
4234     "i2c2_a",
4235     "i2c2_b",
4236     "i2c2_c",
4237     "i2c2_d",
4238     "i2c2_e",
4239 };
4240
4241 static const char * const i2c4_groups[] = {
4242     "i2c4",
4243 };
4244
4245 static const char * const i2c5_groups[] = {
4246     "i2c5",
4247 };
4248
4249 static const char * const i2c6_groups[] = {
4250     "i2c6_a",
4251     "i2c6_b",
4252 };
4253
4254 static const char * const i2c7_groups[] = {
4255     "i2c7_a",
4256     "i2c7_b",
4257 };
4258
4259 static const char * const intc_ex_groups[] = {
4260     "intc_ex_irq0",
4261     "intc_ex_irq1",
4262     "intc_ex_irq2",
4263     "intc_ex_irq3",
4264     "intc_ex_irq4",
4265     "intc_ex_irq5",
4266 };
4267
4268 #ifdef CONFIG_PINCTRL_PFC_R8A77990
4269 static const char * const mlb_3pin_groups[] = {
4270     "mlb_3pin",
4271 };
4272 #endif /* CONFIG_PINCTRL_PFC_R8A77990 */
4273
4274 static const char * const msiof0_groups[] = {
4275     "msiof0_clk",
4276     "msiof0_sync",
4277     "msiof0_ss1",
4278     "msiof0_ss2",
4279     "msiof0_txd",
4280     "msiof0_rxd",
4281 };
4282
4283 static const char * const msiof1_groups[] = {
4284     "msiof1_clk",
4285     "msiof1_sync",
4286     "msiof1_ss1",
4287     "msiof1_ss2",
4288     "msiof1_txd",
4289     "msiof1_rxd",
4290 };
4291
4292 static const char * const msiof2_groups[] = {
4293     "msiof2_clk_a",
4294     "msiof2_sync_a",
4295     "msiof2_ss1_a",
4296     "msiof2_ss2_a",
4297     "msiof2_txd_a",
4298     "msiof2_rxd_a",
4299     "msiof2_clk_b",
4300     "msiof2_sync_b",
4301     "msiof2_ss1_b",
4302     "msiof2_ss2_b",
4303     "msiof2_txd_b",
4304     "msiof2_rxd_b",
4305 };
4306
4307 static const char * const msiof3_groups[] = {
4308     "msiof3_clk_a",
4309     "msiof3_sync_a",
4310     "msiof3_ss1_a",
4311     "msiof3_ss2_a",
4312     "msiof3_txd_a",
4313     "msiof3_rxd_a",
4314     "msiof3_clk_b",
4315     "msiof3_sync_b",
4316     "msiof3_ss1_b",
4317     "msiof3_txd_b",
4318     "msiof3_rxd_b",
4319 };
4320
4321 static const char * const pwm0_groups[] = {
4322     "pwm0_a",
4323     "pwm0_b",
4324 };
4325
4326 static const char * const pwm1_groups[] = {
4327     "pwm1_a",
4328     "pwm1_b",
4329 };
4330
4331 static const char * const pwm2_groups[] = {
4332     "pwm2_a",
4333     "pwm2_b",
4334     "pwm2_c",
4335 };
4336
4337 static const char * const pwm3_groups[] = {
4338     "pwm3_a",
4339     "pwm3_b",
4340     "pwm3_c",
4341 };
4342
4343 static const char * const pwm4_groups[] = {
4344     "pwm4_a",
4345     "pwm4_b",
4346 };
4347
4348 static const char * const pwm5_groups[] = {
4349     "pwm5_a",
4350     "pwm5_b",
4351 };
4352
4353 static const char * const pwm6_groups[] = {
4354     "pwm6_a",
4355     "pwm6_b",
4356 };
4357
4358 static const char * const qspi0_groups[] = {
4359     "qspi0_ctrl",
4360     "qspi0_data2",
4361     "qspi0_data4",
4362 };
4363
4364 static const char * const qspi1_groups[] = {
4365     "qspi1_ctrl",
4366     "qspi1_data2",
4367     "qspi1_data4",
4368 };
4369
4370 static const char * const rpc_groups[] = {
4371     "rpc_clk1",
4372     "rpc_clk2",
4373     "rpc_ctrl",
4374     "rpc_data",
4375     "rpc_reset",
4376     "rpc_int",
4377 };
4378
4379 static const char * const scif0_groups[] = {
4380     "scif0_data_a",
4381     "scif0_clk_a",
4382     "scif0_ctrl_a",
4383     "scif0_data_b",
4384     "scif0_clk_b",
4385 };
4386
4387 static const char * const scif1_groups[] = {
4388     "scif1_data",
4389     "scif1_clk",
4390     "scif1_ctrl",
4391 };
4392
4393 static const char * const scif2_groups[] = {
4394     "scif2_data_a",
4395     "scif2_clk_a",
4396     "scif2_data_b",
4397 };
4398
4399 static const char * const scif3_groups[] = {
4400     "scif3_data_a",
4401     "scif3_clk_a",
4402     "scif3_ctrl_a",
4403     "scif3_data_b",
4404     "scif3_data_c",
4405     "scif3_clk_c",
4406 };
4407
4408 static const char * const scif4_groups[] = {
4409     "scif4_data_a",
4410     "scif4_clk_a",
4411     "scif4_ctrl_a",
4412     "scif4_data_b",
4413     "scif4_clk_b",
4414     "scif4_data_c",
4415     "scif4_ctrl_c",
4416 };
4417
4418 static const char * const scif5_groups[] = {
4419     "scif5_data_a",
4420     "scif5_clk_a",
4421     "scif5_data_b",
4422     "scif5_data_c",
4423 };
4424
4425 static const char * const scif_clk_groups[] = {
4426     "scif_clk_a",
4427     "scif_clk_b",
4428 };
4429
4430 static const char * const sdhi0_groups[] = {
4431     "sdhi0_data1",
4432     "sdhi0_data4",
4433     "sdhi0_ctrl",
4434     "sdhi0_cd",
4435     "sdhi0_wp",
4436 };
4437
4438 static const char * const sdhi1_groups[] = {
4439     "sdhi1_data1",
4440     "sdhi1_data4",
4441     "sdhi1_ctrl",
4442     "sdhi1_cd",
4443     "sdhi1_wp",
4444 };
4445
4446 static const char * const sdhi3_groups[] = {
4447     "sdhi3_data1",
4448     "sdhi3_data4",
4449     "sdhi3_data8",
4450     "sdhi3_ctrl",
4451     "sdhi3_cd",
4452     "sdhi3_wp",
4453     "sdhi3_ds",
4454 };
4455
4456 static const char * const ssi_groups[] = {
4457     "ssi0_data",
4458     "ssi01239_ctrl",
4459     "ssi1_data",
4460     "ssi1_ctrl",
4461     "ssi2_data",
4462     "ssi2_ctrl_a",
4463     "ssi2_ctrl_b",
4464     "ssi3_data",
4465     "ssi349_ctrl",
4466     "ssi4_data",
4467     "ssi4_ctrl",
4468     "ssi5_data",
4469     "ssi5_ctrl",
4470     "ssi6_data",
4471     "ssi6_ctrl",
4472     "ssi7_data",
4473     "ssi78_ctrl",
4474     "ssi8_data",
4475     "ssi9_data",
4476     "ssi9_ctrl_a",
4477     "ssi9_ctrl_b",
4478 };
4479
4480 static const char * const tmu_groups[] = {
4481     "tmu_tclk1_a",
4482     "tmu_tclk1_b",
4483     "tmu_tclk2_a",
4484     "tmu_tclk2_b",
4485 };
4486
4487 static const char * const usb0_groups[] = {
4488     "usb0_a",
4489     "usb0_b",
4490     "usb0_id",
4491 };
4492
4493 static const char * const usb30_groups[] = {
4494     "usb30",
4495     "usb30_id",
4496 };
4497
4498 static const char * const vin4_groups[] = {
4499     "vin4_data8_a",
4500     "vin4_data10_a",
4501     "vin4_data12_a",
4502     "vin4_data16_a",
4503     "vin4_data18_a",
4504     "vin4_data20_a",
4505     "vin4_data24_a",
4506     "vin4_data8_b",
4507     "vin4_data10_b",
4508     "vin4_data12_b",
4509     "vin4_data16_b",
4510     "vin4_data18_b",
4511     "vin4_data20_b",
4512     "vin4_data24_b",
4513     "vin4_g8",
4514     "vin4_sync",
4515     "vin4_field",
4516     "vin4_clkenb",
4517     "vin4_clk",
4518 };
4519
4520 static const char * const vin5_groups[] = {
4521     "vin5_data8_a",
4522     "vin5_data10_a",
4523     "vin5_data12_a",
4524     "vin5_data16_a",
4525     "vin5_data8_b",
4526     "vin5_high8",
4527     "vin5_sync_a",
4528     "vin5_field_a",
4529     "vin5_clkenb_a",
4530     "vin5_clk_a",
4531     "vin5_clk_b",
4532 };
4533
4534 static const struct {
4535     struct sh_pfc_function common[50];
4536 #ifdef CONFIG_PINCTRL_PFC_R8A77990
4537     struct sh_pfc_function automotive[5];
4538 #endif
4539 } pinmux_functions = {
4540     .common = {
4541         SH_PFC_FUNCTION(audio_clk),
4542         SH_PFC_FUNCTION(avb),
4543         SH_PFC_FUNCTION(can0),
4544         SH_PFC_FUNCTION(can1),
4545         SH_PFC_FUNCTION(can_clk),
4546         SH_PFC_FUNCTION(canfd0),
4547         SH_PFC_FUNCTION(canfd1),
4548         SH_PFC_FUNCTION(du),
4549         SH_PFC_FUNCTION(hscif0),
4550         SH_PFC_FUNCTION(hscif1),
4551         SH_PFC_FUNCTION(hscif2),
4552         SH_PFC_FUNCTION(hscif3),
4553         SH_PFC_FUNCTION(hscif4),
4554         SH_PFC_FUNCTION(i2c1),
4555         SH_PFC_FUNCTION(i2c2),
4556         SH_PFC_FUNCTION(i2c4),
4557         SH_PFC_FUNCTION(i2c5),
4558         SH_PFC_FUNCTION(i2c6),
4559         SH_PFC_FUNCTION(i2c7),
4560         SH_PFC_FUNCTION(intc_ex),
4561         SH_PFC_FUNCTION(msiof0),
4562         SH_PFC_FUNCTION(msiof1),
4563         SH_PFC_FUNCTION(msiof2),
4564         SH_PFC_FUNCTION(msiof3),
4565         SH_PFC_FUNCTION(pwm0),
4566         SH_PFC_FUNCTION(pwm1),
4567         SH_PFC_FUNCTION(pwm2),
4568         SH_PFC_FUNCTION(pwm3),
4569         SH_PFC_FUNCTION(pwm4),
4570         SH_PFC_FUNCTION(pwm5),
4571         SH_PFC_FUNCTION(pwm6),
4572         SH_PFC_FUNCTION(qspi0),
4573         SH_PFC_FUNCTION(qspi1),
4574         SH_PFC_FUNCTION(rpc),
4575         SH_PFC_FUNCTION(scif0),
4576         SH_PFC_FUNCTION(scif1),
4577         SH_PFC_FUNCTION(scif2),
4578         SH_PFC_FUNCTION(scif3),
4579         SH_PFC_FUNCTION(scif4),
4580         SH_PFC_FUNCTION(scif5),
4581         SH_PFC_FUNCTION(scif_clk),
4582         SH_PFC_FUNCTION(sdhi0),
4583         SH_PFC_FUNCTION(sdhi1),
4584         SH_PFC_FUNCTION(sdhi3),
4585         SH_PFC_FUNCTION(ssi),
4586         SH_PFC_FUNCTION(tmu),
4587         SH_PFC_FUNCTION(usb0),
4588         SH_PFC_FUNCTION(usb30),
4589         SH_PFC_FUNCTION(vin4),
4590         SH_PFC_FUNCTION(vin5),
4591     },
4592 #ifdef CONFIG_PINCTRL_PFC_R8A77990
4593     .automotive = {
4594         SH_PFC_FUNCTION(drif0),
4595         SH_PFC_FUNCTION(drif1),
4596         SH_PFC_FUNCTION(drif2),
4597         SH_PFC_FUNCTION(drif3),
4598         SH_PFC_FUNCTION(mlb_3pin),
4599     }
4600 #endif /* CONFIG_PINCTRL_PFC_R8A77990 */
4601 };
4602
4603 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4604 #define F_(x, y)    FN_##y
4605 #define FM(x)       FN_##x
4606     { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
4607                  GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
4608                    1, 1, 1, 1, 1, 1, 1),
4609                  GROUP(
4610         /* GP0_31_18 RESERVED */
4611         GP_0_17_FN, GPSR0_17,
4612         GP_0_16_FN, GPSR0_16,
4613         GP_0_15_FN, GPSR0_15,
4614         GP_0_14_FN, GPSR0_14,
4615         GP_0_13_FN, GPSR0_13,
4616         GP_0_12_FN, GPSR0_12,
4617         GP_0_11_FN, GPSR0_11,
4618         GP_0_10_FN, GPSR0_10,
4619         GP_0_9_FN,  GPSR0_9,
4620         GP_0_8_FN,  GPSR0_8,
4621         GP_0_7_FN,  GPSR0_7,
4622         GP_0_6_FN,  GPSR0_6,
4623         GP_0_5_FN,  GPSR0_5,
4624         GP_0_4_FN,  GPSR0_4,
4625         GP_0_3_FN,  GPSR0_3,
4626         GP_0_2_FN,  GPSR0_2,
4627         GP_0_1_FN,  GPSR0_1,
4628         GP_0_0_FN,  GPSR0_0, ))
4629     },
4630     { PINMUX_CFG_REG_VAR("GPSR1", 0xe6060104, 32,
4631                  GROUP(-9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
4632                    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
4633                  GROUP(
4634         /* GP1_31_23 RESERVED */
4635         GP_1_22_FN, GPSR1_22,
4636         GP_1_21_FN, GPSR1_21,
4637         GP_1_20_FN, GPSR1_20,
4638         GP_1_19_FN, GPSR1_19,
4639         GP_1_18_FN, GPSR1_18,
4640         GP_1_17_FN, GPSR1_17,
4641         GP_1_16_FN, GPSR1_16,
4642         GP_1_15_FN, GPSR1_15,
4643         GP_1_14_FN, GPSR1_14,
4644         GP_1_13_FN, GPSR1_13,
4645         GP_1_12_FN, GPSR1_12,
4646         GP_1_11_FN, GPSR1_11,
4647         GP_1_10_FN, GPSR1_10,
4648         GP_1_9_FN,  GPSR1_9,
4649         GP_1_8_FN,  GPSR1_8,
4650         GP_1_7_FN,  GPSR1_7,
4651         GP_1_6_FN,  GPSR1_6,
4652         GP_1_5_FN,  GPSR1_5,
4653         GP_1_4_FN,  GPSR1_4,
4654         GP_1_3_FN,  GPSR1_3,
4655         GP_1_2_FN,  GPSR1_2,
4656         GP_1_1_FN,  GPSR1_1,
4657         GP_1_0_FN,  GPSR1_0, ))
4658     },
4659     { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
4660         0, 0,
4661         0, 0,
4662         0, 0,
4663         0, 0,
4664         0, 0,
4665         0, 0,
4666         GP_2_25_FN, GPSR2_25,
4667         GP_2_24_FN, GPSR2_24,
4668         GP_2_23_FN, GPSR2_23,
4669         GP_2_22_FN, GPSR2_22,
4670         GP_2_21_FN, GPSR2_21,
4671         GP_2_20_FN, GPSR2_20,
4672         GP_2_19_FN, GPSR2_19,
4673         GP_2_18_FN, GPSR2_18,
4674         GP_2_17_FN, GPSR2_17,
4675         GP_2_16_FN, GPSR2_16,
4676         GP_2_15_FN, GPSR2_15,
4677         GP_2_14_FN, GPSR2_14,
4678         GP_2_13_FN, GPSR2_13,
4679         GP_2_12_FN, GPSR2_12,
4680         GP_2_11_FN, GPSR2_11,
4681         GP_2_10_FN, GPSR2_10,
4682         GP_2_9_FN,  GPSR2_9,
4683         GP_2_8_FN,  GPSR2_8,
4684         GP_2_7_FN,  GPSR2_7,
4685         GP_2_6_FN,  GPSR2_6,
4686         GP_2_5_FN,  GPSR2_5,
4687         GP_2_4_FN,  GPSR2_4,
4688         GP_2_3_FN,  GPSR2_3,
4689         GP_2_2_FN,  GPSR2_2,
4690         GP_2_1_FN,  GPSR2_1,
4691         GP_2_0_FN,  GPSR2_0, ))
4692     },
4693     { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
4694                  GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
4695                    1, 1, 1, 1, 1),
4696                  GROUP(
4697         /* GP3_31_16 RESERVED */
4698         GP_3_15_FN, GPSR3_15,
4699         GP_3_14_FN, GPSR3_14,
4700         GP_3_13_FN, GPSR3_13,
4701         GP_3_12_FN, GPSR3_12,
4702         GP_3_11_FN, GPSR3_11,
4703         GP_3_10_FN, GPSR3_10,
4704         GP_3_9_FN,  GPSR3_9,
4705         GP_3_8_FN,  GPSR3_8,
4706         GP_3_7_FN,  GPSR3_7,
4707         GP_3_6_FN,  GPSR3_6,
4708         GP_3_5_FN,  GPSR3_5,
4709         GP_3_4_FN,  GPSR3_4,
4710         GP_3_3_FN,  GPSR3_3,
4711         GP_3_2_FN,  GPSR3_2,
4712         GP_3_1_FN,  GPSR3_1,
4713         GP_3_0_FN,  GPSR3_0, ))
4714     },
4715     { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
4716                  GROUP(-21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
4717                  GROUP(
4718         /* GP4_31_11 RESERVED */
4719         GP_4_10_FN, GPSR4_10,
4720         GP_4_9_FN,  GPSR4_9,
4721         GP_4_8_FN,  GPSR4_8,
4722         GP_4_7_FN,  GPSR4_7,
4723         GP_4_6_FN,  GPSR4_6,
4724         GP_4_5_FN,  GPSR4_5,
4725         GP_4_4_FN,  GPSR4_4,
4726         GP_4_3_FN,  GPSR4_3,
4727         GP_4_2_FN,  GPSR4_2,
4728         GP_4_1_FN,  GPSR4_1,
4729         GP_4_0_FN,  GPSR4_0, ))
4730     },
4731     { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
4732                  GROUP(-12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
4733                    1, 1, 1, 1, 1, 1, 1, 1, 1),
4734                  GROUP(
4735         /* GP5_31_20 RESERVED */
4736         GP_5_19_FN, GPSR5_19,
4737         GP_5_18_FN, GPSR5_18,
4738         GP_5_17_FN, GPSR5_17,
4739         GP_5_16_FN, GPSR5_16,
4740         GP_5_15_FN, GPSR5_15,
4741         GP_5_14_FN, GPSR5_14,
4742         GP_5_13_FN, GPSR5_13,
4743         GP_5_12_FN, GPSR5_12,
4744         GP_5_11_FN, GPSR5_11,
4745         GP_5_10_FN, GPSR5_10,
4746         GP_5_9_FN,  GPSR5_9,
4747         GP_5_8_FN,  GPSR5_8,
4748         GP_5_7_FN,  GPSR5_7,
4749         GP_5_6_FN,  GPSR5_6,
4750         GP_5_5_FN,  GPSR5_5,
4751         GP_5_4_FN,  GPSR5_4,
4752         GP_5_3_FN,  GPSR5_3,
4753         GP_5_2_FN,  GPSR5_2,
4754         GP_5_1_FN,  GPSR5_1,
4755         GP_5_0_FN,  GPSR5_0, ))
4756     },
4757     { PINMUX_CFG_REG_VAR("GPSR6", 0xe6060118, 32,
4758                  GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
4759                    1, 1, 1, 1, 1, 1, 1),
4760                  GROUP(
4761         /* GP6_31_18 RESERVED */
4762         GP_6_17_FN, GPSR6_17,
4763         GP_6_16_FN, GPSR6_16,
4764         GP_6_15_FN, GPSR6_15,
4765         GP_6_14_FN, GPSR6_14,
4766         GP_6_13_FN, GPSR6_13,
4767         GP_6_12_FN, GPSR6_12,
4768         GP_6_11_FN, GPSR6_11,
4769         GP_6_10_FN, GPSR6_10,
4770         GP_6_9_FN,  GPSR6_9,
4771         GP_6_8_FN,  GPSR6_8,
4772         GP_6_7_FN,  GPSR6_7,
4773         GP_6_6_FN,  GPSR6_6,
4774         GP_6_5_FN,  GPSR6_5,
4775         GP_6_4_FN,  GPSR6_4,
4776         GP_6_3_FN,  GPSR6_3,
4777         GP_6_2_FN,  GPSR6_2,
4778         GP_6_1_FN,  GPSR6_1,
4779         GP_6_0_FN,  GPSR6_0, ))
4780     },
4781 #undef F_
4782 #undef FM
4783
4784 #define F_(x, y)    x,
4785 #define FM(x)       FN_##x,
4786     { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
4787         IP0_31_28
4788         IP0_27_24
4789         IP0_23_20
4790         IP0_19_16
4791         IP0_15_12
4792         IP0_11_8
4793         IP0_7_4
4794         IP0_3_0 ))
4795     },
4796     { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
4797         IP1_31_28
4798         IP1_27_24
4799         IP1_23_20
4800         IP1_19_16
4801         IP1_15_12
4802         IP1_11_8
4803         IP1_7_4
4804         IP1_3_0 ))
4805     },
4806     { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
4807         IP2_31_28
4808         IP2_27_24
4809         IP2_23_20
4810         IP2_19_16
4811         IP2_15_12
4812         IP2_11_8
4813         IP2_7_4
4814         IP2_3_0 ))
4815     },
4816     { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
4817         IP3_31_28
4818         IP3_27_24
4819         IP3_23_20
4820         IP3_19_16
4821         IP3_15_12
4822         IP3_11_8
4823         IP3_7_4
4824         IP3_3_0 ))
4825     },
4826     { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
4827         IP4_31_28
4828         IP4_27_24
4829         IP4_23_20
4830         IP4_19_16
4831         IP4_15_12
4832         IP4_11_8
4833         IP4_7_4
4834         IP4_3_0 ))
4835     },
4836     { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
4837         IP5_31_28
4838         IP5_27_24
4839         IP5_23_20
4840         IP5_19_16
4841         IP5_15_12
4842         IP5_11_8
4843         IP5_7_4
4844         IP5_3_0 ))
4845     },
4846     { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
4847         IP6_31_28
4848         IP6_27_24
4849         IP6_23_20
4850         IP6_19_16
4851         IP6_15_12
4852         IP6_11_8
4853         IP6_7_4
4854         IP6_3_0 ))
4855     },
4856     { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
4857         IP7_31_28
4858         IP7_27_24
4859         IP7_23_20
4860         IP7_19_16
4861         IP7_15_12
4862         IP7_11_8
4863         IP7_7_4
4864         IP7_3_0 ))
4865     },
4866     { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
4867         IP8_31_28
4868         IP8_27_24
4869         IP8_23_20
4870         IP8_19_16
4871         IP8_15_12
4872         IP8_11_8
4873         IP8_7_4
4874         IP8_3_0 ))
4875     },
4876     { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
4877         IP9_31_28
4878         IP9_27_24
4879         IP9_23_20
4880         IP9_19_16
4881         IP9_15_12
4882         IP9_11_8
4883         IP9_7_4
4884         IP9_3_0 ))
4885     },
4886     { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
4887         IP10_31_28
4888         IP10_27_24
4889         IP10_23_20
4890         IP10_19_16
4891         IP10_15_12
4892         IP10_11_8
4893         IP10_7_4
4894         IP10_3_0 ))
4895     },
4896     { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
4897         IP11_31_28
4898         IP11_27_24
4899         IP11_23_20
4900         IP11_19_16
4901         IP11_15_12
4902         IP11_11_8
4903         IP11_7_4
4904         IP11_3_0 ))
4905     },
4906     { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
4907         IP12_31_28
4908         IP12_27_24
4909         IP12_23_20
4910         IP12_19_16
4911         IP12_15_12
4912         IP12_11_8
4913         IP12_7_4
4914         IP12_3_0 ))
4915     },
4916     { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
4917         IP13_31_28
4918         IP13_27_24
4919         IP13_23_20
4920         IP13_19_16
4921         IP13_15_12
4922         IP13_11_8
4923         IP13_7_4
4924         IP13_3_0 ))
4925     },
4926     { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
4927         IP14_31_28
4928         IP14_27_24
4929         IP14_23_20
4930         IP14_19_16
4931         IP14_15_12
4932         IP14_11_8
4933         IP14_7_4
4934         IP14_3_0 ))
4935     },
4936     { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
4937         IP15_31_28
4938         IP15_27_24
4939         IP15_23_20
4940         IP15_19_16
4941         IP15_15_12
4942         IP15_11_8
4943         IP15_7_4
4944         IP15_3_0 ))
4945     },
4946 #undef F_
4947 #undef FM
4948
4949 #define F_(x, y)    x,
4950 #define FM(x)       FN_##x,
4951     { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4952                  GROUP(-1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1,
4953                    1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2),
4954                  GROUP(
4955         /* RESERVED 31 */
4956         MOD_SEL0_30_29
4957         MOD_SEL0_28
4958         MOD_SEL0_27_26
4959         MOD_SEL0_25
4960         MOD_SEL0_24
4961         MOD_SEL0_23
4962         MOD_SEL0_22
4963         MOD_SEL0_21_20
4964         MOD_SEL0_19_18_17
4965         MOD_SEL0_16
4966         MOD_SEL0_15
4967         MOD_SEL0_14
4968         MOD_SEL0_13_12
4969         MOD_SEL0_11_10
4970         MOD_SEL0_9
4971         MOD_SEL0_8
4972         MOD_SEL0_7
4973         MOD_SEL0_6_5
4974         MOD_SEL0_4
4975         MOD_SEL0_3
4976         MOD_SEL0_2
4977         MOD_SEL0_1_0 ))
4978     },
4979     { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4980                  GROUP(1, 1, 1, 1, -1, 1, 1, 3, 3, 1, 1, 1,
4981                    1, 2, 2, 2, 1, 1, 2, 1, -4),
4982                  GROUP(
4983         MOD_SEL1_31
4984         MOD_SEL1_30
4985         MOD_SEL1_29
4986         MOD_SEL1_28
4987         /* RESERVED 27 */
4988         MOD_SEL1_26
4989         MOD_SEL1_25
4990         MOD_SEL1_24_23_22
4991         MOD_SEL1_21_20_19
4992         MOD_SEL1_18
4993         MOD_SEL1_17
4994         MOD_SEL1_16
4995         MOD_SEL1_15
4996         MOD_SEL1_14_13
4997         MOD_SEL1_12_11
4998         MOD_SEL1_10_9
4999         MOD_SEL1_8
5000         MOD_SEL1_7
5001         MOD_SEL1_6_5
5002         MOD_SEL1_4
5003         /* RESERVED 3, 2, 1, 0  */ ))
5004     },
5005     { },
5006 };
5007
5008 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5009     { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5010         { RCAR_GP_PIN(3,  0), 18, 2 },  /* SD0_CLK */
5011         { RCAR_GP_PIN(3,  1), 15, 2 },  /* SD0_CMD */
5012         { RCAR_GP_PIN(3,  2), 12, 2 },  /* SD0_DAT0 */
5013         { RCAR_GP_PIN(3,  3),  9, 2 },  /* SD0_DAT1 */
5014         { RCAR_GP_PIN(3,  4),  6, 2 },  /* SD0_DAT2 */
5015         { RCAR_GP_PIN(3,  5),  3, 2 },  /* SD0_DAT3 */
5016         { RCAR_GP_PIN(3,  6),  0, 2 },  /* SD1_CLK */
5017     } },
5018     { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5019         { RCAR_GP_PIN(3,  7), 29, 2 },  /* SD1_CMD */
5020         { RCAR_GP_PIN(3,  8), 26, 2 },  /* SD1_DAT0 */
5021         { RCAR_GP_PIN(3,  9), 23, 2 },  /* SD1_DAT1 */
5022         { RCAR_GP_PIN(3, 10), 20, 2 },  /* SD1_DAT2 */
5023         { RCAR_GP_PIN(3, 11), 17, 2 },  /* SD1_DAT3 */
5024         { RCAR_GP_PIN(4,  0), 14, 2 },  /* SD3_CLK */
5025         { RCAR_GP_PIN(4,  1), 11, 2 },  /* SD3_CMD */
5026         { RCAR_GP_PIN(4,  2),  8, 2 },  /* SD3_DAT0 */
5027         { RCAR_GP_PIN(4,  3),  5, 2 },  /* SD3_DAT1 */
5028         { RCAR_GP_PIN(4,  4),  2, 2 },  /* SD3_DAT2 */
5029     } },
5030     { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5031         { RCAR_GP_PIN(4,  5), 29, 2 },  /* SD3_DAT3 */
5032         { RCAR_GP_PIN(4,  6), 26, 2 },  /* SD3_DAT4 */
5033         { RCAR_GP_PIN(4,  7), 23, 2 },  /* SD3_DAT5 */
5034         { RCAR_GP_PIN(4,  8), 20, 2 },  /* SD3_DAT6 */
5035         { RCAR_GP_PIN(4,  9), 17, 2 },  /* SD3_DAT7 */
5036         { RCAR_GP_PIN(4, 10), 14, 2 },  /* SD3_DS */
5037     } },
5038     { },
5039 };
5040
5041 enum ioctrl_regs {
5042     POCCTRL0,
5043     TDSELCTRL,
5044 };
5045
5046 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5047     [POCCTRL0] = { 0xe6060380, },
5048     [TDSELCTRL] = { 0xe60603c0, },
5049     { /* sentinel */ },
5050 };
5051
5052 static int r8a77990_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
5053 {
5054     int bit = -EINVAL;
5055
5056     *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
5057
5058     if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5059         bit = pin & 0x1f;
5060
5061     if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
5062         bit = (pin & 0x1f) + 19;
5063
5064     return bit;
5065 }
5066
5067 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5068     { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5069          [0] = RCAR_GP_PIN(2, 23),  /* RD# */
5070          [1] = RCAR_GP_PIN(2, 22),  /* BS# */
5071          [2] = RCAR_GP_PIN(2, 21),  /* AVB_PHY_INT */
5072          [3] = PIN_AVB_MDC,     /* AVB_MDC */
5073          [4] = PIN_AVB_MDIO,        /* AVB_MDIO */
5074          [5] = RCAR_GP_PIN(2, 20),  /* AVB_TXCREFCLK */
5075          [6] = PIN_AVB_TD3,     /* AVB_TD3 */
5076          [7] = PIN_AVB_TD2,     /* AVB_TD2 */
5077          [8] = PIN_AVB_TD1,     /* AVB_TD1 */
5078          [9] = PIN_AVB_TD0,     /* AVB_TD0 */
5079         [10] = PIN_AVB_TXC,     /* AVB_TXC */
5080         [11] = PIN_AVB_TX_CTL,      /* AVB_TX_CTL */
5081         [12] = RCAR_GP_PIN(2, 19),  /* AVB_RD3 */
5082         [13] = RCAR_GP_PIN(2, 18),  /* AVB_RD2 */
5083         [14] = RCAR_GP_PIN(2, 17),  /* AVB_RD1 */
5084         [15] = RCAR_GP_PIN(2, 16),  /* AVB_RD0 */
5085         [16] = RCAR_GP_PIN(2, 15),  /* AVB_RXC */
5086         [17] = RCAR_GP_PIN(2, 14),  /* AVB_RX_CTL */
5087         [18] = RCAR_GP_PIN(2, 13),  /* RPC_RESET# */
5088         [19] = RCAR_GP_PIN(2, 12),  /* RPC_INT# */
5089         [20] = RCAR_GP_PIN(2, 11),  /* QSPI1_SSL */
5090         [21] = RCAR_GP_PIN(2, 10),  /* QSPI1_IO3 */
5091         [22] = RCAR_GP_PIN(2,  9),  /* QSPI1_IO2 */
5092         [23] = RCAR_GP_PIN(2,  8),  /* QSPI1_MISO/IO1 */
5093         [24] = RCAR_GP_PIN(2,  7),  /* QSPI1_MOSI/IO0 */
5094         [25] = RCAR_GP_PIN(2,  6),  /* QSPI1_SPCLK */
5095         [26] = RCAR_GP_PIN(2,  5),  /* QSPI0_SSL */
5096         [27] = RCAR_GP_PIN(2,  4),  /* QSPI0_IO3 */
5097         [28] = RCAR_GP_PIN(2,  3),  /* QSPI0_IO2 */
5098         [29] = RCAR_GP_PIN(2,  2),  /* QSPI0_MISO/IO1 */
5099         [30] = RCAR_GP_PIN(2,  1),  /* QSPI0_MOSI/IO0 */
5100         [31] = RCAR_GP_PIN(2,  0),  /* QSPI0_SPCLK */
5101     } },
5102     { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5103          [0] = RCAR_GP_PIN(0,  4),  /* D4 */
5104          [1] = RCAR_GP_PIN(0,  3),  /* D3 */
5105          [2] = RCAR_GP_PIN(0,  2),  /* D2 */
5106          [3] = RCAR_GP_PIN(0,  1),  /* D1 */
5107          [4] = RCAR_GP_PIN(0,  0),  /* D0 */
5108          [5] = RCAR_GP_PIN(1, 22),  /* WE0# */
5109          [6] = RCAR_GP_PIN(1, 21),  /* CS0# */
5110          [7] = RCAR_GP_PIN(1, 20),  /* CLKOUT */
5111          [8] = RCAR_GP_PIN(1, 19),  /* A19 */
5112          [9] = RCAR_GP_PIN(1, 18),  /* A18 */
5113         [10] = RCAR_GP_PIN(1, 17),  /* A17 */
5114         [11] = RCAR_GP_PIN(1, 16),  /* A16 */
5115         [12] = RCAR_GP_PIN(1, 15),  /* A15 */
5116         [13] = RCAR_GP_PIN(1, 14),  /* A14 */
5117         [14] = RCAR_GP_PIN(1, 13),  /* A13 */
5118         [15] = RCAR_GP_PIN(1, 12),  /* A12 */
5119         [16] = RCAR_GP_PIN(1, 11),  /* A11 */
5120         [17] = RCAR_GP_PIN(1, 10),  /* A10 */
5121         [18] = RCAR_GP_PIN(1,  9),  /* A9 */
5122         [19] = RCAR_GP_PIN(1,  8),  /* A8 */
5123         [20] = RCAR_GP_PIN(1,  7),  /* A7 */
5124         [21] = RCAR_GP_PIN(1,  6),  /* A6 */
5125         [22] = RCAR_GP_PIN(1,  5),  /* A5 */
5126         [23] = RCAR_GP_PIN(1,  4),  /* A4 */
5127         [24] = RCAR_GP_PIN(1,  3),  /* A3 */
5128         [25] = RCAR_GP_PIN(1,  2),  /* A2 */
5129         [26] = RCAR_GP_PIN(1,  1),  /* A1 */
5130         [27] = RCAR_GP_PIN(1,  0),  /* A0 */
5131         [28] = SH_PFC_PIN_NONE,
5132         [29] = SH_PFC_PIN_NONE,
5133         [30] = RCAR_GP_PIN(2, 25),  /* EX_WAIT0 */
5134         [31] = RCAR_GP_PIN(2, 24),  /* RD/WR# */
5135     } },
5136     { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5137          [0] = RCAR_GP_PIN(3,  1),  /* SD0_CMD */
5138          [1] = RCAR_GP_PIN(3,  0),  /* SD0_CLK */
5139          [2] = PIN_ASEBRK,      /* ASEBRK */
5140          [3] = SH_PFC_PIN_NONE,
5141          [4] = PIN_TDI,         /* TDI */
5142          [5] = PIN_TMS,         /* TMS */
5143          [6] = PIN_TCK,         /* TCK */
5144          [7] = PIN_TRST_N,      /* TRST# */
5145          [8] = SH_PFC_PIN_NONE,
5146          [9] = SH_PFC_PIN_NONE,
5147         [10] = SH_PFC_PIN_NONE,
5148         [11] = SH_PFC_PIN_NONE,
5149         [12] = SH_PFC_PIN_NONE,
5150         [13] = SH_PFC_PIN_NONE,
5151         [14] = SH_PFC_PIN_NONE,
5152         [15] = PIN_FSCLKST_N,       /* FSCLKST# */
5153         [16] = RCAR_GP_PIN(0, 17),  /* SDA4 */
5154         [17] = RCAR_GP_PIN(0, 16),  /* SCL4 */
5155         [18] = SH_PFC_PIN_NONE,
5156         [19] = SH_PFC_PIN_NONE,
5157         [20] = PIN_PRESETOUT_N,     /* PRESETOUT# */
5158         [21] = RCAR_GP_PIN(0, 15),  /* D15 */
5159         [22] = RCAR_GP_PIN(0, 14),  /* D14 */
5160         [23] = RCAR_GP_PIN(0, 13),  /* D13 */
5161         [24] = RCAR_GP_PIN(0, 12),  /* D12 */
5162         [25] = RCAR_GP_PIN(0, 11),  /* D11 */
5163         [26] = RCAR_GP_PIN(0, 10),  /* D10 */
5164         [27] = RCAR_GP_PIN(0,  9),  /* D9 */
5165         [28] = RCAR_GP_PIN(0,  8),  /* D8 */
5166         [29] = RCAR_GP_PIN(0,  7),  /* D7 */
5167         [30] = RCAR_GP_PIN(0,  6),  /* D6 */
5168         [31] = RCAR_GP_PIN(0,  5),  /* D5 */
5169     } },
5170     { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5171          [0] = RCAR_GP_PIN(5,  0),  /* SCK0_A */
5172          [1] = RCAR_GP_PIN(5,  4),  /* RTS0#_A */
5173          [2] = RCAR_GP_PIN(5,  3),  /* CTS0#_A */
5174          [3] = RCAR_GP_PIN(5,  2),  /* TX0_A */
5175          [4] = RCAR_GP_PIN(5,  1),  /* RX0_A */
5176          [5] = SH_PFC_PIN_NONE,
5177          [6] = SH_PFC_PIN_NONE,
5178          [7] = RCAR_GP_PIN(3, 15),  /* SD1_WP */
5179          [8] = RCAR_GP_PIN(3, 14),  /* SD1_CD */
5180          [9] = RCAR_GP_PIN(3, 13),  /* SD0_WP */
5181         [10] = RCAR_GP_PIN(3, 12),  /* SD0_CD */
5182         [11] = RCAR_GP_PIN(4, 10),  /* SD3_DS */
5183         [12] = RCAR_GP_PIN(4,  9),  /* SD3_DAT7 */
5184         [13] = RCAR_GP_PIN(4,  8),  /* SD3_DAT6 */
5185         [14] = RCAR_GP_PIN(4,  7),  /* SD3_DAT5 */
5186         [15] = RCAR_GP_PIN(4,  6),  /* SD3_DAT4 */
5187         [16] = RCAR_GP_PIN(4,  5),  /* SD3_DAT3 */
5188         [17] = RCAR_GP_PIN(4,  4),  /* SD3_DAT2 */
5189         [18] = RCAR_GP_PIN(4,  3),  /* SD3_DAT1 */
5190         [19] = RCAR_GP_PIN(4,  2),  /* SD3_DAT0 */
5191         [20] = RCAR_GP_PIN(4,  1),  /* SD3_CMD */
5192         [21] = RCAR_GP_PIN(4,  0),  /* SD3_CLK */
5193         [22] = RCAR_GP_PIN(3, 11),  /* SD1_DAT3 */
5194         [23] = RCAR_GP_PIN(3, 10),  /* SD1_DAT2 */
5195         [24] = RCAR_GP_PIN(3,  9),  /* SD1_DAT1 */
5196         [25] = RCAR_GP_PIN(3,  8),  /* SD1_DAT0 */
5197         [26] = RCAR_GP_PIN(3,  7),  /* SD1_CMD */
5198         [27] = RCAR_GP_PIN(3,  6),  /* SD1_CLK */
5199         [28] = RCAR_GP_PIN(3,  5),  /* SD0_DAT3 */
5200         [29] = RCAR_GP_PIN(3,  4),  /* SD0_DAT2 */
5201         [30] = RCAR_GP_PIN(3,  3),  /* SD0_DAT1 */
5202         [31] = RCAR_GP_PIN(3,  2),  /* SD0_DAT0 */
5203     } },
5204     { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5205          [0] = RCAR_GP_PIN(6,  8),  /* AUDIO_CLKA */
5206          [1] = RCAR_GP_PIN(6, 16),  /* SSI_SDATA6 */
5207          [2] = RCAR_GP_PIN(6, 15),  /* SSI_WS6 */
5208          [3] = RCAR_GP_PIN(6, 14),  /* SSI_SCK6 */
5209          [4] = RCAR_GP_PIN(6, 13),  /* SSI_SDATA5 */
5210          [5] = RCAR_GP_PIN(6, 12),  /* SSI_WS5 */
5211          [6] = RCAR_GP_PIN(6, 11),  /* SSI_SCK5 */
5212          [7] = RCAR_GP_PIN(6, 10),  /* SSI_SDATA4 */
5213          [8] = RCAR_GP_PIN(6,  7),  /* SSI_SDATA3 */
5214          [9] = RCAR_GP_PIN(6,  6),  /* SSI_WS349 */
5215         [10] = RCAR_GP_PIN(6,  5),  /* SSI_SCK349 */
5216         [11] = RCAR_GP_PIN(6,  4),  /* SSI_SDATA2 */
5217         [12] = RCAR_GP_PIN(6,  3),  /* SSI_SDATA1 */
5218         [13] = RCAR_GP_PIN(6,  2),  /* SSI_SDATA0 */
5219         [14] = RCAR_GP_PIN(6,  1),  /* SSI_WS01239 */
5220         [15] = RCAR_GP_PIN(6,  0),  /* SSI_SCK01239 */
5221         [16] = PIN_MLB_REF,     /* MLB_REF */
5222         [17] = RCAR_GP_PIN(5, 19),  /* MLB_DAT */
5223         [18] = RCAR_GP_PIN(5, 18),  /* MLB_SIG */
5224         [19] = RCAR_GP_PIN(5, 17),  /* MLB_CLK */
5225         [20] = RCAR_GP_PIN(5, 16),  /* SSI_SDATA9 */
5226         [21] = RCAR_GP_PIN(5, 15),  /* MSIOF0_SS2 */
5227         [22] = RCAR_GP_PIN(5, 14),  /* MSIOF0_SS1 */
5228         [23] = RCAR_GP_PIN(5, 13),  /* MSIOF0_SYNC */
5229         [24] = RCAR_GP_PIN(5, 12),  /* MSIOF0_TXD */
5230         [25] = RCAR_GP_PIN(5, 11),  /* MSIOF0_RXD */
5231         [26] = RCAR_GP_PIN(5, 10),  /* MSIOF0_SCK */
5232         [27] = RCAR_GP_PIN(5,  9),  /* RX2_A */
5233         [28] = RCAR_GP_PIN(5,  8),  /* TX2_A */
5234         [29] = RCAR_GP_PIN(5,  7),  /* SCK2_A */
5235         [30] = RCAR_GP_PIN(5,  6),  /* TX1 */
5236         [31] = RCAR_GP_PIN(5,  5),  /* RX1 */
5237     } },
5238     { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5239          [0] = SH_PFC_PIN_NONE,
5240          [1] = SH_PFC_PIN_NONE,
5241          [2] = SH_PFC_PIN_NONE,
5242          [3] = SH_PFC_PIN_NONE,
5243          [4] = SH_PFC_PIN_NONE,
5244          [5] = SH_PFC_PIN_NONE,
5245          [6] = SH_PFC_PIN_NONE,
5246          [7] = SH_PFC_PIN_NONE,
5247          [8] = SH_PFC_PIN_NONE,
5248          [9] = SH_PFC_PIN_NONE,
5249         [10] = SH_PFC_PIN_NONE,
5250         [11] = SH_PFC_PIN_NONE,
5251         [12] = SH_PFC_PIN_NONE,
5252         [13] = SH_PFC_PIN_NONE,
5253         [14] = SH_PFC_PIN_NONE,
5254         [15] = SH_PFC_PIN_NONE,
5255         [16] = SH_PFC_PIN_NONE,
5256         [17] = SH_PFC_PIN_NONE,
5257         [18] = SH_PFC_PIN_NONE,
5258         [19] = SH_PFC_PIN_NONE,
5259         [20] = SH_PFC_PIN_NONE,
5260         [21] = SH_PFC_PIN_NONE,
5261         [22] = SH_PFC_PIN_NONE,
5262         [23] = SH_PFC_PIN_NONE,
5263         [24] = SH_PFC_PIN_NONE,
5264         [25] = SH_PFC_PIN_NONE,
5265         [26] = SH_PFC_PIN_NONE,
5266         [27] = SH_PFC_PIN_NONE,
5267         [28] = SH_PFC_PIN_NONE,
5268         [29] = SH_PFC_PIN_NONE,
5269         [30] = RCAR_GP_PIN(6,  9),  /* USB30_OVC */
5270         [31] = RCAR_GP_PIN(6, 17),  /* USB30_PWEN */
5271     } },
5272     { /* sentinel */ },
5273 };
5274
5275 static const struct sh_pfc_soc_operations r8a77990_pfc_ops = {
5276     .pin_to_pocctrl = r8a77990_pin_to_pocctrl,
5277     .get_bias = rcar_pinmux_get_bias,
5278     .set_bias = rcar_pinmux_set_bias,
5279 };
5280
5281 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
5282 const struct sh_pfc_soc_info r8a774c0_pinmux_info = {
5283     .name = "r8a774c0_pfc",
5284     .ops = &r8a77990_pfc_ops,
5285     .unlock_reg = 0xe6060000, /* PMMR */
5286
5287     .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5288
5289     .pins = pinmux_pins,
5290     .nr_pins = ARRAY_SIZE(pinmux_pins),
5291     .groups = pinmux_groups.common,
5292     .nr_groups = ARRAY_SIZE(pinmux_groups.common),
5293     .functions = pinmux_functions.common,
5294     .nr_functions = ARRAY_SIZE(pinmux_functions.common),
5295
5296     .cfg_regs = pinmux_config_regs,
5297     .drive_regs = pinmux_drive_regs,
5298     .bias_regs = pinmux_bias_regs,
5299     .ioctrl_regs = pinmux_ioctrl_regs,
5300
5301     .pinmux_data = pinmux_data,
5302     .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5303 };
5304 #endif
5305
5306 #ifdef CONFIG_PINCTRL_PFC_R8A77990
5307 const struct sh_pfc_soc_info r8a77990_pinmux_info = {
5308     .name = "r8a77990_pfc",
5309     .ops = &r8a77990_pfc_ops,
5310     .unlock_reg = 0xe6060000, /* PMMR */
5311
5312     .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5313
5314     .pins = pinmux_pins,
5315     .nr_pins = ARRAY_SIZE(pinmux_pins),
5316     .groups = pinmux_groups.common,
5317     .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
5318         ARRAY_SIZE(pinmux_groups.automotive),
5319     .functions = pinmux_functions.common,
5320     .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
5321         ARRAY_SIZE(pinmux_functions.automotive),
5322
5323     .cfg_regs = pinmux_config_regs,
5324     .drive_regs = pinmux_drive_regs,
5325     .bias_regs = pinmux_bias_regs,
5326     .ioctrl_regs = pinmux_ioctrl_regs,
5327
5328     .pinmux_data = pinmux_data,
5329     .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5330 };
5331 #endif