pinctrl/renesas/pfc-r8a77980.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * R8A77980 processor support - PFC hardware block.
0004  *
0005  * Copyright (C) 2018 Renesas Electronics Corp.
0006  * Copyright (C) 2018 Cogent Embedded, Inc.
0007  *
0008  * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
0009  *
0010  * R-Car Gen3 processor support - PFC hardware block.
0011  *
0012  * Copyright (C) 2015 Renesas Electronics Corporation
0013  */
0014
0015 #include <linux/errno.h>
0016 #include <linux/io.h>
0017 #include <linux/kernel.h>
0018
0019 #include "sh_pfc.h"
0020
0021 #define CPU_ALL_GP(fn, sfx) \
0022     PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
0023     PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
0024     PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
0025     PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
0026     PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
0027     PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
0028
0029 #define CPU_ALL_NOGP(fn)    \
0030     PIN_NOGP_CFG(DCUTCK_LPDCLK, "DCUTCK_LPDCLK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),  \
0031     PIN_NOGP_CFG(DCUTDI_LPDI, "DCUTDI_LPDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),  \
0032     PIN_NOGP_CFG(DCUTMS, "DCUTMS", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
0033     PIN_NOGP_CFG(DCUTRST_N, "DCUTRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),   \
0034     PIN_NOGP_CFG(DU_DOTCLKIN, "DU_DOTCLKIN", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),  \
0035     PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),    \
0036     PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),  \
0037     PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),   \
0038     PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
0039
0040 /*
0041  * F_() : just information
0042  * FM() : macro for FN_xxx / xxx_MARK
0043  */
0044
0045 /* GPSR0 */
0046 #define GPSR0_21    F_(DU_EXODDF_DU_ODDF_DISP_CDE,  IP2_23_20)
0047 #define GPSR0_20    F_(DU_EXVSYNC_DU_VSYNC,     IP2_19_16)
0048 #define GPSR0_19    F_(DU_EXHSYNC_DU_HSYNC,     IP2_15_12)
0049 #define GPSR0_18    F_(DU_DOTCLKOUT,        IP2_11_8)
0050 #define GPSR0_17    F_(DU_DB7,          IP2_7_4)
0051 #define GPSR0_16    F_(DU_DB6,          IP2_3_0)
0052 #define GPSR0_15    F_(DU_DB5,          IP1_31_28)
0053 #define GPSR0_14    F_(DU_DB4,          IP1_27_24)
0054 #define GPSR0_13    F_(DU_DB3,          IP1_23_20)
0055 #define GPSR0_12    F_(DU_DB2,          IP1_19_16)
0056 #define GPSR0_11    F_(DU_DG7,          IP1_15_12)
0057 #define GPSR0_10    F_(DU_DG6,          IP1_11_8)
0058 #define GPSR0_9     F_(DU_DG5,          IP1_7_4)
0059 #define GPSR0_8     F_(DU_DG4,          IP1_3_0)
0060 #define GPSR0_7     F_(DU_DG3,          IP0_31_28)
0061 #define GPSR0_6     F_(DU_DG2,          IP0_27_24)
0062 #define GPSR0_5     F_(DU_DR7,          IP0_23_20)
0063 #define GPSR0_4     F_(DU_DR6,          IP0_19_16)
0064 #define GPSR0_3     F_(DU_DR5,          IP0_15_12)
0065 #define GPSR0_2     F_(DU_DR4,          IP0_11_8)
0066 #define GPSR0_1     F_(DU_DR3,          IP0_7_4)
0067 #define GPSR0_0     F_(DU_DR2,          IP0_3_0)
0068
0069 /* GPSR1 */
0070 #define GPSR1_27    F_(DIGRF_CLKOUT,    IP8_31_28)
0071 #define GPSR1_26    F_(DIGRF_CLKIN,     IP8_27_24)
0072 #define GPSR1_25    F_(CANFD_CLK_A,     IP8_23_20)
0073 #define GPSR1_24    F_(CANFD1_RX,       IP8_19_16)
0074 #define GPSR1_23    F_(CANFD1_TX,       IP8_15_12)
0075 #define GPSR1_22    F_(CANFD0_RX_A,     IP8_11_8)
0076 #define GPSR1_21    F_(CANFD0_TX_A,     IP8_7_4)
0077 #define GPSR1_20    F_(AVB_AVTP_CAPTURE,    IP8_3_0)
0078 #define GPSR1_19    F_(AVB_AVTP_MATCH,  IP7_31_28)
0079 #define GPSR1_18    FM(AVB_LINK)
0080 #define GPSR1_17    FM(AVB_PHY_INT)
0081 #define GPSR1_16    FM(AVB_MAGIC)
0082 #define GPSR1_15    FM(AVB_MDC)
0083 #define GPSR1_14    FM(AVB_MDIO)
0084 #define GPSR1_13    FM(AVB_TXCREFCLK)
0085 #define GPSR1_12    FM(AVB_TD3)
0086 #define GPSR1_11    FM(AVB_TD2)
0087 #define GPSR1_10    FM(AVB_TD1)
0088 #define GPSR1_9     FM(AVB_TD0)
0089 #define GPSR1_8     FM(AVB_TXC)
0090 #define GPSR1_7     FM(AVB_TX_CTL)
0091 #define GPSR1_6     FM(AVB_RD3)
0092 #define GPSR1_5     FM(AVB_RD2)
0093 #define GPSR1_4     FM(AVB_RD1)
0094 #define GPSR1_3     FM(AVB_RD0)
0095 #define GPSR1_2     FM(AVB_RXC)
0096 #define GPSR1_1     FM(AVB_RX_CTL)
0097 #define GPSR1_0     F_(IRQ0,        IP2_27_24)
0098
0099 /* GPSR2 */
0100 #define GPSR2_29    F_(FSO_TOE_N,       IP10_19_16)
0101 #define GPSR2_28    F_(FSO_CFE_1_N,     IP10_15_12)
0102 #define GPSR2_27    F_(FSO_CFE_0_N,     IP10_11_8)
0103 #define GPSR2_26    F_(SDA3,        IP10_7_4)
0104 #define GPSR2_25    F_(SCL3,        IP10_3_0)
0105 #define GPSR2_24    F_(MSIOF0_SS2,      IP9_31_28)
0106 #define GPSR2_23    F_(MSIOF0_SS1,      IP9_27_24)
0107 #define GPSR2_22    F_(MSIOF0_SYNC,     IP9_23_20)
0108 #define GPSR2_21    F_(MSIOF0_SCK,      IP9_19_16)
0109 #define GPSR2_20    F_(MSIOF0_TXD,      IP9_15_12)
0110 #define GPSR2_19    F_(MSIOF0_RXD,      IP9_11_8)
0111 #define GPSR2_18    F_(IRQ5,        IP9_7_4)
0112 #define GPSR2_17    F_(IRQ4,        IP9_3_0)
0113 #define GPSR2_16    F_(VI0_FIELD,       IP4_31_28)
0114 #define GPSR2_15    F_(VI0_DATA11,      IP4_27_24)
0115 #define GPSR2_14    F_(VI0_DATA10,      IP4_23_20)
0116 #define GPSR2_13    F_(VI0_DATA9,       IP4_19_16)
0117 #define GPSR2_12    F_(VI0_DATA8,       IP4_15_12)
0118 #define GPSR2_11    F_(VI0_DATA7,       IP4_11_8)
0119 #define GPSR2_10    F_(VI0_DATA6,       IP4_7_4)
0120 #define GPSR2_9     F_(VI0_DATA5,       IP4_3_0)
0121 #define GPSR2_8     F_(VI0_DATA4,       IP3_31_28)
0122 #define GPSR2_7     F_(VI0_DATA3,       IP3_27_24)
0123 #define GPSR2_6     F_(VI0_DATA2,       IP3_23_20)
0124 #define GPSR2_5     F_(VI0_DATA1,       IP3_19_16)
0125 #define GPSR2_4     F_(VI0_DATA0,       IP3_15_12)
0126 #define GPSR2_3     F_(VI0_VSYNC_N,     IP3_11_8)
0127 #define GPSR2_2     F_(VI0_HSYNC_N,     IP3_7_4)
0128 #define GPSR2_1     F_(VI0_CLKENB,      IP3_3_0)
0129 #define GPSR2_0     F_(VI0_CLK,     IP2_31_28)
0130
0131 /* GPSR3 */
0132 #define GPSR3_16    F_(VI1_FIELD,       IP7_3_0)
0133 #define GPSR3_15    F_(VI1_DATA11,      IP6_31_28)
0134 #define GPSR3_14    F_(VI1_DATA10,      IP6_27_24)
0135 #define GPSR3_13    F_(VI1_DATA9,       IP6_23_20)
0136 #define GPSR3_12    F_(VI1_DATA8,       IP6_19_16)
0137 #define GPSR3_11    F_(VI1_DATA7,       IP6_15_12)
0138 #define GPSR3_10    F_(VI1_DATA6,       IP6_11_8)
0139 #define GPSR3_9     F_(VI1_DATA5,       IP6_7_4)
0140 #define GPSR3_8     F_(VI1_DATA4,       IP6_3_0)
0141 #define GPSR3_7     F_(VI1_DATA3,       IP5_31_28)
0142 #define GPSR3_6     F_(VI1_DATA2,       IP5_27_24)
0143 #define GPSR3_5     F_(VI1_DATA1,       IP5_23_20)
0144 #define GPSR3_4     F_(VI1_DATA0,       IP5_19_16)
0145 #define GPSR3_3     F_(VI1_VSYNC_N,     IP5_15_12)
0146 #define GPSR3_2     F_(VI1_HSYNC_N,     IP5_11_8)
0147 #define GPSR3_1     F_(VI1_CLKENB,      IP5_7_4)
0148 #define GPSR3_0     F_(VI1_CLK,     IP5_3_0)
0149
0150 /* GPSR4 */
0151 #define GPSR4_24    FM(GETHER_LINK_A)
0152 #define GPSR4_23    FM(GETHER_PHY_INT_A)
0153 #define GPSR4_22    FM(GETHER_MAGIC)
0154 #define GPSR4_21    FM(GETHER_MDC_A)
0155 #define GPSR4_20    FM(GETHER_MDIO_A)
0156 #define GPSR4_19    FM(GETHER_TXCREFCLK_MEGA)
0157 #define GPSR4_18    FM(GETHER_TXCREFCLK)
0158 #define GPSR4_17    FM(GETHER_TD3)
0159 #define GPSR4_16    FM(GETHER_TD2)
0160 #define GPSR4_15    FM(GETHER_TD1)
0161 #define GPSR4_14    FM(GETHER_TD0)
0162 #define GPSR4_13    FM(GETHER_TXC)
0163 #define GPSR4_12    FM(GETHER_TX_CTL)
0164 #define GPSR4_11    FM(GETHER_RD3)
0165 #define GPSR4_10    FM(GETHER_RD2)
0166 #define GPSR4_9     FM(GETHER_RD1)
0167 #define GPSR4_8     FM(GETHER_RD0)
0168 #define GPSR4_7     FM(GETHER_RXC)
0169 #define GPSR4_6     FM(GETHER_RX_CTL)
0170 #define GPSR4_5     F_(SDA2,        IP7_27_24)
0171 #define GPSR4_4     F_(SCL2,        IP7_23_20)
0172 #define GPSR4_3     F_(SDA1,        IP7_19_16)
0173 #define GPSR4_2     F_(SCL1,        IP7_15_12)
0174 #define GPSR4_1     F_(SDA0,        IP7_11_8)
0175 #define GPSR4_0     F_(SCL0,        IP7_7_4)
0176
0177 /* GPSR5 */
0178 #define GPSR5_14    FM(RPC_INT_N)
0179 #define GPSR5_13    FM(RPC_WP_N)
0180 #define GPSR5_12    FM(RPC_RESET_N)
0181 #define GPSR5_11    FM(QSPI1_SSL)
0182 #define GPSR5_10    FM(QSPI1_IO3)
0183 #define GPSR5_9     FM(QSPI1_IO2)
0184 #define GPSR5_8     FM(QSPI1_MISO_IO1)
0185 #define GPSR5_7     FM(QSPI1_MOSI_IO0)
0186 #define GPSR5_6     FM(QSPI1_SPCLK)
0187 #define GPSR5_5     FM(QSPI0_SSL)
0188 #define GPSR5_4     FM(QSPI0_IO3)
0189 #define GPSR5_3     FM(QSPI0_IO2)
0190 #define GPSR5_2     FM(QSPI0_MISO_IO1)
0191 #define GPSR5_1     FM(QSPI0_MOSI_IO0)
0192 #define GPSR5_0     FM(QSPI0_SPCLK)
0193
0194
0195 /* IPSRx */     /* 0 */             /* 1 */         /* 2 */         /* 3 */     /* 4 */     /* 5 */     /* 6 - F */
0196 #define IP0_3_0     FM(DU_DR2)          FM(SCK4)        FM(GETHER_RMII_CRS_DV)  FM(A0)      F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0197 #define IP0_7_4     FM(DU_DR3)          FM(RX4)         FM(GETHER_RMII_RX_ER)   FM(A1)      F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0198 #define IP0_11_8    FM(DU_DR4)          FM(TX4)         FM(GETHER_RMII_RXD0)    FM(A2)      F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0199 #define IP0_15_12   FM(DU_DR5)          FM(CTS4_N)      FM(GETHER_RMII_RXD1)    FM(A3)      F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0200 #define IP0_19_16   FM(DU_DR6)          FM(RTS4_N)      FM(GETHER_RMII_TXD_EN)  FM(A4)      F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0201 #define IP0_23_20   FM(DU_DR7)          F_(0, 0)        FM(GETHER_RMII_TXD0)    FM(A5)      F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0202 #define IP0_27_24   FM(DU_DG2)          F_(0, 0)        FM(GETHER_RMII_TXD1)    FM(A6)      F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0203 #define IP0_31_28   FM(DU_DG3)          FM(CPG_CPCKOUT)     FM(GETHER_RMII_REFCLK)  FM(A7)      FM(PWMFSW0) F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0204 #define IP1_3_0     FM(DU_DG4)          FM(SCL5)        F_(0, 0)        FM(A8)      F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0205 #define IP1_7_4     FM(DU_DG5)          FM(SDA5)        FM(GETHER_MDC_B)    FM(A9)      F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0206 #define IP1_11_8    FM(DU_DG6)          FM(SCIF_CLK_A)      FM(GETHER_MDIO_B)   FM(A10)     F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0207 #define IP1_15_12   FM(DU_DG7)          FM(HRX0_A)      F_(0, 0)        FM(A11)     F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0208 #define IP1_19_16   FM(DU_DB2)          FM(HSCK0_A)     F_(0, 0)        FM(A12)     FM(IRQ1)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0209 #define IP1_23_20   FM(DU_DB3)          FM(HRTS0_N_A)       F_(0, 0)        FM(A13)     FM(IRQ2)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0210 #define IP1_27_24   FM(DU_DB4)          FM(HCTS0_N_A)       F_(0, 0)        FM(A14)     FM(IRQ3)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0211 #define IP1_31_28   FM(DU_DB5)          FM(HTX0_A)      FM(PWM0_A)      FM(A15)     F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0212 #define IP2_3_0     FM(DU_DB6)          FM(MSIOF3_RXD)      F_(0, 0)        FM(A16)     F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0213 #define IP2_7_4     FM(DU_DB7)          FM(MSIOF3_TXD)      F_(0, 0)        FM(A17)     F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0214 #define IP2_11_8    FM(DU_DOTCLKOUT)        FM(MSIOF3_SS1)      FM(GETHER_LINK_B)   FM(A18)     F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0215 #define IP2_15_12   FM(DU_EXHSYNC_DU_HSYNC)     FM(MSIOF3_SS2)      FM(GETHER_PHY_INT_B)    FM(A19)     FM(FXR_TXENA_N) F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0216 #define IP2_19_16   FM(DU_EXVSYNC_DU_VSYNC)     FM(MSIOF3_SCK)      F_(0, 0)        F_(0, 0)    FM(FXR_TXENB_N) F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0217 #define IP2_23_20   FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(MSIOF3_SYNC)     F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0218 #define IP2_27_24   FM(IRQ0)            F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0219 #define IP2_31_28   FM(VI0_CLK)         FM(MSIOF2_SCK)      FM(SCK3)        F_(0, 0)    FM(HSCK3)   F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0220 #define IP3_3_0     FM(VI0_CLKENB)          FM(MSIOF2_RXD)      FM(RX3)         FM(RD_WR_N) FM(HCTS3_N) F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0221 #define IP3_7_4     FM(VI0_HSYNC_N)         FM(MSIOF2_TXD)      FM(TX3)         F_(0, 0)    FM(HRTS3_N) F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0222 #define IP3_11_8    FM(VI0_VSYNC_N)         FM(MSIOF2_SYNC)     FM(CTS3_N)      F_(0, 0)    FM(HTX3)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0223 #define IP3_15_12   FM(VI0_DATA0)           FM(MSIOF2_SS1)      FM(RTS3_N)      F_(0, 0)    FM(HRX3)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0224 #define IP3_19_16   FM(VI0_DATA1)           FM(MSIOF2_SS2)      FM(SCK1)        F_(0, 0)    FM(SPEEDIN_A)   F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0225 #define IP3_23_20   FM(VI0_DATA2)           FM(AVB_AVTP_PPS)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0226 #define IP3_27_24   FM(VI0_DATA3)           FM(HSCK1)       F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0227 #define IP3_31_28   FM(VI0_DATA4)           FM(HRTS1_N)     FM(RX1_A)       F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0228 #define IP4_3_0     FM(VI0_DATA5)           FM(HCTS1_N)     FM(TX1_A)       F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0229 #define IP4_7_4     FM(VI0_DATA6)           FM(HTX1)        FM(CTS1_N)      F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0230 #define IP4_11_8    FM(VI0_DATA7)           FM(HRX1)        FM(RTS1_N)      F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0231 #define IP4_15_12   FM(VI0_DATA8)           FM(HSCK2)       F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0232 #define IP4_19_16   FM(VI0_DATA9)           FM(HCTS2_N)     FM(PWM1_A)      F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0233 #define IP4_23_20   FM(VI0_DATA10)          FM(HRTS2_N)     FM(PWM2_A)      F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0234 #define IP4_27_24   FM(VI0_DATA11)          FM(HTX2)        FM(PWM3_A)      F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0235 #define IP4_31_28   FM(VI0_FIELD)           FM(HRX2)        FM(PWM4_A)      FM(CS1_N)   F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0236 #define IP5_3_0     FM(VI1_CLK)         FM(MSIOF1_RXD)      F_(0, 0)        FM(CS0_N)   F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0237 #define IP5_7_4     FM(VI1_CLKENB)          FM(MSIOF1_TXD)      F_(0, 0)        FM(D0)      F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0238 #define IP5_11_8    FM(VI1_HSYNC_N)         FM(MSIOF1_SCK)      F_(0, 0)        FM(D1)      F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0239 #define IP5_15_12   FM(VI1_VSYNC_N)         FM(MSIOF1_SYNC)     F_(0, 0)        FM(D2)      F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0240 #define IP5_19_16   FM(VI1_DATA0)           FM(MSIOF1_SS1)      F_(0, 0)        FM(D3)      FM(MMC_WP)  F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0241 #define IP5_23_20   FM(VI1_DATA1)           FM(MSIOF1_SS2)      F_(0, 0)        FM(D4)      FM(MMC_CD)  F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0242 #define IP5_27_24   FM(VI1_DATA2)           FM(CANFD0_TX_B)     F_(0, 0)        FM(D5)      FM(MMC_DS)  F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0243 #define IP5_31_28   FM(VI1_DATA3)           FM(CANFD0_RX_B)     F_(0, 0)        FM(D6)      FM(MMC_CMD) F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0244 #define IP6_3_0     FM(VI1_DATA4)           FM(CANFD_CLK_B)     F_(0, 0)        FM(D7)      FM(MMC_D0)  F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0245 #define IP6_7_4     FM(VI1_DATA5)           F_(0, 0)        F_(0, 0)        FM(D8)      FM(MMC_D1)  F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0246 #define IP6_11_8    FM(VI1_DATA6)           F_(0, 0)        F_(0, 0)        FM(D9)      FM(MMC_D2)  F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0247 #define IP6_15_12   FM(VI1_DATA7)           F_(0, 0)        F_(0, 0)        FM(D10)     FM(MMC_D3)  F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0248 #define IP6_19_16   FM(VI1_DATA8)           F_(0, 0)        F_(0, 0)        FM(D11)     FM(MMC_CLK) F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0249 #define IP6_23_20   FM(VI1_DATA9)           FM(TCLK1_A)     F_(0, 0)        FM(D12)     FM(MMC_D4)  F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0250 #define IP6_27_24   FM(VI1_DATA10)          FM(TCLK2_A)     F_(0, 0)        FM(D13)     FM(MMC_D5)  F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0251 #define IP6_31_28   FM(VI1_DATA11)          FM(SCL4)        F_(0, 0)        FM(D14)     FM(MMC_D6)  F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0252 #define IP7_3_0     FM(VI1_FIELD)           FM(SDA4)        F_(0, 0)        FM(D15)     FM(MMC_D7)  F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0253 #define IP7_7_4     FM(SCL0)            F_(0, 0)        F_(0, 0)        FM(CLKOUT)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0254 #define IP7_11_8    FM(SDA0)            F_(0, 0)        F_(0, 0)        FM(BS_N)    FM(SCK0)    FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0255 #define IP7_15_12   FM(SCL1)            F_(0, 0)        FM(TPU0TO2)     FM(RD_N)    FM(CTS0_N)  FM(HCTS0_N_B)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0256 #define IP7_19_16   FM(SDA1)            F_(0, 0)        FM(TPU0TO3)     FM(WE0_N)   FM(RTS0_N)  FM(HRTS0_N_B)   F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0257 #define IP7_23_20   FM(SCL2)            F_(0, 0)        F_(0, 0)        FM(WE1_N)   FM(RX0)     FM(HRX0_B)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0258 #define IP7_27_24   FM(SDA2)            F_(0, 0)        F_(0, 0)        FM(EX_WAIT0)    FM(TX0)     FM(HTX0_B)  F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0259 #define IP7_31_28   FM(AVB_AVTP_MATCH)      FM(TPU0TO0)     F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0260 #define IP8_3_0     FM(AVB_AVTP_CAPTURE)        FM(TPU0TO1)     F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0261 #define IP8_7_4     FM(CANFD0_TX_A)         FM(FXR_TXDA)        FM(PWM0_B)      FM(DU_DISP) F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0262 #define IP8_11_8    FM(CANFD0_RX_A)         FM(RXDA_EXTFXR)     FM(PWM1_B)      FM(DU_CDE)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0263 #define IP8_15_12   FM(CANFD1_TX)           FM(FXR_TXDB)        FM(PWM2_B)      FM(TCLK1_B) FM(TX1_B)   F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0264 #define IP8_19_16   FM(CANFD1_RX)           FM(RXDB_EXTFXR)     FM(PWM3_B)      FM(TCLK2_B) FM(RX1_B)   F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0265 #define IP8_23_20   FM(CANFD_CLK_A)         FM(CLK_EXTFXR)      FM(PWM4_B)      FM(SPEEDIN_B)   FM(SCIF_CLK_B)  F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0266 #define IP8_27_24   FM(DIGRF_CLKIN)         FM(DIGRF_CLKEN_IN)  F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0267 #define IP8_31_28   FM(DIGRF_CLKOUT)        FM(DIGRF_CLKEN_OUT) F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0268 #define IP9_3_0     FM(IRQ4)            F_(0, 0)        F_(0, 0)        FM(VI0_DATA12)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0269 #define IP9_7_4     FM(IRQ5)            F_(0, 0)        F_(0, 0)        FM(VI0_DATA13)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0270 #define IP9_11_8    FM(MSIOF0_RXD)          FM(DU_DR0)      F_(0, 0)        FM(VI0_DATA14)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0271 #define IP9_15_12   FM(MSIOF0_TXD)          FM(DU_DR1)      F_(0, 0)        FM(VI0_DATA15)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0272 #define IP9_19_16   FM(MSIOF0_SCK)          FM(DU_DG0)      F_(0, 0)        FM(VI0_DATA16)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0273 #define IP9_23_20   FM(MSIOF0_SYNC)         FM(DU_DG1)      F_(0, 0)        FM(VI0_DATA17)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0274 #define IP9_27_24   FM(MSIOF0_SS1)          FM(DU_DB0)      FM(TCLK3)       FM(VI0_DATA18)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0275 #define IP9_31_28   FM(MSIOF0_SS2)          FM(DU_DB1)      FM(TCLK4)       FM(VI0_DATA19)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0276 #define IP10_3_0    FM(SCL3)            F_(0, 0)        F_(0, 0)        FM(VI0_DATA20)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0277 #define IP10_7_4    FM(SDA3)            F_(0, 0)        F_(0, 0)        FM(VI0_DATA21)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0278 #define IP10_11_8   FM(FSO_CFE_0_N)         F_(0, 0)        F_(0, 0)        FM(VI0_DATA22)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0279 #define IP10_15_12  FM(FSO_CFE_1_N)         F_(0, 0)        F_(0, 0)        FM(VI0_DATA23)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0280 #define IP10_19_16  FM(FSO_TOE_N)           F_(0, 0)        F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0281
0282 #define PINMUX_GPSR \
0283 \
0284                 GPSR2_29 \
0285                 GPSR2_28 \
0286         GPSR1_27    GPSR2_27 \
0287         GPSR1_26    GPSR2_26 \
0288         GPSR1_25    GPSR2_25 \
0289         GPSR1_24    GPSR2_24            GPSR4_24 \
0290         GPSR1_23    GPSR2_23            GPSR4_23 \
0291         GPSR1_22    GPSR2_22            GPSR4_22 \
0292 GPSR0_21    GPSR1_21    GPSR2_21            GPSR4_21 \
0293 GPSR0_20    GPSR1_20    GPSR2_20            GPSR4_20 \
0294 GPSR0_19    GPSR1_19    GPSR2_19            GPSR4_19 \
0295 GPSR0_18    GPSR1_18    GPSR2_18            GPSR4_18 \
0296 GPSR0_17    GPSR1_17    GPSR2_17            GPSR4_17 \
0297 GPSR0_16    GPSR1_16    GPSR2_16    GPSR3_16    GPSR4_16 \
0298 GPSR0_15    GPSR1_15    GPSR2_15    GPSR3_15    GPSR4_15 \
0299 GPSR0_14    GPSR1_14    GPSR2_14    GPSR3_14    GPSR4_14    GPSR5_14 \
0300 GPSR0_13    GPSR1_13    GPSR2_13    GPSR3_13    GPSR4_13    GPSR5_13 \
0301 GPSR0_12    GPSR1_12    GPSR2_12    GPSR3_12    GPSR4_12    GPSR5_12 \
0302 GPSR0_11    GPSR1_11    GPSR2_11    GPSR3_11    GPSR4_11    GPSR5_11 \
0303 GPSR0_10    GPSR1_10    GPSR2_10    GPSR3_10    GPSR4_10    GPSR5_10 \
0304 GPSR0_9     GPSR1_9     GPSR2_9     GPSR3_9     GPSR4_9     GPSR5_9 \
0305 GPSR0_8     GPSR1_8     GPSR2_8     GPSR3_8     GPSR4_8     GPSR5_8 \
0306 GPSR0_7     GPSR1_7     GPSR2_7     GPSR3_7     GPSR4_7     GPSR5_7 \
0307 GPSR0_6     GPSR1_6     GPSR2_6     GPSR3_6     GPSR4_6     GPSR5_6 \
0308 GPSR0_5     GPSR1_5     GPSR2_5     GPSR3_5     GPSR4_5     GPSR5_5 \
0309 GPSR0_4     GPSR1_4     GPSR2_4     GPSR3_4     GPSR4_4     GPSR5_4 \
0310 GPSR0_3     GPSR1_3     GPSR2_3     GPSR3_3     GPSR4_3     GPSR5_3 \
0311 GPSR0_2     GPSR1_2     GPSR2_2     GPSR3_2     GPSR4_2     GPSR5_2 \
0312 GPSR0_1     GPSR1_1     GPSR2_1     GPSR3_1     GPSR4_1     GPSR5_1 \
0313 GPSR0_0     GPSR1_0     GPSR2_0     GPSR3_0     GPSR4_0     GPSR5_0
0314
0315 #define PINMUX_IPSR \
0316 \
0317 FM(IP0_3_0) IP0_3_0     FM(IP1_3_0) IP1_3_0     FM(IP2_3_0) IP2_3_0     FM(IP3_3_0) IP3_3_0 \
0318 FM(IP0_7_4) IP0_7_4     FM(IP1_7_4) IP1_7_4     FM(IP2_7_4) IP2_7_4     FM(IP3_7_4) IP3_7_4 \
0319 FM(IP0_11_8)    IP0_11_8    FM(IP1_11_8)    IP1_11_8    FM(IP2_11_8)    IP2_11_8    FM(IP3_11_8)    IP3_11_8 \
0320 FM(IP0_15_12)   IP0_15_12   FM(IP1_15_12)   IP1_15_12   FM(IP2_15_12)   IP2_15_12   FM(IP3_15_12)   IP3_15_12 \
0321 FM(IP0_19_16)   IP0_19_16   FM(IP1_19_16)   IP1_19_16   FM(IP2_19_16)   IP2_19_16   FM(IP3_19_16)   IP3_19_16 \
0322 FM(IP0_23_20)   IP0_23_20   FM(IP1_23_20)   IP1_23_20   FM(IP2_23_20)   IP2_23_20   FM(IP3_23_20)   IP3_23_20 \
0323 FM(IP0_27_24)   IP0_27_24   FM(IP1_27_24)   IP1_27_24   FM(IP2_27_24)   IP2_27_24   FM(IP3_27_24)   IP3_27_24 \
0324 FM(IP0_31_28)   IP0_31_28   FM(IP1_31_28)   IP1_31_28   FM(IP2_31_28)   IP2_31_28   FM(IP3_31_28)   IP3_31_28 \
0325 \
0326 FM(IP4_3_0) IP4_3_0     FM(IP5_3_0) IP5_3_0     FM(IP6_3_0) IP6_3_0     FM(IP7_3_0) IP7_3_0 \
0327 FM(IP4_7_4) IP4_7_4     FM(IP5_7_4) IP5_7_4     FM(IP6_7_4) IP6_7_4     FM(IP7_7_4) IP7_7_4 \
0328 FM(IP4_11_8)    IP4_11_8    FM(IP5_11_8)    IP5_11_8    FM(IP6_11_8)    IP6_11_8    FM(IP7_11_8)    IP7_11_8 \
0329 FM(IP4_15_12)   IP4_15_12   FM(IP5_15_12)   IP5_15_12   FM(IP6_15_12)   IP6_15_12   FM(IP7_15_12)   IP7_15_12 \
0330 FM(IP4_19_16)   IP4_19_16   FM(IP5_19_16)   IP5_19_16   FM(IP6_19_16)   IP6_19_16   FM(IP7_19_16)   IP7_19_16 \
0331 FM(IP4_23_20)   IP4_23_20   FM(IP5_23_20)   IP5_23_20   FM(IP6_23_20)   IP6_23_20   FM(IP7_23_20)   IP7_23_20 \
0332 FM(IP4_27_24)   IP4_27_24   FM(IP5_27_24)   IP5_27_24   FM(IP6_27_24)   IP6_27_24   FM(IP7_27_24)   IP7_27_24 \
0333 FM(IP4_31_28)   IP4_31_28   FM(IP5_31_28)   IP5_31_28   FM(IP6_31_28)   IP6_31_28   FM(IP7_31_28)   IP7_31_28 \
0334 \
0335 FM(IP8_3_0) IP8_3_0     FM(IP9_3_0) IP9_3_0     FM(IP10_3_0)    IP10_3_0 \
0336 FM(IP8_7_4) IP8_7_4     FM(IP9_7_4) IP9_7_4     FM(IP10_7_4)    IP10_7_4 \
0337 FM(IP8_11_8)    IP8_11_8    FM(IP9_11_8)    IP9_11_8    FM(IP10_11_8)   IP10_11_8 \
0338 FM(IP8_15_12)   IP8_15_12   FM(IP9_15_12)   IP9_15_12   FM(IP10_15_12)  IP10_15_12 \
0339 FM(IP8_19_16)   IP8_19_16   FM(IP9_19_16)   IP9_19_16   FM(IP10_19_16)  IP10_19_16 \
0340 FM(IP8_23_20)   IP8_23_20   FM(IP9_23_20)   IP9_23_20 \
0341 FM(IP8_27_24)   IP8_27_24   FM(IP9_27_24)   IP9_27_24 \
0342 FM(IP8_31_28)   IP8_31_28   FM(IP9_31_28)   IP9_31_28
0343
0344 /* MOD_SEL0 */      /* 0 */         /* 1 */
0345 #define MOD_SEL0_11 FM(SEL_CANFD0_0)    FM(SEL_CANFD0_1)
0346 #define MOD_SEL0_10 FM(SEL_GETHER_0)    FM(SEL_GETHER_1)
0347 #define MOD_SEL0_9  FM(SEL_HSCIF0_0)    FM(SEL_HSCIF0_1)
0348 #define MOD_SEL0_8  FM(SEL_PWM0_0)      FM(SEL_PWM0_1)
0349 #define MOD_SEL0_7  FM(SEL_PWM1_0)      FM(SEL_PWM1_1)
0350 #define MOD_SEL0_6  FM(SEL_PWM2_0)      FM(SEL_PWM2_1)
0351 #define MOD_SEL0_5  FM(SEL_PWM3_0)      FM(SEL_PWM3_1)
0352 #define MOD_SEL0_4  FM(SEL_PWM4_0)      FM(SEL_PWM4_1)
0353 #define MOD_SEL0_2  FM(SEL_RSP_0)       FM(SEL_RSP_1)
0354 #define MOD_SEL0_1  FM(SEL_SCIF1_0)     FM(SEL_SCIF1_1)
0355 #define MOD_SEL0_0  FM(SEL_TMU_0)       FM(SEL_TMU_1)
0356
0357 #define PINMUX_MOD_SELS \
0358 \
0359 MOD_SEL0_11 \
0360 MOD_SEL0_10 \
0361 MOD_SEL0_9 \
0362 MOD_SEL0_8 \
0363 MOD_SEL0_7 \
0364 MOD_SEL0_6 \
0365 MOD_SEL0_5 \
0366 MOD_SEL0_4 \
0367 MOD_SEL0_2 \
0368 MOD_SEL0_1 \
0369 MOD_SEL0_0
0370
0371 enum {
0372     PINMUX_RESERVED = 0,
0373
0374     PINMUX_DATA_BEGIN,
0375     GP_ALL(DATA),
0376     PINMUX_DATA_END,
0377
0378 #define F_(x, y)
0379 #define FM(x)   FN_##x,
0380     PINMUX_FUNCTION_BEGIN,
0381     GP_ALL(FN),
0382     PINMUX_GPSR
0383     PINMUX_IPSR
0384     PINMUX_MOD_SELS
0385     PINMUX_FUNCTION_END,
0386 #undef F_
0387 #undef FM
0388
0389 #define F_(x, y)
0390 #define FM(x)   x##_MARK,
0391     PINMUX_MARK_BEGIN,
0392     PINMUX_GPSR
0393     PINMUX_IPSR
0394     PINMUX_MOD_SELS
0395     PINMUX_MARK_END,
0396 #undef F_
0397 #undef FM
0398 };
0399
0400 static const u16 pinmux_data[] = {
0401     PINMUX_DATA_GP_ALL(),
0402
0403     PINMUX_SINGLE(AVB_RX_CTL),
0404     PINMUX_SINGLE(AVB_RXC),
0405     PINMUX_SINGLE(AVB_RD0),
0406     PINMUX_SINGLE(AVB_RD1),
0407     PINMUX_SINGLE(AVB_RD2),
0408     PINMUX_SINGLE(AVB_RD3),
0409     PINMUX_SINGLE(AVB_TX_CTL),
0410     PINMUX_SINGLE(AVB_TXC),
0411     PINMUX_SINGLE(AVB_TD0),
0412     PINMUX_SINGLE(AVB_TD1),
0413     PINMUX_SINGLE(AVB_TD2),
0414     PINMUX_SINGLE(AVB_TD3),
0415     PINMUX_SINGLE(AVB_TXCREFCLK),
0416     PINMUX_SINGLE(AVB_MDIO),
0417     PINMUX_SINGLE(AVB_MDC),
0418     PINMUX_SINGLE(AVB_MAGIC),
0419     PINMUX_SINGLE(AVB_PHY_INT),
0420     PINMUX_SINGLE(AVB_LINK),
0421
0422     PINMUX_SINGLE(GETHER_RX_CTL),
0423     PINMUX_SINGLE(GETHER_RXC),
0424     PINMUX_SINGLE(GETHER_RD0),
0425     PINMUX_SINGLE(GETHER_RD1),
0426     PINMUX_SINGLE(GETHER_RD2),
0427     PINMUX_SINGLE(GETHER_RD3),
0428     PINMUX_SINGLE(GETHER_TX_CTL),
0429     PINMUX_SINGLE(GETHER_TXC),
0430     PINMUX_SINGLE(GETHER_TD0),
0431     PINMUX_SINGLE(GETHER_TD1),
0432     PINMUX_SINGLE(GETHER_TD2),
0433     PINMUX_SINGLE(GETHER_TD3),
0434     PINMUX_SINGLE(GETHER_TXCREFCLK),
0435     PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA),
0436     PINMUX_SINGLE(GETHER_MDIO_A),
0437     PINMUX_SINGLE(GETHER_MDC_A),
0438     PINMUX_SINGLE(GETHER_MAGIC),
0439     PINMUX_SINGLE(GETHER_PHY_INT_A),
0440     PINMUX_SINGLE(GETHER_LINK_A),
0441
0442     PINMUX_SINGLE(QSPI0_SPCLK),
0443     PINMUX_SINGLE(QSPI0_MOSI_IO0),
0444     PINMUX_SINGLE(QSPI0_MISO_IO1),
0445     PINMUX_SINGLE(QSPI0_IO2),
0446     PINMUX_SINGLE(QSPI0_IO3),
0447     PINMUX_SINGLE(QSPI0_SSL),
0448     PINMUX_SINGLE(QSPI1_SPCLK),
0449     PINMUX_SINGLE(QSPI1_MOSI_IO0),
0450     PINMUX_SINGLE(QSPI1_MISO_IO1),
0451     PINMUX_SINGLE(QSPI1_IO2),
0452     PINMUX_SINGLE(QSPI1_IO3),
0453     PINMUX_SINGLE(QSPI1_SSL),
0454     PINMUX_SINGLE(RPC_RESET_N),
0455     PINMUX_SINGLE(RPC_WP_N),
0456     PINMUX_SINGLE(RPC_INT_N),
0457
0458     /* IPSR0 */
0459     PINMUX_IPSR_GPSR(IP0_3_0,   DU_DR2),
0460     PINMUX_IPSR_GPSR(IP0_3_0,   SCK4),
0461     PINMUX_IPSR_GPSR(IP0_3_0,   GETHER_RMII_CRS_DV),
0462     PINMUX_IPSR_GPSR(IP0_3_0,   A0),
0463
0464     PINMUX_IPSR_GPSR(IP0_7_4,   DU_DR3),
0465     PINMUX_IPSR_GPSR(IP0_7_4,   RX4),
0466     PINMUX_IPSR_GPSR(IP0_7_4,   GETHER_RMII_RX_ER),
0467     PINMUX_IPSR_GPSR(IP0_7_4,   A1),
0468
0469     PINMUX_IPSR_GPSR(IP0_11_8,  DU_DR4),
0470     PINMUX_IPSR_GPSR(IP0_11_8,  TX4),
0471     PINMUX_IPSR_GPSR(IP0_11_8,  GETHER_RMII_RXD0),
0472     PINMUX_IPSR_GPSR(IP0_11_8,  A2),
0473
0474     PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
0475     PINMUX_IPSR_GPSR(IP0_15_12, CTS4_N),
0476     PINMUX_IPSR_GPSR(IP0_15_12, GETHER_RMII_RXD1),
0477     PINMUX_IPSR_GPSR(IP0_15_12, A3),
0478
0479     PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
0480     PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N),
0481     PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN),
0482     PINMUX_IPSR_GPSR(IP0_19_16, A4),
0483
0484     PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
0485     PINMUX_IPSR_GPSR(IP0_23_20, GETHER_RMII_TXD0),
0486     PINMUX_IPSR_GPSR(IP0_23_20, A5),
0487
0488     PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
0489     PINMUX_IPSR_GPSR(IP0_27_24, GETHER_RMII_TXD1),
0490     PINMUX_IPSR_GPSR(IP0_27_24, A6),
0491
0492     PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
0493     PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT),
0494     PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK),
0495     PINMUX_IPSR_GPSR(IP0_31_28, A7),
0496     PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
0497
0498     /* IPSR1 */
0499     PINMUX_IPSR_GPSR(IP1_3_0,   DU_DG4),
0500     PINMUX_IPSR_GPSR(IP1_3_0,   SCL5),
0501     PINMUX_IPSR_GPSR(IP1_3_0,   A8),
0502
0503     PINMUX_IPSR_GPSR(IP1_7_4,   DU_DG5),
0504     PINMUX_IPSR_GPSR(IP1_7_4,   SDA5),
0505     PINMUX_IPSR_MSEL(IP1_7_4,   GETHER_MDC_B, SEL_GETHER_1),
0506     PINMUX_IPSR_GPSR(IP1_7_4,   A9),
0507
0508     PINMUX_IPSR_GPSR(IP1_11_8,  DU_DG6),
0509     PINMUX_IPSR_MSEL(IP1_11_8,  SCIF_CLK_A, SEL_HSCIF0_0),
0510     PINMUX_IPSR_MSEL(IP1_11_8,  GETHER_MDIO_B, SEL_GETHER_1),
0511     PINMUX_IPSR_GPSR(IP1_11_8,  A10),
0512
0513     PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
0514     PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0),
0515     PINMUX_IPSR_GPSR(IP1_15_12, A11),
0516
0517     PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
0518     PINMUX_IPSR_MSEL(IP1_19_16, HSCK0_A, SEL_HSCIF0_0),
0519     PINMUX_IPSR_GPSR(IP1_19_16, A12),
0520     PINMUX_IPSR_GPSR(IP1_19_16, IRQ1),
0521
0522     PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
0523     PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_A, SEL_HSCIF0_0),
0524     PINMUX_IPSR_GPSR(IP1_23_20, A13),
0525     PINMUX_IPSR_GPSR(IP1_23_20, IRQ2),
0526
0527     PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
0528     PINMUX_IPSR_MSEL(IP1_27_24, HCTS0_N_A, SEL_HSCIF0_0),
0529     PINMUX_IPSR_GPSR(IP1_27_24, A14),
0530     PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
0531
0532     PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
0533     PINMUX_IPSR_MSEL(IP1_31_28, HTX0_A, SEL_HSCIF0_0),
0534     PINMUX_IPSR_MSEL(IP1_31_28, PWM0_A, SEL_PWM0_0),
0535     PINMUX_IPSR_GPSR(IP1_31_28, A15),
0536
0537     /* IPSR2 */
0538     PINMUX_IPSR_GPSR(IP2_3_0,   DU_DB6),
0539     PINMUX_IPSR_GPSR(IP2_3_0,   MSIOF3_RXD),
0540     PINMUX_IPSR_GPSR(IP2_3_0,   A16),
0541
0542     PINMUX_IPSR_GPSR(IP2_7_4,   DU_DB7),
0543     PINMUX_IPSR_GPSR(IP2_7_4,   MSIOF3_TXD),
0544     PINMUX_IPSR_GPSR(IP2_7_4,   A17),
0545
0546     PINMUX_IPSR_GPSR(IP2_11_8,  DU_DOTCLKOUT),
0547     PINMUX_IPSR_GPSR(IP2_11_8,  MSIOF3_SS1),
0548     PINMUX_IPSR_MSEL(IP2_11_8,  GETHER_LINK_B, SEL_GETHER_1),
0549     PINMUX_IPSR_GPSR(IP2_11_8,  A18),
0550
0551     PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
0552     PINMUX_IPSR_GPSR(IP2_15_12, MSIOF3_SS2),
0553     PINMUX_IPSR_MSEL(IP2_15_12, GETHER_PHY_INT_B, SEL_GETHER_1),
0554     PINMUX_IPSR_GPSR(IP2_15_12, A19),
0555     PINMUX_IPSR_GPSR(IP2_15_12, FXR_TXENA_N),
0556
0557     PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
0558     PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
0559     PINMUX_IPSR_GPSR(IP2_19_16, FXR_TXENB_N),
0560
0561     PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
0562     PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
0563
0564     PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
0565
0566     PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
0567     PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
0568     PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
0569     PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
0570
0571     /* IPSR3 */
0572     PINMUX_IPSR_GPSR(IP3_3_0,   VI0_CLKENB),
0573     PINMUX_IPSR_GPSR(IP3_3_0,   MSIOF2_RXD),
0574     PINMUX_IPSR_GPSR(IP3_3_0,   RX3),
0575     PINMUX_IPSR_GPSR(IP3_3_0,   RD_WR_N),
0576     PINMUX_IPSR_GPSR(IP3_3_0,   HCTS3_N),
0577
0578     PINMUX_IPSR_GPSR(IP3_7_4,   VI0_HSYNC_N),
0579     PINMUX_IPSR_GPSR(IP3_7_4,   MSIOF2_TXD),
0580     PINMUX_IPSR_GPSR(IP3_7_4,   TX3),
0581     PINMUX_IPSR_GPSR(IP3_7_4,   HRTS3_N),
0582
0583     PINMUX_IPSR_GPSR(IP3_11_8,  VI0_VSYNC_N),
0584     PINMUX_IPSR_GPSR(IP3_11_8,  MSIOF2_SYNC),
0585     PINMUX_IPSR_GPSR(IP3_11_8,  CTS3_N),
0586     PINMUX_IPSR_GPSR(IP3_11_8,  HTX3),
0587
0588     PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
0589     PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
0590     PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
0591     PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
0592
0593     PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
0594     PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
0595     PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
0596     PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
0597
0598     PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
0599     PINMUX_IPSR_GPSR(IP3_23_20, AVB_AVTP_PPS),
0600
0601     PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
0602     PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
0603
0604     PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
0605     PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
0606     PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
0607
0608     /* IPSR4 */
0609     PINMUX_IPSR_GPSR(IP4_3_0,   VI0_DATA5),
0610     PINMUX_IPSR_GPSR(IP4_3_0,   HCTS1_N),
0611     PINMUX_IPSR_MSEL(IP4_3_0,   TX1_A, SEL_SCIF1_0),
0612
0613     PINMUX_IPSR_GPSR(IP4_7_4,   VI0_DATA6),
0614     PINMUX_IPSR_GPSR(IP4_7_4,   HTX1),
0615     PINMUX_IPSR_GPSR(IP4_7_4,   CTS1_N),
0616
0617     PINMUX_IPSR_GPSR(IP4_11_8,  VI0_DATA7),
0618     PINMUX_IPSR_GPSR(IP4_11_8,  HRX1),
0619     PINMUX_IPSR_GPSR(IP4_11_8,  RTS1_N),
0620
0621     PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
0622     PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
0623
0624     PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
0625     PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
0626     PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
0627
0628     PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
0629     PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
0630     PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
0631
0632     PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
0633     PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
0634     PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
0635
0636     PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
0637     PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
0638     PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
0639     PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
0640
0641     /* IPSR5 */
0642     PINMUX_IPSR_GPSR(IP5_3_0,   VI1_CLK),
0643     PINMUX_IPSR_GPSR(IP5_3_0,   MSIOF1_RXD),
0644     PINMUX_IPSR_GPSR(IP5_3_0,   CS0_N),
0645
0646     PINMUX_IPSR_GPSR(IP5_7_4,   VI1_CLKENB),
0647     PINMUX_IPSR_GPSR(IP5_7_4,   MSIOF1_TXD),
0648     PINMUX_IPSR_GPSR(IP5_7_4,   D0),
0649
0650     PINMUX_IPSR_GPSR(IP5_11_8,  VI1_HSYNC_N),
0651     PINMUX_IPSR_GPSR(IP5_11_8,  MSIOF1_SCK),
0652     PINMUX_IPSR_GPSR(IP5_11_8,  D1),
0653
0654     PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
0655     PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
0656     PINMUX_IPSR_GPSR(IP5_15_12, D2),
0657
0658     PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
0659     PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
0660     PINMUX_IPSR_GPSR(IP5_19_16, D3),
0661     PINMUX_IPSR_GPSR(IP5_19_16, MMC_WP),
0662
0663     PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
0664     PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
0665     PINMUX_IPSR_GPSR(IP5_23_20, D4),
0666     PINMUX_IPSR_GPSR(IP5_23_20, MMC_CD),
0667
0668     PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
0669     PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
0670     PINMUX_IPSR_GPSR(IP5_27_24, D5),
0671     PINMUX_IPSR_GPSR(IP5_27_24, MMC_DS),
0672
0673     PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
0674     PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
0675     PINMUX_IPSR_GPSR(IP5_31_28, D6),
0676     PINMUX_IPSR_GPSR(IP5_31_28, MMC_CMD),
0677
0678     /* IPSR6 */
0679     PINMUX_IPSR_GPSR(IP6_3_0,   VI1_DATA4),
0680     PINMUX_IPSR_MSEL(IP6_3_0,   CANFD_CLK_B, SEL_CANFD0_1),
0681     PINMUX_IPSR_GPSR(IP6_3_0,   D7),
0682     PINMUX_IPSR_GPSR(IP6_3_0,   MMC_D0),
0683
0684     PINMUX_IPSR_GPSR(IP6_7_4,   VI1_DATA5),
0685     PINMUX_IPSR_GPSR(IP6_7_4,   D8),
0686     PINMUX_IPSR_GPSR(IP6_7_4,   MMC_D1),
0687
0688     PINMUX_IPSR_GPSR(IP6_11_8,  VI1_DATA6),
0689     PINMUX_IPSR_GPSR(IP6_11_8,  D9),
0690     PINMUX_IPSR_GPSR(IP6_11_8,  MMC_D2),
0691
0692     PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
0693     PINMUX_IPSR_GPSR(IP6_15_12, D10),
0694     PINMUX_IPSR_GPSR(IP6_15_12, MMC_D3),
0695
0696     PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
0697     PINMUX_IPSR_GPSR(IP6_19_16, D11),
0698     PINMUX_IPSR_GPSR(IP6_19_16, MMC_CLK),
0699
0700     PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
0701     PINMUX_IPSR_MSEL(IP6_23_20, TCLK1_A, SEL_TMU_0),
0702     PINMUX_IPSR_GPSR(IP6_23_20, D12),
0703     PINMUX_IPSR_GPSR(IP6_23_20, MMC_D4),
0704
0705     PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
0706     PINMUX_IPSR_MSEL(IP6_27_24, TCLK2_A, SEL_TMU_0),
0707     PINMUX_IPSR_GPSR(IP6_27_24, D13),
0708     PINMUX_IPSR_GPSR(IP6_27_24, MMC_D5),
0709
0710     PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
0711     PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
0712     PINMUX_IPSR_GPSR(IP6_31_28, D14),
0713     PINMUX_IPSR_GPSR(IP6_31_28, MMC_D6),
0714
0715     /* IPSR7 */
0716     PINMUX_IPSR_GPSR(IP7_3_0,   VI1_FIELD),
0717     PINMUX_IPSR_GPSR(IP7_3_0,   SDA4),
0718     PINMUX_IPSR_GPSR(IP7_3_0,   D15),
0719     PINMUX_IPSR_GPSR(IP7_3_0,   MMC_D7),
0720
0721     PINMUX_IPSR_GPSR(IP7_7_4,   SCL0),
0722     PINMUX_IPSR_GPSR(IP7_7_4,   CLKOUT),
0723
0724     PINMUX_IPSR_GPSR(IP7_11_8,  SDA0),
0725     PINMUX_IPSR_GPSR(IP7_11_8,  BS_N),
0726     PINMUX_IPSR_GPSR(IP7_11_8,  SCK0),
0727     PINMUX_IPSR_MSEL(IP7_11_8,  HSCK0_B, SEL_HSCIF0_1),
0728
0729     PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
0730     PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
0731     PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
0732     PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
0733     PINMUX_IPSR_GPSR(IP7_15_12, HCTS0_N_B),
0734
0735     PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
0736     PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
0737     PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
0738     PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
0739     PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1),
0740
0741     PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
0742     PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
0743     PINMUX_IPSR_GPSR(IP7_23_20, RX0),
0744     PINMUX_IPSR_MSEL(IP7_23_20, HRX0_B, SEL_HSCIF0_1),
0745
0746     PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
0747     PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
0748     PINMUX_IPSR_GPSR(IP7_27_24, TX0),
0749     PINMUX_IPSR_MSEL(IP7_27_24, HTX0_B, SEL_HSCIF0_1),
0750
0751     PINMUX_IPSR_GPSR(IP7_31_28, AVB_AVTP_MATCH),
0752     PINMUX_IPSR_GPSR(IP7_31_28, TPU0TO0),
0753
0754     /* IPSR8 */
0755     PINMUX_IPSR_GPSR(IP8_3_0,   AVB_AVTP_CAPTURE),
0756     PINMUX_IPSR_GPSR(IP8_3_0,   TPU0TO1),
0757
0758     PINMUX_IPSR_MSEL(IP8_7_4,   CANFD0_TX_A, SEL_CANFD0_0),
0759     PINMUX_IPSR_GPSR(IP8_7_4,   FXR_TXDA),
0760     PINMUX_IPSR_MSEL(IP8_7_4,   PWM0_B, SEL_PWM0_1),
0761     PINMUX_IPSR_GPSR(IP8_7_4,   DU_DISP),
0762
0763     PINMUX_IPSR_MSEL(IP8_11_8,  CANFD0_RX_A, SEL_CANFD0_0),
0764     PINMUX_IPSR_GPSR(IP8_11_8,  RXDA_EXTFXR),
0765     PINMUX_IPSR_MSEL(IP8_11_8,  PWM1_B, SEL_PWM1_1),
0766     PINMUX_IPSR_GPSR(IP8_11_8,  DU_CDE),
0767
0768     PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_TX),
0769     PINMUX_IPSR_GPSR(IP8_15_12, FXR_TXDB),
0770     PINMUX_IPSR_MSEL(IP8_15_12, PWM2_B, SEL_PWM2_1),
0771     PINMUX_IPSR_MSEL(IP8_15_12, TCLK1_B, SEL_TMU_1),
0772     PINMUX_IPSR_MSEL(IP8_15_12, TX1_B, SEL_SCIF1_1),
0773
0774     PINMUX_IPSR_GPSR(IP8_19_16, CANFD1_RX),
0775     PINMUX_IPSR_GPSR(IP8_19_16, RXDB_EXTFXR),
0776     PINMUX_IPSR_MSEL(IP8_19_16, PWM3_B, SEL_PWM3_1),
0777     PINMUX_IPSR_MSEL(IP8_19_16, TCLK2_B, SEL_TMU_1),
0778     PINMUX_IPSR_MSEL(IP8_19_16, RX1_B, SEL_SCIF1_1),
0779
0780     PINMUX_IPSR_MSEL(IP8_23_20, CANFD_CLK_A, SEL_CANFD0_0),
0781     PINMUX_IPSR_GPSR(IP8_23_20, CLK_EXTFXR),
0782     PINMUX_IPSR_MSEL(IP8_23_20, PWM4_B, SEL_PWM4_1),
0783     PINMUX_IPSR_MSEL(IP8_23_20, SPEEDIN_B, SEL_RSP_1),
0784     PINMUX_IPSR_MSEL(IP8_23_20, SCIF_CLK_B, SEL_HSCIF0_1),
0785
0786     PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKIN),
0787     PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_IN),
0788
0789     PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKOUT),
0790     PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKEN_OUT),
0791
0792     /* IPSR9 */
0793     PINMUX_IPSR_GPSR(IP9_3_0,   IRQ4),
0794     PINMUX_IPSR_GPSR(IP9_3_0,   VI0_DATA12),
0795
0796     PINMUX_IPSR_GPSR(IP9_7_4,   IRQ5),
0797     PINMUX_IPSR_GPSR(IP9_7_4,   VI0_DATA13),
0798
0799     PINMUX_IPSR_GPSR(IP9_11_8,  MSIOF0_RXD),
0800     PINMUX_IPSR_GPSR(IP9_11_8,  DU_DR0),
0801     PINMUX_IPSR_GPSR(IP9_11_8,  VI0_DATA14),
0802
0803     PINMUX_IPSR_GPSR(IP9_15_12, MSIOF0_TXD),
0804     PINMUX_IPSR_GPSR(IP9_15_12, DU_DR1),
0805     PINMUX_IPSR_GPSR(IP9_15_12, VI0_DATA15),
0806
0807     PINMUX_IPSR_GPSR(IP9_19_16, MSIOF0_SCK),
0808     PINMUX_IPSR_GPSR(IP9_19_16, DU_DG0),
0809     PINMUX_IPSR_GPSR(IP9_19_16, VI0_DATA16),
0810
0811     PINMUX_IPSR_GPSR(IP9_23_20, MSIOF0_SYNC),
0812     PINMUX_IPSR_GPSR(IP9_23_20, DU_DG1),
0813     PINMUX_IPSR_GPSR(IP9_23_20, VI0_DATA17),
0814
0815     PINMUX_IPSR_GPSR(IP9_27_24, MSIOF0_SS1),
0816     PINMUX_IPSR_GPSR(IP9_27_24, DU_DB0),
0817     PINMUX_IPSR_GPSR(IP9_27_24, TCLK3),
0818     PINMUX_IPSR_GPSR(IP9_27_24, VI0_DATA18),
0819
0820     PINMUX_IPSR_GPSR(IP9_31_28, MSIOF0_SS2),
0821     PINMUX_IPSR_GPSR(IP9_31_28, DU_DB1),
0822     PINMUX_IPSR_GPSR(IP9_31_28, TCLK4),
0823     PINMUX_IPSR_GPSR(IP9_31_28, VI0_DATA19),
0824
0825     /* IPSR10 */
0826     PINMUX_IPSR_GPSR(IP10_3_0,  SCL3),
0827     PINMUX_IPSR_GPSR(IP10_3_0,  VI0_DATA20),
0828
0829     PINMUX_IPSR_GPSR(IP10_7_4,  SDA3),
0830     PINMUX_IPSR_GPSR(IP10_7_4,  VI0_DATA21),
0831
0832     PINMUX_IPSR_GPSR(IP10_11_8, FSO_CFE_0_N),
0833     PINMUX_IPSR_GPSR(IP10_11_8, VI0_DATA22),
0834
0835     PINMUX_IPSR_GPSR(IP10_15_12,    FSO_CFE_1_N),
0836     PINMUX_IPSR_GPSR(IP10_15_12,    VI0_DATA23),
0837
0838     PINMUX_IPSR_GPSR(IP10_19_16,    FSO_TOE_N),
0839 };
0840
0841 /*
0842  * Pins not associated with a GPIO port.
0843  */
0844 enum {
0845     GP_ASSIGN_LAST(),
0846     NOGP_ALL(),
0847 };
0848
0849 static const struct sh_pfc_pin pinmux_pins[] = {
0850     PINMUX_GPIO_GP_ALL(),
0851     PINMUX_NOGP_ALL(),
0852 };
0853
0854 /* - AVB -------------------------------------------------------------------- */
0855 static const unsigned int avb_link_pins[] = {
0856     /* AVB_LINK */
0857     RCAR_GP_PIN(1, 18),
0858 };
0859 static const unsigned int avb_link_mux[] = {
0860     AVB_LINK_MARK,
0861 };
0862 static const unsigned int avb_magic_pins[] = {
0863     /* AVB_MAGIC */
0864     RCAR_GP_PIN(1, 16),
0865 };
0866 static const unsigned int avb_magic_mux[] = {
0867     AVB_MAGIC_MARK,
0868 };
0869 static const unsigned int avb_phy_int_pins[] = {
0870     /* AVB_PHY_INT */
0871     RCAR_GP_PIN(1, 17),
0872 };
0873 static const unsigned int avb_phy_int_mux[] = {
0874     AVB_PHY_INT_MARK,
0875 };
0876 static const unsigned int avb_mdio_pins[] = {
0877     /* AVB_MDC, AVB_MDIO */
0878     RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
0879 };
0880 static const unsigned int avb_mdio_mux[] = {
0881     AVB_MDC_MARK, AVB_MDIO_MARK,
0882 };
0883 static const unsigned int avb_rgmii_pins[] = {
0884     /*
0885      * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3,
0886      * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3,
0887      */
0888     RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
0889     RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
0890     RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
0891     RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
0892     RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
0893     RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
0894 };
0895 static const unsigned int avb_rgmii_mux[] = {
0896     AVB_TX_CTL_MARK, AVB_TXC_MARK,
0897     AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
0898     AVB_RX_CTL_MARK, AVB_RXC_MARK,
0899     AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
0900 };
0901 static const unsigned int avb_txcrefclk_pins[] = {
0902     /* AVB_TXCREFCLK */
0903     RCAR_GP_PIN(1, 13),
0904 };
0905 static const unsigned int avb_txcrefclk_mux[] = {
0906     AVB_TXCREFCLK_MARK,
0907 };
0908 static const unsigned int avb_avtp_pps_pins[] = {
0909     /* AVB_AVTP_PPS */
0910     RCAR_GP_PIN(2, 6),
0911 };
0912 static const unsigned int avb_avtp_pps_mux[] = {
0913     AVB_AVTP_PPS_MARK,
0914 };
0915 static const unsigned int avb_avtp_capture_pins[] = {
0916     /* AVB_AVTP_CAPTURE */
0917     RCAR_GP_PIN(1, 20),
0918 };
0919 static const unsigned int avb_avtp_capture_mux[] = {
0920     AVB_AVTP_CAPTURE_MARK,
0921 };
0922 static const unsigned int avb_avtp_match_pins[] = {
0923     /* AVB_AVTP_MATCH */
0924     RCAR_GP_PIN(1, 19),
0925 };
0926 static const unsigned int avb_avtp_match_mux[] = {
0927     AVB_AVTP_MATCH_MARK,
0928 };
0929
0930 /* - CANFD0 ----------------------------------------------------------------- */
0931 static const unsigned int canfd0_data_a_pins[] = {
0932     /* CANFD0_TX, CANFD0_RX */
0933     RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
0934 };
0935 static const unsigned int canfd0_data_a_mux[] = {
0936     CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
0937 };
0938 static const unsigned int canfd0_data_b_pins[] = {
0939     /* CANFD0_TX, CANFD0_RX */
0940     RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
0941 };
0942 static const unsigned int canfd0_data_b_mux[] = {
0943     CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
0944 };
0945
0946 /* - CANFD1 ----------------------------------------------------------------- */
0947 static const unsigned int canfd1_data_pins[] = {
0948     /* CANFD1_TX, CANFD1_RX */
0949     RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
0950 };
0951 static const unsigned int canfd1_data_mux[] = {
0952     CANFD1_TX_MARK, CANFD1_RX_MARK,
0953 };
0954
0955 /* - CANFD Clock ------------------------------------------------------------ */
0956 static const unsigned int canfd_clk_a_pins[] = {
0957     /* CANFD_CLK */
0958     RCAR_GP_PIN(1, 25),
0959 };
0960 static const unsigned int canfd_clk_a_mux[] = {
0961     CANFD_CLK_A_MARK,
0962 };
0963 static const unsigned int canfd_clk_b_pins[] = {
0964     /* CANFD_CLK */
0965     RCAR_GP_PIN(3, 8),
0966 };
0967 static const unsigned int canfd_clk_b_mux[] = {
0968     CANFD_CLK_B_MARK,
0969 };
0970
0971 /* - DU --------------------------------------------------------------------- */
0972 static const unsigned int du_rgb666_pins[] = {
0973     /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
0974     RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
0975     RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
0976     RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
0977     RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
0978     RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
0979     RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
0980 };
0981 static const unsigned int du_rgb666_mux[] = {
0982     DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
0983     DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
0984     DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
0985     DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
0986     DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
0987     DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
0988 };
0989 static const unsigned int du_rgb888_pins[] = {
0990     /* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */
0991     RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
0992     RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
0993     RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19),
0994     RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
0995     RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
0996     RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
0997     RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
0998     RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
0999     RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
1000 };
1001 static const unsigned int du_rgb888_mux[] = {
1002     DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
1003     DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
1004     DU_DR1_MARK, DU_DR0_MARK,
1005     DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
1006     DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
1007     DU_DG1_MARK, DU_DG0_MARK,
1008     DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
1009     DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
1010     DU_DB1_MARK, DU_DB0_MARK,
1011 };
1012 static const unsigned int du_clk_out_pins[] = {
1013     /* DU_DOTCLKOUT */
1014     RCAR_GP_PIN(0, 18),
1015 };
1016 static const unsigned int du_clk_out_mux[] = {
1017     DU_DOTCLKOUT_MARK,
1018 };
1019 static const unsigned int du_sync_pins[] = {
1020     /* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */
1021     RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
1022 };
1023 static const unsigned int du_sync_mux[] = {
1024     DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
1025 };
1026 static const unsigned int du_oddf_pins[] = {
1027     /* DU_EXODDF/DU_ODDF/DISP/CDE */
1028     RCAR_GP_PIN(0, 21),
1029 };
1030 static const unsigned int du_oddf_mux[] = {
1031     DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1032 };
1033 static const unsigned int du_cde_pins[] = {
1034     /* DU_CDE */
1035     RCAR_GP_PIN(1, 22),
1036 };
1037 static const unsigned int du_cde_mux[] = {
1038     DU_CDE_MARK,
1039 };
1040 static const unsigned int du_disp_pins[] = {
1041     /* DU_DISP */
1042     RCAR_GP_PIN(1, 21),
1043 };
1044 static const unsigned int du_disp_mux[] = {
1045     DU_DISP_MARK,
1046 };
1047
1048 /* - GETHER ----------------------------------------------------------------- */
1049 static const unsigned int gether_link_a_pins[] = {
1050     /* GETHER_LINK */
1051     RCAR_GP_PIN(4, 24),
1052 };
1053 static const unsigned int gether_link_a_mux[] = {
1054     GETHER_LINK_A_MARK,
1055 };
1056 static const unsigned int gether_phy_int_a_pins[] = {
1057     /* GETHER_PHY_INT */
1058     RCAR_GP_PIN(4, 23),
1059 };
1060 static const unsigned int gether_phy_int_a_mux[] = {
1061     GETHER_PHY_INT_A_MARK,
1062 };
1063 static const unsigned int gether_mdio_a_pins[] = {
1064     /* GETHER_MDC, GETHER_MDIO */
1065     RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
1066 };
1067 static const unsigned int gether_mdio_a_mux[] = {
1068     GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK,
1069 };
1070 static const unsigned int gether_link_b_pins[] = {
1071     /* GETHER_LINK */
1072     RCAR_GP_PIN(0, 18),
1073 };
1074 static const unsigned int gether_link_b_mux[] = {
1075     GETHER_LINK_B_MARK,
1076 };
1077 static const unsigned int gether_phy_int_b_pins[] = {
1078     /* GETHER_PHY_INT */
1079     RCAR_GP_PIN(0, 19),
1080 };
1081 static const unsigned int gether_phy_int_b_mux[] = {
1082     GETHER_PHY_INT_B_MARK,
1083 };
1084 static const unsigned int gether_mdio_b_mux[] = {
1085     GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK,
1086 };
1087 static const unsigned int gether_mdio_b_pins[] = {
1088     /* GETHER_MDC, GETHER_MDIO */
1089     RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1090 };
1091 static const unsigned int gether_magic_pins[] = {
1092     /* GETHER_MAGIC */
1093     RCAR_GP_PIN(4, 22),
1094 };
1095 static const unsigned int gether_magic_mux[] = {
1096     GETHER_MAGIC_MARK,
1097 };
1098 static const unsigned int gether_rgmii_pins[] = {
1099     /*
1100      * GETHER_TX_CTL, GETHER_TXC,
1101      * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3,
1102      * GETHER_RX_CTL, GETHER_RXC,
1103      * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3,
1104      */
1105     RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
1106     RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
1107     RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
1108     RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
1109     RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1110     RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1111 };
1112 static const unsigned int gether_rgmii_mux[] = {
1113     GETHER_TX_CTL_MARK, GETHER_TXC_MARK,
1114     GETHER_TD0_MARK, GETHER_TD1_MARK,
1115     GETHER_TD2_MARK, GETHER_TD3_MARK,
1116     GETHER_RX_CTL_MARK, GETHER_RXC_MARK,
1117     GETHER_RD0_MARK, AVB_RD1_MARK,
1118     GETHER_RD2_MARK, AVB_RD3_MARK,
1119 };
1120 static const unsigned int gether_txcrefclk_pins[] = {
1121     /* GETHER_TXCREFCLK */
1122     RCAR_GP_PIN(4, 18),
1123 };
1124 static const unsigned int gether_txcrefclk_mux[] = {
1125     GETHER_TXCREFCLK_MARK,
1126 };
1127 static const unsigned int gether_txcrefclk_mega_pins[] = {
1128     /* GETHER_TXCREFCLK_MEGA */
1129     RCAR_GP_PIN(4, 19),
1130 };
1131 static const unsigned int gether_txcrefclk_mega_mux[] = {
1132     GETHER_TXCREFCLK_MEGA_MARK,
1133 };
1134 static const unsigned int gether_rmii_pins[] = {
1135     /*
1136      * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER,
1137      * GETHER_RMII_RXD0, GETHER_RMII_RXD1,
1138      * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0,
1139      * GETHER_RMII_TXD1, GETHER_RMII_REFCLK
1140      */
1141     RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
1142     RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
1143     RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
1144     RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
1145 };
1146 static const unsigned int gether_rmii_mux[] = {
1147     GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK,
1148     GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK,
1149     GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK,
1150     GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK,
1151 };
1152
1153 /* - HSCIF0 ----------------------------------------------------------------- */
1154 static const unsigned int hscif0_data_a_pins[] = {
1155     /* HRX0, HTX0 */
1156     RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
1157 };
1158 static const unsigned int hscif0_data_a_mux[] = {
1159     HRX0_A_MARK, HTX0_A_MARK,
1160 };
1161 static const unsigned int hscif0_clk_a_pins[] = {
1162     /* HSCK0 */
1163     RCAR_GP_PIN(0, 12),
1164 };
1165 static const unsigned int hscif0_clk_a_mux[] = {
1166     HSCK0_A_MARK,
1167 };
1168 static const unsigned int hscif0_ctrl_a_pins[] = {
1169     /* HRTS0#, HCTS0# */
1170     RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
1171 };
1172 static const unsigned int hscif0_ctrl_a_mux[] = {
1173     HRTS0_N_A_MARK, HCTS0_N_A_MARK,
1174 };
1175 static const unsigned int hscif0_data_b_pins[] = {
1176     /* HRX0, HTX0 */
1177     RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1178 };
1179 static const unsigned int hscif0_data_b_mux[] = {
1180     HRX0_B_MARK, HTX0_B_MARK,
1181 };
1182 static const unsigned int hscif0_clk_b_pins[] = {
1183     /* HSCK0 */
1184     RCAR_GP_PIN(4, 1),
1185 };
1186 static const unsigned int hscif0_clk_b_mux[] = {
1187     HSCK0_B_MARK,
1188 };
1189 static const unsigned int hscif0_ctrl_b_pins[] = {
1190     /* HRTS0#, HCTS0# */
1191     RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1192 };
1193 static const unsigned int hscif0_ctrl_b_mux[] = {
1194     HRTS0_N_B_MARK, HCTS0_N_B_MARK,
1195 };
1196
1197 /* - HSCIF1 ----------------------------------------------------------------- */
1198 static const unsigned int hscif1_data_pins[] = {
1199     /* HRX1, HTX1 */
1200     RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1201 };
1202 static const unsigned int hscif1_data_mux[] = {
1203     HRX1_MARK, HTX1_MARK,
1204 };
1205 static const unsigned int hscif1_clk_pins[] = {
1206     /* HSCK1 */
1207     RCAR_GP_PIN(2, 7),
1208 };
1209 static const unsigned int hscif1_clk_mux[] = {
1210     HSCK1_MARK,
1211 };
1212 static const unsigned int hscif1_ctrl_pins[] = {
1213     /* HRTS1#, HCTS1# */
1214     RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1215 };
1216 static const unsigned int hscif1_ctrl_mux[] = {
1217     HRTS1_N_MARK, HCTS1_N_MARK,
1218 };
1219
1220 /* - HSCIF2 ----------------------------------------------------------------- */
1221 static const unsigned int hscif2_data_pins[] = {
1222     /* HRX2, HTX2 */
1223     RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
1224 };
1225 static const unsigned int hscif2_data_mux[] = {
1226     HRX2_MARK, HTX2_MARK,
1227 };
1228 static const unsigned int hscif2_clk_pins[] = {
1229     /* HSCK2 */
1230     RCAR_GP_PIN(2, 12),
1231 };
1232 static const unsigned int hscif2_clk_mux[] = {
1233     HSCK2_MARK,
1234 };
1235 static const unsigned int hscif2_ctrl_pins[] = {
1236     /* HRTS2#, HCTS2# */
1237     RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1238 };
1239 static const unsigned int hscif2_ctrl_mux[] = {
1240     HRTS2_N_MARK, HCTS2_N_MARK,
1241 };
1242
1243 /* - HSCIF3 ----------------------------------------------------------------- */
1244 static const unsigned int hscif3_data_pins[] = {
1245     /* HRX3, HTX3 */
1246     RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1247 };
1248 static const unsigned int hscif3_data_mux[] = {
1249     HRX3_MARK, HTX3_MARK,
1250 };
1251 static const unsigned int hscif3_clk_pins[] = {
1252     /* HSCK3 */
1253     RCAR_GP_PIN(2, 0),
1254 };
1255 static const unsigned int hscif3_clk_mux[] = {
1256     HSCK3_MARK,
1257 };
1258 static const unsigned int hscif3_ctrl_pins[] = {
1259     /* HRTS3#, HCTS3# */
1260     RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
1261 };
1262 static const unsigned int hscif3_ctrl_mux[] = {
1263     HRTS3_N_MARK, HCTS3_N_MARK,
1264 };
1265
1266 /* - I2C0 ------------------------------------------------------------------- */
1267 static const unsigned int i2c0_pins[] = {
1268     /* SDA0, SCL0 */
1269     RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
1270 };
1271 static const unsigned int i2c0_mux[] = {
1272     SDA0_MARK, SCL0_MARK,
1273 };
1274
1275 /* - I2C1 ------------------------------------------------------------------- */
1276 static const unsigned int i2c1_pins[] = {
1277     /* SDA1, SCL1 */
1278     RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1279 };
1280 static const unsigned int i2c1_mux[] = {
1281     SDA1_MARK, SCL1_MARK,
1282 };
1283
1284 /* - I2C2 ------------------------------------------------------------------- */
1285 static const unsigned int i2c2_pins[] = {
1286     /* SDA2, SCL2 */
1287     RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
1288 };
1289 static const unsigned int i2c2_mux[] = {
1290     SDA2_MARK, SCL2_MARK,
1291 };
1292
1293 /* - I2C3 ------------------------------------------------------------------- */
1294 static const unsigned int i2c3_pins[] = {
1295     /* SDA3, SCL3 */
1296     RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
1297 };
1298 static const unsigned int i2c3_mux[] = {
1299     SDA3_MARK, SCL3_MARK,
1300 };
1301
1302 /* - I2C4 ------------------------------------------------------------------- */
1303 static const unsigned int i2c4_pins[] = {
1304     /* SDA4, SCL4 */
1305     RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
1306 };
1307 static const unsigned int i2c4_mux[] = {
1308     SDA4_MARK, SCL4_MARK,
1309 };
1310
1311 /* - I2C5 ------------------------------------------------------------------- */
1312 static const unsigned int i2c5_pins[] = {
1313     /* SDA5, SCL5 */
1314     RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1315 };
1316 static const unsigned int i2c5_mux[] = {
1317     SDA5_MARK, SCL5_MARK,
1318 };
1319
1320 /* - INTC-EX ---------------------------------------------------------------- */
1321 static const unsigned int intc_ex_irq0_pins[] = {
1322     /* IRQ0 */
1323     RCAR_GP_PIN(1, 0),
1324 };
1325 static const unsigned int intc_ex_irq0_mux[] = {
1326     IRQ0_MARK,
1327 };
1328 static const unsigned int intc_ex_irq1_pins[] = {
1329     /* IRQ1 */
1330     RCAR_GP_PIN(0, 12),
1331 };
1332 static const unsigned int intc_ex_irq1_mux[] = {
1333     IRQ1_MARK,
1334 };
1335 static const unsigned int intc_ex_irq2_pins[] = {
1336     /* IRQ2 */
1337     RCAR_GP_PIN(0, 13),
1338 };
1339 static const unsigned int intc_ex_irq2_mux[] = {
1340     IRQ2_MARK,
1341 };
1342 static const unsigned int intc_ex_irq3_pins[] = {
1343     /* IRQ3 */
1344     RCAR_GP_PIN(0, 14),
1345 };
1346 static const unsigned int intc_ex_irq3_mux[] = {
1347     IRQ3_MARK,
1348 };
1349 static const unsigned int intc_ex_irq4_pins[] = {
1350     /* IRQ4 */
1351     RCAR_GP_PIN(2, 17),
1352 };
1353 static const unsigned int intc_ex_irq4_mux[] = {
1354     IRQ4_MARK,
1355 };
1356 static const unsigned int intc_ex_irq5_pins[] = {
1357     /* IRQ5 */
1358     RCAR_GP_PIN(2, 18),
1359 };
1360 static const unsigned int intc_ex_irq5_mux[] = {
1361     IRQ5_MARK,
1362 };
1363
1364 /* - MMC -------------------------------------------------------------------- */
1365 static const unsigned int mmc_data_pins[] = {
1366     /* MMC_D[0:7] */
1367     RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1368     RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1369     RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
1370     RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1371 };
1372 static const unsigned int mmc_data_mux[] = {
1373     MMC_D0_MARK, MMC_D1_MARK,
1374     MMC_D2_MARK, MMC_D3_MARK,
1375     MMC_D4_MARK, MMC_D5_MARK,
1376     MMC_D6_MARK, MMC_D7_MARK,
1377 };
1378 static const unsigned int mmc_ctrl_pins[] = {
1379     /* MMC_CLK, MMC_CMD */
1380     RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7),
1381 };
1382 static const unsigned int mmc_ctrl_mux[] = {
1383     MMC_CLK_MARK, MMC_CMD_MARK,
1384 };
1385 static const unsigned int mmc_cd_pins[] = {
1386     /* MMC_CD */
1387     RCAR_GP_PIN(3, 5),
1388 };
1389 static const unsigned int mmc_cd_mux[] = {
1390     MMC_CD_MARK,
1391 };
1392 static const unsigned int mmc_wp_pins[] = {
1393     /* MMC_WP */
1394     RCAR_GP_PIN(3, 4),
1395 };
1396 static const unsigned int mmc_wp_mux[] = {
1397     MMC_WP_MARK,
1398 };
1399 static const unsigned int mmc_ds_pins[] = {
1400     /* MMC_DS */
1401     RCAR_GP_PIN(3, 6),
1402 };
1403 static const unsigned int mmc_ds_mux[] = {
1404     MMC_DS_MARK,
1405 };
1406
1407 /* - MSIOF0 ----------------------------------------------------------------- */
1408 static const unsigned int msiof0_clk_pins[] = {
1409     /* MSIOF0_SCK */
1410     RCAR_GP_PIN(2, 21),
1411 };
1412 static const unsigned int msiof0_clk_mux[] = {
1413     MSIOF0_SCK_MARK,
1414 };
1415 static const unsigned int msiof0_sync_pins[] = {
1416     /* MSIOF0_SYNC */
1417     RCAR_GP_PIN(2, 22),
1418 };
1419 static const unsigned int msiof0_sync_mux[] = {
1420     MSIOF0_SYNC_MARK,
1421 };
1422 static const unsigned int msiof0_ss1_pins[] = {
1423     /* MSIOF0_SS1 */
1424     RCAR_GP_PIN(2, 23),
1425 };
1426 static const unsigned int msiof0_ss1_mux[] = {
1427     MSIOF0_SS1_MARK,
1428 };
1429 static const unsigned int msiof0_ss2_pins[] = {
1430     /* MSIOF0_SS2 */
1431     RCAR_GP_PIN(2, 24),
1432 };
1433 static const unsigned int msiof0_ss2_mux[] = {
1434     MSIOF0_SS2_MARK,
1435 };
1436 static const unsigned int msiof0_txd_pins[] = {
1437     /* MSIOF0_TXD */
1438     RCAR_GP_PIN(2, 20),
1439 };
1440 static const unsigned int msiof0_txd_mux[] = {
1441     MSIOF0_TXD_MARK,
1442 };
1443 static const unsigned int msiof0_rxd_pins[] = {
1444     /* MSIOF0_RXD */
1445     RCAR_GP_PIN(2, 19),
1446 };
1447 static const unsigned int msiof0_rxd_mux[] = {
1448     MSIOF0_RXD_MARK,
1449 };
1450
1451 /* - MSIOF1 ----------------------------------------------------------------- */
1452 static const unsigned int msiof1_clk_pins[] = {
1453     /* MSIOF1_SCK */
1454     RCAR_GP_PIN(3, 2),
1455 };
1456 static const unsigned int msiof1_clk_mux[] = {
1457     MSIOF1_SCK_MARK,
1458 };
1459 static const unsigned int msiof1_sync_pins[] = {
1460     /* MSIOF1_SYNC */
1461     RCAR_GP_PIN(3, 3),
1462 };
1463 static const unsigned int msiof1_sync_mux[] = {
1464     MSIOF1_SYNC_MARK,
1465 };
1466 static const unsigned int msiof1_ss1_pins[] = {
1467     /* MSIOF1_SS1 */
1468     RCAR_GP_PIN(3, 4),
1469 };
1470 static const unsigned int msiof1_ss1_mux[] = {
1471     MSIOF1_SS1_MARK,
1472 };
1473 static const unsigned int msiof1_ss2_pins[] = {
1474     /* MSIOF1_SS2 */
1475     RCAR_GP_PIN(3, 5),
1476 };
1477 static const unsigned int msiof1_ss2_mux[] = {
1478     MSIOF1_SS2_MARK,
1479 };
1480 static const unsigned int msiof1_txd_pins[] = {
1481     /* MSIOF1_TXD */
1482     RCAR_GP_PIN(3, 1),
1483 };
1484 static const unsigned int msiof1_txd_mux[] = {
1485     MSIOF1_TXD_MARK,
1486 };
1487 static const unsigned int msiof1_rxd_pins[] = {
1488     /* MSIOF1_RXD */
1489     RCAR_GP_PIN(3, 0),
1490 };
1491 static const unsigned int msiof1_rxd_mux[] = {
1492     MSIOF1_RXD_MARK,
1493 };
1494
1495 /* - MSIOF2 ----------------------------------------------------------------- */
1496 static const unsigned int msiof2_clk_pins[] = {
1497     /* MSIOF2_SCK */
1498     RCAR_GP_PIN(2, 0),
1499 };
1500 static const unsigned int msiof2_clk_mux[] = {
1501     MSIOF2_SCK_MARK,
1502 };
1503 static const unsigned int msiof2_sync_pins[] = {
1504     /* MSIOF2_SYNC */
1505     RCAR_GP_PIN(2, 3),
1506 };
1507 static const unsigned int msiof2_sync_mux[] = {
1508     MSIOF2_SYNC_MARK,
1509 };
1510 static const unsigned int msiof2_ss1_pins[] = {
1511     /* MSIOF2_SS1 */
1512     RCAR_GP_PIN(2, 4),
1513 };
1514 static const unsigned int msiof2_ss1_mux[] = {
1515     MSIOF2_SS1_MARK,
1516 };
1517 static const unsigned int msiof2_ss2_pins[] = {
1518     /* MSIOF2_SS2 */
1519     RCAR_GP_PIN(2, 5),
1520 };
1521 static const unsigned int msiof2_ss2_mux[] = {
1522     MSIOF2_SS2_MARK,
1523 };
1524 static const unsigned int msiof2_txd_pins[] = {
1525     /* MSIOF2_TXD */
1526     RCAR_GP_PIN(2, 2),
1527 };
1528 static const unsigned int msiof2_txd_mux[] = {
1529     MSIOF2_TXD_MARK,
1530 };
1531 static const unsigned int msiof2_rxd_pins[] = {
1532     /* MSIOF2_RXD */
1533     RCAR_GP_PIN(2, 1),
1534 };
1535 static const unsigned int msiof2_rxd_mux[] = {
1536     MSIOF2_RXD_MARK,
1537 };
1538
1539 /* - MSIOF3 ----------------------------------------------------------------- */
1540 static const unsigned int msiof3_clk_pins[] = {
1541     /* MSIOF3_SCK */
1542     RCAR_GP_PIN(0, 20),
1543 };
1544 static const unsigned int msiof3_clk_mux[] = {
1545     MSIOF3_SCK_MARK,
1546 };
1547 static const unsigned int msiof3_sync_pins[] = {
1548     /* MSIOF3_SYNC */
1549     RCAR_GP_PIN(0, 21),
1550 };
1551 static const unsigned int msiof3_sync_mux[] = {
1552     MSIOF3_SYNC_MARK,
1553 };
1554 static const unsigned int msiof3_ss1_pins[] = {
1555     /* MSIOF3_SS1 */
1556     RCAR_GP_PIN(0, 18),
1557 };
1558 static const unsigned int msiof3_ss1_mux[] = {
1559     MSIOF3_SS1_MARK,
1560 };
1561 static const unsigned int msiof3_ss2_pins[] = {
1562     /* MSIOF3_SS2 */
1563     RCAR_GP_PIN(0, 19),
1564 };
1565 static const unsigned int msiof3_ss2_mux[] = {
1566     MSIOF3_SS2_MARK,
1567 };
1568 static const unsigned int msiof3_txd_pins[] = {
1569     /* MSIOF3_TXD */
1570     RCAR_GP_PIN(0, 17),
1571 };
1572 static const unsigned int msiof3_txd_mux[] = {
1573     MSIOF3_TXD_MARK,
1574 };
1575 static const unsigned int msiof3_rxd_pins[] = {
1576     /* MSIOF3_RXD */
1577     RCAR_GP_PIN(0, 16),
1578 };
1579 static const unsigned int msiof3_rxd_mux[] = {
1580     MSIOF3_RXD_MARK,
1581 };
1582
1583 /* - PWM0 ------------------------------------------------------------------- */
1584 static const unsigned int pwm0_a_pins[] = {
1585     /* PWM0 */
1586     RCAR_GP_PIN(0, 15),
1587 };
1588 static const unsigned int pwm0_a_mux[] = {
1589     PWM0_A_MARK,
1590 };
1591 static const unsigned int pwm0_b_pins[] = {
1592     /* PWM0 */
1593     RCAR_GP_PIN(1, 21),
1594 };
1595 static const unsigned int pwm0_b_mux[] = {
1596     PWM0_B_MARK,
1597 };
1598
1599 /* - PWM1 ------------------------------------------------------------------- */
1600 static const unsigned int pwm1_a_pins[] = {
1601     /* PWM1 */
1602     RCAR_GP_PIN(2, 13),
1603 };
1604 static const unsigned int pwm1_a_mux[] = {
1605     PWM1_A_MARK,
1606 };
1607 static const unsigned int pwm1_b_pins[] = {
1608     /* PWM1 */
1609     RCAR_GP_PIN(1, 22),
1610 };
1611 static const unsigned int pwm1_b_mux[] = {
1612     PWM1_B_MARK,
1613 };
1614
1615 /* - PWM2 ------------------------------------------------------------------- */
1616 static const unsigned int pwm2_a_pins[] = {
1617     /* PWM2 */
1618     RCAR_GP_PIN(2, 14),
1619 };
1620 static const unsigned int pwm2_a_mux[] = {
1621     PWM2_A_MARK,
1622 };
1623 static const unsigned int pwm2_b_pins[] = {
1624     /* PWM2 */
1625     RCAR_GP_PIN(1, 23),
1626 };
1627 static const unsigned int pwm2_b_mux[] = {
1628     PWM2_B_MARK,
1629 };
1630
1631 /* - PWM3 ------------------------------------------------------------------- */
1632 static const unsigned int pwm3_a_pins[] = {
1633     /* PWM3 */
1634     RCAR_GP_PIN(2, 15),
1635 };
1636 static const unsigned int pwm3_a_mux[] = {
1637     PWM3_A_MARK,
1638 };
1639 static const unsigned int pwm3_b_pins[] = {
1640     /* PWM3 */
1641     RCAR_GP_PIN(1, 24),
1642 };
1643 static const unsigned int pwm3_b_mux[] = {
1644     PWM3_B_MARK,
1645 };
1646
1647 /* - PWM4 ------------------------------------------------------------------- */
1648 static const unsigned int pwm4_a_pins[] = {
1649     /* PWM4 */
1650     RCAR_GP_PIN(2, 16),
1651 };
1652 static const unsigned int pwm4_a_mux[] = {
1653     PWM4_A_MARK,
1654 };
1655 static const unsigned int pwm4_b_pins[] = {
1656     /* PWM4 */
1657     RCAR_GP_PIN(1, 25),
1658 };
1659 static const unsigned int pwm4_b_mux[] = {
1660     PWM4_B_MARK,
1661 };
1662
1663 /* - QSPI0 ------------------------------------------------------------------ */
1664 static const unsigned int qspi0_ctrl_pins[] = {
1665     /* SPCLK, SSL */
1666     RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
1667 };
1668 static const unsigned int qspi0_ctrl_mux[] = {
1669     QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
1670 };
1671
1672 /* - QSPI1 ------------------------------------------------------------------ */
1673 static const unsigned int qspi1_ctrl_pins[] = {
1674     /* SPCLK, SSL */
1675     RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
1676 };
1677 static const unsigned int qspi1_ctrl_mux[] = {
1678     QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
1679 };
1680
1681 /* - RPC -------------------------------------------------------------------- */
1682 static const unsigned int rpc_clk_pins[] = {
1683     /* Octal-SPI flash: C/SCLK */
1684     /* HyperFlash: CK, CK# */
1685     RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
1686 };
1687 static const unsigned int rpc_clk_mux[] = {
1688     QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
1689 };
1690 static const unsigned int rpc_ctrl_pins[] = {
1691     /* Octal-SPI flash: S#/CS, DQS */
1692     /* HyperFlash: CS#, RDS */
1693     RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1694 };
1695 static const unsigned int rpc_ctrl_mux[] = {
1696     QSPI0_SSL_MARK, QSPI1_SSL_MARK,
1697 };
1698 static const unsigned int rpc_data_pins[] = {
1699     /* DQ[0:7] */
1700     RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1701     RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
1702     RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
1703     RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
1704 };
1705 static const unsigned int rpc_data_mux[] = {
1706     QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
1707     QSPI0_IO2_MARK, QSPI0_IO3_MARK,
1708     QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
1709     QSPI1_IO2_MARK, QSPI1_IO3_MARK,
1710 };
1711 static const unsigned int rpc_reset_pins[] = {
1712     /* RPC_RESET# */
1713     RCAR_GP_PIN(5, 12),
1714 };
1715 static const unsigned int rpc_reset_mux[] = {
1716     RPC_RESET_N_MARK,
1717 };
1718 static const unsigned int rpc_int_pins[] = {
1719     /* RPC_INT# */
1720     RCAR_GP_PIN(5, 14),
1721 };
1722 static const unsigned int rpc_int_mux[] = {
1723     RPC_INT_N_MARK,
1724 };
1725 static const unsigned int rpc_wp_pins[] = {
1726     /* RPC_WP# */
1727     RCAR_GP_PIN(5, 13),
1728 };
1729 static const unsigned int rpc_wp_mux[] = {
1730     RPC_WP_N_MARK,
1731 };
1732
1733 /* - SCIF0 ------------------------------------------------------------------ */
1734 static const unsigned int scif0_data_pins[] = {
1735     /* RX0, TX0 */
1736     RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
1737 };
1738 static const unsigned int scif0_data_mux[] = {
1739     RX0_MARK, TX0_MARK,
1740 };
1741 static const unsigned int scif0_clk_pins[] = {
1742     /* SCK0 */
1743     RCAR_GP_PIN(4, 1),
1744 };
1745 static const unsigned int scif0_clk_mux[] = {
1746     SCK0_MARK,
1747 };
1748 static const unsigned int scif0_ctrl_pins[] = {
1749     /* RTS0#, CTS0# */
1750     RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
1751 };
1752 static const unsigned int scif0_ctrl_mux[] = {
1753     RTS0_N_MARK, CTS0_N_MARK,
1754 };
1755
1756 /* - SCIF1 ------------------------------------------------------------------ */
1757 static const unsigned int scif1_data_a_pins[] = {
1758     /* RX1, TX1 */
1759     RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1760 };
1761 static const unsigned int scif1_data_a_mux[] = {
1762     RX1_A_MARK, TX1_A_MARK,
1763 };
1764 static const unsigned int scif1_clk_pins[] = {
1765     /* SCK1 */
1766     RCAR_GP_PIN(2, 5),
1767 };
1768 static const unsigned int scif1_clk_mux[] = {
1769     SCK1_MARK,
1770 };
1771 static const unsigned int scif1_ctrl_pins[] = {
1772     /* RTS1#, CTS1# */
1773     RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
1774 };
1775 static const unsigned int scif1_ctrl_mux[] = {
1776     RTS1_N_MARK, CTS1_N_MARK,
1777 };
1778 static const unsigned int scif1_data_b_pins[] = {
1779     /* RX1, TX1 */
1780     RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1781 };
1782 static const unsigned int scif1_data_b_mux[] = {
1783     RX1_B_MARK, TX1_B_MARK,
1784 };
1785
1786 /* - SCIF3 ------------------------------------------------------------------ */
1787 static const unsigned int scif3_data_pins[] = {
1788     /* RX3, TX3 */
1789     RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
1790 };
1791 static const unsigned int scif3_data_mux[] = {
1792     RX3_MARK, TX3_MARK,
1793 };
1794 static const unsigned int scif3_clk_pins[] = {
1795     /* SCK3 */
1796     RCAR_GP_PIN(2, 0),
1797 };
1798 static const unsigned int scif3_clk_mux[] = {
1799     SCK3_MARK,
1800 };
1801 static const unsigned int scif3_ctrl_pins[] = {
1802     /* RTS3#, CTS3# */
1803     RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
1804 };
1805 static const unsigned int scif3_ctrl_mux[] = {
1806     RTS3_N_MARK, CTS3_N_MARK,
1807 };
1808
1809 /* - SCIF4 ------------------------------------------------------------------ */
1810 static const unsigned int scif4_data_pins[] = {
1811     /* RX4, TX4 */
1812     RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
1813 };
1814 static const unsigned int scif4_data_mux[] = {
1815     RX4_MARK, TX4_MARK,
1816 };
1817 static const unsigned int scif4_clk_pins[] = {
1818     /* SCK4 */
1819     RCAR_GP_PIN(0, 0),
1820 };
1821 static const unsigned int scif4_clk_mux[] = {
1822     SCK4_MARK,
1823 };
1824 static const unsigned int scif4_ctrl_pins[] = {
1825     /* RTS4#, CTS4# */
1826     RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
1827 };
1828 static const unsigned int scif4_ctrl_mux[] = {
1829     RTS4_N_MARK, CTS4_N_MARK,
1830 };
1831
1832 /* - SCIF Clock ------------------------------------------------------------- */
1833 static const unsigned int scif_clk_a_pins[] = {
1834     /* SCIF_CLK */
1835     RCAR_GP_PIN(0, 10),
1836 };
1837 static const unsigned int scif_clk_a_mux[] = {
1838     SCIF_CLK_A_MARK,
1839 };
1840 static const unsigned int scif_clk_b_pins[] = {
1841     /* SCIF_CLK */
1842     RCAR_GP_PIN(1, 25),
1843 };
1844 static const unsigned int scif_clk_b_mux[] = {
1845     SCIF_CLK_B_MARK,
1846 };
1847
1848 /* - TMU -------------------------------------------------------------------- */
1849 static const unsigned int tmu_tclk1_a_pins[] = {
1850     /* TCLK1 */
1851     RCAR_GP_PIN(3, 13),
1852 };
1853 static const unsigned int tmu_tclk1_a_mux[] = {
1854     TCLK1_A_MARK,
1855 };
1856 static const unsigned int tmu_tclk1_b_pins[] = {
1857     /* TCLK1 */
1858     RCAR_GP_PIN(1, 23),
1859 };
1860 static const unsigned int tmu_tclk1_b_mux[] = {
1861     TCLK1_B_MARK,
1862 };
1863 static const unsigned int tmu_tclk2_a_pins[] = {
1864     /* TCLK2 */
1865     RCAR_GP_PIN(3, 14),
1866 };
1867 static const unsigned int tmu_tclk2_a_mux[] = {
1868     TCLK2_A_MARK,
1869 };
1870 static const unsigned int tmu_tclk2_b_pins[] = {
1871     /* TCLK2 */
1872     RCAR_GP_PIN(1, 24),
1873 };
1874 static const unsigned int tmu_tclk2_b_mux[] = {
1875     TCLK2_B_MARK,
1876 };
1877
1878 /* - TPU ------------------------------------------------------------------- */
1879 static const unsigned int tpu_to0_pins[] = {
1880     /* TPU0TO0 */
1881     RCAR_GP_PIN(1, 19),
1882 };
1883 static const unsigned int tpu_to0_mux[] = {
1884     TPU0TO0_MARK,
1885 };
1886 static const unsigned int tpu_to1_pins[] = {
1887     /* TPU0TO1 */
1888     RCAR_GP_PIN(1, 20),
1889 };
1890 static const unsigned int tpu_to1_mux[] = {
1891     TPU0TO1_MARK,
1892 };
1893 static const unsigned int tpu_to2_pins[] = {
1894     /* TPU0TO2 */
1895     RCAR_GP_PIN(4, 2),
1896 };
1897 static const unsigned int tpu_to2_mux[] = {
1898     TPU0TO2_MARK,
1899 };
1900 static const unsigned int tpu_to3_pins[] = {
1901     /* TPU0TO3 */
1902     RCAR_GP_PIN(4, 3),
1903 };
1904 static const unsigned int tpu_to3_mux[] = {
1905     TPU0TO3_MARK,
1906 };
1907
1908 /* - VIN0 ------------------------------------------------------------------- */
1909 static const unsigned int vin0_data_pins[] = {
1910     RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1911     RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1912     RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1913     RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1914     RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1915     RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1916     RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1917     RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1918     RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
1919     RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1920     RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1921     RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
1922 };
1923 static const unsigned int vin0_data_mux[] = {
1924     VI0_DATA0_MARK, VI0_DATA1_MARK,
1925     VI0_DATA2_MARK, VI0_DATA3_MARK,
1926     VI0_DATA4_MARK, VI0_DATA5_MARK,
1927     VI0_DATA6_MARK, VI0_DATA7_MARK,
1928     VI0_DATA8_MARK, VI0_DATA9_MARK,
1929     VI0_DATA10_MARK, VI0_DATA11_MARK,
1930     VI0_DATA12_MARK, VI0_DATA13_MARK,
1931     VI0_DATA14_MARK, VI0_DATA15_MARK,
1932     VI0_DATA16_MARK, VI0_DATA17_MARK,
1933     VI0_DATA18_MARK, VI0_DATA19_MARK,
1934     VI0_DATA20_MARK, VI0_DATA21_MARK,
1935     VI0_DATA22_MARK, VI0_DATA23_MARK,
1936 };
1937 static const unsigned int vin0_data18_pins[] = {
1938     RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1939     RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1940     RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
1941     RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
1942     RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
1943     RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
1944     RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
1945     RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
1946     RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
1947 };
1948 static const unsigned int vin0_data18_mux[] = {
1949     VI0_DATA2_MARK, VI0_DATA3_MARK,
1950     VI0_DATA4_MARK, VI0_DATA5_MARK,
1951     VI0_DATA6_MARK, VI0_DATA7_MARK,
1952     VI0_DATA10_MARK, VI0_DATA11_MARK,
1953     VI0_DATA12_MARK, VI0_DATA13_MARK,
1954     VI0_DATA14_MARK, VI0_DATA15_MARK,
1955     VI0_DATA18_MARK, VI0_DATA19_MARK,
1956     VI0_DATA20_MARK, VI0_DATA21_MARK,
1957     VI0_DATA22_MARK, VI0_DATA23_MARK,
1958 };
1959 static const unsigned int vin0_sync_pins[] = {
1960     /* VI0_VSYNC#, VI0_HSYNC# */
1961     RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
1962 };
1963 static const unsigned int vin0_sync_mux[] = {
1964     VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK,
1965 };
1966 static const unsigned int vin0_field_pins[] = {
1967     /* VI0_FIELD */
1968     RCAR_GP_PIN(2, 16),
1969 };
1970 static const unsigned int vin0_field_mux[] = {
1971     VI0_FIELD_MARK,
1972 };
1973 static const unsigned int vin0_clkenb_pins[] = {
1974     /* VI0_CLKENB */
1975     RCAR_GP_PIN(2, 1),
1976 };
1977 static const unsigned int vin0_clkenb_mux[] = {
1978     VI0_CLKENB_MARK,
1979 };
1980 static const unsigned int vin0_clk_pins[] = {
1981     /* VI0_CLK */
1982     RCAR_GP_PIN(2, 0),
1983 };
1984 static const unsigned int vin0_clk_mux[] = {
1985     VI0_CLK_MARK,
1986 };
1987
1988 /* - VIN1 ------------------------------------------------------------------- */
1989 static const unsigned int vin1_data_pins[] = {
1990     RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
1991     RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1992     RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1993     RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
1994     RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1995     RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
1996 };
1997 static const unsigned int vin1_data_mux[] = {
1998     VI1_DATA0_MARK, VI1_DATA1_MARK,
1999     VI1_DATA2_MARK, VI1_DATA3_MARK,
2000     VI1_DATA4_MARK, VI1_DATA5_MARK,
2001     VI1_DATA6_MARK, VI1_DATA7_MARK,
2002     VI1_DATA8_MARK,  VI1_DATA9_MARK,
2003     VI1_DATA10_MARK, VI1_DATA11_MARK,
2004 };
2005 static const unsigned int vin1_sync_pins[] = {
2006     /* VI1_VSYNC#, VI1_HSYNC# */
2007      RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
2008 };
2009 static const unsigned int vin1_sync_mux[] = {
2010     VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK,
2011 };
2012 static const unsigned int vin1_field_pins[] = {
2013     /* VI1_FIELD */
2014     RCAR_GP_PIN(3, 16),
2015 };
2016 static const unsigned int vin1_field_mux[] = {
2017     VI1_FIELD_MARK,
2018 };
2019 static const unsigned int vin1_clkenb_pins[] = {
2020     /* VI1_CLKENB */
2021     RCAR_GP_PIN(3, 1),
2022 };
2023 static const unsigned int vin1_clkenb_mux[] = {
2024     VI1_CLKENB_MARK,
2025 };
2026 static const unsigned int vin1_clk_pins[] = {
2027     /* VI1_CLK */
2028     RCAR_GP_PIN(3, 0),
2029 };
2030 static const unsigned int vin1_clk_mux[] = {
2031     VI1_CLK_MARK,
2032 };
2033
2034 static const struct sh_pfc_pin_group pinmux_groups[] = {
2035     SH_PFC_PIN_GROUP(avb_link),
2036     SH_PFC_PIN_GROUP(avb_magic),
2037     SH_PFC_PIN_GROUP(avb_phy_int),
2038     SH_PFC_PIN_GROUP(avb_mdio),
2039     SH_PFC_PIN_GROUP(avb_rgmii),
2040     SH_PFC_PIN_GROUP(avb_txcrefclk),
2041     SH_PFC_PIN_GROUP(avb_avtp_pps),
2042     SH_PFC_PIN_GROUP(avb_avtp_capture),
2043     SH_PFC_PIN_GROUP(avb_avtp_match),
2044     SH_PFC_PIN_GROUP(canfd0_data_a),
2045     SH_PFC_PIN_GROUP(canfd0_data_b),
2046     SH_PFC_PIN_GROUP(canfd1_data),
2047     SH_PFC_PIN_GROUP(canfd_clk_a),
2048     SH_PFC_PIN_GROUP(canfd_clk_b),
2049     SH_PFC_PIN_GROUP(du_rgb666),
2050     SH_PFC_PIN_GROUP(du_rgb888),
2051     SH_PFC_PIN_GROUP(du_clk_out),
2052     SH_PFC_PIN_GROUP(du_sync),
2053     SH_PFC_PIN_GROUP(du_oddf),
2054     SH_PFC_PIN_GROUP(du_cde),
2055     SH_PFC_PIN_GROUP(du_disp),
2056     SH_PFC_PIN_GROUP(gether_link_a),
2057     SH_PFC_PIN_GROUP(gether_phy_int_a),
2058     SH_PFC_PIN_GROUP(gether_mdio_a),
2059     SH_PFC_PIN_GROUP(gether_link_b),
2060     SH_PFC_PIN_GROUP(gether_phy_int_b),
2061     SH_PFC_PIN_GROUP(gether_mdio_b),
2062     SH_PFC_PIN_GROUP(gether_magic),
2063     SH_PFC_PIN_GROUP(gether_rgmii),
2064     SH_PFC_PIN_GROUP(gether_txcrefclk),
2065     SH_PFC_PIN_GROUP(gether_txcrefclk_mega),
2066     SH_PFC_PIN_GROUP(gether_rmii),
2067     SH_PFC_PIN_GROUP(hscif0_data_a),
2068     SH_PFC_PIN_GROUP(hscif0_clk_a),
2069     SH_PFC_PIN_GROUP(hscif0_ctrl_a),
2070     SH_PFC_PIN_GROUP(hscif0_data_b),
2071     SH_PFC_PIN_GROUP(hscif0_clk_b),
2072     SH_PFC_PIN_GROUP(hscif0_ctrl_b),
2073     SH_PFC_PIN_GROUP(hscif1_data),
2074     SH_PFC_PIN_GROUP(hscif1_clk),
2075     SH_PFC_PIN_GROUP(hscif1_ctrl),
2076     SH_PFC_PIN_GROUP(hscif2_data),
2077     SH_PFC_PIN_GROUP(hscif2_clk),
2078     SH_PFC_PIN_GROUP(hscif2_ctrl),
2079     SH_PFC_PIN_GROUP(hscif3_data),
2080     SH_PFC_PIN_GROUP(hscif3_clk),
2081     SH_PFC_PIN_GROUP(hscif3_ctrl),
2082     SH_PFC_PIN_GROUP(i2c0),
2083     SH_PFC_PIN_GROUP(i2c1),
2084     SH_PFC_PIN_GROUP(i2c2),
2085     SH_PFC_PIN_GROUP(i2c3),
2086     SH_PFC_PIN_GROUP(i2c4),
2087     SH_PFC_PIN_GROUP(i2c5),
2088     SH_PFC_PIN_GROUP(intc_ex_irq0),
2089     SH_PFC_PIN_GROUP(intc_ex_irq1),
2090     SH_PFC_PIN_GROUP(intc_ex_irq2),
2091     SH_PFC_PIN_GROUP(intc_ex_irq3),
2092     SH_PFC_PIN_GROUP(intc_ex_irq4),
2093     SH_PFC_PIN_GROUP(intc_ex_irq5),
2094     BUS_DATA_PIN_GROUP(mmc_data, 1),
2095     BUS_DATA_PIN_GROUP(mmc_data, 4),
2096     BUS_DATA_PIN_GROUP(mmc_data, 8),
2097     SH_PFC_PIN_GROUP(mmc_ctrl),
2098     SH_PFC_PIN_GROUP(mmc_cd),
2099     SH_PFC_PIN_GROUP(mmc_wp),
2100     SH_PFC_PIN_GROUP(mmc_ds),
2101     SH_PFC_PIN_GROUP(msiof0_clk),
2102     SH_PFC_PIN_GROUP(msiof0_sync),
2103     SH_PFC_PIN_GROUP(msiof0_ss1),
2104     SH_PFC_PIN_GROUP(msiof0_ss2),
2105     SH_PFC_PIN_GROUP(msiof0_txd),
2106     SH_PFC_PIN_GROUP(msiof0_rxd),
2107     SH_PFC_PIN_GROUP(msiof1_clk),
2108     SH_PFC_PIN_GROUP(msiof1_sync),
2109     SH_PFC_PIN_GROUP(msiof1_ss1),
2110     SH_PFC_PIN_GROUP(msiof1_ss2),
2111     SH_PFC_PIN_GROUP(msiof1_txd),
2112     SH_PFC_PIN_GROUP(msiof1_rxd),
2113     SH_PFC_PIN_GROUP(msiof2_clk),
2114     SH_PFC_PIN_GROUP(msiof2_sync),
2115     SH_PFC_PIN_GROUP(msiof2_ss1),
2116     SH_PFC_PIN_GROUP(msiof2_ss2),
2117     SH_PFC_PIN_GROUP(msiof2_txd),
2118     SH_PFC_PIN_GROUP(msiof2_rxd),
2119     SH_PFC_PIN_GROUP(msiof3_clk),
2120     SH_PFC_PIN_GROUP(msiof3_sync),
2121     SH_PFC_PIN_GROUP(msiof3_ss1),
2122     SH_PFC_PIN_GROUP(msiof3_ss2),
2123     SH_PFC_PIN_GROUP(msiof3_txd),
2124     SH_PFC_PIN_GROUP(msiof3_rxd),
2125     SH_PFC_PIN_GROUP(pwm0_a),
2126     SH_PFC_PIN_GROUP(pwm0_b),
2127     SH_PFC_PIN_GROUP(pwm1_a),
2128     SH_PFC_PIN_GROUP(pwm1_b),
2129     SH_PFC_PIN_GROUP(pwm2_a),
2130     SH_PFC_PIN_GROUP(pwm2_b),
2131     SH_PFC_PIN_GROUP(pwm3_a),
2132     SH_PFC_PIN_GROUP(pwm3_b),
2133     SH_PFC_PIN_GROUP(pwm4_a),
2134     SH_PFC_PIN_GROUP(pwm4_b),
2135     SH_PFC_PIN_GROUP(qspi0_ctrl),
2136     SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2),
2137     SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4),
2138     SH_PFC_PIN_GROUP(qspi1_ctrl),
2139     SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2),
2140     SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4),
2141     BUS_DATA_PIN_GROUP(rpc_clk, 1),
2142     BUS_DATA_PIN_GROUP(rpc_clk, 2),
2143     SH_PFC_PIN_GROUP(rpc_ctrl),
2144     SH_PFC_PIN_GROUP(rpc_data),
2145     SH_PFC_PIN_GROUP(rpc_reset),
2146     SH_PFC_PIN_GROUP(rpc_int),
2147     SH_PFC_PIN_GROUP(rpc_wp),
2148     SH_PFC_PIN_GROUP(scif0_data),
2149     SH_PFC_PIN_GROUP(scif0_clk),
2150     SH_PFC_PIN_GROUP(scif0_ctrl),
2151     SH_PFC_PIN_GROUP(scif1_data_a),
2152     SH_PFC_PIN_GROUP(scif1_clk),
2153     SH_PFC_PIN_GROUP(scif1_ctrl),
2154     SH_PFC_PIN_GROUP(scif1_data_b),
2155     SH_PFC_PIN_GROUP(scif3_data),
2156     SH_PFC_PIN_GROUP(scif3_clk),
2157     SH_PFC_PIN_GROUP(scif3_ctrl),
2158     SH_PFC_PIN_GROUP(scif4_data),
2159     SH_PFC_PIN_GROUP(scif4_clk),
2160     SH_PFC_PIN_GROUP(scif4_ctrl),
2161     SH_PFC_PIN_GROUP(scif_clk_a),
2162     SH_PFC_PIN_GROUP(scif_clk_b),
2163     SH_PFC_PIN_GROUP(tmu_tclk1_a),
2164     SH_PFC_PIN_GROUP(tmu_tclk1_b),
2165     SH_PFC_PIN_GROUP(tmu_tclk2_a),
2166     SH_PFC_PIN_GROUP(tmu_tclk2_b),
2167     SH_PFC_PIN_GROUP(tpu_to0),
2168     SH_PFC_PIN_GROUP(tpu_to1),
2169     SH_PFC_PIN_GROUP(tpu_to2),
2170     SH_PFC_PIN_GROUP(tpu_to3),
2171     BUS_DATA_PIN_GROUP(vin0_data, 8),
2172     BUS_DATA_PIN_GROUP(vin0_data, 10),
2173     BUS_DATA_PIN_GROUP(vin0_data, 12),
2174     BUS_DATA_PIN_GROUP(vin0_data, 16),
2175     SH_PFC_PIN_GROUP(vin0_data18),
2176     BUS_DATA_PIN_GROUP(vin0_data, 20),
2177     BUS_DATA_PIN_GROUP(vin0_data, 24),
2178     SH_PFC_PIN_GROUP(vin0_sync),
2179     SH_PFC_PIN_GROUP(vin0_field),
2180     SH_PFC_PIN_GROUP(vin0_clkenb),
2181     SH_PFC_PIN_GROUP(vin0_clk),
2182     BUS_DATA_PIN_GROUP(vin1_data, 8),
2183     BUS_DATA_PIN_GROUP(vin1_data, 10),
2184     BUS_DATA_PIN_GROUP(vin1_data, 12),
2185     SH_PFC_PIN_GROUP(vin1_sync),
2186     SH_PFC_PIN_GROUP(vin1_field),
2187     SH_PFC_PIN_GROUP(vin1_clkenb),
2188     SH_PFC_PIN_GROUP(vin1_clk),
2189 };
2190
2191 static const char * const avb_groups[] = {
2192     "avb_link",
2193     "avb_magic",
2194     "avb_phy_int",
2195     "avb_mdio",
2196     "avb_rgmii",
2197     "avb_txcrefclk",
2198     "avb_avtp_pps",
2199     "avb_avtp_capture",
2200     "avb_avtp_match",
2201 };
2202
2203 static const char * const canfd0_groups[] = {
2204     "canfd0_data_a",
2205     "canfd0_data_b",
2206 };
2207
2208 static const char * const canfd1_groups[] = {
2209     "canfd1_data",
2210 };
2211
2212 static const char * const canfd_clk_groups[] = {
2213     "canfd_clk_a",
2214     "canfd_clk_b",
2215 };
2216
2217 static const char * const du_groups[] = {
2218     "du_rgb666",
2219     "du_rgb888",
2220     "du_clk_out",
2221     "du_sync",
2222     "du_oddf",
2223     "du_cde",
2224     "du_disp",
2225 };
2226
2227 static const char * const gether_groups[] = {
2228     "gether_link_a",
2229     "gether_phy_int_a",
2230     "gether_mdio_a",
2231     "gether_link_b",
2232     "gether_phy_int_b",
2233     "gether_mdio_b",
2234     "gether_magic",
2235     "gether_rgmii",
2236     "gether_txcrefclk",
2237     "gether_txcrefclk_mega",
2238     "gether_rmii",
2239 };
2240
2241 static const char * const hscif0_groups[] = {
2242     "hscif0_data_a",
2243     "hscif0_clk_a",
2244     "hscif0_ctrl_a",
2245     "hscif0_data_b",
2246     "hscif0_clk_b",
2247     "hscif0_ctrl_b",
2248 };
2249
2250 static const char * const hscif1_groups[] = {
2251     "hscif1_data",
2252     "hscif1_clk",
2253     "hscif1_ctrl",
2254 };
2255
2256 static const char * const hscif2_groups[] = {
2257     "hscif2_data",
2258     "hscif2_clk",
2259     "hscif2_ctrl",
2260 };
2261
2262 static const char * const hscif3_groups[] = {
2263     "hscif3_data",
2264     "hscif3_clk",
2265     "hscif3_ctrl",
2266 };
2267
2268 static const char * const i2c0_groups[] = {
2269     "i2c0",
2270 };
2271
2272 static const char * const i2c1_groups[] = {
2273     "i2c1",
2274 };
2275
2276 static const char * const i2c2_groups[] = {
2277     "i2c2",
2278 };
2279
2280 static const char * const i2c3_groups[] = {
2281     "i2c3",
2282 };
2283
2284 static const char * const i2c4_groups[] = {
2285     "i2c4",
2286 };
2287
2288 static const char * const i2c5_groups[] = {
2289     "i2c5",
2290 };
2291
2292 static const char * const intc_ex_groups[] = {
2293     "intc_ex_irq0",
2294     "intc_ex_irq1",
2295     "intc_ex_irq2",
2296     "intc_ex_irq3",
2297     "intc_ex_irq4",
2298     "intc_ex_irq5",
2299 };
2300
2301 static const char * const mmc_groups[] = {
2302     "mmc_data1",
2303     "mmc_data4",
2304     "mmc_data8",
2305     "mmc_ctrl",
2306     "mmc_cd",
2307     "mmc_wp",
2308     "mmc_ds",
2309 };
2310
2311 static const char * const msiof0_groups[] = {
2312     "msiof0_clk",
2313     "msiof0_sync",
2314     "msiof0_ss1",
2315     "msiof0_ss2",
2316     "msiof0_txd",
2317     "msiof0_rxd",
2318 };
2319
2320 static const char * const msiof1_groups[] = {
2321     "msiof1_clk",
2322     "msiof1_sync",
2323     "msiof1_ss1",
2324     "msiof1_ss2",
2325     "msiof1_txd",
2326     "msiof1_rxd",
2327 };
2328
2329 static const char * const msiof2_groups[] = {
2330     "msiof2_clk",
2331     "msiof2_sync",
2332     "msiof2_ss1",
2333     "msiof2_ss2",
2334     "msiof2_txd",
2335     "msiof2_rxd",
2336 };
2337
2338 static const char * const msiof3_groups[] = {
2339     "msiof3_clk",
2340     "msiof3_sync",
2341     "msiof3_ss1",
2342     "msiof3_ss2",
2343     "msiof3_txd",
2344     "msiof3_rxd",
2345 };
2346
2347 static const char * const pwm0_groups[] = {
2348     "pwm0_a",
2349     "pwm0_b",
2350 };
2351
2352 static const char * const pwm1_groups[] = {
2353     "pwm1_a",
2354     "pwm1_b",
2355 };
2356
2357 static const char * const pwm2_groups[] = {
2358     "pwm2_a",
2359     "pwm2_b",
2360 };
2361
2362 static const char * const pwm3_groups[] = {
2363     "pwm3_a",
2364     "pwm3_b",
2365 };
2366
2367 static const char * const pwm4_groups[] = {
2368     "pwm4_a",
2369     "pwm4_b",
2370 };
2371
2372 static const char * const qspi0_groups[] = {
2373     "qspi0_ctrl",
2374     "qspi0_data2",
2375     "qspi0_data4",
2376 };
2377
2378 static const char * const qspi1_groups[] = {
2379     "qspi1_ctrl",
2380     "qspi1_data2",
2381     "qspi1_data4",
2382 };
2383
2384 static const char * const rpc_groups[] = {
2385     "rpc_clk1",
2386     "rpc_clk2",
2387     "rpc_ctrl",
2388     "rpc_data",
2389     "rpc_reset",
2390     "rpc_int",
2391     "rpc_wp",
2392 };
2393
2394 static const char * const scif0_groups[] = {
2395     "scif0_data",
2396     "scif0_clk",
2397     "scif0_ctrl",
2398 };
2399
2400 static const char * const scif1_groups[] = {
2401     "scif1_data_a",
2402     "scif1_clk",
2403     "scif1_ctrl",
2404     "scif1_data_b",
2405 };
2406
2407 static const char * const scif3_groups[] = {
2408     "scif3_data",
2409     "scif3_clk",
2410     "scif3_ctrl",
2411 };
2412
2413 static const char * const scif4_groups[] = {
2414     "scif4_data",
2415     "scif4_clk",
2416     "scif4_ctrl",
2417 };
2418
2419 static const char * const scif_clk_groups[] = {
2420     "scif_clk_a",
2421     "scif_clk_b",
2422 };
2423
2424 static const char * const tmu_groups[] = {
2425     "tmu_tclk1_a",
2426     "tmu_tclk1_b",
2427     "tmu_tclk2_a",
2428     "tmu_tclk2_b",
2429 };
2430
2431 static const char * const tpu_groups[] = {
2432     "tpu_to0",
2433     "tpu_to1",
2434     "tpu_to2",
2435     "tpu_to3",
2436 };
2437
2438 static const char * const vin0_groups[] = {
2439     "vin0_data8",
2440     "vin0_data10",
2441     "vin0_data12",
2442     "vin0_data16",
2443     "vin0_data18",
2444     "vin0_data20",
2445     "vin0_data24",
2446     "vin0_sync",
2447     "vin0_field",
2448     "vin0_clkenb",
2449     "vin0_clk",
2450 };
2451
2452 static const char * const vin1_groups[] = {
2453     "vin1_data8",
2454     "vin1_data10",
2455     "vin1_data12",
2456     "vin1_sync",
2457     "vin1_field",
2458     "vin1_clkenb",
2459     "vin1_clk",
2460 };
2461
2462 static const struct sh_pfc_function pinmux_functions[] = {
2463     SH_PFC_FUNCTION(avb),
2464     SH_PFC_FUNCTION(canfd0),
2465     SH_PFC_FUNCTION(canfd1),
2466     SH_PFC_FUNCTION(canfd_clk),
2467     SH_PFC_FUNCTION(du),
2468     SH_PFC_FUNCTION(gether),
2469     SH_PFC_FUNCTION(hscif0),
2470     SH_PFC_FUNCTION(hscif1),
2471     SH_PFC_FUNCTION(hscif2),
2472     SH_PFC_FUNCTION(hscif3),
2473     SH_PFC_FUNCTION(i2c0),
2474     SH_PFC_FUNCTION(i2c1),
2475     SH_PFC_FUNCTION(i2c2),
2476     SH_PFC_FUNCTION(i2c3),
2477     SH_PFC_FUNCTION(i2c4),
2478     SH_PFC_FUNCTION(i2c5),
2479     SH_PFC_FUNCTION(intc_ex),
2480     SH_PFC_FUNCTION(mmc),
2481     SH_PFC_FUNCTION(msiof0),
2482     SH_PFC_FUNCTION(msiof1),
2483     SH_PFC_FUNCTION(msiof2),
2484     SH_PFC_FUNCTION(msiof3),
2485     SH_PFC_FUNCTION(pwm0),
2486     SH_PFC_FUNCTION(pwm1),
2487     SH_PFC_FUNCTION(pwm2),
2488     SH_PFC_FUNCTION(pwm3),
2489     SH_PFC_FUNCTION(pwm4),
2490     SH_PFC_FUNCTION(qspi0),
2491     SH_PFC_FUNCTION(qspi1),
2492     SH_PFC_FUNCTION(rpc),
2493     SH_PFC_FUNCTION(scif0),
2494     SH_PFC_FUNCTION(scif1),
2495     SH_PFC_FUNCTION(scif3),
2496     SH_PFC_FUNCTION(scif4),
2497     SH_PFC_FUNCTION(scif_clk),
2498     SH_PFC_FUNCTION(tmu),
2499     SH_PFC_FUNCTION(tpu),
2500     SH_PFC_FUNCTION(vin0),
2501     SH_PFC_FUNCTION(vin1),
2502 };
2503
2504 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2505 #define F_(x, y)    FN_##y
2506 #define FM(x)       FN_##x
2507     { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
2508                  GROUP(-10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2509                    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
2510                  GROUP(
2511         /* GP0_31_22 RESERVED */
2512         GP_0_21_FN, GPSR0_21,
2513         GP_0_20_FN, GPSR0_20,
2514         GP_0_19_FN, GPSR0_19,
2515         GP_0_18_FN, GPSR0_18,
2516         GP_0_17_FN, GPSR0_17,
2517         GP_0_16_FN, GPSR0_16,
2518         GP_0_15_FN, GPSR0_15,
2519         GP_0_14_FN, GPSR0_14,
2520         GP_0_13_FN, GPSR0_13,
2521         GP_0_12_FN, GPSR0_12,
2522         GP_0_11_FN, GPSR0_11,
2523         GP_0_10_FN, GPSR0_10,
2524         GP_0_9_FN,  GPSR0_9,
2525         GP_0_8_FN,  GPSR0_8,
2526         GP_0_7_FN,  GPSR0_7,
2527         GP_0_6_FN,  GPSR0_6,
2528         GP_0_5_FN,  GPSR0_5,
2529         GP_0_4_FN,  GPSR0_4,
2530         GP_0_3_FN,  GPSR0_3,
2531         GP_0_2_FN,  GPSR0_2,
2532         GP_0_1_FN,  GPSR0_1,
2533         GP_0_0_FN,  GPSR0_0, ))
2534     },
2535     { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
2536         0, 0,
2537         0, 0,
2538         0, 0,
2539         0, 0,
2540         GP_1_27_FN, GPSR1_27,
2541         GP_1_26_FN, GPSR1_26,
2542         GP_1_25_FN, GPSR1_25,
2543         GP_1_24_FN, GPSR1_24,
2544         GP_1_23_FN, GPSR1_23,
2545         GP_1_22_FN, GPSR1_22,
2546         GP_1_21_FN, GPSR1_21,
2547         GP_1_20_FN, GPSR1_20,
2548         GP_1_19_FN, GPSR1_19,
2549         GP_1_18_FN, GPSR1_18,
2550         GP_1_17_FN, GPSR1_17,
2551         GP_1_16_FN, GPSR1_16,
2552         GP_1_15_FN, GPSR1_15,
2553         GP_1_14_FN, GPSR1_14,
2554         GP_1_13_FN, GPSR1_13,
2555         GP_1_12_FN, GPSR1_12,
2556         GP_1_11_FN, GPSR1_11,
2557         GP_1_10_FN, GPSR1_10,
2558         GP_1_9_FN,  GPSR1_9,
2559         GP_1_8_FN,  GPSR1_8,
2560         GP_1_7_FN,  GPSR1_7,
2561         GP_1_6_FN,  GPSR1_6,
2562         GP_1_5_FN,  GPSR1_5,
2563         GP_1_4_FN,  GPSR1_4,
2564         GP_1_3_FN,  GPSR1_3,
2565         GP_1_2_FN,  GPSR1_2,
2566         GP_1_1_FN,  GPSR1_1,
2567         GP_1_0_FN,  GPSR1_0, ))
2568     },
2569     { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
2570         0, 0,
2571         0, 0,
2572         GP_2_29_FN, GPSR2_29,
2573         GP_2_28_FN, GPSR2_28,
2574         GP_2_27_FN, GPSR2_27,
2575         GP_2_26_FN, GPSR2_26,
2576         GP_2_25_FN, GPSR2_25,
2577         GP_2_24_FN, GPSR2_24,
2578         GP_2_23_FN, GPSR2_23,
2579         GP_2_22_FN, GPSR2_22,
2580         GP_2_21_FN, GPSR2_21,
2581         GP_2_20_FN, GPSR2_20,
2582         GP_2_19_FN, GPSR2_19,
2583         GP_2_18_FN, GPSR2_18,
2584         GP_2_17_FN, GPSR2_17,
2585         GP_2_16_FN, GPSR2_16,
2586         GP_2_15_FN, GPSR2_15,
2587         GP_2_14_FN, GPSR2_14,
2588         GP_2_13_FN, GPSR2_13,
2589         GP_2_12_FN, GPSR2_12,
2590         GP_2_11_FN, GPSR2_11,
2591         GP_2_10_FN, GPSR2_10,
2592         GP_2_9_FN,  GPSR2_9,
2593         GP_2_8_FN,  GPSR2_8,
2594         GP_2_7_FN,  GPSR2_7,
2595         GP_2_6_FN,  GPSR2_6,
2596         GP_2_5_FN,  GPSR2_5,
2597         GP_2_4_FN,  GPSR2_4,
2598         GP_2_3_FN,  GPSR2_3,
2599         GP_2_2_FN,  GPSR2_2,
2600         GP_2_1_FN,  GPSR2_1,
2601         GP_2_0_FN,  GPSR2_0, ))
2602     },
2603     { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
2604                  GROUP(-15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2605                    1, 1, 1, 1, 1, 1),
2606                  GROUP(
2607         /* GP3_31_17 RESERVED */
2608         GP_3_16_FN, GPSR3_16,
2609         GP_3_15_FN, GPSR3_15,
2610         GP_3_14_FN, GPSR3_14,
2611         GP_3_13_FN, GPSR3_13,
2612         GP_3_12_FN, GPSR3_12,
2613         GP_3_11_FN, GPSR3_11,
2614         GP_3_10_FN, GPSR3_10,
2615         GP_3_9_FN,  GPSR3_9,
2616         GP_3_8_FN,  GPSR3_8,
2617         GP_3_7_FN,  GPSR3_7,
2618         GP_3_6_FN,  GPSR3_6,
2619         GP_3_5_FN,  GPSR3_5,
2620         GP_3_4_FN,  GPSR3_4,
2621         GP_3_3_FN,  GPSR3_3,
2622         GP_3_2_FN,  GPSR3_2,
2623         GP_3_1_FN,  GPSR3_1,
2624         GP_3_0_FN,  GPSR3_0, ))
2625     },
2626     { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
2627                  GROUP(-7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2628                    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2629                    1, 1),
2630                  GROUP(
2631         /* GP4_31_25 RESERVED */
2632         GP_4_24_FN, GPSR4_24,
2633         GP_4_23_FN, GPSR4_23,
2634         GP_4_22_FN, GPSR4_22,
2635         GP_4_21_FN, GPSR4_21,
2636         GP_4_20_FN, GPSR4_20,
2637         GP_4_19_FN, GPSR4_19,
2638         GP_4_18_FN, GPSR4_18,
2639         GP_4_17_FN, GPSR4_17,
2640         GP_4_16_FN, GPSR4_16,
2641         GP_4_15_FN, GPSR4_15,
2642         GP_4_14_FN, GPSR4_14,
2643         GP_4_13_FN, GPSR4_13,
2644         GP_4_12_FN, GPSR4_12,
2645         GP_4_11_FN, GPSR4_11,
2646         GP_4_10_FN, GPSR4_10,
2647         GP_4_9_FN,  GPSR4_9,
2648         GP_4_8_FN,  GPSR4_8,
2649         GP_4_7_FN,  GPSR4_7,
2650         GP_4_6_FN,  GPSR4_6,
2651         GP_4_5_FN,  GPSR4_5,
2652         GP_4_4_FN,  GPSR4_4,
2653         GP_4_3_FN,  GPSR4_3,
2654         GP_4_2_FN,  GPSR4_2,
2655         GP_4_1_FN,  GPSR4_1,
2656         GP_4_0_FN,  GPSR4_0, ))
2657     },
2658     { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32,
2659                  GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
2660                    1, 1, 1, 1),
2661                  GROUP(
2662         /* GP5_31_15 RESERVED */
2663         GP_5_14_FN, GPSR5_14,
2664         GP_5_13_FN, GPSR5_13,
2665         GP_5_12_FN, GPSR5_12,
2666         GP_5_11_FN, GPSR5_11,
2667         GP_5_10_FN, GPSR5_10,
2668         GP_5_9_FN,  GPSR5_9,
2669         GP_5_8_FN,  GPSR5_8,
2670         GP_5_7_FN,  GPSR5_7,
2671         GP_5_6_FN,  GPSR5_6,
2672         GP_5_5_FN,  GPSR5_5,
2673         GP_5_4_FN,  GPSR5_4,
2674         GP_5_3_FN,  GPSR5_3,
2675         GP_5_2_FN,  GPSR5_2,
2676         GP_5_1_FN,  GPSR5_1,
2677         GP_5_0_FN,  GPSR5_0, ))
2678     },
2679 #undef F_
2680 #undef FM
2681
2682 #define F_(x, y)    x,
2683 #define FM(x)       FN_##x,
2684     { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
2685         IP0_31_28
2686         IP0_27_24
2687         IP0_23_20
2688         IP0_19_16
2689         IP0_15_12
2690         IP0_11_8
2691         IP0_7_4
2692         IP0_3_0 ))
2693     },
2694     { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
2695         IP1_31_28
2696         IP1_27_24
2697         IP1_23_20
2698         IP1_19_16
2699         IP1_15_12
2700         IP1_11_8
2701         IP1_7_4
2702         IP1_3_0 ))
2703     },
2704     { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
2705         IP2_31_28
2706         IP2_27_24
2707         IP2_23_20
2708         IP2_19_16
2709         IP2_15_12
2710         IP2_11_8
2711         IP2_7_4
2712         IP2_3_0 ))
2713     },
2714     { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
2715         IP3_31_28
2716         IP3_27_24
2717         IP3_23_20
2718         IP3_19_16
2719         IP3_15_12
2720         IP3_11_8
2721         IP3_7_4
2722         IP3_3_0 ))
2723     },
2724     { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
2725         IP4_31_28
2726         IP4_27_24
2727         IP4_23_20
2728         IP4_19_16
2729         IP4_15_12
2730         IP4_11_8
2731         IP4_7_4
2732         IP4_3_0 ))
2733     },
2734     { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
2735         IP5_31_28
2736         IP5_27_24
2737         IP5_23_20
2738         IP5_19_16
2739         IP5_15_12
2740         IP5_11_8
2741         IP5_7_4
2742         IP5_3_0 ))
2743     },
2744     { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
2745         IP6_31_28
2746         IP6_27_24
2747         IP6_23_20
2748         IP6_19_16
2749         IP6_15_12
2750         IP6_11_8
2751         IP6_7_4
2752         IP6_3_0 ))
2753     },
2754     { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
2755         IP7_31_28
2756         IP7_27_24
2757         IP7_23_20
2758         IP7_19_16
2759         IP7_15_12
2760         IP7_11_8
2761         IP7_7_4
2762         IP7_3_0 ))
2763     },
2764     { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
2765         IP8_31_28
2766         IP8_27_24
2767         IP8_23_20
2768         IP8_19_16
2769         IP8_15_12
2770         IP8_11_8
2771         IP8_7_4
2772         IP8_3_0 ))
2773     },
2774     { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
2775         IP9_31_28
2776         IP9_27_24
2777         IP9_23_20
2778         IP9_19_16
2779         IP9_15_12
2780         IP9_11_8
2781         IP9_7_4
2782         IP9_3_0 ))
2783     },
2784     { PINMUX_CFG_REG_VAR("IPSR10", 0xe6060228, 32,
2785                  GROUP(-12, 4, 4, 4, 4, 4),
2786                  GROUP(
2787         /* IP10_31_20 RESERVED */
2788         IP10_19_16
2789         IP10_15_12
2790         IP10_11_8
2791         IP10_7_4
2792         IP10_3_0 ))
2793     },
2794 #undef F_
2795 #undef FM
2796
2797 #define F_(x, y)    x,
2798 #define FM(x)       FN_##x,
2799     { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
2800                  GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, -1, 1, 1, 1),
2801                  GROUP(
2802         /* RESERVED 31-12 */
2803         MOD_SEL0_11
2804         MOD_SEL0_10
2805         MOD_SEL0_9
2806         MOD_SEL0_8
2807         MOD_SEL0_7
2808         MOD_SEL0_6
2809         MOD_SEL0_5
2810         MOD_SEL0_4
2811         /* RESERVED 3 */
2812         MOD_SEL0_2
2813         MOD_SEL0_1
2814         MOD_SEL0_0 ))
2815     },
2816     { },
2817 };
2818
2819 enum ioctrl_regs {
2820     POCCTRL0,
2821     POCCTRL1,
2822     POCCTRL2,
2823     POCCTRL3,
2824     TDSELCTRL,
2825 };
2826
2827 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
2828     [POCCTRL0] = { 0xe6060380, },
2829     [POCCTRL1] = { 0xe6060384, },
2830     [POCCTRL2] = { 0xe6060388, },
2831     [POCCTRL3] = { 0xe606038c, },
2832     [TDSELCTRL] = { 0xe60603c0, },
2833     { /* sentinel */ },
2834 };
2835
2836 static int r8a77980_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
2837 {
2838     int bit = pin & 0x1f;
2839
2840     *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
2841     if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
2842         return bit;
2843     else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
2844         return bit + 22;
2845
2846     *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
2847     if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
2848         return bit - 10;
2849     if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
2850         (pin >= RCAR_GP_PIN(3,  0) && pin <= RCAR_GP_PIN(3, 16)))
2851         return bit + 7;
2852
2853     *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
2854     if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
2855         return pin - 25;
2856
2857     return -EINVAL;
2858 }
2859
2860 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
2861     { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
2862         [ 0] = RCAR_GP_PIN(0, 0),   /* DU_DR2 */
2863         [ 1] = RCAR_GP_PIN(0, 1),   /* DU_DR3 */
2864         [ 2] = RCAR_GP_PIN(0, 2),   /* DU_DR4 */
2865         [ 3] = RCAR_GP_PIN(0, 3),   /* DU_DR5 */
2866         [ 4] = RCAR_GP_PIN(0, 4),   /* DU_DR6 */
2867         [ 5] = RCAR_GP_PIN(0, 5),   /* DU_DR7 */
2868         [ 6] = RCAR_GP_PIN(0, 6),   /* DU_DG2 */
2869         [ 7] = RCAR_GP_PIN(0, 7),   /* DU_DG3 */
2870         [ 8] = RCAR_GP_PIN(0, 8),   /* DU_DG4 */
2871         [ 9] = RCAR_GP_PIN(0, 9),   /* DU_DG5 */
2872         [10] = RCAR_GP_PIN(0, 10),  /* DU_DG6 */
2873         [11] = RCAR_GP_PIN(0, 11),  /* DU_DG7 */
2874         [12] = RCAR_GP_PIN(0, 12),  /* DU_DB2 */
2875         [13] = RCAR_GP_PIN(0, 13),  /* DU_DB3 */
2876         [14] = RCAR_GP_PIN(0, 14),  /* DU_DB4 */
2877         [15] = RCAR_GP_PIN(0, 15),  /* DU_DB5 */
2878         [16] = RCAR_GP_PIN(0, 16),  /* DU_DB6 */
2879         [17] = RCAR_GP_PIN(0, 17),  /* DU_DB7 */
2880         [18] = RCAR_GP_PIN(0, 18),  /* DU_DOTCLKOUT */
2881         [19] = RCAR_GP_PIN(0, 19),  /* DU_EXHSYNC/DU_HSYNC */
2882         [20] = RCAR_GP_PIN(0, 20),  /* DU_EXVSYNC/DU_VSYNC */
2883         [21] = RCAR_GP_PIN(0, 21),  /* DU_EXODDF/DU_ODDF/DISP/CDE */
2884         [22] = SH_PFC_PIN_NONE,
2885         [23] = SH_PFC_PIN_NONE,
2886         [24] = PIN_DU_DOTCLKIN,     /* DU_DOTCLKIN */
2887         [25] = SH_PFC_PIN_NONE,
2888         [26] = PIN_PRESETOUT_N,     /* PRESETOUT# */
2889         [27] = SH_PFC_PIN_NONE,
2890         [28] = SH_PFC_PIN_NONE,
2891         [29] = SH_PFC_PIN_NONE,
2892         [30] = PIN_EXTALR,      /* EXTALR */
2893         [31] = PIN_FSCLKST_N,       /* FSCLKST# */
2894     } },
2895     { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
2896         [ 0] = PIN_FSCLKST,     /* FSCLKST */
2897         [ 1] = SH_PFC_PIN_NONE,
2898         [ 2] = RCAR_GP_PIN(1, 0),   /* IRQ0 */
2899         [ 3] = PIN_DCUTRST_N,       /* DCUTRST# */
2900         [ 4] = PIN_DCUTCK_LPDCLK,   /* DCUTCK_LPDCLK */
2901         [ 5] = PIN_DCUTMS,      /* DCUTMS */
2902         [ 6] = PIN_DCUTDI_LPDI,     /* DCUTDI_LPDI */
2903         [ 7] = SH_PFC_PIN_NONE,
2904         [ 8] = RCAR_GP_PIN(2, 0),   /* VI0_CLK */
2905         [ 9] = RCAR_GP_PIN(2, 1),   /* VI0_CLKENB */
2906         [10] = RCAR_GP_PIN(2, 2),   /* VI0_HSYNC# */
2907         [11] = RCAR_GP_PIN(2, 3),   /* VI0_VSYNC# */
2908         [12] = RCAR_GP_PIN(2, 4),   /* VI0_DATA0 */
2909         [13] = RCAR_GP_PIN(2, 5),   /* VI0_DATA1 */
2910         [14] = RCAR_GP_PIN(2, 6),   /* VI0_DATA2 */
2911         [15] = RCAR_GP_PIN(2, 7),   /* VI0_DATA3 */
2912         [16] = RCAR_GP_PIN(2, 8),   /* VI0_DATA4 */
2913         [17] = RCAR_GP_PIN(2, 9),   /* VI0_DATA5 */
2914         [18] = RCAR_GP_PIN(2, 10),  /* VI0_DATA6 */
2915         [19] = RCAR_GP_PIN(2, 11),  /* VI0_DATA7 */
2916         [20] = RCAR_GP_PIN(2, 12),  /* VI0_DATA8 */
2917         [21] = RCAR_GP_PIN(2, 13),  /* VI0_DATA9 */
2918         [22] = RCAR_GP_PIN(2, 14),  /* VI0_DATA10 */
2919         [23] = RCAR_GP_PIN(2, 15),  /* VI0_DATA11 */
2920         [24] = RCAR_GP_PIN(2, 16),  /* VI0_FIELD */
2921         [25] = RCAR_GP_PIN(3, 0),   /* VI1_CLK */
2922         [26] = RCAR_GP_PIN(3, 1),   /* VI1_CLKENB */
2923         [27] = RCAR_GP_PIN(3, 2),   /* VI1_HSYNC# */
2924         [28] = RCAR_GP_PIN(3, 3),   /* VI1_VSYNC# */
2925         [29] = RCAR_GP_PIN(3, 4),   /* VI1_DATA0 */
2926         [30] = RCAR_GP_PIN(3, 5),   /* VI1_DATA1 */
2927         [31] = RCAR_GP_PIN(3, 6),   /* VI1_DATA2 */
2928     } },
2929     { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
2930         [ 0] = RCAR_GP_PIN(3, 7),   /* VI1_DATA3 */
2931         [ 1] = RCAR_GP_PIN(3, 8),   /* VI1_DATA4 */
2932         [ 2] = RCAR_GP_PIN(3, 9),   /* VI1_DATA5 */
2933         [ 3] = RCAR_GP_PIN(3, 10),  /* VI1_DATA6 */
2934         [ 4] = RCAR_GP_PIN(3, 11),  /* VI1_DATA7 */
2935         [ 5] = RCAR_GP_PIN(3, 12),  /* VI1_DATA8 */
2936         [ 6] = RCAR_GP_PIN(3, 13),  /* VI1_DATA9 */
2937         [ 7] = RCAR_GP_PIN(3, 14),  /* VI1_DATA10 */
2938         [ 8] = RCAR_GP_PIN(3, 15),  /* VI1_DATA11 */
2939         [ 9] = RCAR_GP_PIN(3, 16),  /* VI1_FIELD */
2940         [10] = RCAR_GP_PIN(4, 0),   /* SCL0 */
2941         [11] = RCAR_GP_PIN(4, 1),   /* SDA0 */
2942         [12] = RCAR_GP_PIN(4, 2),   /* SCL1 */
2943         [13] = RCAR_GP_PIN(4, 3),   /* SDA1 */
2944         [14] = RCAR_GP_PIN(4, 4),   /* SCL2 */
2945         [15] = RCAR_GP_PIN(4, 5),   /* SDA2 */
2946         [16] = RCAR_GP_PIN(1, 1),   /* AVB_RX_CTL */
2947         [17] = RCAR_GP_PIN(1, 2),   /* AVB_RXC */
2948         [18] = RCAR_GP_PIN(1, 3),   /* AVB_RD0 */
2949         [19] = RCAR_GP_PIN(1, 4),   /* AVB_RD1 */
2950         [20] = RCAR_GP_PIN(1, 5),   /* AVB_RD2 */
2951         [21] = RCAR_GP_PIN(1, 6),   /* AVB_RD3 */
2952         [22] = RCAR_GP_PIN(1, 7),   /* AVB_TX_CTL */
2953         [23] = RCAR_GP_PIN(1, 8),   /* AVB_TXC */
2954         [24] = RCAR_GP_PIN(1, 9),   /* AVB_TD0 */
2955         [25] = RCAR_GP_PIN(1, 10),  /* AVB_TD1 */
2956         [26] = RCAR_GP_PIN(1, 11),  /* AVB_TD2 */
2957         [27] = RCAR_GP_PIN(1, 12),  /* AVB_TD3 */
2958         [28] = RCAR_GP_PIN(1, 13),  /* AVB_TXCREFCLK */
2959         [29] = RCAR_GP_PIN(1, 14),  /* AVB_MDIO */
2960         [30] = RCAR_GP_PIN(1, 15),  /* AVB_MDC */
2961         [31] = RCAR_GP_PIN(1, 16),  /* AVB_MAGIC */
2962     } },
2963     { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
2964         [ 0] = RCAR_GP_PIN(1, 17),  /* AVB_PHY_INT */
2965         [ 1] = RCAR_GP_PIN(1, 18),  /* AVB_LINK */
2966         [ 2] = RCAR_GP_PIN(1, 19),  /* AVB_AVTP_MATCH */
2967         [ 3] = RCAR_GP_PIN(1, 20),  /* AVTP_CAPTURE */
2968         [ 4] = RCAR_GP_PIN(4, 6),   /* GETHER_RX_CTL */
2969         [ 5] = RCAR_GP_PIN(4, 7),   /* GETHER_RXC */
2970         [ 6] = RCAR_GP_PIN(4, 8),   /* GETHER_RD0 */
2971         [ 7] = RCAR_GP_PIN(4, 9),   /* GETHER_RD1 */
2972         [ 8] = RCAR_GP_PIN(4, 10),  /* GETHER_RD2 */
2973         [ 9] = RCAR_GP_PIN(4, 11),  /* GETHER_RD3 */
2974         [10] = RCAR_GP_PIN(4, 12),  /* GETHER_TX_CTL */
2975         [11] = RCAR_GP_PIN(4, 13),  /* GETHER_TXC */
2976         [12] = RCAR_GP_PIN(4, 14),  /* GETHER_TD0 */
2977         [13] = RCAR_GP_PIN(4, 15),  /* GETHER_TD1 */
2978         [14] = RCAR_GP_PIN(4, 16),  /* GETHER_TD2 */
2979         [15] = RCAR_GP_PIN(4, 17),  /* GETHER_TD3 */
2980         [16] = RCAR_GP_PIN(4, 18),  /* GETHER_TXCREFCLK */
2981         [17] = RCAR_GP_PIN(4, 19),  /* GETHER_TXCREFCLK_MEGA */
2982         [18] = RCAR_GP_PIN(4, 20),  /* GETHER_MDIO_A */
2983         [19] = RCAR_GP_PIN(4, 21),  /* GETHER_MDC_A */
2984         [20] = RCAR_GP_PIN(4, 22),  /* GETHER_MAGIC */
2985         [21] = RCAR_GP_PIN(4, 23),  /* GETHER_PHY_INT_A */
2986         [22] = RCAR_GP_PIN(4, 24),  /* GETHER_LINK_A */
2987         [23] = RCAR_GP_PIN(1, 21),  /* CANFD0_TX_A */
2988         [24] = RCAR_GP_PIN(1, 22),  /* CANFD0_RX_A */
2989         [25] = RCAR_GP_PIN(1, 23),  /* CANFD1_TX */
2990         [26] = RCAR_GP_PIN(1, 24),  /* CANFD1_RX */
2991         [27] = RCAR_GP_PIN(1, 25),  /* CAN_CLK_A */
2992         [28] = RCAR_GP_PIN(5, 0),   /* QSPI0_SPCLK */
2993         [29] = RCAR_GP_PIN(5, 1),   /* QSPI0_MOSI_IO0 */
2994         [30] = RCAR_GP_PIN(5, 2),   /* QSPI0_MISO_IO1 */
2995         [31] = RCAR_GP_PIN(5, 3),   /* QSPI0_IO2 */
2996     } },
2997     { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
2998         [ 0] = RCAR_GP_PIN(5, 4),   /* QSPI0_IO3 */
2999         [ 1] = RCAR_GP_PIN(5, 5),   /* QSPI0_SSL */
3000         [ 2] = RCAR_GP_PIN(5, 6),   /* QSPI1_SPCLK */
3001         [ 3] = RCAR_GP_PIN(5, 7),   /* QSPI1_MOSI_IO0 */
3002         [ 4] = RCAR_GP_PIN(5, 8),   /* QSPI1_MISO_IO1 */
3003         [ 5] = RCAR_GP_PIN(5, 9),   /* QSPI1_IO2 */
3004         [ 6] = RCAR_GP_PIN(5, 10),  /* QSPI1_IO3 */
3005         [ 7] = RCAR_GP_PIN(5, 11),  /* QSPI1_SSL */
3006         [ 8] = RCAR_GP_PIN(5, 12),  /* RPC_RESET# */
3007         [ 9] = RCAR_GP_PIN(5, 13),  /* RPC_WP# */
3008         [10] = RCAR_GP_PIN(5, 14),  /* RPC_INT# */
3009         [11] = RCAR_GP_PIN(1, 26),  /* DIGRF_CLKIN */
3010         [12] = RCAR_GP_PIN(1, 27),  /* DIGRF_CLKOUT */
3011         [13] = RCAR_GP_PIN(2, 17),  /* IRQ4 */
3012         [14] = RCAR_GP_PIN(2, 18),  /* IRQ5 */
3013         [15] = RCAR_GP_PIN(2, 25),  /* SCL3 */
3014         [16] = RCAR_GP_PIN(2, 26),  /* SDA3 */
3015         [17] = RCAR_GP_PIN(2, 19),  /* MSIOF0_RXD */
3016         [18] = RCAR_GP_PIN(2, 20),  /* MSIOF0_TXD */
3017         [19] = RCAR_GP_PIN(2, 21),  /* MSIOF0_SCK */
3018         [20] = RCAR_GP_PIN(2, 22),  /* MSIOF0_SYNC */
3019         [21] = RCAR_GP_PIN(2, 23),  /* MSIOF0_SS1 */
3020         [22] = RCAR_GP_PIN(2, 24),  /* MSIOF0_SS2 */
3021         [23] = RCAR_GP_PIN(2, 27),  /* FSO_CFE_0# */
3022         [24] = RCAR_GP_PIN(2, 28),  /* FSO_CFE_1# */
3023         [25] = RCAR_GP_PIN(2, 29),  /* FSO_TOE# */
3024         [26] = SH_PFC_PIN_NONE,
3025         [27] = SH_PFC_PIN_NONE,
3026         [28] = SH_PFC_PIN_NONE,
3027         [29] = SH_PFC_PIN_NONE,
3028         [30] = SH_PFC_PIN_NONE,
3029         [31] = SH_PFC_PIN_NONE,
3030     } },
3031     { /* sentinel */ }
3032 };
3033
3034 static const struct sh_pfc_soc_operations r8a77980_pfc_ops = {
3035     .pin_to_pocctrl = r8a77980_pin_to_pocctrl,
3036     .get_bias = rcar_pinmux_get_bias,
3037     .set_bias = rcar_pinmux_set_bias,
3038 };
3039
3040 const struct sh_pfc_soc_info r8a77980_pinmux_info = {
3041     .name = "r8a77980_pfc",
3042     .ops = &r8a77980_pfc_ops,
3043     .unlock_reg = 0xe6060000, /* PMMR */
3044
3045     .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3046
3047     .pins = pinmux_pins,
3048     .nr_pins = ARRAY_SIZE(pinmux_pins),
3049     .groups = pinmux_groups,
3050     .nr_groups = ARRAY_SIZE(pinmux_groups),
3051     .functions = pinmux_functions,
3052     .nr_functions = ARRAY_SIZE(pinmux_functions),
3053
3054     .cfg_regs = pinmux_config_regs,
3055     .bias_regs = pinmux_bias_regs,
3056     .ioctrl_regs = pinmux_ioctrl_regs,
3057
3058     .pinmux_data = pinmux_data,
3059     .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3060 };