pinctrl/renesas/pfc-r8a7796.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * R8A7796 (R-Car M3-W/W+) support - PFC hardware block.
0004  *
0005  * Copyright (C) 2016-2019 Renesas Electronics Corp.
0006  *
0007  * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
0008  *
0009  * R-Car Gen3 processor support - PFC hardware block.
0010  *
0011  * Copyright (C) 2015  Renesas Electronics Corporation
0012  */
0013
0014 #include <linux/errno.h>
0015 #include <linux/kernel.h>
0016
0017 #include "sh_pfc.h"
0018
0019 #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
0020
0021 #define CPU_ALL_GP(fn, sfx)                     \
0022     PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS),  \
0023     PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS),  \
0024     PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS),  \
0025     PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),  \
0026     PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS),   \
0027     PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS),   \
0028     PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS),   \
0029     PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS),   \
0030     PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),  \
0031     PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS),  \
0032     PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS),  \
0033     PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
0034
0035 #define CPU_ALL_NOGP(fn)                        \
0036     PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS),          \
0037     PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS),      \
0038     PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS),        \
0039     PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS),        \
0040     PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS),        \
0041     PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS),        \
0042     PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS),        \
0043     PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS),      \
0044     PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS),        \
0045     PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS),        \
0046     PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS),        \
0047     PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS),        \
0048     PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS),        \
0049     PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS),    \
0050     PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS),      \
0051     PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS),  \
0052     PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS),  \
0053     PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS),  \
0054     PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
0055     PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, CFG_FLAGS),        \
0056     PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS),        \
0057     PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS),     \
0058     PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS),        \
0059     PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS),        \
0060     PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS),  \
0061     PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS),  \
0062     PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS),    \
0063     PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS),        \
0064     PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS),        \
0065     PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS),        \
0066     PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS),  \
0067     PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS),  \
0068     PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS),    \
0069     PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS),        \
0070     PIN_NOGP_CFG(PRESET_N, "PRESET#", fn, SH_PFC_PIN_CFG_PULL_DOWN),\
0071     PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS),     \
0072     PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS),     \
0073     PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS),       \
0074     PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),  \
0075     PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),  \
0076     PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH),    \
0077     PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS),            \
0078     PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
0079
0080 /*
0081  * F_() : just information
0082  * FM() : macro for FN_xxx / xxx_MARK
0083  */
0084
0085 /* GPSR0 */
0086 #define GPSR0_15    F_(D15,         IP7_11_8)
0087 #define GPSR0_14    F_(D14,         IP7_7_4)
0088 #define GPSR0_13    F_(D13,         IP7_3_0)
0089 #define GPSR0_12    F_(D12,         IP6_31_28)
0090 #define GPSR0_11    F_(D11,         IP6_27_24)
0091 #define GPSR0_10    F_(D10,         IP6_23_20)
0092 #define GPSR0_9     F_(D9,          IP6_19_16)
0093 #define GPSR0_8     F_(D8,          IP6_15_12)
0094 #define GPSR0_7     F_(D7,          IP6_11_8)
0095 #define GPSR0_6     F_(D6,          IP6_7_4)
0096 #define GPSR0_5     F_(D5,          IP6_3_0)
0097 #define GPSR0_4     F_(D4,          IP5_31_28)
0098 #define GPSR0_3     F_(D3,          IP5_27_24)
0099 #define GPSR0_2     F_(D2,          IP5_23_20)
0100 #define GPSR0_1     F_(D1,          IP5_19_16)
0101 #define GPSR0_0     F_(D0,          IP5_15_12)
0102
0103 /* GPSR1 */
0104 #define GPSR1_28    FM(CLKOUT)
0105 #define GPSR1_27    F_(EX_WAIT0_A,      IP5_11_8)
0106 #define GPSR1_26    F_(WE1_N,       IP5_7_4)
0107 #define GPSR1_25    F_(WE0_N,       IP5_3_0)
0108 #define GPSR1_24    F_(RD_WR_N,     IP4_31_28)
0109 #define GPSR1_23    F_(RD_N,        IP4_27_24)
0110 #define GPSR1_22    F_(BS_N,        IP4_23_20)
0111 #define GPSR1_21    F_(CS1_N,       IP4_19_16)
0112 #define GPSR1_20    F_(CS0_N,       IP4_15_12)
0113 #define GPSR1_19    F_(A19,         IP4_11_8)
0114 #define GPSR1_18    F_(A18,         IP4_7_4)
0115 #define GPSR1_17    F_(A17,         IP4_3_0)
0116 #define GPSR1_16    F_(A16,         IP3_31_28)
0117 #define GPSR1_15    F_(A15,         IP3_27_24)
0118 #define GPSR1_14    F_(A14,         IP3_23_20)
0119 #define GPSR1_13    F_(A13,         IP3_19_16)
0120 #define GPSR1_12    F_(A12,         IP3_15_12)
0121 #define GPSR1_11    F_(A11,         IP3_11_8)
0122 #define GPSR1_10    F_(A10,         IP3_7_4)
0123 #define GPSR1_9     F_(A9,          IP3_3_0)
0124 #define GPSR1_8     F_(A8,          IP2_31_28)
0125 #define GPSR1_7     F_(A7,          IP2_27_24)
0126 #define GPSR1_6     F_(A6,          IP2_23_20)
0127 #define GPSR1_5     F_(A5,          IP2_19_16)
0128 #define GPSR1_4     F_(A4,          IP2_15_12)
0129 #define GPSR1_3     F_(A3,          IP2_11_8)
0130 #define GPSR1_2     F_(A2,          IP2_7_4)
0131 #define GPSR1_1     F_(A1,          IP2_3_0)
0132 #define GPSR1_0     F_(A0,          IP1_31_28)
0133
0134 /* GPSR2 */
0135 #define GPSR2_14    F_(AVB_AVTP_CAPTURE_A,  IP0_23_20)
0136 #define GPSR2_13    F_(AVB_AVTP_MATCH_A,    IP0_19_16)
0137 #define GPSR2_12    F_(AVB_LINK,        IP0_15_12)
0138 #define GPSR2_11    F_(AVB_PHY_INT,     IP0_11_8)
0139 #define GPSR2_10    F_(AVB_MAGIC,       IP0_7_4)
0140 #define GPSR2_9     F_(AVB_MDC,     IP0_3_0)
0141 #define GPSR2_8     F_(PWM2_A,      IP1_27_24)
0142 #define GPSR2_7     F_(PWM1_A,      IP1_23_20)
0143 #define GPSR2_6     F_(PWM0,        IP1_19_16)
0144 #define GPSR2_5     F_(IRQ5,        IP1_15_12)
0145 #define GPSR2_4     F_(IRQ4,        IP1_11_8)
0146 #define GPSR2_3     F_(IRQ3,        IP1_7_4)
0147 #define GPSR2_2     F_(IRQ2,        IP1_3_0)
0148 #define GPSR2_1     F_(IRQ1,        IP0_31_28)
0149 #define GPSR2_0     F_(IRQ0,        IP0_27_24)
0150
0151 /* GPSR3 */
0152 #define GPSR3_15    F_(SD1_WP,      IP11_23_20)
0153 #define GPSR3_14    F_(SD1_CD,      IP11_19_16)
0154 #define GPSR3_13    F_(SD0_WP,      IP11_15_12)
0155 #define GPSR3_12    F_(SD0_CD,      IP11_11_8)
0156 #define GPSR3_11    F_(SD1_DAT3,        IP8_31_28)
0157 #define GPSR3_10    F_(SD1_DAT2,        IP8_27_24)
0158 #define GPSR3_9     F_(SD1_DAT1,        IP8_23_20)
0159 #define GPSR3_8     F_(SD1_DAT0,        IP8_19_16)
0160 #define GPSR3_7     F_(SD1_CMD,     IP8_15_12)
0161 #define GPSR3_6     F_(SD1_CLK,     IP8_11_8)
0162 #define GPSR3_5     F_(SD0_DAT3,        IP8_7_4)
0163 #define GPSR3_4     F_(SD0_DAT2,        IP8_3_0)
0164 #define GPSR3_3     F_(SD0_DAT1,        IP7_31_28)
0165 #define GPSR3_2     F_(SD0_DAT0,        IP7_27_24)
0166 #define GPSR3_1     F_(SD0_CMD,     IP7_23_20)
0167 #define GPSR3_0     F_(SD0_CLK,     IP7_19_16)
0168
0169 /* GPSR4 */
0170 #define GPSR4_17    F_(SD3_DS,      IP11_7_4)
0171 #define GPSR4_16    F_(SD3_DAT7,        IP11_3_0)
0172 #define GPSR4_15    F_(SD3_DAT6,        IP10_31_28)
0173 #define GPSR4_14    F_(SD3_DAT5,        IP10_27_24)
0174 #define GPSR4_13    F_(SD3_DAT4,        IP10_23_20)
0175 #define GPSR4_12    F_(SD3_DAT3,        IP10_19_16)
0176 #define GPSR4_11    F_(SD3_DAT2,        IP10_15_12)
0177 #define GPSR4_10    F_(SD3_DAT1,        IP10_11_8)
0178 #define GPSR4_9     F_(SD3_DAT0,        IP10_7_4)
0179 #define GPSR4_8     F_(SD3_CMD,     IP10_3_0)
0180 #define GPSR4_7     F_(SD3_CLK,     IP9_31_28)
0181 #define GPSR4_6     F_(SD2_DS,      IP9_27_24)
0182 #define GPSR4_5     F_(SD2_DAT3,        IP9_23_20)
0183 #define GPSR4_4     F_(SD2_DAT2,        IP9_19_16)
0184 #define GPSR4_3     F_(SD2_DAT1,        IP9_15_12)
0185 #define GPSR4_2     F_(SD2_DAT0,        IP9_11_8)
0186 #define GPSR4_1     F_(SD2_CMD,     IP9_7_4)
0187 #define GPSR4_0     F_(SD2_CLK,     IP9_3_0)
0188
0189 /* GPSR5 */
0190 #define GPSR5_25    F_(MLB_DAT,     IP14_19_16)
0191 #define GPSR5_24    F_(MLB_SIG,     IP14_15_12)
0192 #define GPSR5_23    F_(MLB_CLK,     IP14_11_8)
0193 #define GPSR5_22    FM(MSIOF0_RXD)
0194 #define GPSR5_21    F_(MSIOF0_SS2,      IP14_7_4)
0195 #define GPSR5_20    FM(MSIOF0_TXD)
0196 #define GPSR5_19    F_(MSIOF0_SS1,      IP14_3_0)
0197 #define GPSR5_18    F_(MSIOF0_SYNC,     IP13_31_28)
0198 #define GPSR5_17    FM(MSIOF0_SCK)
0199 #define GPSR5_16    F_(HRTS0_N,     IP13_27_24)
0200 #define GPSR5_15    F_(HCTS0_N,     IP13_23_20)
0201 #define GPSR5_14    F_(HTX0,        IP13_19_16)
0202 #define GPSR5_13    F_(HRX0,        IP13_15_12)
0203 #define GPSR5_12    F_(HSCK0,       IP13_11_8)
0204 #define GPSR5_11    F_(RX2_A,       IP13_7_4)
0205 #define GPSR5_10    F_(TX2_A,       IP13_3_0)
0206 #define GPSR5_9     F_(SCK2,        IP12_31_28)
0207 #define GPSR5_8     F_(RTS1_N,      IP12_27_24)
0208 #define GPSR5_7     F_(CTS1_N,      IP12_23_20)
0209 #define GPSR5_6     F_(TX1_A,       IP12_19_16)
0210 #define GPSR5_5     F_(RX1_A,       IP12_15_12)
0211 #define GPSR5_4     F_(RTS0_N,      IP12_11_8)
0212 #define GPSR5_3     F_(CTS0_N,      IP12_7_4)
0213 #define GPSR5_2     F_(TX0,         IP12_3_0)
0214 #define GPSR5_1     F_(RX0,         IP11_31_28)
0215 #define GPSR5_0     F_(SCK0,        IP11_27_24)
0216
0217 /* GPSR6 */
0218 #define GPSR6_31    F_(GP6_31,      IP18_7_4)
0219 #define GPSR6_30    F_(GP6_30,      IP18_3_0)
0220 #define GPSR6_29    F_(USB30_OVC,       IP17_31_28)
0221 #define GPSR6_28    F_(USB30_PWEN,      IP17_27_24)
0222 #define GPSR6_27    F_(USB1_OVC,        IP17_23_20)
0223 #define GPSR6_26    F_(USB1_PWEN,       IP17_19_16)
0224 #define GPSR6_25    F_(USB0_OVC,        IP17_15_12)
0225 #define GPSR6_24    F_(USB0_PWEN,       IP17_11_8)
0226 #define GPSR6_23    F_(AUDIO_CLKB_B,    IP17_7_4)
0227 #define GPSR6_22    F_(AUDIO_CLKA_A,    IP17_3_0)
0228 #define GPSR6_21    F_(SSI_SDATA9_A,    IP16_31_28)
0229 #define GPSR6_20    F_(SSI_SDATA8,      IP16_27_24)
0230 #define GPSR6_19    F_(SSI_SDATA7,      IP16_23_20)
0231 #define GPSR6_18    F_(SSI_WS78,        IP16_19_16)
0232 #define GPSR6_17    F_(SSI_SCK78,       IP16_15_12)
0233 #define GPSR6_16    F_(SSI_SDATA6,      IP16_11_8)
0234 #define GPSR6_15    F_(SSI_WS6,     IP16_7_4)
0235 #define GPSR6_14    F_(SSI_SCK6,        IP16_3_0)
0236 #define GPSR6_13    FM(SSI_SDATA5)
0237 #define GPSR6_12    FM(SSI_WS5)
0238 #define GPSR6_11    FM(SSI_SCK5)
0239 #define GPSR6_10    F_(SSI_SDATA4,      IP15_31_28)
0240 #define GPSR6_9     F_(SSI_WS4,     IP15_27_24)
0241 #define GPSR6_8     F_(SSI_SCK4,        IP15_23_20)
0242 #define GPSR6_7     F_(SSI_SDATA3,      IP15_19_16)
0243 #define GPSR6_6     F_(SSI_WS349,       IP15_15_12)
0244 #define GPSR6_5     F_(SSI_SCK349,      IP15_11_8)
0245 #define GPSR6_4     F_(SSI_SDATA2_A,    IP15_7_4)
0246 #define GPSR6_3     F_(SSI_SDATA1_A,    IP15_3_0)
0247 #define GPSR6_2     F_(SSI_SDATA0,      IP14_31_28)
0248 #define GPSR6_1     F_(SSI_WS01239,     IP14_27_24)
0249 #define GPSR6_0     F_(SSI_SCK01239,    IP14_23_20)
0250
0251 /* GPSR7 */
0252 #define GPSR7_3     FM(GP7_03)
0253 #define GPSR7_2     FM(GP7_02)
0254 #define GPSR7_1     FM(AVS2)
0255 #define GPSR7_0     FM(AVS1)
0256
0257
0258 /* IPSRx */     /* 0 */         /* 1 */     /* 2 */         /* 3 */             /* 4 */     /* 5 */     /* 6 */         /* 7 */     /* 8 */         /* 9 */     /* A */     /* B */     /* C - F */
0259 #define IP0_3_0     FM(AVB_MDC)     F_(0, 0)    FM(MSIOF2_SS2_C)    F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0260 #define IP0_7_4     FM(AVB_MAGIC)       F_(0, 0)    FM(MSIOF2_SS1_C)    FM(SCK4_A)          F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0261 #define IP0_11_8    FM(AVB_PHY_INT)     F_(0, 0)    FM(MSIOF2_SYNC_C)   FM(RX4_A)           F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0262 #define IP0_15_12   FM(AVB_LINK)        F_(0, 0)    FM(MSIOF2_SCK_C)    FM(TX4_A)           F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0263 #define IP0_19_16   FM(AVB_AVTP_MATCH_A)    F_(0, 0)    FM(MSIOF2_RXD_C)    FM(CTS4_N_A)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0264 #define IP0_23_20   FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)    FM(MSIOF2_TXD_C)    FM(RTS4_N_A)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0265 #define IP0_27_24   FM(IRQ0)        FM(QPOLB)   F_(0, 0)        FM(DU_CDE)          FM(VI4_DATA0_B) FM(CAN0_TX_B)   FM(CANFD0_TX_B)     FM(MSIOF3_SS2_E) F_(0, 0)       F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0266 #define IP0_31_28   FM(IRQ1)        FM(QPOLA)   F_(0, 0)        FM(DU_DISP)         FM(VI4_DATA1_B) FM(CAN0_RX_B)   FM(CANFD0_RX_B)     FM(MSIOF3_SS1_E) F_(0, 0)       F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0267 #define IP1_3_0     FM(IRQ2)        FM(QCPV_QDE)    F_(0, 0)        FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)    F_(0, 0)        FM(MSIOF3_SYNC_E) F_(0, 0)      FM(PWM3_B)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0268 #define IP1_7_4     FM(IRQ3)        FM(QSTVB_QVE)   F_(0, 0)        FM(DU_DOTCLKOUT1)       FM(VI4_DATA3_B) F_(0, 0)    F_(0, 0)        FM(MSIOF3_SCK_E) F_(0, 0)       FM(PWM4_B)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0269 #define IP1_11_8    FM(IRQ4)        FM(QSTH_QHS)    F_(0, 0)        FM(DU_EXHSYNC_DU_HSYNC)     FM(VI4_DATA4_B) F_(0, 0)    F_(0, 0)        FM(MSIOF3_RXD_E) F_(0, 0)       FM(PWM5_B)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0270 #define IP1_15_12   FM(IRQ5)        FM(QSTB_QHE)    F_(0, 0)        FM(DU_EXVSYNC_DU_VSYNC)     FM(VI4_DATA5_B) F_(0, 0)    F_(0, 0)        FM(MSIOF3_TXD_E) F_(0, 0)       FM(PWM6_B)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0271 #define IP1_19_16   FM(PWM0)        FM(AVB_AVTP_PPS)F_(0, 0)        F_(0, 0)            FM(VI4_DATA6_B) F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        FM(IECLK_B) F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0272 #define IP1_23_20   FM(PWM1_A)      F_(0, 0)    F_(0, 0)        FM(HRX3_D)          FM(VI4_DATA7_B) F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        FM(IERX_B)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0273 #define IP1_27_24   FM(PWM2_A)      F_(0, 0)    F_(0, 0)        FM(HTX3_D)          F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        FM(IETX_B)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0274 #define IP1_31_28   FM(A0)          FM(LCDOUT16)    FM(MSIOF3_SYNC_B)   F_(0, 0)            FM(VI4_DATA8)   F_(0, 0)    FM(DU_DB0)      F_(0, 0)    F_(0, 0)        FM(PWM3_A)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0275 #define IP2_3_0     FM(A1)          FM(LCDOUT17)    FM(MSIOF3_TXD_B)    F_(0, 0)            FM(VI4_DATA9)   F_(0, 0)    FM(DU_DB1)      F_(0, 0)    F_(0, 0)        FM(PWM4_A)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0276 #define IP2_7_4     FM(A2)          FM(LCDOUT18)    FM(MSIOF3_SCK_B)    F_(0, 0)            FM(VI4_DATA10)  F_(0, 0)    FM(DU_DB2)      F_(0, 0)    F_(0, 0)        FM(PWM5_A)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0277 #define IP2_11_8    FM(A3)          FM(LCDOUT19)    FM(MSIOF3_RXD_B)    F_(0, 0)            FM(VI4_DATA11)  F_(0, 0)    FM(DU_DB3)      F_(0, 0)    F_(0, 0)        FM(PWM6_A)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0278 #define IP2_15_12   FM(A4)          FM(LCDOUT20)    FM(MSIOF3_SS1_B)    F_(0, 0)            FM(VI4_DATA12)  FM(VI5_DATA12)  FM(DU_DB4)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0279 #define IP2_19_16   FM(A5)          FM(LCDOUT21)    FM(MSIOF3_SS2_B)    FM(SCK4_B)          FM(VI4_DATA13)  FM(VI5_DATA13)  FM(DU_DB5)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0280 #define IP2_23_20   FM(A6)          FM(LCDOUT22)    FM(MSIOF2_SS1_A)    FM(RX4_B)           FM(VI4_DATA14)  FM(VI5_DATA14)  FM(DU_DB6)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0281 #define IP2_27_24   FM(A7)          FM(LCDOUT23)    FM(MSIOF2_SS2_A)    FM(TX4_B)           FM(VI4_DATA15)  FM(VI5_DATA15)  FM(DU_DB7)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0282 #define IP2_31_28   FM(A8)          FM(RX3_B)   FM(MSIOF2_SYNC_A)   FM(HRX4_B)          F_(0, 0)    F_(0, 0)    F_(0, 0)        FM(SDA6_A)  FM(AVB_AVTP_MATCH_B)    FM(PWM1_B)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0283 #define IP3_3_0     FM(A9)          F_(0, 0)    FM(MSIOF2_SCK_A)    FM(CTS4_N_B)            F_(0, 0)    FM(VI5_VSYNC_N) F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0284 #define IP3_7_4     FM(A10)         F_(0, 0)    FM(MSIOF2_RXD_A)    FM(RTS4_N_B)            F_(0, 0)    FM(VI5_HSYNC_N) F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0285 #define IP3_11_8    FM(A11)         FM(TX3_B)   FM(MSIOF2_TXD_A)    FM(HTX4_B)          FM(HSCK4)   FM(VI5_FIELD)   F_(0, 0)        FM(SCL6_A)  FM(AVB_AVTP_CAPTURE_B)  FM(PWM2_B)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0286
0287 /* IPSRx */     /* 0 */         /* 1 */     /* 2 */         /* 3 */             /* 4 */     /* 5 */     /* 6 */         /* 7 */     /* 8 */         /* 9 */     /* A */     /* B */     /* C - F */
0288 #define IP3_15_12   FM(A12)         FM(LCDOUT12)    FM(MSIOF3_SCK_C)    F_(0, 0)            FM(HRX4_A)  FM(VI5_DATA8)   FM(DU_DG4)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0289 #define IP3_19_16   FM(A13)         FM(LCDOUT13)    FM(MSIOF3_SYNC_C)   F_(0, 0)            FM(HTX4_A)  FM(VI5_DATA9)   FM(DU_DG5)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0290 #define IP3_23_20   FM(A14)         FM(LCDOUT14)    FM(MSIOF3_RXD_C)    F_(0, 0)            FM(HCTS4_N) FM(VI5_DATA10)  FM(DU_DG6)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0291 #define IP3_27_24   FM(A15)         FM(LCDOUT15)    FM(MSIOF3_TXD_C)    F_(0, 0)            FM(HRTS4_N) FM(VI5_DATA11)  FM(DU_DG7)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0292 #define IP3_31_28   FM(A16)         FM(LCDOUT8) F_(0, 0)        F_(0, 0)            FM(VI4_FIELD)   F_(0, 0)    FM(DU_DG0)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0293 #define IP4_3_0     FM(A17)         FM(LCDOUT9) F_(0, 0)        F_(0, 0)            FM(VI4_VSYNC_N) F_(0, 0)    FM(DU_DG1)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0294 #define IP4_7_4     FM(A18)         FM(LCDOUT10)    F_(0, 0)        F_(0, 0)            FM(VI4_HSYNC_N) F_(0, 0)    FM(DU_DG2)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0295 #define IP4_11_8    FM(A19)         FM(LCDOUT11)    F_(0, 0)        F_(0, 0)            FM(VI4_CLKENB)  F_(0, 0)    FM(DU_DG3)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0296 #define IP4_15_12   FM(CS0_N)       F_(0, 0)    F_(0, 0)        F_(0, 0)            F_(0, 0)    FM(VI5_CLKENB)  F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0297 #define IP4_19_16   FM(CS1_N)       F_(0, 0)    F_(0, 0)        F_(0, 0)            F_(0, 0)    FM(VI5_CLK) F_(0, 0)        FM(EX_WAIT0_B)  F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0298 #define IP4_23_20   FM(BS_N)        FM(QSTVA_QVS)   FM(MSIOF3_SCK_D)    FM(SCK3)            FM(HSCK3)   F_(0, 0)    F_(0, 0)        F_(0, 0)    FM(CAN1_TX)     FM(CANFD1_TX)   FM(IETX_A)  F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0299 #define IP4_27_24   FM(RD_N)        F_(0, 0)    FM(MSIOF3_SYNC_D)   FM(RX3_A)           FM(HRX3_A)  F_(0, 0)    F_(0, 0)        F_(0, 0)    FM(CAN0_TX_A)       FM(CANFD0_TX_A) F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0300 #define IP4_31_28   FM(RD_WR_N)     F_(0, 0)    FM(MSIOF3_RXD_D)    FM(TX3_A)           FM(HTX3_A)  F_(0, 0)    F_(0, 0)        F_(0, 0)    FM(CAN0_RX_A)       FM(CANFD0_RX_A) F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0301 #define IP5_3_0     FM(WE0_N)       F_(0, 0)    FM(MSIOF3_TXD_D)    FM(CTS3_N)          FM(HCTS3_N) F_(0, 0)    F_(0, 0)        FM(SCL6_B)  FM(CAN_CLK)     F_(0, 0)    FM(IECLK_A) F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0302 #define IP5_7_4     FM(WE1_N)       F_(0, 0)    FM(MSIOF3_SS1_D)    FM(RTS3_N)          FM(HRTS3_N) F_(0, 0)    F_(0, 0)        FM(SDA6_B)  FM(CAN1_RX)     FM(CANFD1_RX)   FM(IERX_A)  F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0303 #define IP5_11_8    FM(EX_WAIT0_A)      FM(QCLK)    F_(0, 0)        F_(0, 0)            FM(VI4_CLK) F_(0, 0)    FM(DU_DOTCLKOUT0)   F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0304 #define IP5_15_12   FM(D0)          FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A)    F_(0, 0)            FM(VI4_DATA16)  FM(VI5_DATA0)   F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0305 #define IP5_19_16   FM(D1)          FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A)   F_(0, 0)            FM(VI4_DATA17)  FM(VI5_DATA1)   F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0306 #define IP5_23_20   FM(D2)          F_(0, 0)    FM(MSIOF3_RXD_A)    F_(0, 0)            FM(VI4_DATA18)  FM(VI5_DATA2)   F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0307 #define IP5_27_24   FM(D3)          F_(0, 0)    FM(MSIOF3_TXD_A)    F_(0, 0)            FM(VI4_DATA19)  FM(VI5_DATA3)   F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0308 #define IP5_31_28   FM(D4)          FM(MSIOF2_SCK_B)F_(0, 0)        F_(0, 0)            FM(VI4_DATA20)  FM(VI5_DATA4)   F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0309 #define IP6_3_0     FM(D5)          FM(MSIOF2_SYNC_B)F_(0, 0)       F_(0, 0)            FM(VI4_DATA21)  FM(VI5_DATA5)   F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0310 #define IP6_7_4     FM(D6)          FM(MSIOF2_RXD_B)F_(0, 0)        F_(0, 0)            FM(VI4_DATA22)  FM(VI5_DATA6)   F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0311 #define IP6_11_8    FM(D7)          FM(MSIOF2_TXD_B)F_(0, 0)        F_(0, 0)            FM(VI4_DATA23)  FM(VI5_DATA7)   F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0312 #define IP6_15_12   FM(D8)          FM(LCDOUT0) FM(MSIOF2_SCK_D)    FM(SCK4_C)          FM(VI4_DATA0_A) F_(0, 0)    FM(DU_DR0)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0313 #define IP6_19_16   FM(D9)          FM(LCDOUT1) FM(MSIOF2_SYNC_D)   F_(0, 0)            FM(VI4_DATA1_A) F_(0, 0)    FM(DU_DR1)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0314 #define IP6_23_20   FM(D10)         FM(LCDOUT2) FM(MSIOF2_RXD_D)    FM(HRX3_B)          FM(VI4_DATA2_A) FM(CTS4_N_C)    FM(DU_DR2)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0315 #define IP6_27_24   FM(D11)         FM(LCDOUT3) FM(MSIOF2_TXD_D)    FM(HTX3_B)          FM(VI4_DATA3_A) FM(RTS4_N_C)    FM(DU_DR3)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0316 #define IP6_31_28   FM(D12)         FM(LCDOUT4) FM(MSIOF2_SS1_D)    FM(RX4_C)           FM(VI4_DATA4_A) F_(0, 0)    FM(DU_DR4)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0317
0318 /* IPSRx */     /* 0 */         /* 1 */     /* 2 */         /* 3 */             /* 4 */     /* 5 */     /* 6 */         /* 7 */     /* 8 */         /* 9 */     /* A */     /* B */     /* C - F */
0319 #define IP7_3_0     FM(D13)         FM(LCDOUT5) FM(MSIOF2_SS2_D)    FM(TX4_C)           FM(VI4_DATA5_A) F_(0, 0)    FM(DU_DR5)      F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0320 #define IP7_7_4     FM(D14)         FM(LCDOUT6) FM(MSIOF3_SS1_A)    FM(HRX3_C)          FM(VI4_DATA6_A) F_(0, 0)    FM(DU_DR6)      FM(SCL6_C)  F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0321 #define IP7_11_8    FM(D15)         FM(LCDOUT7) FM(MSIOF3_SS2_A)    FM(HTX3_C)          FM(VI4_DATA7_A) F_(0, 0)    FM(DU_DR7)      FM(SDA6_C)  F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0322 #define IP7_19_16   FM(SD0_CLK)     F_(0, 0)    FM(MSIOF1_SCK_E)    F_(0, 0)            F_(0, 0)    F_(0, 0)    FM(STP_OPWM_0_B)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0323 #define IP7_23_20   FM(SD0_CMD)     F_(0, 0)    FM(MSIOF1_SYNC_E)   F_(0, 0)            F_(0, 0)    F_(0, 0)    FM(STP_IVCXO27_0_B) F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0324 #define IP7_27_24   FM(SD0_DAT0)        F_(0, 0)    FM(MSIOF1_RXD_E)    F_(0, 0)            F_(0, 0)    FM(TS_SCK0_B)   FM(STP_ISCLK_0_B)   F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0325 #define IP7_31_28   FM(SD0_DAT1)        F_(0, 0)    FM(MSIOF1_TXD_E)    F_(0, 0)            F_(0, 0)    FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B)  F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0326 #define IP8_3_0     FM(SD0_DAT2)        F_(0, 0)    FM(MSIOF1_SS1_E)    F_(0, 0)            F_(0, 0)    FM(TS_SDAT0_B)  FM(STP_ISD_0_B)     F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0327 #define IP8_7_4     FM(SD0_DAT3)        F_(0, 0)    FM(MSIOF1_SS2_E)    F_(0, 0)            F_(0, 0)    FM(TS_SDEN0_B)  FM(STP_ISEN_0_B)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0328 #define IP8_11_8    FM(SD1_CLK)     F_(0, 0)    FM(MSIOF1_SCK_G)    F_(0, 0)            F_(0, 0)    FM(SIM0_CLK_A)  F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0329 #define IP8_15_12   FM(SD1_CMD)     F_(0, 0)    FM(MSIOF1_SYNC_G)   FM(NFCE_N_B)            F_(0, 0)    FM(SIM0_D_A)    FM(STP_IVCXO27_1_B) F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0330 #define IP8_19_16   FM(SD1_DAT0)        FM(SD2_DAT4)    FM(MSIOF1_RXD_G)    FM(NFWP_N_B)            F_(0, 0)    FM(TS_SCK1_B)   FM(STP_ISCLK_1_B)   F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0331 #define IP8_23_20   FM(SD1_DAT1)        FM(SD2_DAT5)    FM(MSIOF1_TXD_G)    FM(NFDATA14_B)          F_(0, 0)    FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)  F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0332 #define IP8_27_24   FM(SD1_DAT2)        FM(SD2_DAT6)    FM(MSIOF1_SS1_G)    FM(NFDATA15_B)          F_(0, 0)    FM(TS_SDAT1_B)  FM(STP_ISD_1_B)     F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0333 #define IP8_31_28   FM(SD1_DAT3)        FM(SD2_DAT7)    FM(MSIOF1_SS2_G)    FM(NFRB_N_B)            F_(0, 0)    FM(TS_SDEN1_B)  FM(STP_ISEN_1_B)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0334 #define IP9_3_0     FM(SD2_CLK)     F_(0, 0)    FM(NFDATA8)     F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0335 #define IP9_7_4     FM(SD2_CMD)     F_(0, 0)    FM(NFDATA9)     F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0336 #define IP9_11_8    FM(SD2_DAT0)        F_(0, 0)    FM(NFDATA10)        F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0337 #define IP9_15_12   FM(SD2_DAT1)        F_(0, 0)    FM(NFDATA11)        F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0338 #define IP9_19_16   FM(SD2_DAT2)        F_(0, 0)    FM(NFDATA12)        F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0339 #define IP9_23_20   FM(SD2_DAT3)        F_(0, 0)    FM(NFDATA13)        F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0340 #define IP9_27_24   FM(SD2_DS)      F_(0, 0)    FM(NFALE)       F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0341 #define IP9_31_28   FM(SD3_CLK)     F_(0, 0)    FM(NFWE_N)      F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0342 #define IP10_3_0    FM(SD3_CMD)     F_(0, 0)    FM(NFRE_N)      F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0343 #define IP10_7_4    FM(SD3_DAT0)        F_(0, 0)    FM(NFDATA0)     F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0344 #define IP10_11_8   FM(SD3_DAT1)        F_(0, 0)    FM(NFDATA1)     F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0345 #define IP10_15_12  FM(SD3_DAT2)        F_(0, 0)    FM(NFDATA2)     F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0346 #define IP10_19_16  FM(SD3_DAT3)        F_(0, 0)    FM(NFDATA3)     F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0347 #define IP10_23_20  FM(SD3_DAT4)        FM(SD2_CD_A)    FM(NFDATA4)     F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0348 #define IP10_27_24  FM(SD3_DAT5)        FM(SD2_WP_A)    FM(NFDATA5)     F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0349 #define IP10_31_28  FM(SD3_DAT6)        FM(SD3_CD)  FM(NFDATA6)     F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0350 #define IP11_3_0    FM(SD3_DAT7)        FM(SD3_WP)  FM(NFDATA7)     F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0351 #define IP11_7_4    FM(SD3_DS)      F_(0, 0)    FM(NFCLE)       F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0352 #define IP11_11_8   FM(SD0_CD)      F_(0, 0)    FM(NFDATA14_A)      F_(0, 0)            FM(SCL2_B)  FM(SIM0_RST_A)  F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0353
0354 /* IPSRx */     /* 0 */         /* 1 */     /* 2 */         /* 3 */             /* 4 */     /* 5 */     /* 6 */         /* 7 */     /* 8 */         /* 9 */     /* A */     /* B */     /* C - F */
0355 #define IP11_15_12  FM(SD0_WP)      F_(0, 0)    FM(NFDATA15_A)      F_(0, 0)            FM(SDA2_B)  F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0356 #define IP11_19_16  FM(SD1_CD)      F_(0, 0)    FM(NFRB_N_A)        F_(0, 0)            F_(0, 0)    FM(SIM0_CLK_B)  F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0357 #define IP11_23_20  FM(SD1_WP)      F_(0, 0)    FM(NFCE_N_A)        F_(0, 0)            F_(0, 0)    FM(SIM0_D_B)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0358 #define IP11_27_24  FM(SCK0)        FM(HSCK1_B) FM(MSIOF1_SS2_B)    FM(AUDIO_CLKC_B)        FM(SDA2_A)  FM(SIM0_RST_B)  FM(STP_OPWM_0_C)    FM(RIF0_CLK_B)  F_(0, 0)        FM(ADICHS2) FM(SCK5_B)  F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0359 #define IP11_31_28  FM(RX0)         FM(HRX1_B)  F_(0, 0)        F_(0, 0)            F_(0, 0)    FM(TS_SCK0_C)   FM(STP_ISCLK_0_C)   FM(RIF0_D0_B)   F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0360 #define IP12_3_0    FM(TX0)         FM(HTX1_B)  F_(0, 0)        F_(0, 0)            F_(0, 0)    FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)  FM(RIF0_D1_B)   F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0361 #define IP12_7_4    FM(CTS0_N)      FM(HCTS1_N_B)   FM(MSIOF1_SYNC_B)   F_(0, 0)            F_(0, 0)    FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)  FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C)  FM(ADICS_SAMP)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0362 #define IP12_11_8   FM(RTS0_N)      FM(HRTS1_N_B)   FM(MSIOF1_SS1_B)    FM(AUDIO_CLKA_B)        FM(SCL2_A)  F_(0, 0)    FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0)        FM(ADICHS1) F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0363 #define IP12_15_12  FM(RX1_A)       FM(HRX1_A)  F_(0, 0)        F_(0, 0)            F_(0, 0)    FM(TS_SDAT0_C)  FM(STP_ISD_0_C)     FM(RIF1_CLK_C)  F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0364 #define IP12_19_16  FM(TX1_A)       FM(HTX1_A)  F_(0, 0)        F_(0, 0)            F_(0, 0)    FM(TS_SDEN0_C)  FM(STP_ISEN_0_C)    FM(RIF1_D0_C)   F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0365 #define IP12_23_20  FM(CTS1_N)      FM(HCTS1_N_A)   FM(MSIOF1_RXD_B)    F_(0, 0)            F_(0, 0)    FM(TS_SDEN1_C)  FM(STP_ISEN_1_C)    FM(RIF1_D0_B)   F_(0, 0)        FM(ADIDATA) F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0366 #define IP12_27_24  FM(RTS1_N)      FM(HRTS1_N_A)   FM(MSIOF1_TXD_B)    F_(0, 0)            F_(0, 0)    FM(TS_SDAT1_C)  FM(STP_ISD_1_C)     FM(RIF1_D1_B)   F_(0, 0)        FM(ADICHS0) F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0367 #define IP12_31_28  FM(SCK2)        FM(SCIF_CLK_B)  FM(MSIOF1_SCK_B)    F_(0, 0)            F_(0, 0)    FM(TS_SCK1_C)   FM(STP_ISCLK_1_C)   FM(RIF1_CLK_B)  F_(0, 0)        FM(ADICLK)  F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0368 #define IP13_3_0    FM(TX2_A)       F_(0, 0)    F_(0, 0)        FM(SD2_CD_B)            FM(SCL1_A)  F_(0, 0)    FM(FMCLK_A)     FM(RIF1_D1_C)   F_(0, 0)        FM(FSO_CFE_0_N) F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0369 #define IP13_7_4    FM(RX2_A)       F_(0, 0)    F_(0, 0)        FM(SD2_WP_B)            FM(SDA1_A)  F_(0, 0)    FM(FMIN_A)      FM(RIF1_SYNC_C) F_(0, 0)        FM(FSO_CFE_1_N) F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0370 #define IP13_11_8   FM(HSCK0)       F_(0, 0)    FM(MSIOF1_SCK_D)    FM(AUDIO_CLKB_A)        FM(SSI_SDATA1_B)FM(TS_SCK0_D)   FM(STP_ISCLK_0_D)   FM(RIF0_CLK_C)  F_(0, 0)        F_(0, 0)    FM(RX5_B)   F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0371 #define IP13_15_12  FM(HRX0)        F_(0, 0)    FM(MSIOF1_RXD_D)    F_(0, 0)            FM(SSI_SDATA2_B)FM(TS_SDEN0_D)  FM(STP_ISEN_0_D)    FM(RIF0_D0_C)   F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0372 #define IP13_19_16  FM(HTX0)        F_(0, 0)    FM(MSIOF1_TXD_D)    F_(0, 0)            FM(SSI_SDATA9_B)FM(TS_SDAT0_D)  FM(STP_ISD_0_D)     FM(RIF0_D1_C)   F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0373 #define IP13_23_20  FM(HCTS0_N)     FM(RX2_B)   FM(MSIOF1_SYNC_D)   F_(0, 0)            FM(SSI_SCK9_A)  FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D)  FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0374 #define IP13_27_24  FM(HRTS0_N)     FM(TX2_B)   FM(MSIOF1_SS1_D)    F_(0, 0)            FM(SSI_WS9_A)   F_(0, 0)    FM(STP_IVCXO27_0_D) FM(BPFCLK_A)    FM(AUDIO_CLKOUT2_A) F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0375 #define IP13_31_28  FM(MSIOF0_SYNC)     F_(0, 0)    F_(0, 0)        F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    FM(AUDIO_CLKOUT_A)  F_(0, 0)    FM(TX5_B)   F_(0, 0)    F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
0376 #define IP14_3_0    FM(MSIOF0_SS1)      FM(RX5_A)   FM(NFWP_N_A)        FM(AUDIO_CLKA_C)        FM(SSI_SCK2_A)  F_(0, 0)    FM(STP_IVCXO27_0_C) F_(0, 0)    FM(AUDIO_CLKOUT3_A) F_(0, 0)    FM(TCLK1_B) F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0377 #define IP14_7_4    FM(MSIOF0_SS2)      FM(TX5_A)   FM(MSIOF1_SS2_D)    FM(AUDIO_CLKC_A)        FM(SSI_WS2_A)   F_(0, 0)    FM(STP_OPWM_0_D)    F_(0, 0)    FM(AUDIO_CLKOUT_D)  F_(0, 0)    FM(SPEEDIN_B)   F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0378 #define IP14_11_8   FM(MLB_CLK)     F_(0, 0)    FM(MSIOF1_SCK_F)    F_(0, 0)            FM(SCL1_B)  F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0379 #define IP14_15_12  FM(MLB_SIG)     FM(RX1_B)   FM(MSIOF1_SYNC_F)   F_(0, 0)            FM(SDA1_B)  F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0380 #define IP14_19_16  FM(MLB_DAT)     FM(TX1_B)   FM(MSIOF1_RXD_F)    F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0381 #define IP14_23_20  FM(SSI_SCK01239)    F_(0, 0)    FM(MSIOF1_TXD_F)    F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0382 #define IP14_27_24  FM(SSI_WS01239)     F_(0, 0)    FM(MSIOF1_SS1_F)    F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0383
0384 /* IPSRx */     /* 0 */         /* 1 */     /* 2 */         /* 3 */             /* 4 */     /* 5 */     /* 6 */         /* 7 */     /* 8 */         /* 9 */     /* A */     /* B */     /* C - F */
0385 #define IP14_31_28  FM(SSI_SDATA0)      F_(0, 0)    FM(MSIOF1_SS2_F)    F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0386 #define IP15_3_0    FM(SSI_SDATA1_A)    F_(0, 0)    F_(0, 0)        F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0387 #define IP15_7_4    FM(SSI_SDATA2_A)    F_(0, 0)    F_(0, 0)        F_(0, 0)            FM(SSI_SCK1_B)  F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0388 #define IP15_11_8   FM(SSI_SCK349)      F_(0, 0)    FM(MSIOF1_SS1_A)    F_(0, 0)            F_(0, 0)    F_(0, 0)    FM(STP_OPWM_0_A)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0389 #define IP15_15_12  FM(SSI_WS349)       FM(HCTS2_N_A)   FM(MSIOF1_SS2_A)    F_(0, 0)            F_(0, 0)    F_(0, 0)    FM(STP_IVCXO27_0_A) F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0390 #define IP15_19_16  FM(SSI_SDATA3)      FM(HRTS2_N_A)   FM(MSIOF1_TXD_A)    F_(0, 0)            F_(0, 0)    FM(TS_SCK0_A)   FM(STP_ISCLK_0_A)   FM(RIF0_D1_A)   FM(RIF2_D0_A)       F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0391 #define IP15_23_20  FM(SSI_SCK4)        FM(HRX2_A)  FM(MSIOF1_SCK_A)    F_(0, 0)            F_(0, 0)    FM(TS_SDAT0_A)  FM(STP_ISD_0_A)     FM(RIF0_CLK_A)  FM(RIF2_CLK_A)      F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0392 #define IP15_27_24  FM(SSI_WS4)     FM(HTX2_A)  FM(MSIOF1_SYNC_A)   F_(0, 0)            F_(0, 0)    FM(TS_SDEN0_A)  FM(STP_ISEN_0_A)    FM(RIF0_SYNC_A) FM(RIF2_SYNC_A)     F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0393 #define IP15_31_28  FM(SSI_SDATA4)      FM(HSCK2_A) FM(MSIOF1_RXD_A)    F_(0, 0)            F_(0, 0)    FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A)  FM(RIF0_D0_A)   FM(RIF2_D1_A)       F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0394 #define IP16_3_0    FM(SSI_SCK6)        F_(0, 0)    F_(0, 0)        FM(SIM0_RST_D)          F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0395 #define IP16_7_4    FM(SSI_WS6)     F_(0, 0)    F_(0, 0)        FM(SIM0_D_D)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0396 #define IP16_11_8   FM(SSI_SDATA6)      F_(0, 0)    F_(0, 0)        FM(SIM0_CLK_D)          F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0397 #define IP16_15_12  FM(SSI_SCK78)       FM(HRX2_B)  FM(MSIOF1_SCK_C)    F_(0, 0)            F_(0, 0)    FM(TS_SCK1_A)   FM(STP_ISCLK_1_A)   FM(RIF1_CLK_A)  FM(RIF3_CLK_A)      F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0398 #define IP16_19_16  FM(SSI_WS78)        FM(HTX2_B)  FM(MSIOF1_SYNC_C)   F_(0, 0)            F_(0, 0)    FM(TS_SDAT1_A)  FM(STP_ISD_1_A)     FM(RIF1_SYNC_A) FM(RIF3_SYNC_A)     F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0399 #define IP16_23_20  FM(SSI_SDATA7)      FM(HCTS2_N_B)   FM(MSIOF1_RXD_C)    F_(0, 0)            F_(0, 0)    FM(TS_SDEN1_A)  FM(STP_ISEN_1_A)    FM(RIF1_D0_A)   FM(RIF3_D0_A)       F_(0, 0)    FM(TCLK2_A) F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0400 #define IP16_27_24  FM(SSI_SDATA8)      FM(HRTS2_N_B)   FM(MSIOF1_TXD_C)    F_(0, 0)            F_(0, 0)    FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A)  FM(RIF1_D1_A)   FM(RIF3_D1_A)       F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0401 #define IP16_31_28  FM(SSI_SDATA9_A)    FM(HSCK2_B) FM(MSIOF1_SS1_C)    FM(HSCK1_A)         FM(SSI_WS1_B)   FM(SCK1)    FM(STP_IVCXO27_1_A) FM(SCK5_A)  F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0402 #define IP17_3_0    FM(AUDIO_CLKA_A)    F_(0, 0)    F_(0, 0)        F_(0, 0)            F_(0, 0)    F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)        F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0403 #define IP17_7_4    FM(AUDIO_CLKB_B)    FM(SCIF_CLK_A)  F_(0, 0)        F_(0, 0)            F_(0, 0)    F_(0, 0)    FM(STP_IVCXO27_1_D) FM(REMOCON_A)   F_(0, 0)        F_(0, 0)    FM(TCLK1_A) F_(0, 0)    F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0404 #define IP17_11_8   FM(USB0_PWEN)       F_(0, 0)    F_(0, 0)        FM(SIM0_RST_C)          F_(0, 0)    FM(TS_SCK1_D)   FM(STP_ISCLK_1_D)   FM(BPFCLK_B)    FM(RIF3_CLK_B)      F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
0405 #define IP17_15_12  FM(USB0_OVC)        F_(0, 0)    F_(0, 0)        FM(SIM0_D_C)            F_(0, 0)    FM(TS_SDAT1_D)  FM(STP_ISD_1_D)     F_(0, 0)    FM(RIF3_SYNC_B)     F_(0, 0)    F_(0, 0)    F_(0, 0)    F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
0406 #define IP17_19_16  FM(USB1_PWEN)       F_(0, 0)    F_(0, 0)        FM(SIM0_CLK_C)          FM(SSI_SCK1_A)  FM(TS_SCK0_E)   FM(STP_ISCLK_0_E)   FM(FMCLK_B) FM(RIF2_CLK_B)      F_(0, 0)    FM(SPEEDIN_A)   F_(0, 0)    F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
0407 #define IP17_23_20  FM(USB1_OVC)        F_(0, 0)    FM(MSIOF1_SS2_C)    F_(0, 0)            FM(SSI_WS1_A)   FM(TS_SDAT0_E)  FM(STP_ISD_0_E)     FM(FMIN_B)  FM(RIF2_SYNC_B)     F_(0, 0)    FM(REMOCON_B)   F_(0, 0)    F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
0408 #define IP17_27_24  FM(USB30_PWEN)      F_(0, 0)    F_(0, 0)        FM(AUDIO_CLKOUT_B)      FM(SSI_SCK2_B)  FM(TS_SDEN1_D)  FM(STP_ISEN_1_D)    FM(STP_OPWM_0_E)FM(RIF3_D0_B)       F_(0, 0)    FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
0409 #define IP17_31_28  FM(USB30_OVC)       F_(0, 0)    F_(0, 0)        FM(AUDIO_CLKOUT1_B)     FM(SSI_WS2_B)   FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)  FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)    F_(0, 0)    FM(FSO_TOE_N)   FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0410 #define IP18_3_0    FM(GP6_30)      F_(0, 0)    F_(0, 0)        FM(AUDIO_CLKOUT2_B)     FM(SSI_SCK9_B)  FM(TS_SDEN0_E)  FM(STP_ISEN_0_E)    F_(0, 0)    FM(RIF2_D0_B)       F_(0, 0)    F_(0, 0)    FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
0411 #define IP18_7_4    FM(GP6_31)      F_(0, 0)    F_(0, 0)        FM(AUDIO_CLKOUT3_B)     FM(SSI_WS9_B)   FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)  F_(0, 0)    FM(RIF2_D1_B)       F_(0, 0)    F_(0, 0)    FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
0412
0413 #define PINMUX_GPSR \
0414 \
0415                                                 GPSR6_31 \
0416                                                 GPSR6_30 \
0417                                                 GPSR6_29 \
0418         GPSR1_28                                    GPSR6_28 \
0419         GPSR1_27                                    GPSR6_27 \
0420         GPSR1_26                                    GPSR6_26 \
0421         GPSR1_25                            GPSR5_25    GPSR6_25 \
0422         GPSR1_24                            GPSR5_24    GPSR6_24 \
0423         GPSR1_23                            GPSR5_23    GPSR6_23 \
0424         GPSR1_22                            GPSR5_22    GPSR6_22 \
0425         GPSR1_21                            GPSR5_21    GPSR6_21 \
0426         GPSR1_20                            GPSR5_20    GPSR6_20 \
0427         GPSR1_19                            GPSR5_19    GPSR6_19 \
0428         GPSR1_18                            GPSR5_18    GPSR6_18 \
0429         GPSR1_17                    GPSR4_17    GPSR5_17    GPSR6_17 \
0430         GPSR1_16                    GPSR4_16    GPSR5_16    GPSR6_16 \
0431 GPSR0_15    GPSR1_15            GPSR3_15    GPSR4_15    GPSR5_15    GPSR6_15 \
0432 GPSR0_14    GPSR1_14    GPSR2_14    GPSR3_14    GPSR4_14    GPSR5_14    GPSR6_14 \
0433 GPSR0_13    GPSR1_13    GPSR2_13    GPSR3_13    GPSR4_13    GPSR5_13    GPSR6_13 \
0434 GPSR0_12    GPSR1_12    GPSR2_12    GPSR3_12    GPSR4_12    GPSR5_12    GPSR6_12 \
0435 GPSR0_11    GPSR1_11    GPSR2_11    GPSR3_11    GPSR4_11    GPSR5_11    GPSR6_11 \
0436 GPSR0_10    GPSR1_10    GPSR2_10    GPSR3_10    GPSR4_10    GPSR5_10    GPSR6_10 \
0437 GPSR0_9     GPSR1_9     GPSR2_9     GPSR3_9     GPSR4_9     GPSR5_9     GPSR6_9 \
0438 GPSR0_8     GPSR1_8     GPSR2_8     GPSR3_8     GPSR4_8     GPSR5_8     GPSR6_8 \
0439 GPSR0_7     GPSR1_7     GPSR2_7     GPSR3_7     GPSR4_7     GPSR5_7     GPSR6_7 \
0440 GPSR0_6     GPSR1_6     GPSR2_6     GPSR3_6     GPSR4_6     GPSR5_6     GPSR6_6 \
0441 GPSR0_5     GPSR1_5     GPSR2_5     GPSR3_5     GPSR4_5     GPSR5_5     GPSR6_5 \
0442 GPSR0_4     GPSR1_4     GPSR2_4     GPSR3_4     GPSR4_4     GPSR5_4     GPSR6_4 \
0443 GPSR0_3     GPSR1_3     GPSR2_3     GPSR3_3     GPSR4_3     GPSR5_3     GPSR6_3     GPSR7_3 \
0444 GPSR0_2     GPSR1_2     GPSR2_2     GPSR3_2     GPSR4_2     GPSR5_2     GPSR6_2     GPSR7_2 \
0445 GPSR0_1     GPSR1_1     GPSR2_1     GPSR3_1     GPSR4_1     GPSR5_1     GPSR6_1     GPSR7_1 \
0446 GPSR0_0     GPSR1_0     GPSR2_0     GPSR3_0     GPSR4_0     GPSR5_0     GPSR6_0     GPSR7_0
0447
0448 #define PINMUX_IPSR             \
0449 \
0450 FM(IP0_3_0) IP0_3_0     FM(IP1_3_0) IP1_3_0     FM(IP2_3_0) IP2_3_0     FM(IP3_3_0) IP3_3_0 \
0451 FM(IP0_7_4) IP0_7_4     FM(IP1_7_4) IP1_7_4     FM(IP2_7_4) IP2_7_4     FM(IP3_7_4) IP3_7_4 \
0452 FM(IP0_11_8)    IP0_11_8    FM(IP1_11_8)    IP1_11_8    FM(IP2_11_8)    IP2_11_8    FM(IP3_11_8)    IP3_11_8 \
0453 FM(IP0_15_12)   IP0_15_12   FM(IP1_15_12)   IP1_15_12   FM(IP2_15_12)   IP2_15_12   FM(IP3_15_12)   IP3_15_12 \
0454 FM(IP0_19_16)   IP0_19_16   FM(IP1_19_16)   IP1_19_16   FM(IP2_19_16)   IP2_19_16   FM(IP3_19_16)   IP3_19_16 \
0455 FM(IP0_23_20)   IP0_23_20   FM(IP1_23_20)   IP1_23_20   FM(IP2_23_20)   IP2_23_20   FM(IP3_23_20)   IP3_23_20 \
0456 FM(IP0_27_24)   IP0_27_24   FM(IP1_27_24)   IP1_27_24   FM(IP2_27_24)   IP2_27_24   FM(IP3_27_24)   IP3_27_24 \
0457 FM(IP0_31_28)   IP0_31_28   FM(IP1_31_28)   IP1_31_28   FM(IP2_31_28)   IP2_31_28   FM(IP3_31_28)   IP3_31_28 \
0458 \
0459 FM(IP4_3_0) IP4_3_0     FM(IP5_3_0) IP5_3_0     FM(IP6_3_0) IP6_3_0     FM(IP7_3_0) IP7_3_0 \
0460 FM(IP4_7_4) IP4_7_4     FM(IP5_7_4) IP5_7_4     FM(IP6_7_4) IP6_7_4     FM(IP7_7_4) IP7_7_4 \
0461 FM(IP4_11_8)    IP4_11_8    FM(IP5_11_8)    IP5_11_8    FM(IP6_11_8)    IP6_11_8    FM(IP7_11_8)    IP7_11_8 \
0462 FM(IP4_15_12)   IP4_15_12   FM(IP5_15_12)   IP5_15_12   FM(IP6_15_12)   IP6_15_12 \
0463 FM(IP4_19_16)   IP4_19_16   FM(IP5_19_16)   IP5_19_16   FM(IP6_19_16)   IP6_19_16   FM(IP7_19_16)   IP7_19_16 \
0464 FM(IP4_23_20)   IP4_23_20   FM(IP5_23_20)   IP5_23_20   FM(IP6_23_20)   IP6_23_20   FM(IP7_23_20)   IP7_23_20 \
0465 FM(IP4_27_24)   IP4_27_24   FM(IP5_27_24)   IP5_27_24   FM(IP6_27_24)   IP6_27_24   FM(IP7_27_24)   IP7_27_24 \
0466 FM(IP4_31_28)   IP4_31_28   FM(IP5_31_28)   IP5_31_28   FM(IP6_31_28)   IP6_31_28   FM(IP7_31_28)   IP7_31_28 \
0467 \
0468 FM(IP8_3_0) IP8_3_0     FM(IP9_3_0) IP9_3_0     FM(IP10_3_0)    IP10_3_0    FM(IP11_3_0)    IP11_3_0 \
0469 FM(IP8_7_4) IP8_7_4     FM(IP9_7_4) IP9_7_4     FM(IP10_7_4)    IP10_7_4    FM(IP11_7_4)    IP11_7_4 \
0470 FM(IP8_11_8)    IP8_11_8    FM(IP9_11_8)    IP9_11_8    FM(IP10_11_8)   IP10_11_8   FM(IP11_11_8)   IP11_11_8 \
0471 FM(IP8_15_12)   IP8_15_12   FM(IP9_15_12)   IP9_15_12   FM(IP10_15_12)  IP10_15_12  FM(IP11_15_12)  IP11_15_12 \
0472 FM(IP8_19_16)   IP8_19_16   FM(IP9_19_16)   IP9_19_16   FM(IP10_19_16)  IP10_19_16  FM(IP11_19_16)  IP11_19_16 \
0473 FM(IP8_23_20)   IP8_23_20   FM(IP9_23_20)   IP9_23_20   FM(IP10_23_20)  IP10_23_20  FM(IP11_23_20)  IP11_23_20 \
0474 FM(IP8_27_24)   IP8_27_24   FM(IP9_27_24)   IP9_27_24   FM(IP10_27_24)  IP10_27_24  FM(IP11_27_24)  IP11_27_24 \
0475 FM(IP8_31_28)   IP8_31_28   FM(IP9_31_28)   IP9_31_28   FM(IP10_31_28)  IP10_31_28  FM(IP11_31_28)  IP11_31_28 \
0476 \
0477 FM(IP12_3_0)    IP12_3_0    FM(IP13_3_0)    IP13_3_0    FM(IP14_3_0)    IP14_3_0    FM(IP15_3_0)    IP15_3_0 \
0478 FM(IP12_7_4)    IP12_7_4    FM(IP13_7_4)    IP13_7_4    FM(IP14_7_4)    IP14_7_4    FM(IP15_7_4)    IP15_7_4 \
0479 FM(IP12_11_8)   IP12_11_8   FM(IP13_11_8)   IP13_11_8   FM(IP14_11_8)   IP14_11_8   FM(IP15_11_8)   IP15_11_8 \
0480 FM(IP12_15_12)  IP12_15_12  FM(IP13_15_12)  IP13_15_12  FM(IP14_15_12)  IP14_15_12  FM(IP15_15_12)  IP15_15_12 \
0481 FM(IP12_19_16)  IP12_19_16  FM(IP13_19_16)  IP13_19_16  FM(IP14_19_16)  IP14_19_16  FM(IP15_19_16)  IP15_19_16 \
0482 FM(IP12_23_20)  IP12_23_20  FM(IP13_23_20)  IP13_23_20  FM(IP14_23_20)  IP14_23_20  FM(IP15_23_20)  IP15_23_20 \
0483 FM(IP12_27_24)  IP12_27_24  FM(IP13_27_24)  IP13_27_24  FM(IP14_27_24)  IP14_27_24  FM(IP15_27_24)  IP15_27_24 \
0484 FM(IP12_31_28)  IP12_31_28  FM(IP13_31_28)  IP13_31_28  FM(IP14_31_28)  IP14_31_28  FM(IP15_31_28)  IP15_31_28 \
0485 \
0486 FM(IP16_3_0)    IP16_3_0    FM(IP17_3_0)    IP17_3_0    FM(IP18_3_0)    IP18_3_0 \
0487 FM(IP16_7_4)    IP16_7_4    FM(IP17_7_4)    IP17_7_4    FM(IP18_7_4)    IP18_7_4 \
0488 FM(IP16_11_8)   IP16_11_8   FM(IP17_11_8)   IP17_11_8 \
0489 FM(IP16_15_12)  IP16_15_12  FM(IP17_15_12)  IP17_15_12 \
0490 FM(IP16_19_16)  IP16_19_16  FM(IP17_19_16)  IP17_19_16 \
0491 FM(IP16_23_20)  IP16_23_20  FM(IP17_23_20)  IP17_23_20 \
0492 FM(IP16_27_24)  IP16_27_24  FM(IP17_27_24)  IP17_27_24 \
0493 FM(IP16_31_28)  IP16_31_28  FM(IP17_31_28)  IP17_31_28
0494
0495 /* MOD_SEL0 */          /* 0 */         /* 1 */         /* 2 */         /* 3 */         /* 4 */         /* 5 */         /* 6 */         /* 7 */
0496 #define MOD_SEL0_31_30_29   FM(SEL_MSIOF3_0)    FM(SEL_MSIOF3_1)    FM(SEL_MSIOF3_2)    FM(SEL_MSIOF3_3)    FM(SEL_MSIOF3_4)    F_(0, 0)        F_(0, 0)        F_(0, 0)
0497 #define MOD_SEL0_28_27      FM(SEL_MSIOF2_0)    FM(SEL_MSIOF2_1)    FM(SEL_MSIOF2_2)    FM(SEL_MSIOF2_3)
0498 #define MOD_SEL0_26_25_24   FM(SEL_MSIOF1_0)    FM(SEL_MSIOF1_1)    FM(SEL_MSIOF1_2)    FM(SEL_MSIOF1_3)    FM(SEL_MSIOF1_4)    FM(SEL_MSIOF1_5)    FM(SEL_MSIOF1_6)    F_(0, 0)
0499 #define MOD_SEL0_23     FM(SEL_LBSC_0)      FM(SEL_LBSC_1)
0500 #define MOD_SEL0_22     FM(SEL_IEBUS_0)     FM(SEL_IEBUS_1)
0501 #define MOD_SEL0_21     FM(SEL_I2C2_0)      FM(SEL_I2C2_1)
0502 #define MOD_SEL0_20     FM(SEL_I2C1_0)      FM(SEL_I2C1_1)
0503 #define MOD_SEL0_19     FM(SEL_HSCIF4_0)    FM(SEL_HSCIF4_1)
0504 #define MOD_SEL0_18_17      FM(SEL_HSCIF3_0)    FM(SEL_HSCIF3_1)    FM(SEL_HSCIF3_2)    FM(SEL_HSCIF3_3)
0505 #define MOD_SEL0_16     FM(SEL_HSCIF1_0)    FM(SEL_HSCIF1_1)
0506 #define MOD_SEL0_14_13      FM(SEL_HSCIF2_0)    FM(SEL_HSCIF2_1)    FM(SEL_HSCIF2_2)    F_(0, 0)
0507 #define MOD_SEL0_12     FM(SEL_ETHERAVB_0)  FM(SEL_ETHERAVB_1)
0508 #define MOD_SEL0_11     FM(SEL_DRIF3_0)     FM(SEL_DRIF3_1)
0509 #define MOD_SEL0_10     FM(SEL_DRIF2_0)     FM(SEL_DRIF2_1)
0510 #define MOD_SEL0_9_8        FM(SEL_DRIF1_0)     FM(SEL_DRIF1_1)     FM(SEL_DRIF1_2)     F_(0, 0)
0511 #define MOD_SEL0_7_6        FM(SEL_DRIF0_0)     FM(SEL_DRIF0_1)     FM(SEL_DRIF0_2)     F_(0, 0)
0512 #define MOD_SEL0_5      FM(SEL_CANFD0_0)    FM(SEL_CANFD0_1)
0513 #define MOD_SEL0_4_3        FM(SEL_ADGA_0)      FM(SEL_ADGA_1)      FM(SEL_ADGA_2)      FM(SEL_ADGA_3)
0514
0515 /* MOD_SEL1 */          /* 0 */         /* 1 */         /* 2 */         /* 3 */         /* 4 */         /* 5 */         /* 6 */         /* 7 */
0516 #define MOD_SEL1_31_30      FM(SEL_TSIF1_0)     FM(SEL_TSIF1_1)     FM(SEL_TSIF1_2)     FM(SEL_TSIF1_3)
0517 #define MOD_SEL1_29_28_27   FM(SEL_TSIF0_0)     FM(SEL_TSIF0_1)     FM(SEL_TSIF0_2)     FM(SEL_TSIF0_3)     FM(SEL_TSIF0_4)     F_(0, 0)        F_(0, 0)        F_(0, 0)
0518 #define MOD_SEL1_26     FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
0519 #define MOD_SEL1_25_24      FM(SEL_SSP1_1_0)    FM(SEL_SSP1_1_1)    FM(SEL_SSP1_1_2)    FM(SEL_SSP1_1_3)
0520 #define MOD_SEL1_23_22_21   FM(SEL_SSP1_0_0)    FM(SEL_SSP1_0_1)    FM(SEL_SSP1_0_2)    FM(SEL_SSP1_0_3)    FM(SEL_SSP1_0_4)    F_(0, 0)        F_(0, 0)        F_(0, 0)
0521 #define MOD_SEL1_20     FM(SEL_SSI1_0)      FM(SEL_SSI1_1)
0522 #define MOD_SEL1_19     FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
0523 #define MOD_SEL1_18_17      FM(SEL_SIMCARD_0)   FM(SEL_SIMCARD_1)   FM(SEL_SIMCARD_2)   FM(SEL_SIMCARD_3)
0524 #define MOD_SEL1_16     FM(SEL_SDHI2_0)     FM(SEL_SDHI2_1)
0525 #define MOD_SEL1_15_14      FM(SEL_SCIF4_0)     FM(SEL_SCIF4_1)     FM(SEL_SCIF4_2)     F_(0, 0)
0526 #define MOD_SEL1_13     FM(SEL_SCIF3_0)     FM(SEL_SCIF3_1)
0527 #define MOD_SEL1_12     FM(SEL_SCIF2_0)     FM(SEL_SCIF2_1)
0528 #define MOD_SEL1_11     FM(SEL_SCIF1_0)     FM(SEL_SCIF1_1)
0529 #define MOD_SEL1_10     FM(SEL_SCIF_0)      FM(SEL_SCIF_1)
0530 #define MOD_SEL1_9      FM(SEL_REMOCON_0)   FM(SEL_REMOCON_1)
0531 #define MOD_SEL1_6      FM(SEL_RCAN0_0)     FM(SEL_RCAN0_1)
0532 #define MOD_SEL1_5      FM(SEL_PWM6_0)      FM(SEL_PWM6_1)
0533 #define MOD_SEL1_4      FM(SEL_PWM5_0)      FM(SEL_PWM5_1)
0534 #define MOD_SEL1_3      FM(SEL_PWM4_0)      FM(SEL_PWM4_1)
0535 #define MOD_SEL1_2      FM(SEL_PWM3_0)      FM(SEL_PWM3_1)
0536 #define MOD_SEL1_1      FM(SEL_PWM2_0)      FM(SEL_PWM2_1)
0537 #define MOD_SEL1_0      FM(SEL_PWM1_0)      FM(SEL_PWM1_1)
0538
0539 /* MOD_SEL2 */          /* 0 */         /* 1 */         /* 2 */         /* 3 */         /* 4 */         /* 5 */         /* 6 */         /* 7 */
0540 #define MOD_SEL2_31     FM(I2C_SEL_5_0)     FM(I2C_SEL_5_1)
0541 #define MOD_SEL2_30     FM(I2C_SEL_3_0)     FM(I2C_SEL_3_1)
0542 #define MOD_SEL2_29     FM(I2C_SEL_0_0)     FM(I2C_SEL_0_1)
0543 #define MOD_SEL2_28_27      FM(SEL_FM_0)        FM(SEL_FM_1)        FM(SEL_FM_2)        FM(SEL_FM_3)
0544 #define MOD_SEL2_26     FM(SEL_SCIF5_0)     FM(SEL_SCIF5_1)
0545 #define MOD_SEL2_25_24_23   FM(SEL_I2C6_0)      FM(SEL_I2C6_1)      FM(SEL_I2C6_2)      F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)        F_(0, 0)
0546 #define MOD_SEL2_22     FM(SEL_NDF_0)       FM(SEL_NDF_1)
0547 #define MOD_SEL2_21     FM(SEL_SSI2_0)      FM(SEL_SSI2_1)
0548 #define MOD_SEL2_20     FM(SEL_SSI9_0)      FM(SEL_SSI9_1)
0549 #define MOD_SEL2_19     FM(SEL_TIMER_TMU2_0)    FM(SEL_TIMER_TMU2_1)
0550 #define MOD_SEL2_18     FM(SEL_ADGB_0)      FM(SEL_ADGB_1)
0551 #define MOD_SEL2_17     FM(SEL_ADGC_0)      FM(SEL_ADGC_1)
0552 #define MOD_SEL2_0      FM(SEL_VIN4_0)      FM(SEL_VIN4_1)
0553
0554 #define PINMUX_MOD_SELS \
0555 \
0556 MOD_SEL0_31_30_29   MOD_SEL1_31_30      MOD_SEL2_31 \
0557                         MOD_SEL2_30 \
0558             MOD_SEL1_29_28_27   MOD_SEL2_29 \
0559 MOD_SEL0_28_27                  MOD_SEL2_28_27 \
0560 MOD_SEL0_26_25_24   MOD_SEL1_26     MOD_SEL2_26 \
0561             MOD_SEL1_25_24      MOD_SEL2_25_24_23 \
0562 MOD_SEL0_23     MOD_SEL1_23_22_21 \
0563 MOD_SEL0_22                 MOD_SEL2_22 \
0564 MOD_SEL0_21                 MOD_SEL2_21 \
0565 MOD_SEL0_20     MOD_SEL1_20     MOD_SEL2_20 \
0566 MOD_SEL0_19     MOD_SEL1_19     MOD_SEL2_19 \
0567 MOD_SEL0_18_17      MOD_SEL1_18_17      MOD_SEL2_18 \
0568                         MOD_SEL2_17 \
0569 MOD_SEL0_16     MOD_SEL1_16 \
0570             MOD_SEL1_15_14 \
0571 MOD_SEL0_14_13 \
0572             MOD_SEL1_13 \
0573 MOD_SEL0_12     MOD_SEL1_12 \
0574 MOD_SEL0_11     MOD_SEL1_11 \
0575 MOD_SEL0_10     MOD_SEL1_10 \
0576 MOD_SEL0_9_8        MOD_SEL1_9 \
0577 MOD_SEL0_7_6 \
0578             MOD_SEL1_6 \
0579 MOD_SEL0_5      MOD_SEL1_5 \
0580 MOD_SEL0_4_3        MOD_SEL1_4 \
0581             MOD_SEL1_3 \
0582             MOD_SEL1_2 \
0583             MOD_SEL1_1 \
0584             MOD_SEL1_0      MOD_SEL2_0
0585
0586 /*
0587  * These pins are not able to be muxed but have other properties
0588  * that can be set, such as drive-strength or pull-up/pull-down enable.
0589  */
0590 #define PINMUX_STATIC \
0591     FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
0592     FM(QSPI0_IO2) FM(QSPI0_IO3) \
0593     FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
0594     FM(QSPI1_IO2) FM(QSPI1_IO3) \
0595     FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
0596     FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
0597     FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
0598     FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
0599     FM(PRESETOUT) \
0600     FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
0601     FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
0602
0603 #define PINMUX_PHYS \
0604     FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
0605
0606 enum {
0607     PINMUX_RESERVED = 0,
0608
0609     PINMUX_DATA_BEGIN,
0610     GP_ALL(DATA),
0611     PINMUX_DATA_END,
0612
0613 #define F_(x, y)
0614 #define FM(x)   FN_##x,
0615     PINMUX_FUNCTION_BEGIN,
0616     GP_ALL(FN),
0617     PINMUX_GPSR
0618     PINMUX_IPSR
0619     PINMUX_MOD_SELS
0620     PINMUX_FUNCTION_END,
0621 #undef F_
0622 #undef FM
0623
0624 #define F_(x, y)
0625 #define FM(x)   x##_MARK,
0626     PINMUX_MARK_BEGIN,
0627     PINMUX_GPSR
0628     PINMUX_IPSR
0629     PINMUX_MOD_SELS
0630     PINMUX_STATIC
0631     PINMUX_PHYS
0632     PINMUX_MARK_END,
0633 #undef F_
0634 #undef FM
0635 };
0636
0637 static const u16 pinmux_data[] = {
0638     PINMUX_DATA_GP_ALL(),
0639
0640     PINMUX_SINGLE(AVS1),
0641     PINMUX_SINGLE(AVS2),
0642     PINMUX_SINGLE(CLKOUT),
0643     PINMUX_SINGLE(GP7_03),
0644     PINMUX_SINGLE(GP7_02),
0645     PINMUX_SINGLE(MSIOF0_RXD),
0646     PINMUX_SINGLE(MSIOF0_SCK),
0647     PINMUX_SINGLE(MSIOF0_TXD),
0648     PINMUX_SINGLE(SSI_SCK5),
0649     PINMUX_SINGLE(SSI_SDATA5),
0650     PINMUX_SINGLE(SSI_WS5),
0651
0652     /* IPSR0 */
0653     PINMUX_IPSR_GPSR(IP0_3_0,   AVB_MDC),
0654     PINMUX_IPSR_MSEL(IP0_3_0,   MSIOF2_SS2_C,       SEL_MSIOF2_2),
0655
0656     PINMUX_IPSR_GPSR(IP0_7_4,   AVB_MAGIC),
0657     PINMUX_IPSR_MSEL(IP0_7_4,   MSIOF2_SS1_C,       SEL_MSIOF2_2),
0658     PINMUX_IPSR_MSEL(IP0_7_4,   SCK4_A,         SEL_SCIF4_0),
0659
0660     PINMUX_IPSR_GPSR(IP0_11_8,  AVB_PHY_INT),
0661     PINMUX_IPSR_MSEL(IP0_11_8,  MSIOF2_SYNC_C,      SEL_MSIOF2_2),
0662     PINMUX_IPSR_MSEL(IP0_11_8,  RX4_A,          SEL_SCIF4_0),
0663
0664     PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
0665     PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C,       SEL_MSIOF2_2),
0666     PINMUX_IPSR_MSEL(IP0_15_12, TX4_A,          SEL_SCIF4_0),
0667
0668     PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A,  I2C_SEL_5_0,    SEL_ETHERAVB_0),
0669     PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C,      I2C_SEL_5_0,    SEL_MSIOF2_2),
0670     PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A,      I2C_SEL_5_0,    SEL_SCIF4_0),
0671     PINMUX_IPSR_PHYS(IP0_19_16, SCL5,           I2C_SEL_5_1),
0672
0673     PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A,    I2C_SEL_5_0,    SEL_ETHERAVB_0),
0674     PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C,      I2C_SEL_5_0,    SEL_MSIOF2_2),
0675     PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A,      I2C_SEL_5_0,    SEL_SCIF4_0),
0676     PINMUX_IPSR_PHYS(IP0_23_20, SDA5,           I2C_SEL_5_1),
0677
0678     PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
0679     PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
0680     PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
0681     PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B,        SEL_VIN4_1),
0682     PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B,      SEL_RCAN0_1),
0683     PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B,        SEL_CANFD0_1),
0684     PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E,       SEL_MSIOF3_4),
0685
0686     PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
0687     PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
0688     PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
0689     PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B,        SEL_VIN4_1),
0690     PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B,      SEL_RCAN0_1),
0691     PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B,        SEL_CANFD0_1),
0692     PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E,       SEL_MSIOF3_4),
0693
0694     /* IPSR1 */
0695     PINMUX_IPSR_GPSR(IP1_3_0,   IRQ2),
0696     PINMUX_IPSR_GPSR(IP1_3_0,   QCPV_QDE),
0697     PINMUX_IPSR_GPSR(IP1_3_0,   DU_EXODDF_DU_ODDF_DISP_CDE),
0698     PINMUX_IPSR_MSEL(IP1_3_0,   VI4_DATA2_B,        SEL_VIN4_1),
0699     PINMUX_IPSR_MSEL(IP1_3_0,   PWM3_B,         SEL_PWM3_1),
0700     PINMUX_IPSR_MSEL(IP1_3_0,   MSIOF3_SYNC_E,      SEL_MSIOF3_4),
0701
0702     PINMUX_IPSR_GPSR(IP1_7_4,   IRQ3),
0703     PINMUX_IPSR_GPSR(IP1_7_4,   QSTVB_QVE),
0704     PINMUX_IPSR_GPSR(IP1_7_4,   DU_DOTCLKOUT1),
0705     PINMUX_IPSR_MSEL(IP1_7_4,   VI4_DATA3_B,        SEL_VIN4_1),
0706     PINMUX_IPSR_MSEL(IP1_7_4,   PWM4_B,         SEL_PWM4_1),
0707     PINMUX_IPSR_MSEL(IP1_7_4,   MSIOF3_SCK_E,       SEL_MSIOF3_4),
0708
0709     PINMUX_IPSR_GPSR(IP1_11_8,  IRQ4),
0710     PINMUX_IPSR_GPSR(IP1_11_8,  QSTH_QHS),
0711     PINMUX_IPSR_GPSR(IP1_11_8,  DU_EXHSYNC_DU_HSYNC),
0712     PINMUX_IPSR_MSEL(IP1_11_8,  VI4_DATA4_B,        SEL_VIN4_1),
0713     PINMUX_IPSR_MSEL(IP1_11_8,  PWM5_B,         SEL_PWM5_1),
0714     PINMUX_IPSR_MSEL(IP1_11_8,  MSIOF3_RXD_E,       SEL_MSIOF3_4),
0715
0716     PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
0717     PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
0718     PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
0719     PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B,        SEL_VIN4_1),
0720     PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B,         SEL_PWM6_1),
0721     PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E,       SEL_MSIOF3_4),
0722
0723     PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
0724     PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
0725     PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B,        SEL_VIN4_1),
0726     PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B,        SEL_IEBUS_1),
0727
0728     PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A,        I2C_SEL_3_0,    SEL_PWM1_0),
0729     PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D,        I2C_SEL_3_0,    SEL_HSCIF3_3),
0730     PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B,       I2C_SEL_3_0,    SEL_VIN4_1),
0731     PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B,        I2C_SEL_3_0,    SEL_IEBUS_1),
0732     PINMUX_IPSR_PHYS(IP1_23_20, SCL3,           I2C_SEL_3_1),
0733
0734     PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A,        I2C_SEL_3_0,    SEL_PWM2_0),
0735     PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D,        I2C_SEL_3_0,    SEL_HSCIF3_3),
0736     PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B,        I2C_SEL_3_0,    SEL_IEBUS_1),
0737     PINMUX_IPSR_PHYS(IP1_27_24, SDA3,           I2C_SEL_3_1),
0738
0739     PINMUX_IPSR_GPSR(IP1_31_28, A0),
0740     PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
0741     PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B,      SEL_MSIOF3_1),
0742     PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
0743     PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
0744     PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A,         SEL_PWM3_0),
0745
0746     /* IPSR2 */
0747     PINMUX_IPSR_GPSR(IP2_3_0,   A1),
0748     PINMUX_IPSR_GPSR(IP2_3_0,   LCDOUT17),
0749     PINMUX_IPSR_MSEL(IP2_3_0,   MSIOF3_TXD_B,       SEL_MSIOF3_1),
0750     PINMUX_IPSR_GPSR(IP2_3_0,   VI4_DATA9),
0751     PINMUX_IPSR_GPSR(IP2_3_0,   DU_DB1),
0752     PINMUX_IPSR_MSEL(IP2_3_0,   PWM4_A,         SEL_PWM4_0),
0753
0754     PINMUX_IPSR_GPSR(IP2_7_4,   A2),
0755     PINMUX_IPSR_GPSR(IP2_7_4,   LCDOUT18),
0756     PINMUX_IPSR_MSEL(IP2_7_4,   MSIOF3_SCK_B,       SEL_MSIOF3_1),
0757     PINMUX_IPSR_GPSR(IP2_7_4,   VI4_DATA10),
0758     PINMUX_IPSR_GPSR(IP2_7_4,   DU_DB2),
0759     PINMUX_IPSR_MSEL(IP2_7_4,   PWM5_A,         SEL_PWM5_0),
0760
0761     PINMUX_IPSR_GPSR(IP2_11_8,  A3),
0762     PINMUX_IPSR_GPSR(IP2_11_8,  LCDOUT19),
0763     PINMUX_IPSR_MSEL(IP2_11_8,  MSIOF3_RXD_B,       SEL_MSIOF3_1),
0764     PINMUX_IPSR_GPSR(IP2_11_8,  VI4_DATA11),
0765     PINMUX_IPSR_GPSR(IP2_11_8,  DU_DB3),
0766     PINMUX_IPSR_MSEL(IP2_11_8,  PWM6_A,         SEL_PWM6_0),
0767
0768     PINMUX_IPSR_GPSR(IP2_15_12, A4),
0769     PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
0770     PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B,       SEL_MSIOF3_1),
0771     PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
0772     PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
0773     PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
0774
0775     PINMUX_IPSR_GPSR(IP2_19_16, A5),
0776     PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
0777     PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B,       SEL_MSIOF3_1),
0778     PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B,         SEL_SCIF4_1),
0779     PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
0780     PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
0781     PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
0782
0783     PINMUX_IPSR_GPSR(IP2_23_20, A6),
0784     PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
0785     PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A,       SEL_MSIOF2_0),
0786     PINMUX_IPSR_MSEL(IP2_23_20, RX4_B,          SEL_SCIF4_1),
0787     PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
0788     PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
0789     PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
0790
0791     PINMUX_IPSR_GPSR(IP2_27_24, A7),
0792     PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
0793     PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A,       SEL_MSIOF2_0),
0794     PINMUX_IPSR_MSEL(IP2_27_24, TX4_B,          SEL_SCIF4_1),
0795     PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
0796     PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
0797     PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
0798
0799     PINMUX_IPSR_GPSR(IP2_31_28, A8),
0800     PINMUX_IPSR_MSEL(IP2_31_28, RX3_B,          SEL_SCIF3_1),
0801     PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A,      SEL_MSIOF2_0),
0802     PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B,         SEL_HSCIF4_1),
0803     PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A,         SEL_I2C6_0),
0804     PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B,   SEL_ETHERAVB_1),
0805     PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B,         SEL_PWM1_1),
0806
0807     /* IPSR3 */
0808     PINMUX_IPSR_GPSR(IP3_3_0,   A9),
0809     PINMUX_IPSR_MSEL(IP3_3_0,   MSIOF2_SCK_A,       SEL_MSIOF2_0),
0810     PINMUX_IPSR_MSEL(IP3_3_0,   CTS4_N_B,       SEL_SCIF4_1),
0811     PINMUX_IPSR_GPSR(IP3_3_0,   VI5_VSYNC_N),
0812
0813     PINMUX_IPSR_GPSR(IP3_7_4,   A10),
0814     PINMUX_IPSR_MSEL(IP3_7_4,   MSIOF2_RXD_A,       SEL_MSIOF2_0),
0815     PINMUX_IPSR_MSEL(IP3_7_4,   RTS4_N_B,       SEL_SCIF4_1),
0816     PINMUX_IPSR_GPSR(IP3_7_4,   VI5_HSYNC_N),
0817
0818     PINMUX_IPSR_GPSR(IP3_11_8,  A11),
0819     PINMUX_IPSR_MSEL(IP3_11_8,  TX3_B,          SEL_SCIF3_1),
0820     PINMUX_IPSR_MSEL(IP3_11_8,  MSIOF2_TXD_A,       SEL_MSIOF2_0),
0821     PINMUX_IPSR_MSEL(IP3_11_8,  HTX4_B,         SEL_HSCIF4_1),
0822     PINMUX_IPSR_GPSR(IP3_11_8,  HSCK4),
0823     PINMUX_IPSR_GPSR(IP3_11_8,  VI5_FIELD),
0824     PINMUX_IPSR_MSEL(IP3_11_8,  SCL6_A,         SEL_I2C6_0),
0825     PINMUX_IPSR_MSEL(IP3_11_8,  AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
0826     PINMUX_IPSR_MSEL(IP3_11_8,  PWM2_B,         SEL_PWM2_1),
0827
0828     PINMUX_IPSR_GPSR(IP3_15_12, A12),
0829     PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
0830     PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C,       SEL_MSIOF3_2),
0831     PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A,         SEL_HSCIF4_0),
0832     PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
0833     PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
0834
0835     PINMUX_IPSR_GPSR(IP3_19_16, A13),
0836     PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
0837     PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C,      SEL_MSIOF3_2),
0838     PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A,         SEL_HSCIF4_0),
0839     PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
0840     PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
0841
0842     PINMUX_IPSR_GPSR(IP3_23_20, A14),
0843     PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
0844     PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C,       SEL_MSIOF3_2),
0845     PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
0846     PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
0847     PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
0848
0849     PINMUX_IPSR_GPSR(IP3_27_24, A15),
0850     PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
0851     PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C,       SEL_MSIOF3_2),
0852     PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
0853     PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
0854     PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
0855
0856     PINMUX_IPSR_GPSR(IP3_31_28, A16),
0857     PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
0858     PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
0859     PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
0860
0861     /* IPSR4 */
0862     PINMUX_IPSR_GPSR(IP4_3_0,   A17),
0863     PINMUX_IPSR_GPSR(IP4_3_0,   LCDOUT9),
0864     PINMUX_IPSR_GPSR(IP4_3_0,   VI4_VSYNC_N),
0865     PINMUX_IPSR_GPSR(IP4_3_0,   DU_DG1),
0866
0867     PINMUX_IPSR_GPSR(IP4_7_4,   A18),
0868     PINMUX_IPSR_GPSR(IP4_7_4,   LCDOUT10),
0869     PINMUX_IPSR_GPSR(IP4_7_4,   VI4_HSYNC_N),
0870     PINMUX_IPSR_GPSR(IP4_7_4,   DU_DG2),
0871
0872     PINMUX_IPSR_GPSR(IP4_11_8,  A19),
0873     PINMUX_IPSR_GPSR(IP4_11_8,  LCDOUT11),
0874     PINMUX_IPSR_GPSR(IP4_11_8,  VI4_CLKENB),
0875     PINMUX_IPSR_GPSR(IP4_11_8,  DU_DG3),
0876
0877     PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
0878     PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
0879
0880     PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
0881     PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
0882     PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B,     SEL_LBSC_1),
0883
0884     PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
0885     PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
0886     PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D,       SEL_MSIOF3_3),
0887     PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
0888     PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
0889     PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
0890     PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
0891     PINMUX_IPSR_MSEL(IP4_23_20, IETX_A,         SEL_IEBUS_0),
0892
0893     PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
0894     PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D,      SEL_MSIOF3_3),
0895     PINMUX_IPSR_MSEL(IP4_27_24, RX3_A,          SEL_SCIF3_0),
0896     PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A,         SEL_HSCIF3_0),
0897     PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A,      SEL_RCAN0_0),
0898     PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A,        SEL_CANFD0_0),
0899
0900     PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
0901     PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D,       SEL_MSIOF3_3),
0902     PINMUX_IPSR_MSEL(IP4_31_28, TX3_A,          SEL_SCIF3_0),
0903     PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A,         SEL_HSCIF3_0),
0904     PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A,      SEL_RCAN0_0),
0905     PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A,        SEL_CANFD0_0),
0906
0907     /* IPSR5 */
0908     PINMUX_IPSR_GPSR(IP5_3_0,   WE0_N),
0909     PINMUX_IPSR_MSEL(IP5_3_0,   MSIOF3_TXD_D,       SEL_MSIOF3_3),
0910     PINMUX_IPSR_GPSR(IP5_3_0,   CTS3_N),
0911     PINMUX_IPSR_GPSR(IP5_3_0,   HCTS3_N),
0912     PINMUX_IPSR_MSEL(IP5_3_0,   SCL6_B,         SEL_I2C6_1),
0913     PINMUX_IPSR_GPSR(IP5_3_0,   CAN_CLK),
0914     PINMUX_IPSR_MSEL(IP5_3_0,   IECLK_A,        SEL_IEBUS_0),
0915
0916     PINMUX_IPSR_GPSR(IP5_7_4,   WE1_N),
0917     PINMUX_IPSR_MSEL(IP5_7_4,   MSIOF3_SS1_D,       SEL_MSIOF3_3),
0918     PINMUX_IPSR_GPSR(IP5_7_4,   RTS3_N),
0919     PINMUX_IPSR_GPSR(IP5_7_4,   HRTS3_N),
0920     PINMUX_IPSR_MSEL(IP5_7_4,   SDA6_B,         SEL_I2C6_1),
0921     PINMUX_IPSR_GPSR(IP5_7_4,   CAN1_RX),
0922     PINMUX_IPSR_GPSR(IP5_7_4,   CANFD1_RX),
0923     PINMUX_IPSR_MSEL(IP5_7_4,   IERX_A,         SEL_IEBUS_0),
0924
0925     PINMUX_IPSR_MSEL(IP5_11_8,  EX_WAIT0_A,     SEL_LBSC_0),
0926     PINMUX_IPSR_GPSR(IP5_11_8,  QCLK),
0927     PINMUX_IPSR_GPSR(IP5_11_8,  VI4_CLK),
0928     PINMUX_IPSR_GPSR(IP5_11_8,  DU_DOTCLKOUT0),
0929
0930     PINMUX_IPSR_GPSR(IP5_15_12, D0),
0931     PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B,       SEL_MSIOF2_1),
0932     PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A,       SEL_MSIOF3_0),
0933     PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
0934     PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
0935
0936     PINMUX_IPSR_GPSR(IP5_19_16, D1),
0937     PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B,       SEL_MSIOF2_1),
0938     PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A,      SEL_MSIOF3_0),
0939     PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
0940     PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
0941
0942     PINMUX_IPSR_GPSR(IP5_23_20, D2),
0943     PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A,       SEL_MSIOF3_0),
0944     PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
0945     PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
0946
0947     PINMUX_IPSR_GPSR(IP5_27_24, D3),
0948     PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A,       SEL_MSIOF3_0),
0949     PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
0950     PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
0951
0952     PINMUX_IPSR_GPSR(IP5_31_28, D4),
0953     PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B,       SEL_MSIOF2_1),
0954     PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
0955     PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
0956
0957     /* IPSR6 */
0958     PINMUX_IPSR_GPSR(IP6_3_0,   D5),
0959     PINMUX_IPSR_MSEL(IP6_3_0,   MSIOF2_SYNC_B,      SEL_MSIOF2_1),
0960     PINMUX_IPSR_GPSR(IP6_3_0,   VI4_DATA21),
0961     PINMUX_IPSR_GPSR(IP6_3_0,   VI5_DATA5),
0962
0963     PINMUX_IPSR_GPSR(IP6_7_4,   D6),
0964     PINMUX_IPSR_MSEL(IP6_7_4,   MSIOF2_RXD_B,       SEL_MSIOF2_1),
0965     PINMUX_IPSR_GPSR(IP6_7_4,   VI4_DATA22),
0966     PINMUX_IPSR_GPSR(IP6_7_4,   VI5_DATA6),
0967
0968     PINMUX_IPSR_GPSR(IP6_11_8,  D7),
0969     PINMUX_IPSR_MSEL(IP6_11_8,  MSIOF2_TXD_B,       SEL_MSIOF2_1),
0970     PINMUX_IPSR_GPSR(IP6_11_8,  VI4_DATA23),
0971     PINMUX_IPSR_GPSR(IP6_11_8,  VI5_DATA7),
0972
0973     PINMUX_IPSR_GPSR(IP6_15_12, D8),
0974     PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
0975     PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D,       SEL_MSIOF2_3),
0976     PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C,         SEL_SCIF4_2),
0977     PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A,        SEL_VIN4_0),
0978     PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
0979
0980     PINMUX_IPSR_GPSR(IP6_19_16, D9),
0981     PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
0982     PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D,      SEL_MSIOF2_3),
0983     PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A,        SEL_VIN4_0),
0984     PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
0985
0986     PINMUX_IPSR_GPSR(IP6_23_20, D10),
0987     PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
0988     PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D,       SEL_MSIOF2_3),
0989     PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B,         SEL_HSCIF3_1),
0990     PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A,        SEL_VIN4_0),
0991     PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C,       SEL_SCIF4_2),
0992     PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
0993
0994     PINMUX_IPSR_GPSR(IP6_27_24, D11),
0995     PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
0996     PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D,       SEL_MSIOF2_3),
0997     PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B,         SEL_HSCIF3_1),
0998     PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A,        SEL_VIN4_0),
0999     PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C,       SEL_SCIF4_2),
1000     PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
1001
1002     PINMUX_IPSR_GPSR(IP6_31_28, D12),
1003     PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
1004     PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D,       SEL_MSIOF2_3),
1005     PINMUX_IPSR_MSEL(IP6_31_28, RX4_C,          SEL_SCIF4_2),
1006     PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A,        SEL_VIN4_0),
1007     PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
1008
1009     /* IPSR7 */
1010     PINMUX_IPSR_GPSR(IP7_3_0,   D13),
1011     PINMUX_IPSR_GPSR(IP7_3_0,   LCDOUT5),
1012     PINMUX_IPSR_MSEL(IP7_3_0,   MSIOF2_SS2_D,       SEL_MSIOF2_3),
1013     PINMUX_IPSR_MSEL(IP7_3_0,   TX4_C,          SEL_SCIF4_2),
1014     PINMUX_IPSR_MSEL(IP7_3_0,   VI4_DATA5_A,        SEL_VIN4_0),
1015     PINMUX_IPSR_GPSR(IP7_3_0,   DU_DR5),
1016
1017     PINMUX_IPSR_GPSR(IP7_7_4,   D14),
1018     PINMUX_IPSR_GPSR(IP7_7_4,   LCDOUT6),
1019     PINMUX_IPSR_MSEL(IP7_7_4,   MSIOF3_SS1_A,       SEL_MSIOF3_0),
1020     PINMUX_IPSR_MSEL(IP7_7_4,   HRX3_C,         SEL_HSCIF3_2),
1021     PINMUX_IPSR_MSEL(IP7_7_4,   VI4_DATA6_A,        SEL_VIN4_0),
1022     PINMUX_IPSR_GPSR(IP7_7_4,   DU_DR6),
1023     PINMUX_IPSR_MSEL(IP7_7_4,   SCL6_C,         SEL_I2C6_2),
1024
1025     PINMUX_IPSR_GPSR(IP7_11_8,  D15),
1026     PINMUX_IPSR_GPSR(IP7_11_8,  LCDOUT7),
1027     PINMUX_IPSR_MSEL(IP7_11_8,  MSIOF3_SS2_A,       SEL_MSIOF3_0),
1028     PINMUX_IPSR_MSEL(IP7_11_8,  HTX3_C,         SEL_HSCIF3_2),
1029     PINMUX_IPSR_MSEL(IP7_11_8,  VI4_DATA7_A,        SEL_VIN4_0),
1030     PINMUX_IPSR_GPSR(IP7_11_8,  DU_DR7),
1031     PINMUX_IPSR_MSEL(IP7_11_8,  SDA6_C,         SEL_I2C6_2),
1032
1033     PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
1034     PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E,       SEL_MSIOF1_4),
1035     PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B,       SEL_SSP1_0_1),
1036
1037     PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1038     PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E,      SEL_MSIOF1_4),
1039     PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B,    SEL_SSP1_0_1),
1040
1041     PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1042     PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E,       SEL_MSIOF1_4),
1043     PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B,      SEL_TSIF0_1),
1044     PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B,      SEL_SSP1_0_1),
1045
1046     PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1047     PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E,       SEL_MSIOF1_4),
1048     PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B,       SEL_TSIF0_1),
1049     PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B,     SEL_SSP1_0_1),
1050
1051     /* IPSR8 */
1052     PINMUX_IPSR_GPSR(IP8_3_0,   SD0_DAT2),
1053     PINMUX_IPSR_MSEL(IP8_3_0,   MSIOF1_SS1_E,       SEL_MSIOF1_4),
1054     PINMUX_IPSR_MSEL(IP8_3_0,   TS_SDAT0_B,     SEL_TSIF0_1),
1055     PINMUX_IPSR_MSEL(IP8_3_0,   STP_ISD_0_B,        SEL_SSP1_0_1),
1056
1057     PINMUX_IPSR_GPSR(IP8_7_4,   SD0_DAT3),
1058     PINMUX_IPSR_MSEL(IP8_7_4,   MSIOF1_SS2_E,       SEL_MSIOF1_4),
1059     PINMUX_IPSR_MSEL(IP8_7_4,   TS_SDEN0_B,     SEL_TSIF0_1),
1060     PINMUX_IPSR_MSEL(IP8_7_4,   STP_ISEN_0_B,       SEL_SSP1_0_1),
1061
1062     PINMUX_IPSR_GPSR(IP8_11_8,  SD1_CLK),
1063     PINMUX_IPSR_MSEL(IP8_11_8,  MSIOF1_SCK_G,       SEL_MSIOF1_6),
1064     PINMUX_IPSR_MSEL(IP8_11_8,  SIM0_CLK_A,     SEL_SIMCARD_0),
1065
1066     PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1067     PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G,      SEL_MSIOF1_6),
1068     PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B,       SEL_NDF_1),
1069     PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A,       SEL_SIMCARD_0),
1070     PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B,    SEL_SSP1_1_1),
1071
1072     PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1073     PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1074     PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G,       SEL_MSIOF1_6),
1075     PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B,       SEL_NDF_1),
1076     PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B,      SEL_TSIF1_1),
1077     PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B,      SEL_SSP1_1_1),
1078
1079     PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1080     PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1081     PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G,       SEL_MSIOF1_6),
1082     PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B,     SEL_NDF_1),
1083     PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B,       SEL_TSIF1_1),
1084     PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B,     SEL_SSP1_1_1),
1085
1086     PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1087     PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1088     PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G,       SEL_MSIOF1_6),
1089     PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B,     SEL_NDF_1),
1090     PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B,     SEL_TSIF1_1),
1091     PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B,        SEL_SSP1_1_1),
1092
1093     PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1094     PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1095     PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G,       SEL_MSIOF1_6),
1096     PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B,       SEL_NDF_1),
1097     PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B,     SEL_TSIF1_1),
1098     PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B,       SEL_SSP1_1_1),
1099
1100     /* IPSR9 */
1101     PINMUX_IPSR_GPSR(IP9_3_0,   SD2_CLK),
1102     PINMUX_IPSR_GPSR(IP9_3_0,   NFDATA8),
1103
1104     PINMUX_IPSR_GPSR(IP9_7_4,   SD2_CMD),
1105     PINMUX_IPSR_GPSR(IP9_7_4,   NFDATA9),
1106
1107     PINMUX_IPSR_GPSR(IP9_11_8,  SD2_DAT0),
1108     PINMUX_IPSR_GPSR(IP9_11_8,  NFDATA10),
1109
1110     PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1111     PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1112
1113     PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1114     PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1115
1116     PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1117     PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1118
1119     PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1120     PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1121
1122     PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1123     PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1124
1125     /* IPSR10 */
1126     PINMUX_IPSR_GPSR(IP10_3_0,  SD3_CMD),
1127     PINMUX_IPSR_GPSR(IP10_3_0,  NFRE_N),
1128
1129     PINMUX_IPSR_GPSR(IP10_7_4,  SD3_DAT0),
1130     PINMUX_IPSR_GPSR(IP10_7_4,  NFDATA0),
1131
1132     PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1133     PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1134
1135     PINMUX_IPSR_GPSR(IP10_15_12,    SD3_DAT2),
1136     PINMUX_IPSR_GPSR(IP10_15_12,    NFDATA2),
1137
1138     PINMUX_IPSR_GPSR(IP10_19_16,    SD3_DAT3),
1139     PINMUX_IPSR_GPSR(IP10_19_16,    NFDATA3),
1140
1141     PINMUX_IPSR_GPSR(IP10_23_20,    SD3_DAT4),
1142     PINMUX_IPSR_MSEL(IP10_23_20,    SD2_CD_A,       SEL_SDHI2_0),
1143     PINMUX_IPSR_GPSR(IP10_23_20,    NFDATA4),
1144
1145     PINMUX_IPSR_GPSR(IP10_27_24,    SD3_DAT5),
1146     PINMUX_IPSR_MSEL(IP10_27_24,    SD2_WP_A,       SEL_SDHI2_0),
1147     PINMUX_IPSR_GPSR(IP10_27_24,    NFDATA5),
1148
1149     PINMUX_IPSR_GPSR(IP10_31_28,    SD3_DAT6),
1150     PINMUX_IPSR_GPSR(IP10_31_28,    SD3_CD),
1151     PINMUX_IPSR_GPSR(IP10_31_28,    NFDATA6),
1152
1153     /* IPSR11 */
1154     PINMUX_IPSR_GPSR(IP11_3_0,  SD3_DAT7),
1155     PINMUX_IPSR_GPSR(IP11_3_0,  SD3_WP),
1156     PINMUX_IPSR_GPSR(IP11_3_0,  NFDATA7),
1157
1158     PINMUX_IPSR_GPSR(IP11_7_4,  SD3_DS),
1159     PINMUX_IPSR_GPSR(IP11_7_4,  NFCLE),
1160
1161     PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1162     PINMUX_IPSR_MSEL(IP11_11_8, NFDATA14_A,     SEL_NDF_0),
1163     PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B,         SEL_I2C2_1),
1164     PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A,     SEL_SIMCARD_0),
1165
1166     PINMUX_IPSR_GPSR(IP11_15_12,    SD0_WP),
1167     PINMUX_IPSR_MSEL(IP11_15_12,    NFDATA15_A,     SEL_NDF_0),
1168     PINMUX_IPSR_MSEL(IP11_15_12,    SDA2_B,         SEL_I2C2_1),
1169
1170     PINMUX_IPSR_MSEL(IP11_19_16,    SD1_CD,         I2C_SEL_0_0),
1171     PINMUX_IPSR_PHYS_MSEL(IP11_19_16, NFRB_N_A,     I2C_SEL_0_0,    SEL_NDF_0),
1172     PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B,       I2C_SEL_0_0,    SEL_SIMCARD_1),
1173     PINMUX_IPSR_PHYS(IP11_19_16,    SCL0,           I2C_SEL_0_1),
1174
1175     PINMUX_IPSR_MSEL(IP11_23_20,    SD1_WP,         I2C_SEL_0_0),
1176     PINMUX_IPSR_PHYS_MSEL(IP11_23_20, NFCE_N_A,     I2C_SEL_0_0,    SEL_NDF_0),
1177     PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B,     I2C_SEL_0_0,    SEL_SIMCARD_1),
1178     PINMUX_IPSR_PHYS(IP11_23_20,    SDA0,           I2C_SEL_0_1),
1179
1180     PINMUX_IPSR_GPSR(IP11_27_24,    SCK0),
1181     PINMUX_IPSR_MSEL(IP11_27_24,    HSCK1_B,        SEL_HSCIF1_1),
1182     PINMUX_IPSR_MSEL(IP11_27_24,    MSIOF1_SS2_B,       SEL_MSIOF1_1),
1183     PINMUX_IPSR_MSEL(IP11_27_24,    AUDIO_CLKC_B,       SEL_ADGC_1),
1184     PINMUX_IPSR_MSEL(IP11_27_24,    SDA2_A,         SEL_I2C2_0),
1185     PINMUX_IPSR_MSEL(IP11_27_24,    SIM0_RST_B,     SEL_SIMCARD_1),
1186     PINMUX_IPSR_MSEL(IP11_27_24,    STP_OPWM_0_C,       SEL_SSP1_0_2),
1187     PINMUX_IPSR_MSEL(IP11_27_24,    RIF0_CLK_B,     SEL_DRIF0_1),
1188     PINMUX_IPSR_GPSR(IP11_27_24,    ADICHS2),
1189     PINMUX_IPSR_MSEL(IP11_27_24,    SCK5_B,         SEL_SCIF5_1),
1190
1191     PINMUX_IPSR_GPSR(IP11_31_28,    RX0),
1192     PINMUX_IPSR_MSEL(IP11_31_28,    HRX1_B,         SEL_HSCIF1_1),
1193     PINMUX_IPSR_MSEL(IP11_31_28,    TS_SCK0_C,      SEL_TSIF0_2),
1194     PINMUX_IPSR_MSEL(IP11_31_28,    STP_ISCLK_0_C,      SEL_SSP1_0_2),
1195     PINMUX_IPSR_MSEL(IP11_31_28,    RIF0_D0_B,      SEL_DRIF0_1),
1196
1197     /* IPSR12 */
1198     PINMUX_IPSR_GPSR(IP12_3_0,  TX0),
1199     PINMUX_IPSR_MSEL(IP12_3_0,  HTX1_B,         SEL_HSCIF1_1),
1200     PINMUX_IPSR_MSEL(IP12_3_0,  TS_SPSYNC0_C,       SEL_TSIF0_2),
1201     PINMUX_IPSR_MSEL(IP12_3_0,  STP_ISSYNC_0_C,     SEL_SSP1_0_2),
1202     PINMUX_IPSR_MSEL(IP12_3_0,  RIF0_D1_B,      SEL_DRIF0_1),
1203
1204     PINMUX_IPSR_GPSR(IP12_7_4,  CTS0_N),
1205     PINMUX_IPSR_MSEL(IP12_7_4,  HCTS1_N_B,      SEL_HSCIF1_1),
1206     PINMUX_IPSR_MSEL(IP12_7_4,  MSIOF1_SYNC_B,      SEL_MSIOF1_1),
1207     PINMUX_IPSR_MSEL(IP12_7_4,  TS_SPSYNC1_C,       SEL_TSIF1_2),
1208     PINMUX_IPSR_MSEL(IP12_7_4,  STP_ISSYNC_1_C,     SEL_SSP1_1_2),
1209     PINMUX_IPSR_MSEL(IP12_7_4,  RIF1_SYNC_B,        SEL_DRIF1_1),
1210     PINMUX_IPSR_GPSR(IP12_7_4,  AUDIO_CLKOUT_C),
1211     PINMUX_IPSR_GPSR(IP12_7_4,  ADICS_SAMP),
1212
1213     PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
1214     PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B,      SEL_HSCIF1_1),
1215     PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B,       SEL_MSIOF1_1),
1216     PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B,       SEL_ADGA_1),
1217     PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A,         SEL_I2C2_0),
1218     PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C,    SEL_SSP1_1_2),
1219     PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B,        SEL_DRIF0_1),
1220     PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1221
1222     PINMUX_IPSR_MSEL(IP12_15_12,    RX1_A,          SEL_SCIF1_0),
1223     PINMUX_IPSR_MSEL(IP12_15_12,    HRX1_A,         SEL_HSCIF1_0),
1224     PINMUX_IPSR_MSEL(IP12_15_12,    TS_SDAT0_C,     SEL_TSIF0_2),
1225     PINMUX_IPSR_MSEL(IP12_15_12,    STP_ISD_0_C,        SEL_SSP1_0_2),
1226     PINMUX_IPSR_MSEL(IP12_15_12,    RIF1_CLK_C,     SEL_DRIF1_2),
1227
1228     PINMUX_IPSR_MSEL(IP12_19_16,    TX1_A,          SEL_SCIF1_0),
1229     PINMUX_IPSR_MSEL(IP12_19_16,    HTX1_A,         SEL_HSCIF1_0),
1230     PINMUX_IPSR_MSEL(IP12_19_16,    TS_SDEN0_C,     SEL_TSIF0_2),
1231     PINMUX_IPSR_MSEL(IP12_19_16,    STP_ISEN_0_C,       SEL_SSP1_0_2),
1232     PINMUX_IPSR_MSEL(IP12_19_16,    RIF1_D0_C,      SEL_DRIF1_2),
1233
1234     PINMUX_IPSR_GPSR(IP12_23_20,    CTS1_N),
1235     PINMUX_IPSR_MSEL(IP12_23_20,    HCTS1_N_A,      SEL_HSCIF1_0),
1236     PINMUX_IPSR_MSEL(IP12_23_20,    MSIOF1_RXD_B,       SEL_MSIOF1_1),
1237     PINMUX_IPSR_MSEL(IP12_23_20,    TS_SDEN1_C,     SEL_TSIF1_2),
1238     PINMUX_IPSR_MSEL(IP12_23_20,    STP_ISEN_1_C,       SEL_SSP1_1_2),
1239     PINMUX_IPSR_MSEL(IP12_23_20,    RIF1_D0_B,      SEL_DRIF1_1),
1240     PINMUX_IPSR_GPSR(IP12_23_20,    ADIDATA),
1241
1242     PINMUX_IPSR_GPSR(IP12_27_24,    RTS1_N),
1243     PINMUX_IPSR_MSEL(IP12_27_24,    HRTS1_N_A,      SEL_HSCIF1_0),
1244     PINMUX_IPSR_MSEL(IP12_27_24,    MSIOF1_TXD_B,       SEL_MSIOF1_1),
1245     PINMUX_IPSR_MSEL(IP12_27_24,    TS_SDAT1_C,     SEL_TSIF1_2),
1246     PINMUX_IPSR_MSEL(IP12_27_24,    STP_ISD_1_C,        SEL_SSP1_1_2),
1247     PINMUX_IPSR_MSEL(IP12_27_24,    RIF1_D1_B,      SEL_DRIF1_1),
1248     PINMUX_IPSR_GPSR(IP12_27_24,    ADICHS0),
1249
1250     PINMUX_IPSR_GPSR(IP12_31_28,    SCK2),
1251     PINMUX_IPSR_MSEL(IP12_31_28,    SCIF_CLK_B,     SEL_SCIF_1),
1252     PINMUX_IPSR_MSEL(IP12_31_28,    MSIOF1_SCK_B,       SEL_MSIOF1_1),
1253     PINMUX_IPSR_MSEL(IP12_31_28,    TS_SCK1_C,      SEL_TSIF1_2),
1254     PINMUX_IPSR_MSEL(IP12_31_28,    STP_ISCLK_1_C,      SEL_SSP1_1_2),
1255     PINMUX_IPSR_MSEL(IP12_31_28,    RIF1_CLK_B,     SEL_DRIF1_1),
1256     PINMUX_IPSR_GPSR(IP12_31_28,    ADICLK),
1257
1258     /* IPSR13 */
1259     PINMUX_IPSR_MSEL(IP13_3_0,  TX2_A,          SEL_SCIF2_0),
1260     PINMUX_IPSR_MSEL(IP13_3_0,  SD2_CD_B,       SEL_SDHI2_1),
1261     PINMUX_IPSR_MSEL(IP13_3_0,  SCL1_A,         SEL_I2C1_0),
1262     PINMUX_IPSR_MSEL(IP13_3_0,  FMCLK_A,        SEL_FM_0),
1263     PINMUX_IPSR_MSEL(IP13_3_0,  RIF1_D1_C,      SEL_DRIF1_2),
1264     PINMUX_IPSR_GPSR(IP13_3_0,  FSO_CFE_0_N),
1265
1266     PINMUX_IPSR_MSEL(IP13_7_4,  RX2_A,          SEL_SCIF2_0),
1267     PINMUX_IPSR_MSEL(IP13_7_4,  SD2_WP_B,       SEL_SDHI2_1),
1268     PINMUX_IPSR_MSEL(IP13_7_4,  SDA1_A,         SEL_I2C1_0),
1269     PINMUX_IPSR_MSEL(IP13_7_4,  FMIN_A,         SEL_FM_0),
1270     PINMUX_IPSR_MSEL(IP13_7_4,  RIF1_SYNC_C,        SEL_DRIF1_2),
1271     PINMUX_IPSR_GPSR(IP13_7_4,  FSO_CFE_1_N),
1272
1273     PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1274     PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D,       SEL_MSIOF1_3),
1275     PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A,       SEL_ADGB_0),
1276     PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B,       SEL_SSI1_1),
1277     PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D,      SEL_TSIF0_3),
1278     PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D,      SEL_SSP1_0_3),
1279     PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C,     SEL_DRIF0_2),
1280     PINMUX_IPSR_MSEL(IP13_11_8, RX5_B,          SEL_SCIF5_1),
1281
1282     PINMUX_IPSR_GPSR(IP13_15_12,    HRX0),
1283     PINMUX_IPSR_MSEL(IP13_15_12,    MSIOF1_RXD_D,       SEL_MSIOF1_3),
1284     PINMUX_IPSR_MSEL(IP13_15_12,    SSI_SDATA2_B,       SEL_SSI2_1),
1285     PINMUX_IPSR_MSEL(IP13_15_12,    TS_SDEN0_D,     SEL_TSIF0_3),
1286     PINMUX_IPSR_MSEL(IP13_15_12,    STP_ISEN_0_D,       SEL_SSP1_0_3),
1287     PINMUX_IPSR_MSEL(IP13_15_12,    RIF0_D0_C,      SEL_DRIF0_2),
1288
1289     PINMUX_IPSR_GPSR(IP13_19_16,    HTX0),
1290     PINMUX_IPSR_MSEL(IP13_19_16,    MSIOF1_TXD_D,       SEL_MSIOF1_3),
1291     PINMUX_IPSR_MSEL(IP13_19_16,    SSI_SDATA9_B,       SEL_SSI9_1),
1292     PINMUX_IPSR_MSEL(IP13_19_16,    TS_SDAT0_D,     SEL_TSIF0_3),
1293     PINMUX_IPSR_MSEL(IP13_19_16,    STP_ISD_0_D,        SEL_SSP1_0_3),
1294     PINMUX_IPSR_MSEL(IP13_19_16,    RIF0_D1_C,      SEL_DRIF0_2),
1295
1296     PINMUX_IPSR_GPSR(IP13_23_20,    HCTS0_N),
1297     PINMUX_IPSR_MSEL(IP13_23_20,    RX2_B,          SEL_SCIF2_1),
1298     PINMUX_IPSR_MSEL(IP13_23_20,    MSIOF1_SYNC_D,      SEL_MSIOF1_3),
1299     PINMUX_IPSR_MSEL(IP13_23_20,    SSI_SCK9_A,     SEL_SSI9_0),
1300     PINMUX_IPSR_MSEL(IP13_23_20,    TS_SPSYNC0_D,       SEL_TSIF0_3),
1301     PINMUX_IPSR_MSEL(IP13_23_20,    STP_ISSYNC_0_D,     SEL_SSP1_0_3),
1302     PINMUX_IPSR_MSEL(IP13_23_20,    RIF0_SYNC_C,        SEL_DRIF0_2),
1303     PINMUX_IPSR_GPSR(IP13_23_20,    AUDIO_CLKOUT1_A),
1304
1305     PINMUX_IPSR_GPSR(IP13_27_24,    HRTS0_N),
1306     PINMUX_IPSR_MSEL(IP13_27_24,    TX2_B,          SEL_SCIF2_1),
1307     PINMUX_IPSR_MSEL(IP13_27_24,    MSIOF1_SS1_D,       SEL_MSIOF1_3),
1308     PINMUX_IPSR_MSEL(IP13_27_24,    SSI_WS9_A,      SEL_SSI9_0),
1309     PINMUX_IPSR_MSEL(IP13_27_24,    STP_IVCXO27_0_D,    SEL_SSP1_0_3),
1310     PINMUX_IPSR_MSEL(IP13_27_24,    BPFCLK_A,       SEL_FM_0),
1311     PINMUX_IPSR_GPSR(IP13_27_24,    AUDIO_CLKOUT2_A),
1312
1313     PINMUX_IPSR_GPSR(IP13_31_28,    MSIOF0_SYNC),
1314     PINMUX_IPSR_GPSR(IP13_31_28,    AUDIO_CLKOUT_A),
1315     PINMUX_IPSR_MSEL(IP13_31_28,    TX5_B,          SEL_SCIF5_1),
1316     PINMUX_IPSR_MSEL(IP13_31_28,    BPFCLK_D,       SEL_FM_3),
1317
1318     /* IPSR14 */
1319     PINMUX_IPSR_GPSR(IP14_3_0,  MSIOF0_SS1),
1320     PINMUX_IPSR_MSEL(IP14_3_0,  RX5_A,          SEL_SCIF5_0),
1321     PINMUX_IPSR_MSEL(IP14_3_0,  NFWP_N_A,       SEL_NDF_0),
1322     PINMUX_IPSR_MSEL(IP14_3_0,  AUDIO_CLKA_C,       SEL_ADGA_2),
1323     PINMUX_IPSR_MSEL(IP14_3_0,  SSI_SCK2_A,     SEL_SSI2_0),
1324     PINMUX_IPSR_MSEL(IP14_3_0,  STP_IVCXO27_0_C,    SEL_SSP1_0_2),
1325     PINMUX_IPSR_GPSR(IP14_3_0,  AUDIO_CLKOUT3_A),
1326     PINMUX_IPSR_MSEL(IP14_3_0,  TCLK1_B,        SEL_TIMER_TMU_1),
1327
1328     PINMUX_IPSR_GPSR(IP14_7_4,  MSIOF0_SS2),
1329     PINMUX_IPSR_MSEL(IP14_7_4,  TX5_A,          SEL_SCIF5_0),
1330     PINMUX_IPSR_MSEL(IP14_7_4,  MSIOF1_SS2_D,       SEL_MSIOF1_3),
1331     PINMUX_IPSR_MSEL(IP14_7_4,  AUDIO_CLKC_A,       SEL_ADGC_0),
1332     PINMUX_IPSR_MSEL(IP14_7_4,  SSI_WS2_A,      SEL_SSI2_0),
1333     PINMUX_IPSR_MSEL(IP14_7_4,  STP_OPWM_0_D,       SEL_SSP1_0_3),
1334     PINMUX_IPSR_GPSR(IP14_7_4,  AUDIO_CLKOUT_D),
1335     PINMUX_IPSR_MSEL(IP14_7_4,  SPEEDIN_B,      SEL_SPEED_PULSE_1),
1336
1337     PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1338     PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F,       SEL_MSIOF1_5),
1339     PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B,         SEL_I2C1_1),
1340
1341     PINMUX_IPSR_GPSR(IP14_15_12,    MLB_SIG),
1342     PINMUX_IPSR_MSEL(IP14_15_12,    RX1_B,          SEL_SCIF1_1),
1343     PINMUX_IPSR_MSEL(IP14_15_12,    MSIOF1_SYNC_F,      SEL_MSIOF1_5),
1344     PINMUX_IPSR_MSEL(IP14_15_12,    SDA1_B,         SEL_I2C1_1),
1345
1346     PINMUX_IPSR_GPSR(IP14_19_16,    MLB_DAT),
1347     PINMUX_IPSR_MSEL(IP14_19_16,    TX1_B,          SEL_SCIF1_1),
1348     PINMUX_IPSR_MSEL(IP14_19_16,    MSIOF1_RXD_F,       SEL_MSIOF1_5),
1349
1350     PINMUX_IPSR_GPSR(IP14_23_20,    SSI_SCK01239),
1351     PINMUX_IPSR_MSEL(IP14_23_20,    MSIOF1_TXD_F,       SEL_MSIOF1_5),
1352
1353     PINMUX_IPSR_GPSR(IP14_27_24,    SSI_WS01239),
1354     PINMUX_IPSR_MSEL(IP14_27_24,    MSIOF1_SS1_F,       SEL_MSIOF1_5),
1355
1356     PINMUX_IPSR_GPSR(IP14_31_28,    SSI_SDATA0),
1357     PINMUX_IPSR_MSEL(IP14_31_28,    MSIOF1_SS2_F,       SEL_MSIOF1_5),
1358
1359     /* IPSR15 */
1360     PINMUX_IPSR_MSEL(IP15_3_0,  SSI_SDATA1_A,       SEL_SSI1_0),
1361
1362     PINMUX_IPSR_MSEL(IP15_7_4,  SSI_SDATA2_A,       SEL_SSI2_0),
1363     PINMUX_IPSR_MSEL(IP15_7_4,  SSI_SCK1_B,     SEL_SSI1_1),
1364
1365     PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1366     PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A,       SEL_MSIOF1_0),
1367     PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A,       SEL_SSP1_0_0),
1368
1369     PINMUX_IPSR_GPSR(IP15_15_12,    SSI_WS349),
1370     PINMUX_IPSR_MSEL(IP15_15_12,    HCTS2_N_A,      SEL_HSCIF2_0),
1371     PINMUX_IPSR_MSEL(IP15_15_12,    MSIOF1_SS2_A,       SEL_MSIOF1_0),
1372     PINMUX_IPSR_MSEL(IP15_15_12,    STP_IVCXO27_0_A,    SEL_SSP1_0_0),
1373
1374     PINMUX_IPSR_GPSR(IP15_19_16,    SSI_SDATA3),
1375     PINMUX_IPSR_MSEL(IP15_19_16,    HRTS2_N_A,      SEL_HSCIF2_0),
1376     PINMUX_IPSR_MSEL(IP15_19_16,    MSIOF1_TXD_A,       SEL_MSIOF1_0),
1377     PINMUX_IPSR_MSEL(IP15_19_16,    TS_SCK0_A,      SEL_TSIF0_0),
1378     PINMUX_IPSR_MSEL(IP15_19_16,    STP_ISCLK_0_A,      SEL_SSP1_0_0),
1379     PINMUX_IPSR_MSEL(IP15_19_16,    RIF0_D1_A,      SEL_DRIF0_0),
1380     PINMUX_IPSR_MSEL(IP15_19_16,    RIF2_D0_A,      SEL_DRIF2_0),
1381
1382     PINMUX_IPSR_GPSR(IP15_23_20,    SSI_SCK4),
1383     PINMUX_IPSR_MSEL(IP15_23_20,    HRX2_A,         SEL_HSCIF2_0),
1384     PINMUX_IPSR_MSEL(IP15_23_20,    MSIOF1_SCK_A,       SEL_MSIOF1_0),
1385     PINMUX_IPSR_MSEL(IP15_23_20,    TS_SDAT0_A,     SEL_TSIF0_0),
1386     PINMUX_IPSR_MSEL(IP15_23_20,    STP_ISD_0_A,        SEL_SSP1_0_0),
1387     PINMUX_IPSR_MSEL(IP15_23_20,    RIF0_CLK_A,     SEL_DRIF0_0),
1388     PINMUX_IPSR_MSEL(IP15_23_20,    RIF2_CLK_A,     SEL_DRIF2_0),
1389
1390     PINMUX_IPSR_GPSR(IP15_27_24,    SSI_WS4),
1391     PINMUX_IPSR_MSEL(IP15_27_24,    HTX2_A,         SEL_HSCIF2_0),
1392     PINMUX_IPSR_MSEL(IP15_27_24,    MSIOF1_SYNC_A,      SEL_MSIOF1_0),
1393     PINMUX_IPSR_MSEL(IP15_27_24,    TS_SDEN0_A,     SEL_TSIF0_0),
1394     PINMUX_IPSR_MSEL(IP15_27_24,    STP_ISEN_0_A,       SEL_SSP1_0_0),
1395     PINMUX_IPSR_MSEL(IP15_27_24,    RIF0_SYNC_A,        SEL_DRIF0_0),
1396     PINMUX_IPSR_MSEL(IP15_27_24,    RIF2_SYNC_A,        SEL_DRIF2_0),
1397
1398     PINMUX_IPSR_GPSR(IP15_31_28,    SSI_SDATA4),
1399     PINMUX_IPSR_MSEL(IP15_31_28,    HSCK2_A,        SEL_HSCIF2_0),
1400     PINMUX_IPSR_MSEL(IP15_31_28,    MSIOF1_RXD_A,       SEL_MSIOF1_0),
1401     PINMUX_IPSR_MSEL(IP15_31_28,    TS_SPSYNC0_A,       SEL_TSIF0_0),
1402     PINMUX_IPSR_MSEL(IP15_31_28,    STP_ISSYNC_0_A,     SEL_SSP1_0_0),
1403     PINMUX_IPSR_MSEL(IP15_31_28,    RIF0_D0_A,      SEL_DRIF0_0),
1404     PINMUX_IPSR_MSEL(IP15_31_28,    RIF2_D1_A,      SEL_DRIF2_0),
1405
1406     /* IPSR16 */
1407     PINMUX_IPSR_GPSR(IP16_3_0,  SSI_SCK6),
1408     PINMUX_IPSR_MSEL(IP16_3_0,  SIM0_RST_D,     SEL_SIMCARD_3),
1409
1410     PINMUX_IPSR_GPSR(IP16_7_4,  SSI_WS6),
1411     PINMUX_IPSR_MSEL(IP16_7_4,  SIM0_D_D,       SEL_SIMCARD_3),
1412
1413     PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1414     PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D,     SEL_SIMCARD_3),
1415
1416     PINMUX_IPSR_GPSR(IP16_15_12,    SSI_SCK78),
1417     PINMUX_IPSR_MSEL(IP16_15_12,    HRX2_B,         SEL_HSCIF2_1),
1418     PINMUX_IPSR_MSEL(IP16_15_12,    MSIOF1_SCK_C,       SEL_MSIOF1_2),
1419     PINMUX_IPSR_MSEL(IP16_15_12,    TS_SCK1_A,      SEL_TSIF1_0),
1420     PINMUX_IPSR_MSEL(IP16_15_12,    STP_ISCLK_1_A,      SEL_SSP1_1_0),
1421     PINMUX_IPSR_MSEL(IP16_15_12,    RIF1_CLK_A,     SEL_DRIF1_0),
1422     PINMUX_IPSR_MSEL(IP16_15_12,    RIF3_CLK_A,     SEL_DRIF3_0),
1423
1424     PINMUX_IPSR_GPSR(IP16_19_16,    SSI_WS78),
1425     PINMUX_IPSR_MSEL(IP16_19_16,    HTX2_B,         SEL_HSCIF2_1),
1426     PINMUX_IPSR_MSEL(IP16_19_16,    MSIOF1_SYNC_C,      SEL_MSIOF1_2),
1427     PINMUX_IPSR_MSEL(IP16_19_16,    TS_SDAT1_A,     SEL_TSIF1_0),
1428     PINMUX_IPSR_MSEL(IP16_19_16,    STP_ISD_1_A,        SEL_SSP1_1_0),
1429     PINMUX_IPSR_MSEL(IP16_19_16,    RIF1_SYNC_A,        SEL_DRIF1_0),
1430     PINMUX_IPSR_MSEL(IP16_19_16,    RIF3_SYNC_A,        SEL_DRIF3_0),
1431
1432     PINMUX_IPSR_GPSR(IP16_23_20,    SSI_SDATA7),
1433     PINMUX_IPSR_MSEL(IP16_23_20,    HCTS2_N_B,      SEL_HSCIF2_1),
1434     PINMUX_IPSR_MSEL(IP16_23_20,    MSIOF1_RXD_C,       SEL_MSIOF1_2),
1435     PINMUX_IPSR_MSEL(IP16_23_20,    TS_SDEN1_A,     SEL_TSIF1_0),
1436     PINMUX_IPSR_MSEL(IP16_23_20,    STP_ISEN_1_A,       SEL_SSP1_1_0),
1437     PINMUX_IPSR_MSEL(IP16_23_20,    RIF1_D0_A,      SEL_DRIF1_0),
1438     PINMUX_IPSR_MSEL(IP16_23_20,    RIF3_D0_A,      SEL_DRIF3_0),
1439     PINMUX_IPSR_MSEL(IP16_23_20,    TCLK2_A,        SEL_TIMER_TMU2_0),
1440
1441     PINMUX_IPSR_GPSR(IP16_27_24,    SSI_SDATA8),
1442     PINMUX_IPSR_MSEL(IP16_27_24,    HRTS2_N_B,      SEL_HSCIF2_1),
1443     PINMUX_IPSR_MSEL(IP16_27_24,    MSIOF1_TXD_C,       SEL_MSIOF1_2),
1444     PINMUX_IPSR_MSEL(IP16_27_24,    TS_SPSYNC1_A,       SEL_TSIF1_0),
1445     PINMUX_IPSR_MSEL(IP16_27_24,    STP_ISSYNC_1_A,     SEL_SSP1_1_0),
1446     PINMUX_IPSR_MSEL(IP16_27_24,    RIF1_D1_A,      SEL_DRIF1_0),
1447     PINMUX_IPSR_MSEL(IP16_27_24,    RIF3_D1_A,      SEL_DRIF3_0),
1448
1449     PINMUX_IPSR_MSEL(IP16_31_28,    SSI_SDATA9_A,       SEL_SSI9_0),
1450     PINMUX_IPSR_MSEL(IP16_31_28,    HSCK2_B,        SEL_HSCIF2_1),
1451     PINMUX_IPSR_MSEL(IP16_31_28,    MSIOF1_SS1_C,       SEL_MSIOF1_2),
1452     PINMUX_IPSR_MSEL(IP16_31_28,    HSCK1_A,        SEL_HSCIF1_0),
1453     PINMUX_IPSR_MSEL(IP16_31_28,    SSI_WS1_B,      SEL_SSI1_1),
1454     PINMUX_IPSR_GPSR(IP16_31_28,    SCK1),
1455     PINMUX_IPSR_MSEL(IP16_31_28,    STP_IVCXO27_1_A,    SEL_SSP1_1_0),
1456     PINMUX_IPSR_MSEL(IP16_31_28,    SCK5_A,         SEL_SCIF5_0),
1457
1458     /* IPSR17 */
1459     PINMUX_IPSR_MSEL(IP17_3_0,  AUDIO_CLKA_A,       SEL_ADGA_0),
1460
1461     PINMUX_IPSR_MSEL(IP17_7_4,  AUDIO_CLKB_B,       SEL_ADGB_1),
1462     PINMUX_IPSR_MSEL(IP17_7_4,  SCIF_CLK_A,     SEL_SCIF_0),
1463     PINMUX_IPSR_MSEL(IP17_7_4,  STP_IVCXO27_1_D,    SEL_SSP1_1_3),
1464     PINMUX_IPSR_MSEL(IP17_7_4,  REMOCON_A,      SEL_REMOCON_0),
1465     PINMUX_IPSR_MSEL(IP17_7_4,  TCLK1_A,        SEL_TIMER_TMU_0),
1466
1467     PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1468     PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C,     SEL_SIMCARD_2),
1469     PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D,      SEL_TSIF1_3),
1470     PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D,      SEL_SSP1_1_3),
1471     PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B,       SEL_FM_1),
1472     PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B,     SEL_DRIF3_1),
1473     PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C,        SEL_HSCIF2_2),
1474
1475     PINMUX_IPSR_GPSR(IP17_15_12,    USB0_OVC),
1476     PINMUX_IPSR_MSEL(IP17_15_12,    SIM0_D_C,       SEL_SIMCARD_2),
1477     PINMUX_IPSR_MSEL(IP17_15_12,    TS_SDAT1_D,     SEL_TSIF1_3),
1478     PINMUX_IPSR_MSEL(IP17_15_12,    STP_ISD_1_D,        SEL_SSP1_1_3),
1479     PINMUX_IPSR_MSEL(IP17_15_12,    RIF3_SYNC_B,        SEL_DRIF3_1),
1480     PINMUX_IPSR_MSEL(IP17_15_12,    HRX2_C,         SEL_HSCIF2_2),
1481
1482     PINMUX_IPSR_GPSR(IP17_19_16,    USB1_PWEN),
1483     PINMUX_IPSR_MSEL(IP17_19_16,    SIM0_CLK_C,     SEL_SIMCARD_2),
1484     PINMUX_IPSR_MSEL(IP17_19_16,    SSI_SCK1_A,     SEL_SSI1_0),
1485     PINMUX_IPSR_MSEL(IP17_19_16,    TS_SCK0_E,      SEL_TSIF0_4),
1486     PINMUX_IPSR_MSEL(IP17_19_16,    STP_ISCLK_0_E,      SEL_SSP1_0_4),
1487     PINMUX_IPSR_MSEL(IP17_19_16,    FMCLK_B,        SEL_FM_1),
1488     PINMUX_IPSR_MSEL(IP17_19_16,    RIF2_CLK_B,     SEL_DRIF2_1),
1489     PINMUX_IPSR_MSEL(IP17_19_16,    SPEEDIN_A,      SEL_SPEED_PULSE_0),
1490     PINMUX_IPSR_MSEL(IP17_19_16,    HTX2_C,         SEL_HSCIF2_2),
1491
1492     PINMUX_IPSR_GPSR(IP17_23_20,    USB1_OVC),
1493     PINMUX_IPSR_MSEL(IP17_23_20,    MSIOF1_SS2_C,       SEL_MSIOF1_2),
1494     PINMUX_IPSR_MSEL(IP17_23_20,    SSI_WS1_A,      SEL_SSI1_0),
1495     PINMUX_IPSR_MSEL(IP17_23_20,    TS_SDAT0_E,     SEL_TSIF0_4),
1496     PINMUX_IPSR_MSEL(IP17_23_20,    STP_ISD_0_E,        SEL_SSP1_0_4),
1497     PINMUX_IPSR_MSEL(IP17_23_20,    FMIN_B,         SEL_FM_1),
1498     PINMUX_IPSR_MSEL(IP17_23_20,    RIF2_SYNC_B,        SEL_DRIF2_1),
1499     PINMUX_IPSR_MSEL(IP17_23_20,    REMOCON_B,      SEL_REMOCON_1),
1500     PINMUX_IPSR_MSEL(IP17_23_20,    HCTS2_N_C,      SEL_HSCIF2_2),
1501
1502     PINMUX_IPSR_GPSR(IP17_27_24,    USB30_PWEN),
1503     PINMUX_IPSR_GPSR(IP17_27_24,    AUDIO_CLKOUT_B),
1504     PINMUX_IPSR_MSEL(IP17_27_24,    SSI_SCK2_B,     SEL_SSI2_1),
1505     PINMUX_IPSR_MSEL(IP17_27_24,    TS_SDEN1_D,     SEL_TSIF1_3),
1506     PINMUX_IPSR_MSEL(IP17_27_24,    STP_ISEN_1_D,       SEL_SSP1_1_3),
1507     PINMUX_IPSR_MSEL(IP17_27_24,    STP_OPWM_0_E,       SEL_SSP1_0_4),
1508     PINMUX_IPSR_MSEL(IP17_27_24,    RIF3_D0_B,      SEL_DRIF3_1),
1509     PINMUX_IPSR_MSEL(IP17_27_24,    TCLK2_B,        SEL_TIMER_TMU2_1),
1510     PINMUX_IPSR_GPSR(IP17_27_24,    TPU0TO0),
1511     PINMUX_IPSR_MSEL(IP17_27_24,    BPFCLK_C,       SEL_FM_2),
1512     PINMUX_IPSR_MSEL(IP17_27_24,    HRTS2_N_C,      SEL_HSCIF2_2),
1513
1514     PINMUX_IPSR_GPSR(IP17_31_28,    USB30_OVC),
1515     PINMUX_IPSR_GPSR(IP17_31_28,    AUDIO_CLKOUT1_B),
1516     PINMUX_IPSR_MSEL(IP17_31_28,    SSI_WS2_B,      SEL_SSI2_1),
1517     PINMUX_IPSR_MSEL(IP17_31_28,    TS_SPSYNC1_D,       SEL_TSIF1_3),
1518     PINMUX_IPSR_MSEL(IP17_31_28,    STP_ISSYNC_1_D,     SEL_SSP1_1_3),
1519     PINMUX_IPSR_MSEL(IP17_31_28,    STP_IVCXO27_0_E,    SEL_SSP1_0_4),
1520     PINMUX_IPSR_MSEL(IP17_31_28,    RIF3_D1_B,      SEL_DRIF3_1),
1521     PINMUX_IPSR_GPSR(IP17_31_28,    FSO_TOE_N),
1522     PINMUX_IPSR_GPSR(IP17_31_28,    TPU0TO1),
1523
1524     /* IPSR18 */
1525     PINMUX_IPSR_GPSR(IP18_3_0,  GP6_30),
1526     PINMUX_IPSR_GPSR(IP18_3_0,  AUDIO_CLKOUT2_B),
1527     PINMUX_IPSR_MSEL(IP18_3_0,  SSI_SCK9_B,     SEL_SSI9_1),
1528     PINMUX_IPSR_MSEL(IP18_3_0,  TS_SDEN0_E,     SEL_TSIF0_4),
1529     PINMUX_IPSR_MSEL(IP18_3_0,  STP_ISEN_0_E,       SEL_SSP1_0_4),
1530     PINMUX_IPSR_MSEL(IP18_3_0,  RIF2_D0_B,      SEL_DRIF2_1),
1531     PINMUX_IPSR_GPSR(IP18_3_0,  TPU0TO2),
1532     PINMUX_IPSR_MSEL(IP18_3_0,  FMCLK_C,        SEL_FM_2),
1533     PINMUX_IPSR_MSEL(IP18_3_0,  FMCLK_D,        SEL_FM_3),
1534
1535     PINMUX_IPSR_GPSR(IP18_7_4,  GP6_31),
1536     PINMUX_IPSR_GPSR(IP18_7_4,  AUDIO_CLKOUT3_B),
1537     PINMUX_IPSR_MSEL(IP18_7_4,  SSI_WS9_B,      SEL_SSI9_1),
1538     PINMUX_IPSR_MSEL(IP18_7_4,  TS_SPSYNC0_E,       SEL_TSIF0_4),
1539     PINMUX_IPSR_MSEL(IP18_7_4,  STP_ISSYNC_0_E,     SEL_SSP1_0_4),
1540     PINMUX_IPSR_MSEL(IP18_7_4,  RIF2_D1_B,      SEL_DRIF2_1),
1541     PINMUX_IPSR_GPSR(IP18_7_4,  TPU0TO3),
1542     PINMUX_IPSR_MSEL(IP18_7_4,  FMIN_C,         SEL_FM_2),
1543     PINMUX_IPSR_MSEL(IP18_7_4,  FMIN_D,         SEL_FM_3),
1544
1545 /*
1546  * Static pins can not be muxed between different functions but
1547  * still need mark entries in the pinmux list. Add each static
1548  * pin to the list without an associated function. The sh-pfc
1549  * core will do the right thing and skip trying to mux the pin
1550  * while still applying configuration to it.
1551  */
1552 #define FM(x)   PINMUX_DATA(x##_MARK, 0),
1553     PINMUX_STATIC
1554 #undef FM
1555 };
1556
1557 /*
1558  * Pins not associated with a GPIO port.
1559  */
1560 enum {
1561     GP_ASSIGN_LAST(),
1562     NOGP_ALL(),
1563 };
1564
1565 static const struct sh_pfc_pin pinmux_pins[] = {
1566     PINMUX_GPIO_GP_ALL(),
1567     PINMUX_NOGP_ALL(),
1568 };
1569
1570 /* - AUDIO CLOCK ------------------------------------------------------------ */
1571 static const unsigned int audio_clk_a_a_pins[] = {
1572     /* CLK A */
1573     RCAR_GP_PIN(6, 22),
1574 };
1575 static const unsigned int audio_clk_a_a_mux[] = {
1576     AUDIO_CLKA_A_MARK,
1577 };
1578 static const unsigned int audio_clk_a_b_pins[] = {
1579     /* CLK A */
1580     RCAR_GP_PIN(5, 4),
1581 };
1582 static const unsigned int audio_clk_a_b_mux[] = {
1583     AUDIO_CLKA_B_MARK,
1584 };
1585 static const unsigned int audio_clk_a_c_pins[] = {
1586     /* CLK A */
1587     RCAR_GP_PIN(5, 19),
1588 };
1589 static const unsigned int audio_clk_a_c_mux[] = {
1590     AUDIO_CLKA_C_MARK,
1591 };
1592 static const unsigned int audio_clk_b_a_pins[] = {
1593     /* CLK B */
1594     RCAR_GP_PIN(5, 12),
1595 };
1596 static const unsigned int audio_clk_b_a_mux[] = {
1597     AUDIO_CLKB_A_MARK,
1598 };
1599 static const unsigned int audio_clk_b_b_pins[] = {
1600     /* CLK B */
1601     RCAR_GP_PIN(6, 23),
1602 };
1603 static const unsigned int audio_clk_b_b_mux[] = {
1604     AUDIO_CLKB_B_MARK,
1605 };
1606 static const unsigned int audio_clk_c_a_pins[] = {
1607     /* CLK C */
1608     RCAR_GP_PIN(5, 21),
1609 };
1610 static const unsigned int audio_clk_c_a_mux[] = {
1611     AUDIO_CLKC_A_MARK,
1612 };
1613 static const unsigned int audio_clk_c_b_pins[] = {
1614     /* CLK C */
1615     RCAR_GP_PIN(5, 0),
1616 };
1617 static const unsigned int audio_clk_c_b_mux[] = {
1618     AUDIO_CLKC_B_MARK,
1619 };
1620 static const unsigned int audio_clkout_a_pins[] = {
1621     /* CLKOUT */
1622     RCAR_GP_PIN(5, 18),
1623 };
1624 static const unsigned int audio_clkout_a_mux[] = {
1625     AUDIO_CLKOUT_A_MARK,
1626 };
1627 static const unsigned int audio_clkout_b_pins[] = {
1628     /* CLKOUT */
1629     RCAR_GP_PIN(6, 28),
1630 };
1631 static const unsigned int audio_clkout_b_mux[] = {
1632     AUDIO_CLKOUT_B_MARK,
1633 };
1634 static const unsigned int audio_clkout_c_pins[] = {
1635     /* CLKOUT */
1636     RCAR_GP_PIN(5, 3),
1637 };
1638 static const unsigned int audio_clkout_c_mux[] = {
1639     AUDIO_CLKOUT_C_MARK,
1640 };
1641 static const unsigned int audio_clkout_d_pins[] = {
1642     /* CLKOUT */
1643     RCAR_GP_PIN(5, 21),
1644 };
1645 static const unsigned int audio_clkout_d_mux[] = {
1646     AUDIO_CLKOUT_D_MARK,
1647 };
1648 static const unsigned int audio_clkout1_a_pins[] = {
1649     /* CLKOUT1 */
1650     RCAR_GP_PIN(5, 15),
1651 };
1652 static const unsigned int audio_clkout1_a_mux[] = {
1653     AUDIO_CLKOUT1_A_MARK,
1654 };
1655 static const unsigned int audio_clkout1_b_pins[] = {
1656     /* CLKOUT1 */
1657     RCAR_GP_PIN(6, 29),
1658 };
1659 static const unsigned int audio_clkout1_b_mux[] = {
1660     AUDIO_CLKOUT1_B_MARK,
1661 };
1662 static const unsigned int audio_clkout2_a_pins[] = {
1663     /* CLKOUT2 */
1664     RCAR_GP_PIN(5, 16),
1665 };
1666 static const unsigned int audio_clkout2_a_mux[] = {
1667     AUDIO_CLKOUT2_A_MARK,
1668 };
1669 static const unsigned int audio_clkout2_b_pins[] = {
1670     /* CLKOUT2 */
1671     RCAR_GP_PIN(6, 30),
1672 };
1673 static const unsigned int audio_clkout2_b_mux[] = {
1674     AUDIO_CLKOUT2_B_MARK,
1675 };
1676
1677 static const unsigned int audio_clkout3_a_pins[] = {
1678     /* CLKOUT3 */
1679     RCAR_GP_PIN(5, 19),
1680 };
1681 static const unsigned int audio_clkout3_a_mux[] = {
1682     AUDIO_CLKOUT3_A_MARK,
1683 };
1684 static const unsigned int audio_clkout3_b_pins[] = {
1685     /* CLKOUT3 */
1686     RCAR_GP_PIN(6, 31),
1687 };
1688 static const unsigned int audio_clkout3_b_mux[] = {
1689     AUDIO_CLKOUT3_B_MARK,
1690 };
1691
1692 /* - EtherAVB --------------------------------------------------------------- */
1693 static const unsigned int avb_link_pins[] = {
1694     /* AVB_LINK */
1695     RCAR_GP_PIN(2, 12),
1696 };
1697 static const unsigned int avb_link_mux[] = {
1698     AVB_LINK_MARK,
1699 };
1700 static const unsigned int avb_magic_pins[] = {
1701     /* AVB_MAGIC_ */
1702     RCAR_GP_PIN(2, 10),
1703 };
1704 static const unsigned int avb_magic_mux[] = {
1705     AVB_MAGIC_MARK,
1706 };
1707 static const unsigned int avb_phy_int_pins[] = {
1708     /* AVB_PHY_INT */
1709     RCAR_GP_PIN(2, 11),
1710 };
1711 static const unsigned int avb_phy_int_mux[] = {
1712     AVB_PHY_INT_MARK,
1713 };
1714 static const unsigned int avb_mdio_pins[] = {
1715     /* AVB_MDC, AVB_MDIO */
1716     RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
1717 };
1718 static const unsigned int avb_mdio_mux[] = {
1719     AVB_MDC_MARK, AVB_MDIO_MARK,
1720 };
1721 static const unsigned int avb_mii_pins[] = {
1722     /*
1723      * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1724      * AVB_TD1, AVB_TD2, AVB_TD3,
1725      * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1726      * AVB_RD1, AVB_RD2, AVB_RD3,
1727      * AVB_TXCREFCLK
1728      */
1729     PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
1730     PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
1731     PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
1732     PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
1733     PIN_AVB_TXCREFCLK,
1734 };
1735 static const unsigned int avb_mii_mux[] = {
1736     AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1737     AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1738     AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1739     AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1740     AVB_TXCREFCLK_MARK,
1741 };
1742 static const unsigned int avb_avtp_pps_pins[] = {
1743     /* AVB_AVTP_PPS */
1744     RCAR_GP_PIN(2, 6),
1745 };
1746 static const unsigned int avb_avtp_pps_mux[] = {
1747     AVB_AVTP_PPS_MARK,
1748 };
1749 static const unsigned int avb_avtp_match_a_pins[] = {
1750     /* AVB_AVTP_MATCH_A */
1751     RCAR_GP_PIN(2, 13),
1752 };
1753 static const unsigned int avb_avtp_match_a_mux[] = {
1754     AVB_AVTP_MATCH_A_MARK,
1755 };
1756 static const unsigned int avb_avtp_capture_a_pins[] = {
1757     /* AVB_AVTP_CAPTURE_A */
1758     RCAR_GP_PIN(2, 14),
1759 };
1760 static const unsigned int avb_avtp_capture_a_mux[] = {
1761     AVB_AVTP_CAPTURE_A_MARK,
1762 };
1763 static const unsigned int avb_avtp_match_b_pins[] = {
1764     /*  AVB_AVTP_MATCH_B */
1765     RCAR_GP_PIN(1, 8),
1766 };
1767 static const unsigned int avb_avtp_match_b_mux[] = {
1768     AVB_AVTP_MATCH_B_MARK,
1769 };
1770 static const unsigned int avb_avtp_capture_b_pins[] = {
1771     /* AVB_AVTP_CAPTURE_B */
1772     RCAR_GP_PIN(1, 11),
1773 };
1774 static const unsigned int avb_avtp_capture_b_mux[] = {
1775     AVB_AVTP_CAPTURE_B_MARK,
1776 };
1777
1778 /* - CAN ------------------------------------------------------------------ */
1779 static const unsigned int can0_data_a_pins[] = {
1780     /* TX, RX */
1781     RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1782 };
1783 static const unsigned int can0_data_a_mux[] = {
1784     CAN0_TX_A_MARK,     CAN0_RX_A_MARK,
1785 };
1786 static const unsigned int can0_data_b_pins[] = {
1787     /* TX, RX */
1788     RCAR_GP_PIN(2, 0),  RCAR_GP_PIN(2, 1),
1789 };
1790 static const unsigned int can0_data_b_mux[] = {
1791     CAN0_TX_B_MARK,     CAN0_RX_B_MARK,
1792 };
1793 static const unsigned int can1_data_pins[] = {
1794     /* TX, RX */
1795     RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1796 };
1797 static const unsigned int can1_data_mux[] = {
1798     CAN1_TX_MARK,       CAN1_RX_MARK,
1799 };
1800
1801 /* - CAN Clock -------------------------------------------------------------- */
1802 static const unsigned int can_clk_pins[] = {
1803     /* CLK */
1804     RCAR_GP_PIN(1, 25),
1805 };
1806 static const unsigned int can_clk_mux[] = {
1807     CAN_CLK_MARK,
1808 };
1809
1810 /* - CAN FD --------------------------------------------------------------- */
1811 static const unsigned int canfd0_data_a_pins[] = {
1812     /* TX, RX */
1813     RCAR_GP_PIN(1, 23),     RCAR_GP_PIN(1, 24),
1814 };
1815 static const unsigned int canfd0_data_a_mux[] = {
1816     CANFD0_TX_A_MARK,       CANFD0_RX_A_MARK,
1817 };
1818 static const unsigned int canfd0_data_b_pins[] = {
1819     /* TX, RX */
1820     RCAR_GP_PIN(2, 0),      RCAR_GP_PIN(2, 1),
1821 };
1822 static const unsigned int canfd0_data_b_mux[] = {
1823     CANFD0_TX_B_MARK,       CANFD0_RX_B_MARK,
1824 };
1825 static const unsigned int canfd1_data_pins[] = {
1826     /* TX, RX */
1827     RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 26),
1828 };
1829 static const unsigned int canfd1_data_mux[] = {
1830     CANFD1_TX_MARK,         CANFD1_RX_MARK,
1831 };
1832
1833 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
1834 /* - DRIF0 --------------------------------------------------------------- */
1835 static const unsigned int drif0_ctrl_a_pins[] = {
1836     /* CLK, SYNC */
1837     RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1838 };
1839 static const unsigned int drif0_ctrl_a_mux[] = {
1840     RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1841 };
1842 static const unsigned int drif0_data0_a_pins[] = {
1843     /* D0 */
1844     RCAR_GP_PIN(6, 10),
1845 };
1846 static const unsigned int drif0_data0_a_mux[] = {
1847     RIF0_D0_A_MARK,
1848 };
1849 static const unsigned int drif0_data1_a_pins[] = {
1850     /* D1 */
1851     RCAR_GP_PIN(6, 7),
1852 };
1853 static const unsigned int drif0_data1_a_mux[] = {
1854     RIF0_D1_A_MARK,
1855 };
1856 static const unsigned int drif0_ctrl_b_pins[] = {
1857     /* CLK, SYNC */
1858     RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1859 };
1860 static const unsigned int drif0_ctrl_b_mux[] = {
1861     RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1862 };
1863 static const unsigned int drif0_data0_b_pins[] = {
1864     /* D0 */
1865     RCAR_GP_PIN(5, 1),
1866 };
1867 static const unsigned int drif0_data0_b_mux[] = {
1868     RIF0_D0_B_MARK,
1869 };
1870 static const unsigned int drif0_data1_b_pins[] = {
1871     /* D1 */
1872     RCAR_GP_PIN(5, 2),
1873 };
1874 static const unsigned int drif0_data1_b_mux[] = {
1875     RIF0_D1_B_MARK,
1876 };
1877 static const unsigned int drif0_ctrl_c_pins[] = {
1878     /* CLK, SYNC */
1879     RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1880 };
1881 static const unsigned int drif0_ctrl_c_mux[] = {
1882     RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1883 };
1884 static const unsigned int drif0_data0_c_pins[] = {
1885     /* D0 */
1886     RCAR_GP_PIN(5, 13),
1887 };
1888 static const unsigned int drif0_data0_c_mux[] = {
1889     RIF0_D0_C_MARK,
1890 };
1891 static const unsigned int drif0_data1_c_pins[] = {
1892     /* D1 */
1893     RCAR_GP_PIN(5, 14),
1894 };
1895 static const unsigned int drif0_data1_c_mux[] = {
1896     RIF0_D1_C_MARK,
1897 };
1898 /* - DRIF1 --------------------------------------------------------------- */
1899 static const unsigned int drif1_ctrl_a_pins[] = {
1900     /* CLK, SYNC */
1901     RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1902 };
1903 static const unsigned int drif1_ctrl_a_mux[] = {
1904     RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1905 };
1906 static const unsigned int drif1_data0_a_pins[] = {
1907     /* D0 */
1908     RCAR_GP_PIN(6, 19),
1909 };
1910 static const unsigned int drif1_data0_a_mux[] = {
1911     RIF1_D0_A_MARK,
1912 };
1913 static const unsigned int drif1_data1_a_pins[] = {
1914     /* D1 */
1915     RCAR_GP_PIN(6, 20),
1916 };
1917 static const unsigned int drif1_data1_a_mux[] = {
1918     RIF1_D1_A_MARK,
1919 };
1920 static const unsigned int drif1_ctrl_b_pins[] = {
1921     /* CLK, SYNC */
1922     RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1923 };
1924 static const unsigned int drif1_ctrl_b_mux[] = {
1925     RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1926 };
1927 static const unsigned int drif1_data0_b_pins[] = {
1928     /* D0 */
1929     RCAR_GP_PIN(5, 7),
1930 };
1931 static const unsigned int drif1_data0_b_mux[] = {
1932     RIF1_D0_B_MARK,
1933 };
1934 static const unsigned int drif1_data1_b_pins[] = {
1935     /* D1 */
1936     RCAR_GP_PIN(5, 8),
1937 };
1938 static const unsigned int drif1_data1_b_mux[] = {
1939     RIF1_D1_B_MARK,
1940 };
1941 static const unsigned int drif1_ctrl_c_pins[] = {
1942     /* CLK, SYNC */
1943     RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1944 };
1945 static const unsigned int drif1_ctrl_c_mux[] = {
1946     RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1947 };
1948 static const unsigned int drif1_data0_c_pins[] = {
1949     /* D0 */
1950     RCAR_GP_PIN(5, 6),
1951 };
1952 static const unsigned int drif1_data0_c_mux[] = {
1953     RIF1_D0_C_MARK,
1954 };
1955 static const unsigned int drif1_data1_c_pins[] = {
1956     /* D1 */
1957     RCAR_GP_PIN(5, 10),
1958 };
1959 static const unsigned int drif1_data1_c_mux[] = {
1960     RIF1_D1_C_MARK,
1961 };
1962 /* - DRIF2 --------------------------------------------------------------- */
1963 static const unsigned int drif2_ctrl_a_pins[] = {
1964     /* CLK, SYNC */
1965     RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1966 };
1967 static const unsigned int drif2_ctrl_a_mux[] = {
1968     RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1969 };
1970 static const unsigned int drif2_data0_a_pins[] = {
1971     /* D0 */
1972     RCAR_GP_PIN(6, 7),
1973 };
1974 static const unsigned int drif2_data0_a_mux[] = {
1975     RIF2_D0_A_MARK,
1976 };
1977 static const unsigned int drif2_data1_a_pins[] = {
1978     /* D1 */
1979     RCAR_GP_PIN(6, 10),
1980 };
1981 static const unsigned int drif2_data1_a_mux[] = {
1982     RIF2_D1_A_MARK,
1983 };
1984 static const unsigned int drif2_ctrl_b_pins[] = {
1985     /* CLK, SYNC */
1986     RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1987 };
1988 static const unsigned int drif2_ctrl_b_mux[] = {
1989     RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1990 };
1991 static const unsigned int drif2_data0_b_pins[] = {
1992     /* D0 */
1993     RCAR_GP_PIN(6, 30),
1994 };
1995 static const unsigned int drif2_data0_b_mux[] = {
1996     RIF2_D0_B_MARK,
1997 };
1998 static const unsigned int drif2_data1_b_pins[] = {
1999     /* D1 */
2000     RCAR_GP_PIN(6, 31),
2001 };
2002 static const unsigned int drif2_data1_b_mux[] = {
2003     RIF2_D1_B_MARK,
2004 };
2005 /* - DRIF3 --------------------------------------------------------------- */
2006 static const unsigned int drif3_ctrl_a_pins[] = {
2007     /* CLK, SYNC */
2008     RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2009 };
2010 static const unsigned int drif3_ctrl_a_mux[] = {
2011     RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2012 };
2013 static const unsigned int drif3_data0_a_pins[] = {
2014     /* D0 */
2015     RCAR_GP_PIN(6, 19),
2016 };
2017 static const unsigned int drif3_data0_a_mux[] = {
2018     RIF3_D0_A_MARK,
2019 };
2020 static const unsigned int drif3_data1_a_pins[] = {
2021     /* D1 */
2022     RCAR_GP_PIN(6, 20),
2023 };
2024 static const unsigned int drif3_data1_a_mux[] = {
2025     RIF3_D1_A_MARK,
2026 };
2027 static const unsigned int drif3_ctrl_b_pins[] = {
2028     /* CLK, SYNC */
2029     RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2030 };
2031 static const unsigned int drif3_ctrl_b_mux[] = {
2032     RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2033 };
2034 static const unsigned int drif3_data0_b_pins[] = {
2035     /* D0 */
2036     RCAR_GP_PIN(6, 28),
2037 };
2038 static const unsigned int drif3_data0_b_mux[] = {
2039     RIF3_D0_B_MARK,
2040 };
2041 static const unsigned int drif3_data1_b_pins[] = {
2042     /* D1 */
2043     RCAR_GP_PIN(6, 29),
2044 };
2045 static const unsigned int drif3_data1_b_mux[] = {
2046     RIF3_D1_B_MARK,
2047 };
2048 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
2049
2050 /* - DU --------------------------------------------------------------------- */
2051 static const unsigned int du_rgb666_pins[] = {
2052     /* R[7:2], G[7:2], B[7:2] */
2053     RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2054     RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2055     RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2056     RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2057     RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2058     RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2059 };
2060 static const unsigned int du_rgb666_mux[] = {
2061     DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2062     DU_DR3_MARK, DU_DR2_MARK,
2063     DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2064     DU_DG3_MARK, DU_DG2_MARK,
2065     DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2066     DU_DB3_MARK, DU_DB2_MARK,
2067 };
2068 static const unsigned int du_rgb888_pins[] = {
2069     /* R[7:0], G[7:0], B[7:0] */
2070     RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2071     RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2072     RCAR_GP_PIN(0, 9),  RCAR_GP_PIN(0, 8),
2073     RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2074     RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2075     RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2076     RCAR_GP_PIN(1, 7),  RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),
2077     RCAR_GP_PIN(1, 4),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),
2078     RCAR_GP_PIN(1, 1),  RCAR_GP_PIN(1, 0),
2079 };
2080 static const unsigned int du_rgb888_mux[] = {
2081     DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2082     DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2083     DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2084     DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2085     DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2086     DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2087 };
2088 static const unsigned int du_clk_out_0_pins[] = {
2089     /* CLKOUT */
2090     RCAR_GP_PIN(1, 27),
2091 };
2092 static const unsigned int du_clk_out_0_mux[] = {
2093     DU_DOTCLKOUT0_MARK
2094 };
2095 static const unsigned int du_clk_out_1_pins[] = {
2096     /* CLKOUT */
2097     RCAR_GP_PIN(2, 3),
2098 };
2099 static const unsigned int du_clk_out_1_mux[] = {
2100     DU_DOTCLKOUT1_MARK
2101 };
2102 static const unsigned int du_sync_pins[] = {
2103     /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2104     RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2105 };
2106 static const unsigned int du_sync_mux[] = {
2107     DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2108 };
2109 static const unsigned int du_oddf_pins[] = {
2110     /* EXDISP/EXODDF/EXCDE */
2111     RCAR_GP_PIN(2, 2),
2112 };
2113 static const unsigned int du_oddf_mux[] = {
2114     DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2115 };
2116 static const unsigned int du_cde_pins[] = {
2117     /* CDE */
2118     RCAR_GP_PIN(2, 0),
2119 };
2120 static const unsigned int du_cde_mux[] = {
2121     DU_CDE_MARK,
2122 };
2123 static const unsigned int du_disp_pins[] = {
2124     /* DISP */
2125     RCAR_GP_PIN(2, 1),
2126 };
2127 static const unsigned int du_disp_mux[] = {
2128     DU_DISP_MARK,
2129 };
2130
2131 /* - HSCIF0 ----------------------------------------------------------------- */
2132 static const unsigned int hscif0_data_pins[] = {
2133     /* RX, TX */
2134     RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2135 };
2136 static const unsigned int hscif0_data_mux[] = {
2137     HRX0_MARK, HTX0_MARK,
2138 };
2139 static const unsigned int hscif0_clk_pins[] = {
2140     /* SCK */
2141     RCAR_GP_PIN(5, 12),
2142 };
2143 static const unsigned int hscif0_clk_mux[] = {
2144     HSCK0_MARK,
2145 };
2146 static const unsigned int hscif0_ctrl_pins[] = {
2147     /* RTS, CTS */
2148     RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2149 };
2150 static const unsigned int hscif0_ctrl_mux[] = {
2151     HRTS0_N_MARK, HCTS0_N_MARK,
2152 };
2153 /* - HSCIF1 ----------------------------------------------------------------- */
2154 static const unsigned int hscif1_data_a_pins[] = {
2155     /* RX, TX */
2156     RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2157 };
2158 static const unsigned int hscif1_data_a_mux[] = {
2159     HRX1_A_MARK, HTX1_A_MARK,
2160 };
2161 static const unsigned int hscif1_clk_a_pins[] = {
2162     /* SCK */
2163     RCAR_GP_PIN(6, 21),
2164 };
2165 static const unsigned int hscif1_clk_a_mux[] = {
2166     HSCK1_A_MARK,
2167 };
2168 static const unsigned int hscif1_ctrl_a_pins[] = {
2169     /* RTS, CTS */
2170     RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2171 };
2172 static const unsigned int hscif1_ctrl_a_mux[] = {
2173     HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2174 };
2175
2176 static const unsigned int hscif1_data_b_pins[] = {
2177     /* RX, TX */
2178     RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2179 };
2180 static const unsigned int hscif1_data_b_mux[] = {
2181     HRX1_B_MARK, HTX1_B_MARK,
2182 };
2183 static const unsigned int hscif1_clk_b_pins[] = {
2184     /* SCK */
2185     RCAR_GP_PIN(5, 0),
2186 };
2187 static const unsigned int hscif1_clk_b_mux[] = {
2188     HSCK1_B_MARK,
2189 };
2190 static const unsigned int hscif1_ctrl_b_pins[] = {
2191     /* RTS, CTS */
2192     RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2193 };
2194 static const unsigned int hscif1_ctrl_b_mux[] = {
2195     HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2196 };
2197 /* - HSCIF2 ----------------------------------------------------------------- */
2198 static const unsigned int hscif2_data_a_pins[] = {
2199     /* RX, TX */
2200     RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2201 };
2202 static const unsigned int hscif2_data_a_mux[] = {
2203     HRX2_A_MARK, HTX2_A_MARK,
2204 };
2205 static const unsigned int hscif2_clk_a_pins[] = {
2206     /* SCK */
2207     RCAR_GP_PIN(6, 10),
2208 };
2209 static const unsigned int hscif2_clk_a_mux[] = {
2210     HSCK2_A_MARK,
2211 };
2212 static const unsigned int hscif2_ctrl_a_pins[] = {
2213     /* RTS, CTS */
2214     RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2215 };
2216 static const unsigned int hscif2_ctrl_a_mux[] = {
2217     HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2218 };
2219
2220 static const unsigned int hscif2_data_b_pins[] = {
2221     /* RX, TX */
2222     RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2223 };
2224 static const unsigned int hscif2_data_b_mux[] = {
2225     HRX2_B_MARK, HTX2_B_MARK,
2226 };
2227 static const unsigned int hscif2_clk_b_pins[] = {
2228     /* SCK */
2229     RCAR_GP_PIN(6, 21),
2230 };
2231 static const unsigned int hscif2_clk_b_mux[] = {
2232     HSCK2_B_MARK,
2233 };
2234 static const unsigned int hscif2_ctrl_b_pins[] = {
2235     /* RTS, CTS */
2236     RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2237 };
2238 static const unsigned int hscif2_ctrl_b_mux[] = {
2239     HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2240 };
2241
2242 static const unsigned int hscif2_data_c_pins[] = {
2243     /* RX, TX */
2244     RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2245 };
2246 static const unsigned int hscif2_data_c_mux[] = {
2247     HRX2_C_MARK, HTX2_C_MARK,
2248 };
2249 static const unsigned int hscif2_clk_c_pins[] = {
2250     /* SCK */
2251     RCAR_GP_PIN(6, 24),
2252 };
2253 static const unsigned int hscif2_clk_c_mux[] = {
2254     HSCK2_C_MARK,
2255 };
2256 static const unsigned int hscif2_ctrl_c_pins[] = {
2257     /* RTS, CTS */
2258     RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2259 };
2260 static const unsigned int hscif2_ctrl_c_mux[] = {
2261     HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2262 };
2263 /* - HSCIF3 ----------------------------------------------------------------- */
2264 static const unsigned int hscif3_data_a_pins[] = {
2265     /* RX, TX */
2266     RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2267 };
2268 static const unsigned int hscif3_data_a_mux[] = {
2269     HRX3_A_MARK, HTX3_A_MARK,
2270 };
2271 static const unsigned int hscif3_clk_pins[] = {
2272     /* SCK */
2273     RCAR_GP_PIN(1, 22),
2274 };
2275 static const unsigned int hscif3_clk_mux[] = {
2276     HSCK3_MARK,
2277 };
2278 static const unsigned int hscif3_ctrl_pins[] = {
2279     /* RTS, CTS */
2280     RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2281 };
2282 static const unsigned int hscif3_ctrl_mux[] = {
2283     HRTS3_N_MARK, HCTS3_N_MARK,
2284 };
2285
2286 static const unsigned int hscif3_data_b_pins[] = {
2287     /* RX, TX */
2288     RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2289 };
2290 static const unsigned int hscif3_data_b_mux[] = {
2291     HRX3_B_MARK, HTX3_B_MARK,
2292 };
2293 static const unsigned int hscif3_data_c_pins[] = {
2294     /* RX, TX */
2295     RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2296 };
2297 static const unsigned int hscif3_data_c_mux[] = {
2298     HRX3_C_MARK, HTX3_C_MARK,
2299 };
2300 static const unsigned int hscif3_data_d_pins[] = {
2301     /* RX, TX */
2302     RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2303 };
2304 static const unsigned int hscif3_data_d_mux[] = {
2305     HRX3_D_MARK, HTX3_D_MARK,
2306 };
2307 /* - HSCIF4 ----------------------------------------------------------------- */
2308 static const unsigned int hscif4_data_a_pins[] = {
2309     /* RX, TX */
2310     RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2311 };
2312 static const unsigned int hscif4_data_a_mux[] = {
2313     HRX4_A_MARK, HTX4_A_MARK,
2314 };
2315 static const unsigned int hscif4_clk_pins[] = {
2316     /* SCK */
2317     RCAR_GP_PIN(1, 11),
2318 };
2319 static const unsigned int hscif4_clk_mux[] = {
2320     HSCK4_MARK,
2321 };
2322 static const unsigned int hscif4_ctrl_pins[] = {
2323     /* RTS, CTS */
2324     RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2325 };
2326 static const unsigned int hscif4_ctrl_mux[] = {
2327     HRTS4_N_MARK, HCTS4_N_MARK,
2328 };
2329
2330 static const unsigned int hscif4_data_b_pins[] = {
2331     /* RX, TX */
2332     RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2333 };
2334 static const unsigned int hscif4_data_b_mux[] = {
2335     HRX4_B_MARK, HTX4_B_MARK,
2336 };
2337
2338 /* - I2C -------------------------------------------------------------------- */
2339 static const unsigned int i2c0_pins[] = {
2340     /* SCL, SDA */
2341     RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2342 };
2343
2344 static const unsigned int i2c0_mux[] = {
2345     SCL0_MARK, SDA0_MARK,
2346 };
2347
2348 static const unsigned int i2c1_a_pins[] = {
2349     /* SDA, SCL */
2350     RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2351 };
2352 static const unsigned int i2c1_a_mux[] = {
2353     SDA1_A_MARK, SCL1_A_MARK,
2354 };
2355 static const unsigned int i2c1_b_pins[] = {
2356     /* SDA, SCL */
2357     RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2358 };
2359 static const unsigned int i2c1_b_mux[] = {
2360     SDA1_B_MARK, SCL1_B_MARK,
2361 };
2362 static const unsigned int i2c2_a_pins[] = {
2363     /* SDA, SCL */
2364     RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2365 };
2366 static const unsigned int i2c2_a_mux[] = {
2367     SDA2_A_MARK, SCL2_A_MARK,
2368 };
2369 static const unsigned int i2c2_b_pins[] = {
2370     /* SDA, SCL */
2371     RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2372 };
2373 static const unsigned int i2c2_b_mux[] = {
2374     SDA2_B_MARK, SCL2_B_MARK,
2375 };
2376
2377 static const unsigned int i2c3_pins[] = {
2378     /* SCL, SDA */
2379     RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2380 };
2381
2382 static const unsigned int i2c3_mux[] = {
2383     SCL3_MARK, SDA3_MARK,
2384 };
2385
2386 static const unsigned int i2c5_pins[] = {
2387     /* SCL, SDA */
2388     RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2389 };
2390
2391 static const unsigned int i2c5_mux[] = {
2392     SCL5_MARK, SDA5_MARK,
2393 };
2394
2395 static const unsigned int i2c6_a_pins[] = {
2396     /* SDA, SCL */
2397     RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2398 };
2399 static const unsigned int i2c6_a_mux[] = {
2400     SDA6_A_MARK, SCL6_A_MARK,
2401 };
2402 static const unsigned int i2c6_b_pins[] = {
2403     /* SDA, SCL */
2404     RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2405 };
2406 static const unsigned int i2c6_b_mux[] = {
2407     SDA6_B_MARK, SCL6_B_MARK,
2408 };
2409 static const unsigned int i2c6_c_pins[] = {
2410     /* SDA, SCL */
2411     RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2412 };
2413 static const unsigned int i2c6_c_mux[] = {
2414     SDA6_C_MARK, SCL6_C_MARK,
2415 };
2416
2417 /* - INTC-EX ---------------------------------------------------------------- */
2418 static const unsigned int intc_ex_irq0_pins[] = {
2419     /* IRQ0 */
2420     RCAR_GP_PIN(2, 0),
2421 };
2422 static const unsigned int intc_ex_irq0_mux[] = {
2423     IRQ0_MARK,
2424 };
2425 static const unsigned int intc_ex_irq1_pins[] = {
2426     /* IRQ1 */
2427     RCAR_GP_PIN(2, 1),
2428 };
2429 static const unsigned int intc_ex_irq1_mux[] = {
2430     IRQ1_MARK,
2431 };
2432 static const unsigned int intc_ex_irq2_pins[] = {
2433     /* IRQ2 */
2434     RCAR_GP_PIN(2, 2),
2435 };
2436 static const unsigned int intc_ex_irq2_mux[] = {
2437     IRQ2_MARK,
2438 };
2439 static const unsigned int intc_ex_irq3_pins[] = {
2440     /* IRQ3 */
2441     RCAR_GP_PIN(2, 3),
2442 };
2443 static const unsigned int intc_ex_irq3_mux[] = {
2444     IRQ3_MARK,
2445 };
2446 static const unsigned int intc_ex_irq4_pins[] = {
2447     /* IRQ4 */
2448     RCAR_GP_PIN(2, 4),
2449 };
2450 static const unsigned int intc_ex_irq4_mux[] = {
2451     IRQ4_MARK,
2452 };
2453 static const unsigned int intc_ex_irq5_pins[] = {
2454     /* IRQ5 */
2455     RCAR_GP_PIN(2, 5),
2456 };
2457 static const unsigned int intc_ex_irq5_mux[] = {
2458     IRQ5_MARK,
2459 };
2460
2461 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
2462 /* - MLB+ ------------------------------------------------------------------- */
2463 static const unsigned int mlb_3pin_pins[] = {
2464     RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2465 };
2466 static const unsigned int mlb_3pin_mux[] = {
2467     MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2468 };
2469 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
2470
2471 /* - MSIOF0 ----------------------------------------------------------------- */
2472 static const unsigned int msiof0_clk_pins[] = {
2473     /* SCK */
2474     RCAR_GP_PIN(5, 17),
2475 };
2476 static const unsigned int msiof0_clk_mux[] = {
2477     MSIOF0_SCK_MARK,
2478 };
2479 static const unsigned int msiof0_sync_pins[] = {
2480     /* SYNC */
2481     RCAR_GP_PIN(5, 18),
2482 };
2483 static const unsigned int msiof0_sync_mux[] = {
2484     MSIOF0_SYNC_MARK,
2485 };
2486 static const unsigned int msiof0_ss1_pins[] = {
2487     /* SS1 */
2488     RCAR_GP_PIN(5, 19),
2489 };
2490 static const unsigned int msiof0_ss1_mux[] = {
2491     MSIOF0_SS1_MARK,
2492 };
2493 static const unsigned int msiof0_ss2_pins[] = {
2494     /* SS2 */
2495     RCAR_GP_PIN(5, 21),
2496 };
2497 static const unsigned int msiof0_ss2_mux[] = {
2498     MSIOF0_SS2_MARK,
2499 };
2500 static const unsigned int msiof0_txd_pins[] = {
2501     /* TXD */
2502     RCAR_GP_PIN(5, 20),
2503 };
2504 static const unsigned int msiof0_txd_mux[] = {
2505     MSIOF0_TXD_MARK,
2506 };
2507 static const unsigned int msiof0_rxd_pins[] = {
2508     /* RXD */
2509     RCAR_GP_PIN(5, 22),
2510 };
2511 static const unsigned int msiof0_rxd_mux[] = {
2512     MSIOF0_RXD_MARK,
2513 };
2514 /* - MSIOF1 ----------------------------------------------------------------- */
2515 static const unsigned int msiof1_clk_a_pins[] = {
2516     /* SCK */
2517     RCAR_GP_PIN(6, 8),
2518 };
2519 static const unsigned int msiof1_clk_a_mux[] = {
2520     MSIOF1_SCK_A_MARK,
2521 };
2522 static const unsigned int msiof1_sync_a_pins[] = {
2523     /* SYNC */
2524     RCAR_GP_PIN(6, 9),
2525 };
2526 static const unsigned int msiof1_sync_a_mux[] = {
2527     MSIOF1_SYNC_A_MARK,
2528 };
2529 static const unsigned int msiof1_ss1_a_pins[] = {
2530     /* SS1 */
2531     RCAR_GP_PIN(6, 5),
2532 };
2533 static const unsigned int msiof1_ss1_a_mux[] = {
2534     MSIOF1_SS1_A_MARK,
2535 };
2536 static const unsigned int msiof1_ss2_a_pins[] = {
2537     /* SS2 */
2538     RCAR_GP_PIN(6, 6),
2539 };
2540 static const unsigned int msiof1_ss2_a_mux[] = {
2541     MSIOF1_SS2_A_MARK,
2542 };
2543 static const unsigned int msiof1_txd_a_pins[] = {
2544     /* TXD */
2545     RCAR_GP_PIN(6, 7),
2546 };
2547 static const unsigned int msiof1_txd_a_mux[] = {
2548     MSIOF1_TXD_A_MARK,
2549 };
2550 static const unsigned int msiof1_rxd_a_pins[] = {
2551     /* RXD */
2552     RCAR_GP_PIN(6, 10),
2553 };
2554 static const unsigned int msiof1_rxd_a_mux[] = {
2555     MSIOF1_RXD_A_MARK,
2556 };
2557 static const unsigned int msiof1_clk_b_pins[] = {
2558     /* SCK */
2559     RCAR_GP_PIN(5, 9),
2560 };
2561 static const unsigned int msiof1_clk_b_mux[] = {
2562     MSIOF1_SCK_B_MARK,
2563 };
2564 static const unsigned int msiof1_sync_b_pins[] = {
2565     /* SYNC */
2566     RCAR_GP_PIN(5, 3),
2567 };
2568 static const unsigned int msiof1_sync_b_mux[] = {
2569     MSIOF1_SYNC_B_MARK,
2570 };
2571 static const unsigned int msiof1_ss1_b_pins[] = {
2572     /* SS1 */
2573     RCAR_GP_PIN(5, 4),
2574 };
2575 static const unsigned int msiof1_ss1_b_mux[] = {
2576     MSIOF1_SS1_B_MARK,
2577 };
2578 static const unsigned int msiof1_ss2_b_pins[] = {
2579     /* SS2 */
2580     RCAR_GP_PIN(5, 0),
2581 };
2582 static const unsigned int msiof1_ss2_b_mux[] = {
2583     MSIOF1_SS2_B_MARK,
2584 };
2585 static const unsigned int msiof1_txd_b_pins[] = {
2586     /* TXD */
2587     RCAR_GP_PIN(5, 8),
2588 };
2589 static const unsigned int msiof1_txd_b_mux[] = {
2590     MSIOF1_TXD_B_MARK,
2591 };
2592 static const unsigned int msiof1_rxd_b_pins[] = {
2593     /* RXD */
2594     RCAR_GP_PIN(5, 7),
2595 };
2596 static const unsigned int msiof1_rxd_b_mux[] = {
2597     MSIOF1_RXD_B_MARK,
2598 };
2599 static const unsigned int msiof1_clk_c_pins[] = {
2600     /* SCK */
2601     RCAR_GP_PIN(6, 17),
2602 };
2603 static const unsigned int msiof1_clk_c_mux[] = {
2604     MSIOF1_SCK_C_MARK,
2605 };
2606 static const unsigned int msiof1_sync_c_pins[] = {
2607     /* SYNC */
2608     RCAR_GP_PIN(6, 18),
2609 };
2610 static const unsigned int msiof1_sync_c_mux[] = {
2611     MSIOF1_SYNC_C_MARK,
2612 };
2613 static const unsigned int msiof1_ss1_c_pins[] = {
2614     /* SS1 */
2615     RCAR_GP_PIN(6, 21),
2616 };
2617 static const unsigned int msiof1_ss1_c_mux[] = {
2618     MSIOF1_SS1_C_MARK,
2619 };
2620 static const unsigned int msiof1_ss2_c_pins[] = {
2621     /* SS2 */
2622     RCAR_GP_PIN(6, 27),
2623 };
2624 static const unsigned int msiof1_ss2_c_mux[] = {
2625     MSIOF1_SS2_C_MARK,
2626 };
2627 static const unsigned int msiof1_txd_c_pins[] = {
2628     /* TXD */
2629     RCAR_GP_PIN(6, 20),
2630 };
2631 static const unsigned int msiof1_txd_c_mux[] = {
2632     MSIOF1_TXD_C_MARK,
2633 };
2634 static const unsigned int msiof1_rxd_c_pins[] = {
2635     /* RXD */
2636     RCAR_GP_PIN(6, 19),
2637 };
2638 static const unsigned int msiof1_rxd_c_mux[] = {
2639     MSIOF1_RXD_C_MARK,
2640 };
2641 static const unsigned int msiof1_clk_d_pins[] = {
2642     /* SCK */
2643     RCAR_GP_PIN(5, 12),
2644 };
2645 static const unsigned int msiof1_clk_d_mux[] = {
2646     MSIOF1_SCK_D_MARK,
2647 };
2648 static const unsigned int msiof1_sync_d_pins[] = {
2649     /* SYNC */
2650     RCAR_GP_PIN(5, 15),
2651 };
2652 static const unsigned int msiof1_sync_d_mux[] = {
2653     MSIOF1_SYNC_D_MARK,
2654 };
2655 static const unsigned int msiof1_ss1_d_pins[] = {
2656     /* SS1 */
2657     RCAR_GP_PIN(5, 16),
2658 };
2659 static const unsigned int msiof1_ss1_d_mux[] = {
2660     MSIOF1_SS1_D_MARK,
2661 };
2662 static const unsigned int msiof1_ss2_d_pins[] = {
2663     /* SS2 */
2664     RCAR_GP_PIN(5, 21),
2665 };
2666 static const unsigned int msiof1_ss2_d_mux[] = {
2667     MSIOF1_SS2_D_MARK,
2668 };
2669 static const unsigned int msiof1_txd_d_pins[] = {
2670     /* TXD */
2671     RCAR_GP_PIN(5, 14),
2672 };
2673 static const unsigned int msiof1_txd_d_mux[] = {
2674     MSIOF1_TXD_D_MARK,
2675 };
2676 static const unsigned int msiof1_rxd_d_pins[] = {
2677     /* RXD */
2678     RCAR_GP_PIN(5, 13),
2679 };
2680 static const unsigned int msiof1_rxd_d_mux[] = {
2681     MSIOF1_RXD_D_MARK,
2682 };
2683 static const unsigned int msiof1_clk_e_pins[] = {
2684     /* SCK */
2685     RCAR_GP_PIN(3, 0),
2686 };
2687 static const unsigned int msiof1_clk_e_mux[] = {
2688     MSIOF1_SCK_E_MARK,
2689 };
2690 static const unsigned int msiof1_sync_e_pins[] = {
2691     /* SYNC */
2692     RCAR_GP_PIN(3, 1),
2693 };
2694 static const unsigned int msiof1_sync_e_mux[] = {
2695     MSIOF1_SYNC_E_MARK,
2696 };
2697 static const unsigned int msiof1_ss1_e_pins[] = {
2698     /* SS1 */
2699     RCAR_GP_PIN(3, 4),
2700 };
2701 static const unsigned int msiof1_ss1_e_mux[] = {
2702     MSIOF1_SS1_E_MARK,
2703 };
2704 static const unsigned int msiof1_ss2_e_pins[] = {
2705     /* SS2 */
2706     RCAR_GP_PIN(3, 5),
2707 };
2708 static const unsigned int msiof1_ss2_e_mux[] = {
2709     MSIOF1_SS2_E_MARK,
2710 };
2711 static const unsigned int msiof1_txd_e_pins[] = {
2712     /* TXD */
2713     RCAR_GP_PIN(3, 3),
2714 };
2715 static const unsigned int msiof1_txd_e_mux[] = {
2716     MSIOF1_TXD_E_MARK,
2717 };
2718 static const unsigned int msiof1_rxd_e_pins[] = {
2719     /* RXD */
2720     RCAR_GP_PIN(3, 2),
2721 };
2722 static const unsigned int msiof1_rxd_e_mux[] = {
2723     MSIOF1_RXD_E_MARK,
2724 };
2725 static const unsigned int msiof1_clk_f_pins[] = {
2726     /* SCK */
2727     RCAR_GP_PIN(5, 23),
2728 };
2729 static const unsigned int msiof1_clk_f_mux[] = {
2730     MSIOF1_SCK_F_MARK,
2731 };
2732 static const unsigned int msiof1_sync_f_pins[] = {
2733     /* SYNC */
2734     RCAR_GP_PIN(5, 24),
2735 };
2736 static const unsigned int msiof1_sync_f_mux[] = {
2737     MSIOF1_SYNC_F_MARK,
2738 };
2739 static const unsigned int msiof1_ss1_f_pins[] = {
2740     /* SS1 */
2741     RCAR_GP_PIN(6, 1),
2742 };
2743 static const unsigned int msiof1_ss1_f_mux[] = {
2744     MSIOF1_SS1_F_MARK,
2745 };
2746 static const unsigned int msiof1_ss2_f_pins[] = {
2747     /* SS2 */
2748     RCAR_GP_PIN(6, 2),
2749 };
2750 static const unsigned int msiof1_ss2_f_mux[] = {
2751     MSIOF1_SS2_F_MARK,
2752 };
2753 static const unsigned int msiof1_txd_f_pins[] = {
2754     /* TXD */
2755     RCAR_GP_PIN(6, 0),
2756 };
2757 static const unsigned int msiof1_txd_f_mux[] = {
2758     MSIOF1_TXD_F_MARK,
2759 };
2760 static const unsigned int msiof1_rxd_f_pins[] = {
2761     /* RXD */
2762     RCAR_GP_PIN(5, 25),
2763 };
2764 static const unsigned int msiof1_rxd_f_mux[] = {
2765     MSIOF1_RXD_F_MARK,
2766 };
2767 static const unsigned int msiof1_clk_g_pins[] = {
2768     /* SCK */
2769     RCAR_GP_PIN(3, 6),
2770 };
2771 static const unsigned int msiof1_clk_g_mux[] = {
2772     MSIOF1_SCK_G_MARK,
2773 };
2774 static const unsigned int msiof1_sync_g_pins[] = {
2775     /* SYNC */
2776     RCAR_GP_PIN(3, 7),
2777 };
2778 static const unsigned int msiof1_sync_g_mux[] = {
2779     MSIOF1_SYNC_G_MARK,
2780 };
2781 static const unsigned int msiof1_ss1_g_pins[] = {
2782     /* SS1 */
2783     RCAR_GP_PIN(3, 10),
2784 };
2785 static const unsigned int msiof1_ss1_g_mux[] = {
2786     MSIOF1_SS1_G_MARK,
2787 };
2788 static const unsigned int msiof1_ss2_g_pins[] = {
2789     /* SS2 */
2790     RCAR_GP_PIN(3, 11),
2791 };
2792 static const unsigned int msiof1_ss2_g_mux[] = {
2793     MSIOF1_SS2_G_MARK,
2794 };
2795 static const unsigned int msiof1_txd_g_pins[] = {
2796     /* TXD */
2797     RCAR_GP_PIN(3, 9),
2798 };
2799 static const unsigned int msiof1_txd_g_mux[] = {
2800     MSIOF1_TXD_G_MARK,
2801 };
2802 static const unsigned int msiof1_rxd_g_pins[] = {
2803     /* RXD */
2804     RCAR_GP_PIN(3, 8),
2805 };
2806 static const unsigned int msiof1_rxd_g_mux[] = {
2807     MSIOF1_RXD_G_MARK,
2808 };
2809 /* - MSIOF2 ----------------------------------------------------------------- */
2810 static const unsigned int msiof2_clk_a_pins[] = {
2811     /* SCK */
2812     RCAR_GP_PIN(1, 9),
2813 };
2814 static const unsigned int msiof2_clk_a_mux[] = {
2815     MSIOF2_SCK_A_MARK,
2816 };
2817 static const unsigned int msiof2_sync_a_pins[] = {
2818     /* SYNC */
2819     RCAR_GP_PIN(1, 8),
2820 };
2821 static const unsigned int msiof2_sync_a_mux[] = {
2822     MSIOF2_SYNC_A_MARK,
2823 };
2824 static const unsigned int msiof2_ss1_a_pins[] = {
2825     /* SS1 */
2826     RCAR_GP_PIN(1, 6),
2827 };
2828 static const unsigned int msiof2_ss1_a_mux[] = {
2829     MSIOF2_SS1_A_MARK,
2830 };
2831 static const unsigned int msiof2_ss2_a_pins[] = {
2832     /* SS2 */
2833     RCAR_GP_PIN(1, 7),
2834 };
2835 static const unsigned int msiof2_ss2_a_mux[] = {
2836     MSIOF2_SS2_A_MARK,
2837 };
2838 static const unsigned int msiof2_txd_a_pins[] = {
2839     /* TXD */
2840     RCAR_GP_PIN(1, 11),
2841 };
2842 static const unsigned int msiof2_txd_a_mux[] = {
2843     MSIOF2_TXD_A_MARK,
2844 };
2845 static const unsigned int msiof2_rxd_a_pins[] = {
2846     /* RXD */
2847     RCAR_GP_PIN(1, 10),
2848 };
2849 static const unsigned int msiof2_rxd_a_mux[] = {
2850     MSIOF2_RXD_A_MARK,
2851 };
2852 static const unsigned int msiof2_clk_b_pins[] = {
2853     /* SCK */
2854     RCAR_GP_PIN(0, 4),
2855 };
2856 static const unsigned int msiof2_clk_b_mux[] = {
2857     MSIOF2_SCK_B_MARK,
2858 };
2859 static const unsigned int msiof2_sync_b_pins[] = {
2860     /* SYNC */
2861     RCAR_GP_PIN(0, 5),
2862 };
2863 static const unsigned int msiof2_sync_b_mux[] = {
2864     MSIOF2_SYNC_B_MARK,
2865 };
2866 static const unsigned int msiof2_ss1_b_pins[] = {
2867     /* SS1 */
2868     RCAR_GP_PIN(0, 0),
2869 };
2870 static const unsigned int msiof2_ss1_b_mux[] = {
2871     MSIOF2_SS1_B_MARK,
2872 };
2873 static const unsigned int msiof2_ss2_b_pins[] = {
2874     /* SS2 */
2875     RCAR_GP_PIN(0, 1),
2876 };
2877 static const unsigned int msiof2_ss2_b_mux[] = {
2878     MSIOF2_SS2_B_MARK,
2879 };
2880 static const unsigned int msiof2_txd_b_pins[] = {
2881     /* TXD */
2882     RCAR_GP_PIN(0, 7),
2883 };
2884 static const unsigned int msiof2_txd_b_mux[] = {
2885     MSIOF2_TXD_B_MARK,
2886 };
2887 static const unsigned int msiof2_rxd_b_pins[] = {
2888     /* RXD */
2889     RCAR_GP_PIN(0, 6),
2890 };
2891 static const unsigned int msiof2_rxd_b_mux[] = {
2892     MSIOF2_RXD_B_MARK,
2893 };
2894 static const unsigned int msiof2_clk_c_pins[] = {
2895     /* SCK */
2896     RCAR_GP_PIN(2, 12),
2897 };
2898 static const unsigned int msiof2_clk_c_mux[] = {
2899     MSIOF2_SCK_C_MARK,
2900 };
2901 static const unsigned int msiof2_sync_c_pins[] = {
2902     /* SYNC */
2903     RCAR_GP_PIN(2, 11),
2904 };
2905 static const unsigned int msiof2_sync_c_mux[] = {
2906     MSIOF2_SYNC_C_MARK,
2907 };
2908 static const unsigned int msiof2_ss1_c_pins[] = {
2909     /* SS1 */
2910     RCAR_GP_PIN(2, 10),
2911 };
2912 static const unsigned int msiof2_ss1_c_mux[] = {
2913     MSIOF2_SS1_C_MARK,
2914 };
2915 static const unsigned int msiof2_ss2_c_pins[] = {
2916     /* SS2 */
2917     RCAR_GP_PIN(2, 9),
2918 };
2919 static const unsigned int msiof2_ss2_c_mux[] = {
2920     MSIOF2_SS2_C_MARK,
2921 };
2922 static const unsigned int msiof2_txd_c_pins[] = {
2923     /* TXD */
2924     RCAR_GP_PIN(2, 14),
2925 };
2926 static const unsigned int msiof2_txd_c_mux[] = {
2927     MSIOF2_TXD_C_MARK,
2928 };
2929 static const unsigned int msiof2_rxd_c_pins[] = {
2930     /* RXD */
2931     RCAR_GP_PIN(2, 13),
2932 };
2933 static const unsigned int msiof2_rxd_c_mux[] = {
2934     MSIOF2_RXD_C_MARK,
2935 };
2936 static const unsigned int msiof2_clk_d_pins[] = {
2937     /* SCK */
2938     RCAR_GP_PIN(0, 8),
2939 };
2940 static const unsigned int msiof2_clk_d_mux[] = {
2941     MSIOF2_SCK_D_MARK,
2942 };
2943 static const unsigned int msiof2_sync_d_pins[] = {
2944     /* SYNC */
2945     RCAR_GP_PIN(0, 9),
2946 };
2947 static const unsigned int msiof2_sync_d_mux[] = {
2948     MSIOF2_SYNC_D_MARK,
2949 };
2950 static const unsigned int msiof2_ss1_d_pins[] = {
2951     /* SS1 */
2952     RCAR_GP_PIN(0, 12),
2953 };
2954 static const unsigned int msiof2_ss1_d_mux[] = {
2955     MSIOF2_SS1_D_MARK,
2956 };
2957 static const unsigned int msiof2_ss2_d_pins[] = {
2958     /* SS2 */
2959     RCAR_GP_PIN(0, 13),
2960 };
2961 static const unsigned int msiof2_ss2_d_mux[] = {
2962     MSIOF2_SS2_D_MARK,
2963 };
2964 static const unsigned int msiof2_txd_d_pins[] = {
2965     /* TXD */
2966     RCAR_GP_PIN(0, 11),
2967 };
2968 static const unsigned int msiof2_txd_d_mux[] = {
2969     MSIOF2_TXD_D_MARK,
2970 };
2971 static const unsigned int msiof2_rxd_d_pins[] = {
2972     /* RXD */
2973     RCAR_GP_PIN(0, 10),
2974 };
2975 static const unsigned int msiof2_rxd_d_mux[] = {
2976     MSIOF2_RXD_D_MARK,
2977 };
2978 /* - MSIOF3 ----------------------------------------------------------------- */
2979 static const unsigned int msiof3_clk_a_pins[] = {
2980     /* SCK */
2981     RCAR_GP_PIN(0, 0),
2982 };
2983 static const unsigned int msiof3_clk_a_mux[] = {
2984     MSIOF3_SCK_A_MARK,
2985 };
2986 static const unsigned int msiof3_sync_a_pins[] = {
2987     /* SYNC */
2988     RCAR_GP_PIN(0, 1),
2989 };
2990 static const unsigned int msiof3_sync_a_mux[] = {
2991     MSIOF3_SYNC_A_MARK,
2992 };
2993 static const unsigned int msiof3_ss1_a_pins[] = {
2994     /* SS1 */
2995     RCAR_GP_PIN(0, 14),
2996 };
2997 static const unsigned int msiof3_ss1_a_mux[] = {
2998     MSIOF3_SS1_A_MARK,
2999 };
3000 static const unsigned int msiof3_ss2_a_pins[] = {
3001     /* SS2 */
3002     RCAR_GP_PIN(0, 15),
3003 };
3004 static const unsigned int msiof3_ss2_a_mux[] = {
3005     MSIOF3_SS2_A_MARK,
3006 };
3007 static const unsigned int msiof3_txd_a_pins[] = {
3008     /* TXD */
3009     RCAR_GP_PIN(0, 3),
3010 };
3011 static const unsigned int msiof3_txd_a_mux[] = {
3012     MSIOF3_TXD_A_MARK,
3013 };
3014 static const unsigned int msiof3_rxd_a_pins[] = {
3015     /* RXD */
3016     RCAR_GP_PIN(0, 2),
3017 };
3018 static const unsigned int msiof3_rxd_a_mux[] = {
3019     MSIOF3_RXD_A_MARK,
3020 };
3021 static const unsigned int msiof3_clk_b_pins[] = {
3022     /* SCK */
3023     RCAR_GP_PIN(1, 2),
3024 };
3025 static const unsigned int msiof3_clk_b_mux[] = {
3026     MSIOF3_SCK_B_MARK,
3027 };
3028 static const unsigned int msiof3_sync_b_pins[] = {
3029     /* SYNC */
3030     RCAR_GP_PIN(1, 0),
3031 };
3032 static const unsigned int msiof3_sync_b_mux[] = {
3033     MSIOF3_SYNC_B_MARK,
3034 };
3035 static const unsigned int msiof3_ss1_b_pins[] = {
3036     /* SS1 */
3037     RCAR_GP_PIN(1, 4),
3038 };
3039 static const unsigned int msiof3_ss1_b_mux[] = {
3040     MSIOF3_SS1_B_MARK,
3041 };
3042 static const unsigned int msiof3_ss2_b_pins[] = {
3043     /* SS2 */
3044     RCAR_GP_PIN(1, 5),
3045 };
3046 static const unsigned int msiof3_ss2_b_mux[] = {
3047     MSIOF3_SS2_B_MARK,
3048 };
3049 static const unsigned int msiof3_txd_b_pins[] = {
3050     /* TXD */
3051     RCAR_GP_PIN(1, 1),
3052 };
3053 static const unsigned int msiof3_txd_b_mux[] = {
3054     MSIOF3_TXD_B_MARK,
3055 };
3056 static const unsigned int msiof3_rxd_b_pins[] = {
3057     /* RXD */
3058     RCAR_GP_PIN(1, 3),
3059 };
3060 static const unsigned int msiof3_rxd_b_mux[] = {
3061     MSIOF3_RXD_B_MARK,
3062 };
3063 static const unsigned int msiof3_clk_c_pins[] = {
3064     /* SCK */
3065     RCAR_GP_PIN(1, 12),
3066 };
3067 static const unsigned int msiof3_clk_c_mux[] = {
3068     MSIOF3_SCK_C_MARK,
3069 };
3070 static const unsigned int msiof3_sync_c_pins[] = {
3071     /* SYNC */
3072     RCAR_GP_PIN(1, 13),
3073 };
3074 static const unsigned int msiof3_sync_c_mux[] = {
3075     MSIOF3_SYNC_C_MARK,
3076 };
3077 static const unsigned int msiof3_txd_c_pins[] = {
3078     /* TXD */
3079     RCAR_GP_PIN(1, 15),
3080 };
3081 static const unsigned int msiof3_txd_c_mux[] = {
3082     MSIOF3_TXD_C_MARK,
3083 };
3084 static const unsigned int msiof3_rxd_c_pins[] = {
3085     /* RXD */
3086     RCAR_GP_PIN(1, 14),
3087 };
3088 static const unsigned int msiof3_rxd_c_mux[] = {
3089     MSIOF3_RXD_C_MARK,
3090 };
3091 static const unsigned int msiof3_clk_d_pins[] = {
3092     /* SCK */
3093     RCAR_GP_PIN(1, 22),
3094 };
3095 static const unsigned int msiof3_clk_d_mux[] = {
3096     MSIOF3_SCK_D_MARK,
3097 };
3098 static const unsigned int msiof3_sync_d_pins[] = {
3099     /* SYNC */
3100     RCAR_GP_PIN(1, 23),
3101 };
3102 static const unsigned int msiof3_sync_d_mux[] = {
3103     MSIOF3_SYNC_D_MARK,
3104 };
3105 static const unsigned int msiof3_ss1_d_pins[] = {
3106     /* SS1 */
3107     RCAR_GP_PIN(1, 26),
3108 };
3109 static const unsigned int msiof3_ss1_d_mux[] = {
3110     MSIOF3_SS1_D_MARK,
3111 };
3112 static const unsigned int msiof3_txd_d_pins[] = {
3113     /* TXD */
3114     RCAR_GP_PIN(1, 25),
3115 };
3116 static const unsigned int msiof3_txd_d_mux[] = {
3117     MSIOF3_TXD_D_MARK,
3118 };
3119 static const unsigned int msiof3_rxd_d_pins[] = {
3120     /* RXD */
3121     RCAR_GP_PIN(1, 24),
3122 };
3123 static const unsigned int msiof3_rxd_d_mux[] = {
3124     MSIOF3_RXD_D_MARK,
3125 };
3126
3127 static const unsigned int msiof3_clk_e_pins[] = {
3128     /* SCK */
3129     RCAR_GP_PIN(2, 3),
3130 };
3131 static const unsigned int msiof3_clk_e_mux[] = {
3132     MSIOF3_SCK_E_MARK,
3133 };
3134 static const unsigned int msiof3_sync_e_pins[] = {
3135     /* SYNC */
3136     RCAR_GP_PIN(2, 2),
3137 };
3138 static const unsigned int msiof3_sync_e_mux[] = {
3139     MSIOF3_SYNC_E_MARK,
3140 };
3141 static const unsigned int msiof3_ss1_e_pins[] = {
3142     /* SS1 */
3143     RCAR_GP_PIN(2, 1),
3144 };
3145 static const unsigned int msiof3_ss1_e_mux[] = {
3146     MSIOF3_SS1_E_MARK,
3147 };
3148 static const unsigned int msiof3_ss2_e_pins[] = {
3149     /* SS2 */
3150     RCAR_GP_PIN(2, 0),
3151 };
3152 static const unsigned int msiof3_ss2_e_mux[] = {
3153     MSIOF3_SS2_E_MARK,
3154 };
3155 static const unsigned int msiof3_txd_e_pins[] = {
3156     /* TXD */
3157     RCAR_GP_PIN(2, 5),
3158 };
3159 static const unsigned int msiof3_txd_e_mux[] = {
3160     MSIOF3_TXD_E_MARK,
3161 };
3162 static const unsigned int msiof3_rxd_e_pins[] = {
3163     /* RXD */
3164     RCAR_GP_PIN(2, 4),
3165 };
3166 static const unsigned int msiof3_rxd_e_mux[] = {
3167     MSIOF3_RXD_E_MARK,
3168 };
3169
3170 /* - PWM0 --------------------------------------------------------------------*/
3171 static const unsigned int pwm0_pins[] = {
3172     /* PWM */
3173     RCAR_GP_PIN(2, 6),
3174 };
3175 static const unsigned int pwm0_mux[] = {
3176     PWM0_MARK,
3177 };
3178 /* - PWM1 --------------------------------------------------------------------*/
3179 static const unsigned int pwm1_a_pins[] = {
3180     /* PWM */
3181     RCAR_GP_PIN(2, 7),
3182 };
3183 static const unsigned int pwm1_a_mux[] = {
3184     PWM1_A_MARK,
3185 };
3186 static const unsigned int pwm1_b_pins[] = {
3187     /* PWM */
3188     RCAR_GP_PIN(1, 8),
3189 };
3190 static const unsigned int pwm1_b_mux[] = {
3191     PWM1_B_MARK,
3192 };
3193 /* - PWM2 --------------------------------------------------------------------*/
3194 static const unsigned int pwm2_a_pins[] = {
3195     /* PWM */
3196     RCAR_GP_PIN(2, 8),
3197 };
3198 static const unsigned int pwm2_a_mux[] = {
3199     PWM2_A_MARK,
3200 };
3201 static const unsigned int pwm2_b_pins[] = {
3202     /* PWM */
3203     RCAR_GP_PIN(1, 11),
3204 };
3205 static const unsigned int pwm2_b_mux[] = {
3206     PWM2_B_MARK,
3207 };
3208 /* - PWM3 --------------------------------------------------------------------*/
3209 static const unsigned int pwm3_a_pins[] = {
3210     /* PWM */
3211     RCAR_GP_PIN(1, 0),
3212 };
3213 static const unsigned int pwm3_a_mux[] = {
3214     PWM3_A_MARK,
3215 };
3216 static const unsigned int pwm3_b_pins[] = {
3217     /* PWM */
3218     RCAR_GP_PIN(2, 2),
3219 };
3220 static const unsigned int pwm3_b_mux[] = {
3221     PWM3_B_MARK,
3222 };
3223 /* - PWM4 --------------------------------------------------------------------*/
3224 static const unsigned int pwm4_a_pins[] = {
3225     /* PWM */
3226     RCAR_GP_PIN(1, 1),
3227 };
3228 static const unsigned int pwm4_a_mux[] = {
3229     PWM4_A_MARK,
3230 };
3231 static const unsigned int pwm4_b_pins[] = {
3232     /* PWM */
3233     RCAR_GP_PIN(2, 3),
3234 };
3235 static const unsigned int pwm4_b_mux[] = {
3236     PWM4_B_MARK,
3237 };
3238 /* - PWM5 --------------------------------------------------------------------*/
3239 static const unsigned int pwm5_a_pins[] = {
3240     /* PWM */
3241     RCAR_GP_PIN(1, 2),
3242 };
3243 static const unsigned int pwm5_a_mux[] = {
3244     PWM5_A_MARK,
3245 };
3246 static const unsigned int pwm5_b_pins[] = {
3247     /* PWM */
3248     RCAR_GP_PIN(2, 4),
3249 };
3250 static const unsigned int pwm5_b_mux[] = {
3251     PWM5_B_MARK,
3252 };
3253 /* - PWM6 --------------------------------------------------------------------*/
3254 static const unsigned int pwm6_a_pins[] = {
3255     /* PWM */
3256     RCAR_GP_PIN(1, 3),
3257 };
3258 static const unsigned int pwm6_a_mux[] = {
3259     PWM6_A_MARK,
3260 };
3261 static const unsigned int pwm6_b_pins[] = {
3262     /* PWM */
3263     RCAR_GP_PIN(2, 5),
3264 };
3265 static const unsigned int pwm6_b_mux[] = {
3266     PWM6_B_MARK,
3267 };
3268
3269 /* - QSPI0 ------------------------------------------------------------------ */
3270 static const unsigned int qspi0_ctrl_pins[] = {
3271     /* QSPI0_SPCLK, QSPI0_SSL */
3272     PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
3273 };
3274 static const unsigned int qspi0_ctrl_mux[] = {
3275     QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
3276 };
3277 static const unsigned int qspi0_data_pins[] = {
3278     /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
3279     PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
3280     /* QSPI0_IO2, QSPI0_IO3 */
3281     PIN_QSPI0_IO2, PIN_QSPI0_IO3,
3282 };
3283 static const unsigned int qspi0_data_mux[] = {
3284     QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
3285     QSPI0_IO2_MARK, QSPI0_IO3_MARK,
3286 };
3287 /* - QSPI1 ------------------------------------------------------------------ */
3288 static const unsigned int qspi1_ctrl_pins[] = {
3289     /* QSPI1_SPCLK, QSPI1_SSL */
3290     PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
3291 };
3292 static const unsigned int qspi1_ctrl_mux[] = {
3293     QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
3294 };
3295 static const unsigned int qspi1_data_pins[] = {
3296     /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
3297     PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
3298     /* QSPI1_IO2, QSPI1_IO3 */
3299     PIN_QSPI1_IO2, PIN_QSPI1_IO3,
3300 };
3301 static const unsigned int qspi1_data_mux[] = {
3302     QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
3303     QSPI1_IO2_MARK, QSPI1_IO3_MARK,
3304 };
3305
3306 /* - SCIF0 ------------------------------------------------------------------ */
3307 static const unsigned int scif0_data_pins[] = {
3308     /* RX, TX */
3309     RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3310 };
3311 static const unsigned int scif0_data_mux[] = {
3312     RX0_MARK, TX0_MARK,
3313 };
3314 static const unsigned int scif0_clk_pins[] = {
3315     /* SCK */
3316     RCAR_GP_PIN(5, 0),
3317 };
3318 static const unsigned int scif0_clk_mux[] = {
3319     SCK0_MARK,
3320 };
3321 static const unsigned int scif0_ctrl_pins[] = {
3322     /* RTS, CTS */
3323     RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3324 };
3325 static const unsigned int scif0_ctrl_mux[] = {
3326     RTS0_N_MARK, CTS0_N_MARK,
3327 };
3328 /* - SCIF1 ------------------------------------------------------------------ */
3329 static const unsigned int scif1_data_a_pins[] = {
3330     /* RX, TX */
3331     RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3332 };
3333 static const unsigned int scif1_data_a_mux[] = {
3334     RX1_A_MARK, TX1_A_MARK,
3335 };
3336 static const unsigned int scif1_clk_pins[] = {
3337     /* SCK */
3338     RCAR_GP_PIN(6, 21),
3339 };
3340 static const unsigned int scif1_clk_mux[] = {
3341     SCK1_MARK,
3342 };
3343 static const unsigned int scif1_ctrl_pins[] = {
3344     /* RTS, CTS */
3345     RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3346 };
3347 static const unsigned int scif1_ctrl_mux[] = {
3348     RTS1_N_MARK, CTS1_N_MARK,
3349 };
3350
3351 static const unsigned int scif1_data_b_pins[] = {
3352     /* RX, TX */
3353     RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3354 };
3355 static const unsigned int scif1_data_b_mux[] = {
3356     RX1_B_MARK, TX1_B_MARK,
3357 };
3358 /* - SCIF2 ------------------------------------------------------------------ */
3359 static const unsigned int scif2_data_a_pins[] = {
3360     /* RX, TX */
3361     RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3362 };
3363 static const unsigned int scif2_data_a_mux[] = {
3364     RX2_A_MARK, TX2_A_MARK,
3365 };
3366 static const unsigned int scif2_clk_pins[] = {
3367     /* SCK */
3368     RCAR_GP_PIN(5, 9),
3369 };
3370 static const unsigned int scif2_clk_mux[] = {
3371     SCK2_MARK,
3372 };
3373 static const unsigned int scif2_data_b_pins[] = {
3374     /* RX, TX */
3375     RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3376 };
3377 static const unsigned int scif2_data_b_mux[] = {
3378     RX2_B_MARK, TX2_B_MARK,
3379 };
3380 /* - SCIF3 ------------------------------------------------------------------ */
3381 static const unsigned int scif3_data_a_pins[] = {
3382     /* RX, TX */
3383     RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3384 };
3385 static const unsigned int scif3_data_a_mux[] = {
3386     RX3_A_MARK, TX3_A_MARK,
3387 };
3388 static const unsigned int scif3_clk_pins[] = {
3389     /* SCK */
3390     RCAR_GP_PIN(1, 22),
3391 };
3392 static const unsigned int scif3_clk_mux[] = {
3393     SCK3_MARK,
3394 };
3395 static const unsigned int scif3_ctrl_pins[] = {
3396     /* RTS, CTS */
3397     RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3398 };
3399 static const unsigned int scif3_ctrl_mux[] = {
3400     RTS3_N_MARK, CTS3_N_MARK,
3401 };
3402 static const unsigned int scif3_data_b_pins[] = {
3403     /* RX, TX */
3404     RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3405 };
3406 static const unsigned int scif3_data_b_mux[] = {
3407     RX3_B_MARK, TX3_B_MARK,
3408 };
3409 /* - SCIF4 ------------------------------------------------------------------ */
3410 static const unsigned int scif4_data_a_pins[] = {
3411     /* RX, TX */
3412     RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3413 };
3414 static const unsigned int scif4_data_a_mux[] = {
3415     RX4_A_MARK, TX4_A_MARK,
3416 };
3417 static const unsigned int scif4_clk_a_pins[] = {
3418     /* SCK */
3419     RCAR_GP_PIN(2, 10),
3420 };
3421 static const unsigned int scif4_clk_a_mux[] = {
3422     SCK4_A_MARK,
3423 };
3424 static const unsigned int scif4_ctrl_a_pins[] = {
3425     /* RTS, CTS */
3426     RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3427 };
3428 static const unsigned int scif4_ctrl_a_mux[] = {
3429     RTS4_N_A_MARK, CTS4_N_A_MARK,
3430 };
3431 static const unsigned int scif4_data_b_pins[] = {
3432     /* RX, TX */
3433     RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3434 };
3435 static const unsigned int scif4_data_b_mux[] = {
3436     RX4_B_MARK, TX4_B_MARK,
3437 };
3438 static const unsigned int scif4_clk_b_pins[] = {
3439     /* SCK */
3440     RCAR_GP_PIN(1, 5),
3441 };
3442 static const unsigned int scif4_clk_b_mux[] = {
3443     SCK4_B_MARK,
3444 };
3445 static const unsigned int scif4_ctrl_b_pins[] = {
3446     /* RTS, CTS */
3447     RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3448 };
3449 static const unsigned int scif4_ctrl_b_mux[] = {
3450     RTS4_N_B_MARK, CTS4_N_B_MARK,
3451 };
3452 static const unsigned int scif4_data_c_pins[] = {
3453     /* RX, TX */
3454     RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3455 };
3456 static const unsigned int scif4_data_c_mux[] = {
3457     RX4_C_MARK, TX4_C_MARK,
3458 };
3459 static const unsigned int scif4_clk_c_pins[] = {
3460     /* SCK */
3461     RCAR_GP_PIN(0, 8),
3462 };
3463 static const unsigned int scif4_clk_c_mux[] = {
3464     SCK4_C_MARK,
3465 };
3466 static const unsigned int scif4_ctrl_c_pins[] = {
3467     /* RTS, CTS */
3468     RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3469 };
3470 static const unsigned int scif4_ctrl_c_mux[] = {
3471     RTS4_N_C_MARK, CTS4_N_C_MARK,
3472 };
3473 /* - SCIF5 ------------------------------------------------------------------ */
3474 static const unsigned int scif5_data_a_pins[] = {
3475     /* RX, TX */
3476     RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3477 };
3478 static const unsigned int scif5_data_a_mux[] = {
3479     RX5_A_MARK, TX5_A_MARK,
3480 };
3481 static const unsigned int scif5_clk_a_pins[] = {
3482     /* SCK */
3483     RCAR_GP_PIN(6, 21),
3484 };
3485 static const unsigned int scif5_clk_a_mux[] = {
3486     SCK5_A_MARK,
3487 };
3488
3489 static const unsigned int scif5_data_b_pins[] = {
3490     /* RX, TX */
3491     RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3492 };
3493 static const unsigned int scif5_data_b_mux[] = {
3494     RX5_B_MARK, TX5_B_MARK,
3495 };
3496 static const unsigned int scif5_clk_b_pins[] = {
3497     /* SCK */
3498     RCAR_GP_PIN(5, 0),
3499 };
3500 static const unsigned int scif5_clk_b_mux[] = {
3501     SCK5_B_MARK,
3502 };
3503
3504 /* - SCIF Clock ------------------------------------------------------------- */
3505 static const unsigned int scif_clk_a_pins[] = {
3506     /* SCIF_CLK */
3507     RCAR_GP_PIN(6, 23),
3508 };
3509 static const unsigned int scif_clk_a_mux[] = {
3510     SCIF_CLK_A_MARK,
3511 };
3512 static const unsigned int scif_clk_b_pins[] = {
3513     /* SCIF_CLK */
3514     RCAR_GP_PIN(5, 9),
3515 };
3516 static const unsigned int scif_clk_b_mux[] = {
3517     SCIF_CLK_B_MARK,
3518 };
3519
3520 /* - SDHI0 ------------------------------------------------------------------ */
3521 static const unsigned int sdhi0_data_pins[] = {
3522     /* D[0:3] */
3523     RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3524     RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3525 };
3526 static const unsigned int sdhi0_data_mux[] = {
3527     SD0_DAT0_MARK, SD0_DAT1_MARK,
3528     SD0_DAT2_MARK, SD0_DAT3_MARK,
3529 };
3530 static const unsigned int sdhi0_ctrl_pins[] = {
3531     /* CLK, CMD */
3532     RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3533 };
3534 static const unsigned int sdhi0_ctrl_mux[] = {
3535     SD0_CLK_MARK, SD0_CMD_MARK,
3536 };
3537 static const unsigned int sdhi0_cd_pins[] = {
3538     /* CD */
3539     RCAR_GP_PIN(3, 12),
3540 };
3541 static const unsigned int sdhi0_cd_mux[] = {
3542     SD0_CD_MARK,
3543 };
3544 static const unsigned int sdhi0_wp_pins[] = {
3545     /* WP */
3546     RCAR_GP_PIN(3, 13),
3547 };
3548 static const unsigned int sdhi0_wp_mux[] = {
3549     SD0_WP_MARK,
3550 };
3551 /* - SDHI1 ------------------------------------------------------------------ */
3552 static const unsigned int sdhi1_data_pins[] = {
3553     /* D[0:3] */
3554     RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3555     RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3556 };
3557 static const unsigned int sdhi1_data_mux[] = {
3558     SD1_DAT0_MARK, SD1_DAT1_MARK,
3559     SD1_DAT2_MARK, SD1_DAT3_MARK,
3560 };
3561 static const unsigned int sdhi1_ctrl_pins[] = {
3562     /* CLK, CMD */
3563     RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3564 };
3565 static const unsigned int sdhi1_ctrl_mux[] = {
3566     SD1_CLK_MARK, SD1_CMD_MARK,
3567 };
3568 static const unsigned int sdhi1_cd_pins[] = {
3569     /* CD */
3570     RCAR_GP_PIN(3, 14),
3571 };
3572 static const unsigned int sdhi1_cd_mux[] = {
3573     SD1_CD_MARK,
3574 };
3575 static const unsigned int sdhi1_wp_pins[] = {
3576     /* WP */
3577     RCAR_GP_PIN(3, 15),
3578 };
3579 static const unsigned int sdhi1_wp_mux[] = {
3580     SD1_WP_MARK,
3581 };
3582 /* - SDHI2 ------------------------------------------------------------------ */
3583 static const unsigned int sdhi2_data_pins[] = {
3584     /* D[0:7] */
3585     RCAR_GP_PIN(4, 2),  RCAR_GP_PIN(4, 3),
3586     RCAR_GP_PIN(4, 4),  RCAR_GP_PIN(4, 5),
3587     RCAR_GP_PIN(3, 8),  RCAR_GP_PIN(3, 9),
3588     RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3589 };
3590 static const unsigned int sdhi2_data_mux[] = {
3591     SD2_DAT0_MARK, SD2_DAT1_MARK,
3592     SD2_DAT2_MARK, SD2_DAT3_MARK,
3593     SD2_DAT4_MARK, SD2_DAT5_MARK,
3594     SD2_DAT6_MARK, SD2_DAT7_MARK,
3595 };
3596 static const unsigned int sdhi2_ctrl_pins[] = {
3597     /* CLK, CMD */
3598     RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3599 };
3600 static const unsigned int sdhi2_ctrl_mux[] = {
3601     SD2_CLK_MARK, SD2_CMD_MARK,
3602 };
3603 static const unsigned int sdhi2_cd_a_pins[] = {
3604     /* CD */
3605     RCAR_GP_PIN(4, 13),
3606 };
3607 static const unsigned int sdhi2_cd_a_mux[] = {
3608     SD2_CD_A_MARK,
3609 };
3610 static const unsigned int sdhi2_cd_b_pins[] = {
3611     /* CD */
3612     RCAR_GP_PIN(5, 10),
3613 };
3614 static const unsigned int sdhi2_cd_b_mux[] = {
3615     SD2_CD_B_MARK,
3616 };
3617 static const unsigned int sdhi2_wp_a_pins[] = {
3618     /* WP */
3619     RCAR_GP_PIN(4, 14),
3620 };
3621 static const unsigned int sdhi2_wp_a_mux[] = {
3622     SD2_WP_A_MARK,
3623 };
3624 static const unsigned int sdhi2_wp_b_pins[] = {
3625     /* WP */
3626     RCAR_GP_PIN(5, 11),
3627 };
3628 static const unsigned int sdhi2_wp_b_mux[] = {
3629     SD2_WP_B_MARK,
3630 };
3631 static const unsigned int sdhi2_ds_pins[] = {
3632     /* DS */
3633     RCAR_GP_PIN(4, 6),
3634 };
3635 static const unsigned int sdhi2_ds_mux[] = {
3636     SD2_DS_MARK,
3637 };
3638 /* - SDHI3 ------------------------------------------------------------------ */
3639 static const unsigned int sdhi3_data_pins[] = {
3640     /* D[0:7] */
3641     RCAR_GP_PIN(4, 9),  RCAR_GP_PIN(4, 10),
3642     RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3643     RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3644     RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3645 };
3646 static const unsigned int sdhi3_data_mux[] = {
3647     SD3_DAT0_MARK, SD3_DAT1_MARK,
3648     SD3_DAT2_MARK, SD3_DAT3_MARK,
3649     SD3_DAT4_MARK, SD3_DAT5_MARK,
3650     SD3_DAT6_MARK, SD3_DAT7_MARK,
3651 };
3652 static const unsigned int sdhi3_ctrl_pins[] = {
3653     /* CLK, CMD */
3654     RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3655 };
3656 static const unsigned int sdhi3_ctrl_mux[] = {
3657     SD3_CLK_MARK, SD3_CMD_MARK,
3658 };
3659 static const unsigned int sdhi3_cd_pins[] = {
3660     /* CD */
3661     RCAR_GP_PIN(4, 15),
3662 };
3663 static const unsigned int sdhi3_cd_mux[] = {
3664     SD3_CD_MARK,
3665 };
3666 static const unsigned int sdhi3_wp_pins[] = {
3667     /* WP */
3668     RCAR_GP_PIN(4, 16),
3669 };
3670 static const unsigned int sdhi3_wp_mux[] = {
3671     SD3_WP_MARK,
3672 };
3673 static const unsigned int sdhi3_ds_pins[] = {
3674     /* DS */
3675     RCAR_GP_PIN(4, 17),
3676 };
3677 static const unsigned int sdhi3_ds_mux[] = {
3678     SD3_DS_MARK,
3679 };
3680
3681 /* - SSI -------------------------------------------------------------------- */
3682 static const unsigned int ssi0_data_pins[] = {
3683     /* SDATA */
3684     RCAR_GP_PIN(6, 2),
3685 };
3686 static const unsigned int ssi0_data_mux[] = {
3687     SSI_SDATA0_MARK,
3688 };
3689 static const unsigned int ssi01239_ctrl_pins[] = {
3690     /* SCK, WS */
3691     RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3692 };
3693 static const unsigned int ssi01239_ctrl_mux[] = {
3694     SSI_SCK01239_MARK, SSI_WS01239_MARK,
3695 };
3696 static const unsigned int ssi1_data_a_pins[] = {
3697     /* SDATA */
3698     RCAR_GP_PIN(6, 3),
3699 };
3700 static const unsigned int ssi1_data_a_mux[] = {
3701     SSI_SDATA1_A_MARK,
3702 };
3703 static const unsigned int ssi1_data_b_pins[] = {
3704     /* SDATA */
3705     RCAR_GP_PIN(5, 12),
3706 };
3707 static const unsigned int ssi1_data_b_mux[] = {
3708     SSI_SDATA1_B_MARK,
3709 };
3710 static const unsigned int ssi1_ctrl_a_pins[] = {
3711     /* SCK, WS */
3712     RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3713 };
3714 static const unsigned int ssi1_ctrl_a_mux[] = {
3715     SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3716 };
3717 static const unsigned int ssi1_ctrl_b_pins[] = {
3718     /* SCK, WS */
3719     RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3720 };
3721 static const unsigned int ssi1_ctrl_b_mux[] = {
3722     SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3723 };
3724 static const unsigned int ssi2_data_a_pins[] = {
3725     /* SDATA */
3726     RCAR_GP_PIN(6, 4),
3727 };
3728 static const unsigned int ssi2_data_a_mux[] = {
3729     SSI_SDATA2_A_MARK,
3730 };
3731 static const unsigned int ssi2_data_b_pins[] = {
3732     /* SDATA */
3733     RCAR_GP_PIN(5, 13),
3734 };
3735 static const unsigned int ssi2_data_b_mux[] = {
3736     SSI_SDATA2_B_MARK,
3737 };
3738 static const unsigned int ssi2_ctrl_a_pins[] = {
3739     /* SCK, WS */
3740     RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3741 };
3742 static const unsigned int ssi2_ctrl_a_mux[] = {
3743     SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3744 };
3745 static const unsigned int ssi2_ctrl_b_pins[] = {
3746     /* SCK, WS */
3747     RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3748 };
3749 static const unsigned int ssi2_ctrl_b_mux[] = {
3750     SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3751 };
3752 static const unsigned int ssi3_data_pins[] = {
3753     /* SDATA */
3754     RCAR_GP_PIN(6, 7),
3755 };
3756 static const unsigned int ssi3_data_mux[] = {
3757     SSI_SDATA3_MARK,
3758 };
3759 static const unsigned int ssi349_ctrl_pins[] = {
3760     /* SCK, WS */
3761     RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3762 };
3763 static const unsigned int ssi349_ctrl_mux[] = {
3764     SSI_SCK349_MARK, SSI_WS349_MARK,
3765 };
3766 static const unsigned int ssi4_data_pins[] = {
3767     /* SDATA */
3768     RCAR_GP_PIN(6, 10),
3769 };
3770 static const unsigned int ssi4_data_mux[] = {
3771     SSI_SDATA4_MARK,
3772 };
3773 static const unsigned int ssi4_ctrl_pins[] = {
3774     /* SCK, WS */
3775     RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3776 };
3777 static const unsigned int ssi4_ctrl_mux[] = {
3778     SSI_SCK4_MARK, SSI_WS4_MARK,
3779 };
3780 static const unsigned int ssi5_data_pins[] = {
3781     /* SDATA */
3782     RCAR_GP_PIN(6, 13),
3783 };
3784 static const unsigned int ssi5_data_mux[] = {
3785     SSI_SDATA5_MARK,
3786 };
3787 static const unsigned int ssi5_ctrl_pins[] = {
3788     /* SCK, WS */
3789     RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3790 };
3791 static const unsigned int ssi5_ctrl_mux[] = {
3792     SSI_SCK5_MARK, SSI_WS5_MARK,
3793 };
3794 static const unsigned int ssi6_data_pins[] = {
3795     /* SDATA */
3796     RCAR_GP_PIN(6, 16),
3797 };
3798 static const unsigned int ssi6_data_mux[] = {
3799     SSI_SDATA6_MARK,
3800 };
3801 static const unsigned int ssi6_ctrl_pins[] = {
3802     /* SCK, WS */
3803     RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3804 };
3805 static const unsigned int ssi6_ctrl_mux[] = {
3806     SSI_SCK6_MARK, SSI_WS6_MARK,
3807 };
3808 static const unsigned int ssi7_data_pins[] = {
3809     /* SDATA */
3810     RCAR_GP_PIN(6, 19),
3811 };
3812 static const unsigned int ssi7_data_mux[] = {
3813     SSI_SDATA7_MARK,
3814 };
3815 static const unsigned int ssi78_ctrl_pins[] = {
3816     /* SCK, WS */
3817     RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3818 };
3819 static const unsigned int ssi78_ctrl_mux[] = {
3820     SSI_SCK78_MARK, SSI_WS78_MARK,
3821 };
3822 static const unsigned int ssi8_data_pins[] = {
3823     /* SDATA */
3824     RCAR_GP_PIN(6, 20),
3825 };
3826 static const unsigned int ssi8_data_mux[] = {
3827     SSI_SDATA8_MARK,
3828 };
3829 static const unsigned int ssi9_data_a_pins[] = {
3830     /* SDATA */
3831     RCAR_GP_PIN(6, 21),
3832 };
3833 static const unsigned int ssi9_data_a_mux[] = {
3834     SSI_SDATA9_A_MARK,
3835 };
3836 static const unsigned int ssi9_data_b_pins[] = {
3837     /* SDATA */
3838     RCAR_GP_PIN(5, 14),
3839 };
3840 static const unsigned int ssi9_data_b_mux[] = {
3841     SSI_SDATA9_B_MARK,
3842 };
3843 static const unsigned int ssi9_ctrl_a_pins[] = {
3844     /* SCK, WS */
3845     RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3846 };
3847 static const unsigned int ssi9_ctrl_a_mux[] = {
3848     SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3849 };
3850 static const unsigned int ssi9_ctrl_b_pins[] = {
3851     /* SCK, WS */
3852     RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3853 };
3854 static const unsigned int ssi9_ctrl_b_mux[] = {
3855     SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3856 };
3857
3858 /* - TMU -------------------------------------------------------------------- */
3859 static const unsigned int tmu_tclk1_a_pins[] = {
3860     /* TCLK */
3861     RCAR_GP_PIN(6, 23),
3862 };
3863 static const unsigned int tmu_tclk1_a_mux[] = {
3864     TCLK1_A_MARK,
3865 };
3866 static const unsigned int tmu_tclk1_b_pins[] = {
3867     /* TCLK */
3868     RCAR_GP_PIN(5, 19),
3869 };
3870 static const unsigned int tmu_tclk1_b_mux[] = {
3871     TCLK1_B_MARK,
3872 };
3873 static const unsigned int tmu_tclk2_a_pins[] = {
3874     /* TCLK */
3875     RCAR_GP_PIN(6, 19),
3876 };
3877 static const unsigned int tmu_tclk2_a_mux[] = {
3878     TCLK2_A_MARK,
3879 };
3880 static const unsigned int tmu_tclk2_b_pins[] = {
3881     /* TCLK */
3882     RCAR_GP_PIN(6, 28),
3883 };
3884 static const unsigned int tmu_tclk2_b_mux[] = {
3885     TCLK2_B_MARK,
3886 };
3887
3888 /* - TPU ------------------------------------------------------------------- */
3889 static const unsigned int tpu_to0_pins[] = {
3890     /* TPU0TO0 */
3891     RCAR_GP_PIN(6, 28),
3892 };
3893 static const unsigned int tpu_to0_mux[] = {
3894     TPU0TO0_MARK,
3895 };
3896 static const unsigned int tpu_to1_pins[] = {
3897     /* TPU0TO1 */
3898     RCAR_GP_PIN(6, 29),
3899 };
3900 static const unsigned int tpu_to1_mux[] = {
3901     TPU0TO1_MARK,
3902 };
3903 static const unsigned int tpu_to2_pins[] = {
3904     /* TPU0TO2 */
3905     RCAR_GP_PIN(6, 30),
3906 };
3907 static const unsigned int tpu_to2_mux[] = {
3908     TPU0TO2_MARK,
3909 };
3910 static const unsigned int tpu_to3_pins[] = {
3911     /* TPU0TO3 */
3912     RCAR_GP_PIN(6, 31),
3913 };
3914 static const unsigned int tpu_to3_mux[] = {
3915     TPU0TO3_MARK,
3916 };
3917
3918 /* - USB0 ------------------------------------------------------------------- */
3919 static const unsigned int usb0_pins[] = {
3920     /* PWEN, OVC */
3921     RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3922 };
3923 static const unsigned int usb0_mux[] = {
3924     USB0_PWEN_MARK, USB0_OVC_MARK,
3925 };
3926 /* - USB1 ------------------------------------------------------------------- */
3927 static const unsigned int usb1_pins[] = {
3928     /* PWEN, OVC */
3929     RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3930 };
3931 static const unsigned int usb1_mux[] = {
3932     USB1_PWEN_MARK, USB1_OVC_MARK,
3933 };
3934
3935 /* - USB30 ------------------------------------------------------------------ */
3936 static const unsigned int usb30_pins[] = {
3937     /* PWEN, OVC */
3938     RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3939 };
3940 static const unsigned int usb30_mux[] = {
3941     USB30_PWEN_MARK, USB30_OVC_MARK,
3942 };
3943
3944 /* - VIN4 ------------------------------------------------------------------- */
3945 static const unsigned int vin4_data18_a_pins[] = {
3946     RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3947     RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3948     RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3949     RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3950     RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3951     RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3952     RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3953     RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3954     RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3955 };
3956 static const unsigned int vin4_data18_a_mux[] = {
3957     VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3958     VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3959     VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3960     VI4_DATA10_MARK, VI4_DATA11_MARK,
3961     VI4_DATA12_MARK, VI4_DATA13_MARK,
3962     VI4_DATA14_MARK, VI4_DATA15_MARK,
3963     VI4_DATA18_MARK, VI4_DATA19_MARK,
3964     VI4_DATA20_MARK, VI4_DATA21_MARK,
3965     VI4_DATA22_MARK, VI4_DATA23_MARK,
3966 };
3967 static const unsigned int vin4_data18_b_pins[] = {
3968     RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3969     RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3970     RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3971     RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3972     RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3973     RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3974     RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3975     RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3976     RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3977 };
3978 static const unsigned int vin4_data18_b_mux[] = {
3979     VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3980     VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3981     VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3982     VI4_DATA10_MARK, VI4_DATA11_MARK,
3983     VI4_DATA12_MARK, VI4_DATA13_MARK,
3984     VI4_DATA14_MARK, VI4_DATA15_MARK,
3985     VI4_DATA18_MARK, VI4_DATA19_MARK,
3986     VI4_DATA20_MARK, VI4_DATA21_MARK,
3987     VI4_DATA22_MARK, VI4_DATA23_MARK,
3988 };
3989 static const unsigned int vin4_data_a_pins[] = {
3990     RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3991     RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3992     RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3993     RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3994     RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3995     RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3996     RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3997     RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3998     RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3999     RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4000     RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4001     RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4002 };
4003 static const unsigned int vin4_data_a_mux[] = {
4004     VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4005     VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4006     VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4007     VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4008     VI4_DATA8_MARK,  VI4_DATA9_MARK,
4009     VI4_DATA10_MARK, VI4_DATA11_MARK,
4010     VI4_DATA12_MARK, VI4_DATA13_MARK,
4011     VI4_DATA14_MARK, VI4_DATA15_MARK,
4012     VI4_DATA16_MARK, VI4_DATA17_MARK,
4013     VI4_DATA18_MARK, VI4_DATA19_MARK,
4014     VI4_DATA20_MARK, VI4_DATA21_MARK,
4015     VI4_DATA22_MARK, VI4_DATA23_MARK,
4016 };
4017 static const unsigned int vin4_data_b_pins[] = {
4018     RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4019     RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4020     RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4021     RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4022     RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4023     RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4024     RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4025     RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4026     RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4027     RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4028     RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4029     RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4030 };
4031 static const unsigned int vin4_data_b_mux[] = {
4032     VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4033     VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4034     VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4035     VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4036     VI4_DATA8_MARK,  VI4_DATA9_MARK,
4037     VI4_DATA10_MARK, VI4_DATA11_MARK,
4038     VI4_DATA12_MARK, VI4_DATA13_MARK,
4039     VI4_DATA14_MARK, VI4_DATA15_MARK,
4040     VI4_DATA16_MARK, VI4_DATA17_MARK,
4041     VI4_DATA18_MARK, VI4_DATA19_MARK,
4042     VI4_DATA20_MARK, VI4_DATA21_MARK,
4043     VI4_DATA22_MARK, VI4_DATA23_MARK,
4044 };
4045 static const unsigned int vin4_sync_pins[] = {
4046     /* HSYNC#, VSYNC# */
4047     RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4048 };
4049 static const unsigned int vin4_sync_mux[] = {
4050     VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4051 };
4052 static const unsigned int vin4_field_pins[] = {
4053     /* FIELD */
4054     RCAR_GP_PIN(1, 16),
4055 };
4056 static const unsigned int vin4_field_mux[] = {
4057     VI4_FIELD_MARK,
4058 };
4059 static const unsigned int vin4_clkenb_pins[] = {
4060     /* CLKENB */
4061     RCAR_GP_PIN(1, 19),
4062 };
4063 static const unsigned int vin4_clkenb_mux[] = {
4064     VI4_CLKENB_MARK,
4065 };
4066 static const unsigned int vin4_clk_pins[] = {
4067     /* CLK */
4068     RCAR_GP_PIN(1, 27),
4069 };
4070 static const unsigned int vin4_clk_mux[] = {
4071     VI4_CLK_MARK,
4072 };
4073
4074 /* - VIN5 ------------------------------------------------------------------- */
4075 static const unsigned int vin5_data_pins[] = {
4076     RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4077     RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4078     RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4079     RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4080     RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4081     RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4082     RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4083     RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4084 };
4085 static const unsigned int vin5_data_mux[] = {
4086     VI5_DATA0_MARK, VI5_DATA1_MARK,
4087     VI5_DATA2_MARK, VI5_DATA3_MARK,
4088     VI5_DATA4_MARK, VI5_DATA5_MARK,
4089     VI5_DATA6_MARK, VI5_DATA7_MARK,
4090     VI5_DATA8_MARK,  VI5_DATA9_MARK,
4091     VI5_DATA10_MARK, VI5_DATA11_MARK,
4092     VI5_DATA12_MARK, VI5_DATA13_MARK,
4093     VI5_DATA14_MARK, VI5_DATA15_MARK,
4094 };
4095 static const unsigned int vin5_sync_pins[] = {
4096     /* HSYNC#, VSYNC# */
4097     RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4098 };
4099 static const unsigned int vin5_sync_mux[] = {
4100     VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4101 };
4102 static const unsigned int vin5_field_pins[] = {
4103     RCAR_GP_PIN(1, 11),
4104 };
4105 static const unsigned int vin5_field_mux[] = {
4106     /* FIELD */
4107     VI5_FIELD_MARK,
4108 };
4109 static const unsigned int vin5_clkenb_pins[] = {
4110     RCAR_GP_PIN(1, 20),
4111 };
4112 static const unsigned int vin5_clkenb_mux[] = {
4113     /* CLKENB */
4114     VI5_CLKENB_MARK,
4115 };
4116 static const unsigned int vin5_clk_pins[] = {
4117     RCAR_GP_PIN(1, 21),
4118 };
4119 static const unsigned int vin5_clk_mux[] = {
4120     /* CLK */
4121     VI5_CLK_MARK,
4122 };
4123
4124 static const struct {
4125     struct sh_pfc_pin_group common[324];
4126 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4127     struct sh_pfc_pin_group automotive[31];
4128 #endif
4129 } pinmux_groups = {
4130     .common = {
4131         SH_PFC_PIN_GROUP(audio_clk_a_a),
4132         SH_PFC_PIN_GROUP(audio_clk_a_b),
4133         SH_PFC_PIN_GROUP(audio_clk_a_c),
4134         SH_PFC_PIN_GROUP(audio_clk_b_a),
4135         SH_PFC_PIN_GROUP(audio_clk_b_b),
4136         SH_PFC_PIN_GROUP(audio_clk_c_a),
4137         SH_PFC_PIN_GROUP(audio_clk_c_b),
4138         SH_PFC_PIN_GROUP(audio_clkout_a),
4139         SH_PFC_PIN_GROUP(audio_clkout_b),
4140         SH_PFC_PIN_GROUP(audio_clkout_c),
4141         SH_PFC_PIN_GROUP(audio_clkout_d),
4142         SH_PFC_PIN_GROUP(audio_clkout1_a),
4143         SH_PFC_PIN_GROUP(audio_clkout1_b),
4144         SH_PFC_PIN_GROUP(audio_clkout2_a),
4145         SH_PFC_PIN_GROUP(audio_clkout2_b),
4146         SH_PFC_PIN_GROUP(audio_clkout3_a),
4147         SH_PFC_PIN_GROUP(audio_clkout3_b),
4148         SH_PFC_PIN_GROUP(avb_link),
4149         SH_PFC_PIN_GROUP(avb_magic),
4150         SH_PFC_PIN_GROUP(avb_phy_int),
4151         SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio),  /* Deprecated */
4152         SH_PFC_PIN_GROUP(avb_mdio),
4153         SH_PFC_PIN_GROUP(avb_mii),
4154         SH_PFC_PIN_GROUP(avb_avtp_pps),
4155         SH_PFC_PIN_GROUP(avb_avtp_match_a),
4156         SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4157         SH_PFC_PIN_GROUP(avb_avtp_match_b),
4158         SH_PFC_PIN_GROUP(avb_avtp_capture_b),
4159         SH_PFC_PIN_GROUP(can0_data_a),
4160         SH_PFC_PIN_GROUP(can0_data_b),
4161         SH_PFC_PIN_GROUP(can1_data),
4162         SH_PFC_PIN_GROUP(can_clk),
4163         SH_PFC_PIN_GROUP(canfd0_data_a),
4164         SH_PFC_PIN_GROUP(canfd0_data_b),
4165         SH_PFC_PIN_GROUP(canfd1_data),
4166         SH_PFC_PIN_GROUP(du_rgb666),
4167         SH_PFC_PIN_GROUP(du_rgb888),
4168         SH_PFC_PIN_GROUP(du_clk_out_0),
4169         SH_PFC_PIN_GROUP(du_clk_out_1),
4170         SH_PFC_PIN_GROUP(du_sync),
4171         SH_PFC_PIN_GROUP(du_oddf),
4172         SH_PFC_PIN_GROUP(du_cde),
4173         SH_PFC_PIN_GROUP(du_disp),
4174         SH_PFC_PIN_GROUP(hscif0_data),
4175         SH_PFC_PIN_GROUP(hscif0_clk),
4176         SH_PFC_PIN_GROUP(hscif0_ctrl),
4177         SH_PFC_PIN_GROUP(hscif1_data_a),
4178         SH_PFC_PIN_GROUP(hscif1_clk_a),
4179         SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4180         SH_PFC_PIN_GROUP(hscif1_data_b),
4181         SH_PFC_PIN_GROUP(hscif1_clk_b),
4182         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4183         SH_PFC_PIN_GROUP(hscif2_data_a),
4184         SH_PFC_PIN_GROUP(hscif2_clk_a),
4185         SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4186         SH_PFC_PIN_GROUP(hscif2_data_b),
4187         SH_PFC_PIN_GROUP(hscif2_clk_b),
4188         SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4189         SH_PFC_PIN_GROUP(hscif2_data_c),
4190         SH_PFC_PIN_GROUP(hscif2_clk_c),
4191         SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4192         SH_PFC_PIN_GROUP(hscif3_data_a),
4193         SH_PFC_PIN_GROUP(hscif3_clk),
4194         SH_PFC_PIN_GROUP(hscif3_ctrl),
4195         SH_PFC_PIN_GROUP(hscif3_data_b),
4196         SH_PFC_PIN_GROUP(hscif3_data_c),
4197         SH_PFC_PIN_GROUP(hscif3_data_d),
4198         SH_PFC_PIN_GROUP(hscif4_data_a),
4199         SH_PFC_PIN_GROUP(hscif4_clk),
4200         SH_PFC_PIN_GROUP(hscif4_ctrl),
4201         SH_PFC_PIN_GROUP(hscif4_data_b),
4202         SH_PFC_PIN_GROUP(i2c0),
4203         SH_PFC_PIN_GROUP(i2c1_a),
4204         SH_PFC_PIN_GROUP(i2c1_b),
4205         SH_PFC_PIN_GROUP(i2c2_a),
4206         SH_PFC_PIN_GROUP(i2c2_b),
4207         SH_PFC_PIN_GROUP(i2c3),
4208         SH_PFC_PIN_GROUP(i2c5),
4209         SH_PFC_PIN_GROUP(i2c6_a),
4210         SH_PFC_PIN_GROUP(i2c6_b),
4211         SH_PFC_PIN_GROUP(i2c6_c),
4212         SH_PFC_PIN_GROUP(intc_ex_irq0),
4213         SH_PFC_PIN_GROUP(intc_ex_irq1),
4214         SH_PFC_PIN_GROUP(intc_ex_irq2),
4215         SH_PFC_PIN_GROUP(intc_ex_irq3),
4216         SH_PFC_PIN_GROUP(intc_ex_irq4),
4217         SH_PFC_PIN_GROUP(intc_ex_irq5),
4218         SH_PFC_PIN_GROUP(msiof0_clk),
4219         SH_PFC_PIN_GROUP(msiof0_sync),
4220         SH_PFC_PIN_GROUP(msiof0_ss1),
4221         SH_PFC_PIN_GROUP(msiof0_ss2),
4222         SH_PFC_PIN_GROUP(msiof0_txd),
4223         SH_PFC_PIN_GROUP(msiof0_rxd),
4224         SH_PFC_PIN_GROUP(msiof1_clk_a),
4225         SH_PFC_PIN_GROUP(msiof1_sync_a),
4226         SH_PFC_PIN_GROUP(msiof1_ss1_a),
4227         SH_PFC_PIN_GROUP(msiof1_ss2_a),
4228         SH_PFC_PIN_GROUP(msiof1_txd_a),
4229         SH_PFC_PIN_GROUP(msiof1_rxd_a),
4230         SH_PFC_PIN_GROUP(msiof1_clk_b),
4231         SH_PFC_PIN_GROUP(msiof1_sync_b),
4232         SH_PFC_PIN_GROUP(msiof1_ss1_b),
4233         SH_PFC_PIN_GROUP(msiof1_ss2_b),
4234         SH_PFC_PIN_GROUP(msiof1_txd_b),
4235         SH_PFC_PIN_GROUP(msiof1_rxd_b),
4236         SH_PFC_PIN_GROUP(msiof1_clk_c),
4237         SH_PFC_PIN_GROUP(msiof1_sync_c),
4238         SH_PFC_PIN_GROUP(msiof1_ss1_c),
4239         SH_PFC_PIN_GROUP(msiof1_ss2_c),
4240         SH_PFC_PIN_GROUP(msiof1_txd_c),
4241         SH_PFC_PIN_GROUP(msiof1_rxd_c),
4242         SH_PFC_PIN_GROUP(msiof1_clk_d),
4243         SH_PFC_PIN_GROUP(msiof1_sync_d),
4244         SH_PFC_PIN_GROUP(msiof1_ss1_d),
4245         SH_PFC_PIN_GROUP(msiof1_ss2_d),
4246         SH_PFC_PIN_GROUP(msiof1_txd_d),
4247         SH_PFC_PIN_GROUP(msiof1_rxd_d),
4248         SH_PFC_PIN_GROUP(msiof1_clk_e),
4249         SH_PFC_PIN_GROUP(msiof1_sync_e),
4250         SH_PFC_PIN_GROUP(msiof1_ss1_e),
4251         SH_PFC_PIN_GROUP(msiof1_ss2_e),
4252         SH_PFC_PIN_GROUP(msiof1_txd_e),
4253         SH_PFC_PIN_GROUP(msiof1_rxd_e),
4254         SH_PFC_PIN_GROUP(msiof1_clk_f),
4255         SH_PFC_PIN_GROUP(msiof1_sync_f),
4256         SH_PFC_PIN_GROUP(msiof1_ss1_f),
4257         SH_PFC_PIN_GROUP(msiof1_ss2_f),
4258         SH_PFC_PIN_GROUP(msiof1_txd_f),
4259         SH_PFC_PIN_GROUP(msiof1_rxd_f),
4260         SH_PFC_PIN_GROUP(msiof1_clk_g),
4261         SH_PFC_PIN_GROUP(msiof1_sync_g),
4262         SH_PFC_PIN_GROUP(msiof1_ss1_g),
4263         SH_PFC_PIN_GROUP(msiof1_ss2_g),
4264         SH_PFC_PIN_GROUP(msiof1_txd_g),
4265         SH_PFC_PIN_GROUP(msiof1_rxd_g),
4266         SH_PFC_PIN_GROUP(msiof2_clk_a),
4267         SH_PFC_PIN_GROUP(msiof2_sync_a),
4268         SH_PFC_PIN_GROUP(msiof2_ss1_a),
4269         SH_PFC_PIN_GROUP(msiof2_ss2_a),
4270         SH_PFC_PIN_GROUP(msiof2_txd_a),
4271         SH_PFC_PIN_GROUP(msiof2_rxd_a),
4272         SH_PFC_PIN_GROUP(msiof2_clk_b),
4273         SH_PFC_PIN_GROUP(msiof2_sync_b),
4274         SH_PFC_PIN_GROUP(msiof2_ss1_b),
4275         SH_PFC_PIN_GROUP(msiof2_ss2_b),
4276         SH_PFC_PIN_GROUP(msiof2_txd_b),
4277         SH_PFC_PIN_GROUP(msiof2_rxd_b),
4278         SH_PFC_PIN_GROUP(msiof2_clk_c),
4279         SH_PFC_PIN_GROUP(msiof2_sync_c),
4280         SH_PFC_PIN_GROUP(msiof2_ss1_c),
4281         SH_PFC_PIN_GROUP(msiof2_ss2_c),
4282         SH_PFC_PIN_GROUP(msiof2_txd_c),
4283         SH_PFC_PIN_GROUP(msiof2_rxd_c),
4284         SH_PFC_PIN_GROUP(msiof2_clk_d),
4285         SH_PFC_PIN_GROUP(msiof2_sync_d),
4286         SH_PFC_PIN_GROUP(msiof2_ss1_d),
4287         SH_PFC_PIN_GROUP(msiof2_ss2_d),
4288         SH_PFC_PIN_GROUP(msiof2_txd_d),
4289         SH_PFC_PIN_GROUP(msiof2_rxd_d),
4290         SH_PFC_PIN_GROUP(msiof3_clk_a),
4291         SH_PFC_PIN_GROUP(msiof3_sync_a),
4292         SH_PFC_PIN_GROUP(msiof3_ss1_a),
4293         SH_PFC_PIN_GROUP(msiof3_ss2_a),
4294         SH_PFC_PIN_GROUP(msiof3_txd_a),
4295         SH_PFC_PIN_GROUP(msiof3_rxd_a),
4296         SH_PFC_PIN_GROUP(msiof3_clk_b),
4297         SH_PFC_PIN_GROUP(msiof3_sync_b),
4298         SH_PFC_PIN_GROUP(msiof3_ss1_b),
4299         SH_PFC_PIN_GROUP(msiof3_ss2_b),
4300         SH_PFC_PIN_GROUP(msiof3_txd_b),
4301         SH_PFC_PIN_GROUP(msiof3_rxd_b),
4302         SH_PFC_PIN_GROUP(msiof3_clk_c),
4303         SH_PFC_PIN_GROUP(msiof3_sync_c),
4304         SH_PFC_PIN_GROUP(msiof3_txd_c),
4305         SH_PFC_PIN_GROUP(msiof3_rxd_c),
4306         SH_PFC_PIN_GROUP(msiof3_clk_d),
4307         SH_PFC_PIN_GROUP(msiof3_sync_d),
4308         SH_PFC_PIN_GROUP(msiof3_ss1_d),
4309         SH_PFC_PIN_GROUP(msiof3_txd_d),
4310         SH_PFC_PIN_GROUP(msiof3_rxd_d),
4311         SH_PFC_PIN_GROUP(msiof3_clk_e),
4312         SH_PFC_PIN_GROUP(msiof3_sync_e),
4313         SH_PFC_PIN_GROUP(msiof3_ss1_e),
4314         SH_PFC_PIN_GROUP(msiof3_ss2_e),
4315         SH_PFC_PIN_GROUP(msiof3_txd_e),
4316         SH_PFC_PIN_GROUP(msiof3_rxd_e),
4317         SH_PFC_PIN_GROUP(pwm0),
4318         SH_PFC_PIN_GROUP(pwm1_a),
4319         SH_PFC_PIN_GROUP(pwm1_b),
4320         SH_PFC_PIN_GROUP(pwm2_a),
4321         SH_PFC_PIN_GROUP(pwm2_b),
4322         SH_PFC_PIN_GROUP(pwm3_a),
4323         SH_PFC_PIN_GROUP(pwm3_b),
4324         SH_PFC_PIN_GROUP(pwm4_a),
4325         SH_PFC_PIN_GROUP(pwm4_b),
4326         SH_PFC_PIN_GROUP(pwm5_a),
4327         SH_PFC_PIN_GROUP(pwm5_b),
4328         SH_PFC_PIN_GROUP(pwm6_a),
4329         SH_PFC_PIN_GROUP(pwm6_b),
4330         SH_PFC_PIN_GROUP(qspi0_ctrl),
4331         BUS_DATA_PIN_GROUP(qspi0_data, 2),
4332         BUS_DATA_PIN_GROUP(qspi0_data, 4),
4333         SH_PFC_PIN_GROUP(qspi1_ctrl),
4334         BUS_DATA_PIN_GROUP(qspi1_data, 2),
4335         BUS_DATA_PIN_GROUP(qspi1_data, 4),
4336         SH_PFC_PIN_GROUP(scif0_data),
4337         SH_PFC_PIN_GROUP(scif0_clk),
4338         SH_PFC_PIN_GROUP(scif0_ctrl),
4339         SH_PFC_PIN_GROUP(scif1_data_a),
4340         SH_PFC_PIN_GROUP(scif1_clk),
4341         SH_PFC_PIN_GROUP(scif1_ctrl),
4342         SH_PFC_PIN_GROUP(scif1_data_b),
4343         SH_PFC_PIN_GROUP(scif2_data_a),
4344         SH_PFC_PIN_GROUP(scif2_clk),
4345         SH_PFC_PIN_GROUP(scif2_data_b),
4346         SH_PFC_PIN_GROUP(scif3_data_a),
4347         SH_PFC_PIN_GROUP(scif3_clk),
4348         SH_PFC_PIN_GROUP(scif3_ctrl),
4349         SH_PFC_PIN_GROUP(scif3_data_b),
4350         SH_PFC_PIN_GROUP(scif4_data_a),
4351         SH_PFC_PIN_GROUP(scif4_clk_a),
4352         SH_PFC_PIN_GROUP(scif4_ctrl_a),
4353         SH_PFC_PIN_GROUP(scif4_data_b),
4354         SH_PFC_PIN_GROUP(scif4_clk_b),
4355         SH_PFC_PIN_GROUP(scif4_ctrl_b),
4356         SH_PFC_PIN_GROUP(scif4_data_c),
4357         SH_PFC_PIN_GROUP(scif4_clk_c),
4358         SH_PFC_PIN_GROUP(scif4_ctrl_c),
4359         SH_PFC_PIN_GROUP(scif5_data_a),
4360         SH_PFC_PIN_GROUP(scif5_clk_a),
4361         SH_PFC_PIN_GROUP(scif5_data_b),
4362         SH_PFC_PIN_GROUP(scif5_clk_b),
4363         SH_PFC_PIN_GROUP(scif_clk_a),
4364         SH_PFC_PIN_GROUP(scif_clk_b),
4365         BUS_DATA_PIN_GROUP(sdhi0_data, 1),
4366         BUS_DATA_PIN_GROUP(sdhi0_data, 4),
4367         SH_PFC_PIN_GROUP(sdhi0_ctrl),
4368         SH_PFC_PIN_GROUP(sdhi0_cd),
4369         SH_PFC_PIN_GROUP(sdhi0_wp),
4370         BUS_DATA_PIN_GROUP(sdhi1_data, 1),
4371         BUS_DATA_PIN_GROUP(sdhi1_data, 4),
4372         SH_PFC_PIN_GROUP(sdhi1_ctrl),
4373         SH_PFC_PIN_GROUP(sdhi1_cd),
4374         SH_PFC_PIN_GROUP(sdhi1_wp),
4375         BUS_DATA_PIN_GROUP(sdhi2_data, 1),
4376         BUS_DATA_PIN_GROUP(sdhi2_data, 4),
4377         BUS_DATA_PIN_GROUP(sdhi2_data, 8),
4378         SH_PFC_PIN_GROUP(sdhi2_ctrl),
4379         SH_PFC_PIN_GROUP(sdhi2_cd_a),
4380         SH_PFC_PIN_GROUP(sdhi2_wp_a),
4381         SH_PFC_PIN_GROUP(sdhi2_cd_b),
4382         SH_PFC_PIN_GROUP(sdhi2_wp_b),
4383         SH_PFC_PIN_GROUP(sdhi2_ds),
4384         BUS_DATA_PIN_GROUP(sdhi3_data, 1),
4385         BUS_DATA_PIN_GROUP(sdhi3_data, 4),
4386         BUS_DATA_PIN_GROUP(sdhi3_data, 8),
4387         SH_PFC_PIN_GROUP(sdhi3_ctrl),
4388         SH_PFC_PIN_GROUP(sdhi3_cd),
4389         SH_PFC_PIN_GROUP(sdhi3_wp),
4390         SH_PFC_PIN_GROUP(sdhi3_ds),
4391         SH_PFC_PIN_GROUP(ssi0_data),
4392         SH_PFC_PIN_GROUP(ssi01239_ctrl),
4393         SH_PFC_PIN_GROUP(ssi1_data_a),
4394         SH_PFC_PIN_GROUP(ssi1_data_b),
4395         SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4396         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4397         SH_PFC_PIN_GROUP(ssi2_data_a),
4398         SH_PFC_PIN_GROUP(ssi2_data_b),
4399         SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4400         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4401         SH_PFC_PIN_GROUP(ssi3_data),
4402         SH_PFC_PIN_GROUP(ssi349_ctrl),
4403         SH_PFC_PIN_GROUP(ssi4_data),
4404         SH_PFC_PIN_GROUP(ssi4_ctrl),
4405         SH_PFC_PIN_GROUP(ssi5_data),
4406         SH_PFC_PIN_GROUP(ssi5_ctrl),
4407         SH_PFC_PIN_GROUP(ssi6_data),
4408         SH_PFC_PIN_GROUP(ssi6_ctrl),
4409         SH_PFC_PIN_GROUP(ssi7_data),
4410         SH_PFC_PIN_GROUP(ssi78_ctrl),
4411         SH_PFC_PIN_GROUP(ssi8_data),
4412         SH_PFC_PIN_GROUP(ssi9_data_a),
4413         SH_PFC_PIN_GROUP(ssi9_data_b),
4414         SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4415         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4416         SH_PFC_PIN_GROUP(tmu_tclk1_a),
4417         SH_PFC_PIN_GROUP(tmu_tclk1_b),
4418         SH_PFC_PIN_GROUP(tmu_tclk2_a),
4419         SH_PFC_PIN_GROUP(tmu_tclk2_b),
4420         SH_PFC_PIN_GROUP(tpu_to0),
4421         SH_PFC_PIN_GROUP(tpu_to1),
4422         SH_PFC_PIN_GROUP(tpu_to2),
4423         SH_PFC_PIN_GROUP(tpu_to3),
4424         SH_PFC_PIN_GROUP(usb0),
4425         SH_PFC_PIN_GROUP(usb1),
4426         SH_PFC_PIN_GROUP(usb30),
4427         BUS_DATA_PIN_GROUP(vin4_data, 8, _a),
4428         BUS_DATA_PIN_GROUP(vin4_data, 10, _a),
4429         BUS_DATA_PIN_GROUP(vin4_data, 12, _a),
4430         BUS_DATA_PIN_GROUP(vin4_data, 16, _a),
4431         SH_PFC_PIN_GROUP(vin4_data18_a),
4432         BUS_DATA_PIN_GROUP(vin4_data, 20, _a),
4433         BUS_DATA_PIN_GROUP(vin4_data, 24, _a),
4434         BUS_DATA_PIN_GROUP(vin4_data, 8, _b),
4435         BUS_DATA_PIN_GROUP(vin4_data, 10, _b),
4436         BUS_DATA_PIN_GROUP(vin4_data, 12, _b),
4437         BUS_DATA_PIN_GROUP(vin4_data, 16, _b),
4438         SH_PFC_PIN_GROUP(vin4_data18_b),
4439         BUS_DATA_PIN_GROUP(vin4_data, 20, _b),
4440         BUS_DATA_PIN_GROUP(vin4_data, 24, _b),
4441         SH_PFC_PIN_GROUP_SUBSET(vin4_g8, vin4_data_a, 8, 8),
4442         SH_PFC_PIN_GROUP(vin4_sync),
4443         SH_PFC_PIN_GROUP(vin4_field),
4444         SH_PFC_PIN_GROUP(vin4_clkenb),
4445         SH_PFC_PIN_GROUP(vin4_clk),
4446         BUS_DATA_PIN_GROUP(vin5_data, 8),
4447         BUS_DATA_PIN_GROUP(vin5_data, 10),
4448         BUS_DATA_PIN_GROUP(vin5_data, 12),
4449         BUS_DATA_PIN_GROUP(vin5_data, 16),
4450         SH_PFC_PIN_GROUP_SUBSET(vin5_high8, vin5_data, 8, 8),
4451         SH_PFC_PIN_GROUP(vin5_sync),
4452         SH_PFC_PIN_GROUP(vin5_field),
4453         SH_PFC_PIN_GROUP(vin5_clkenb),
4454         SH_PFC_PIN_GROUP(vin5_clk),
4455     },
4456 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4457     .automotive = {
4458         SH_PFC_PIN_GROUP(drif0_ctrl_a),
4459         SH_PFC_PIN_GROUP(drif0_data0_a),
4460         SH_PFC_PIN_GROUP(drif0_data1_a),
4461         SH_PFC_PIN_GROUP(drif0_ctrl_b),
4462         SH_PFC_PIN_GROUP(drif0_data0_b),
4463         SH_PFC_PIN_GROUP(drif0_data1_b),
4464         SH_PFC_PIN_GROUP(drif0_ctrl_c),
4465         SH_PFC_PIN_GROUP(drif0_data0_c),
4466         SH_PFC_PIN_GROUP(drif0_data1_c),
4467         SH_PFC_PIN_GROUP(drif1_ctrl_a),
4468         SH_PFC_PIN_GROUP(drif1_data0_a),
4469         SH_PFC_PIN_GROUP(drif1_data1_a),
4470         SH_PFC_PIN_GROUP(drif1_ctrl_b),
4471         SH_PFC_PIN_GROUP(drif1_data0_b),
4472         SH_PFC_PIN_GROUP(drif1_data1_b),
4473         SH_PFC_PIN_GROUP(drif1_ctrl_c),
4474         SH_PFC_PIN_GROUP(drif1_data0_c),
4475         SH_PFC_PIN_GROUP(drif1_data1_c),
4476         SH_PFC_PIN_GROUP(drif2_ctrl_a),
4477         SH_PFC_PIN_GROUP(drif2_data0_a),
4478         SH_PFC_PIN_GROUP(drif2_data1_a),
4479         SH_PFC_PIN_GROUP(drif2_ctrl_b),
4480         SH_PFC_PIN_GROUP(drif2_data0_b),
4481         SH_PFC_PIN_GROUP(drif2_data1_b),
4482         SH_PFC_PIN_GROUP(drif3_ctrl_a),
4483         SH_PFC_PIN_GROUP(drif3_data0_a),
4484         SH_PFC_PIN_GROUP(drif3_data1_a),
4485         SH_PFC_PIN_GROUP(drif3_ctrl_b),
4486         SH_PFC_PIN_GROUP(drif3_data0_b),
4487         SH_PFC_PIN_GROUP(drif3_data1_b),
4488         SH_PFC_PIN_GROUP(mlb_3pin),
4489     }
4490 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
4491 };
4492
4493 static const char * const audio_clk_groups[] = {
4494     "audio_clk_a_a",
4495     "audio_clk_a_b",
4496     "audio_clk_a_c",
4497     "audio_clk_b_a",
4498     "audio_clk_b_b",
4499     "audio_clk_c_a",
4500     "audio_clk_c_b",
4501     "audio_clkout_a",
4502     "audio_clkout_b",
4503     "audio_clkout_c",
4504     "audio_clkout_d",
4505     "audio_clkout1_a",
4506     "audio_clkout1_b",
4507     "audio_clkout2_a",
4508     "audio_clkout2_b",
4509     "audio_clkout3_a",
4510     "audio_clkout3_b",
4511 };
4512
4513 static const char * const avb_groups[] = {
4514     "avb_link",
4515     "avb_magic",
4516     "avb_phy_int",
4517     "avb_mdc",  /* Deprecated, please use "avb_mdio" instead */
4518     "avb_mdio",
4519     "avb_mii",
4520     "avb_avtp_pps",
4521     "avb_avtp_match_a",
4522     "avb_avtp_capture_a",
4523     "avb_avtp_match_b",
4524     "avb_avtp_capture_b",
4525 };
4526
4527 static const char * const can0_groups[] = {
4528     "can0_data_a",
4529     "can0_data_b",
4530 };
4531
4532 static const char * const can1_groups[] = {
4533     "can1_data",
4534 };
4535
4536 static const char * const can_clk_groups[] = {
4537     "can_clk",
4538 };
4539
4540 static const char * const canfd0_groups[] = {
4541     "canfd0_data_a",
4542     "canfd0_data_b",
4543 };
4544
4545 static const char * const canfd1_groups[] = {
4546     "canfd1_data",
4547 };
4548
4549 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4550 static const char * const drif0_groups[] = {
4551     "drif0_ctrl_a",
4552     "drif0_data0_a",
4553     "drif0_data1_a",
4554     "drif0_ctrl_b",
4555     "drif0_data0_b",
4556     "drif0_data1_b",
4557     "drif0_ctrl_c",
4558     "drif0_data0_c",
4559     "drif0_data1_c",
4560 };
4561
4562 static const char * const drif1_groups[] = {
4563     "drif1_ctrl_a",
4564     "drif1_data0_a",
4565     "drif1_data1_a",
4566     "drif1_ctrl_b",
4567     "drif1_data0_b",
4568     "drif1_data1_b",
4569     "drif1_ctrl_c",
4570     "drif1_data0_c",
4571     "drif1_data1_c",
4572 };
4573
4574 static const char * const drif2_groups[] = {
4575     "drif2_ctrl_a",
4576     "drif2_data0_a",
4577     "drif2_data1_a",
4578     "drif2_ctrl_b",
4579     "drif2_data0_b",
4580     "drif2_data1_b",
4581 };
4582
4583 static const char * const drif3_groups[] = {
4584     "drif3_ctrl_a",
4585     "drif3_data0_a",
4586     "drif3_data1_a",
4587     "drif3_ctrl_b",
4588     "drif3_data0_b",
4589     "drif3_data1_b",
4590 };
4591 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
4592
4593 static const char * const du_groups[] = {
4594     "du_rgb666",
4595     "du_rgb888",
4596     "du_clk_out_0",
4597     "du_clk_out_1",
4598     "du_sync",
4599     "du_oddf",
4600     "du_cde",
4601     "du_disp",
4602 };
4603
4604 static const char * const hscif0_groups[] = {
4605     "hscif0_data",
4606     "hscif0_clk",
4607     "hscif0_ctrl",
4608 };
4609
4610 static const char * const hscif1_groups[] = {
4611     "hscif1_data_a",
4612     "hscif1_clk_a",
4613     "hscif1_ctrl_a",
4614     "hscif1_data_b",
4615     "hscif1_clk_b",
4616     "hscif1_ctrl_b",
4617 };
4618
4619 static const char * const hscif2_groups[] = {
4620     "hscif2_data_a",
4621     "hscif2_clk_a",
4622     "hscif2_ctrl_a",
4623     "hscif2_data_b",
4624     "hscif2_clk_b",
4625     "hscif2_ctrl_b",
4626     "hscif2_data_c",
4627     "hscif2_clk_c",
4628     "hscif2_ctrl_c",
4629 };
4630
4631 static const char * const hscif3_groups[] = {
4632     "hscif3_data_a",
4633     "hscif3_clk",
4634     "hscif3_ctrl",
4635     "hscif3_data_b",
4636     "hscif3_data_c",
4637     "hscif3_data_d",
4638 };
4639
4640 static const char * const hscif4_groups[] = {
4641     "hscif4_data_a",
4642     "hscif4_clk",
4643     "hscif4_ctrl",
4644     "hscif4_data_b",
4645 };
4646
4647 static const char * const i2c0_groups[] = {
4648     "i2c0",
4649 };
4650
4651 static const char * const i2c1_groups[] = {
4652     "i2c1_a",
4653     "i2c1_b",
4654 };
4655
4656 static const char * const i2c2_groups[] = {
4657     "i2c2_a",
4658     "i2c2_b",
4659 };
4660
4661 static const char * const i2c3_groups[] = {
4662     "i2c3",
4663 };
4664
4665 static const char * const i2c5_groups[] = {
4666     "i2c5",
4667 };
4668
4669 static const char * const i2c6_groups[] = {
4670     "i2c6_a",
4671     "i2c6_b",
4672     "i2c6_c",
4673 };
4674
4675 static const char * const intc_ex_groups[] = {
4676     "intc_ex_irq0",
4677     "intc_ex_irq1",
4678     "intc_ex_irq2",
4679     "intc_ex_irq3",
4680     "intc_ex_irq4",
4681     "intc_ex_irq5",
4682 };
4683
4684 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
4685 static const char * const mlb_3pin_groups[] = {
4686     "mlb_3pin",
4687 };
4688 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
4689
4690 static const char * const msiof0_groups[] = {
4691     "msiof0_clk",
4692     "msiof0_sync",
4693     "msiof0_ss1",
4694     "msiof0_ss2",
4695     "msiof0_txd",
4696     "msiof0_rxd",
4697 };
4698
4699 static const char * const msiof1_groups[] = {
4700     "msiof1_clk_a",
4701     "msiof1_sync_a",
4702     "msiof1_ss1_a",
4703     "msiof1_ss2_a",
4704     "msiof1_txd_a",
4705     "msiof1_rxd_a",
4706     "msiof1_clk_b",
4707     "msiof1_sync_b",
4708     "msiof1_ss1_b",
4709     "msiof1_ss2_b",
4710     "msiof1_txd_b",
4711     "msiof1_rxd_b",
4712     "msiof1_clk_c",
4713     "msiof1_sync_c",
4714     "msiof1_ss1_c",
4715     "msiof1_ss2_c",
4716     "msiof1_txd_c",
4717     "msiof1_rxd_c",
4718     "msiof1_clk_d",
4719     "msiof1_sync_d",
4720     "msiof1_ss1_d",
4721     "msiof1_ss2_d",
4722     "msiof1_txd_d",
4723     "msiof1_rxd_d",
4724     "msiof1_clk_e",
4725     "msiof1_sync_e",
4726     "msiof1_ss1_e",
4727     "msiof1_ss2_e",
4728     "msiof1_txd_e",
4729     "msiof1_rxd_e",
4730     "msiof1_clk_f",
4731     "msiof1_sync_f",
4732     "msiof1_ss1_f",
4733     "msiof1_ss2_f",
4734     "msiof1_txd_f",
4735     "msiof1_rxd_f",
4736     "msiof1_clk_g",
4737     "msiof1_sync_g",
4738     "msiof1_ss1_g",
4739     "msiof1_ss2_g",
4740     "msiof1_txd_g",
4741     "msiof1_rxd_g",
4742 };
4743
4744 static const char * const msiof2_groups[] = {
4745     "msiof2_clk_a",
4746     "msiof2_sync_a",
4747     "msiof2_ss1_a",
4748     "msiof2_ss2_a",
4749     "msiof2_txd_a",
4750     "msiof2_rxd_a",
4751     "msiof2_clk_b",
4752     "msiof2_sync_b",
4753     "msiof2_ss1_b",
4754     "msiof2_ss2_b",
4755     "msiof2_txd_b",
4756     "msiof2_rxd_b",
4757     "msiof2_clk_c",
4758     "msiof2_sync_c",
4759     "msiof2_ss1_c",
4760     "msiof2_ss2_c",
4761     "msiof2_txd_c",
4762     "msiof2_rxd_c",
4763     "msiof2_clk_d",
4764     "msiof2_sync_d",
4765     "msiof2_ss1_d",
4766     "msiof2_ss2_d",
4767     "msiof2_txd_d",
4768     "msiof2_rxd_d",
4769 };
4770
4771 static const char * const msiof3_groups[] = {
4772     "msiof3_clk_a",
4773     "msiof3_sync_a",
4774     "msiof3_ss1_a",
4775     "msiof3_ss2_a",
4776     "msiof3_txd_a",
4777     "msiof3_rxd_a",
4778     "msiof3_clk_b",
4779     "msiof3_sync_b",
4780     "msiof3_ss1_b",
4781     "msiof3_ss2_b",
4782     "msiof3_txd_b",
4783     "msiof3_rxd_b",
4784     "msiof3_clk_c",
4785     "msiof3_sync_c",
4786     "msiof3_txd_c",
4787     "msiof3_rxd_c",
4788     "msiof3_clk_d",
4789     "msiof3_sync_d",
4790     "msiof3_ss1_d",
4791     "msiof3_txd_d",
4792     "msiof3_rxd_d",
4793     "msiof3_clk_e",
4794     "msiof3_sync_e",
4795     "msiof3_ss1_e",
4796     "msiof3_ss2_e",
4797     "msiof3_txd_e",
4798     "msiof3_rxd_e",
4799 };
4800
4801 static const char * const pwm0_groups[] = {
4802     "pwm0",
4803 };
4804
4805 static const char * const pwm1_groups[] = {
4806     "pwm1_a",
4807     "pwm1_b",
4808 };
4809
4810 static const char * const pwm2_groups[] = {
4811     "pwm2_a",
4812     "pwm2_b",
4813 };
4814
4815 static const char * const pwm3_groups[] = {
4816     "pwm3_a",
4817     "pwm3_b",
4818 };
4819
4820 static const char * const pwm4_groups[] = {
4821     "pwm4_a",
4822     "pwm4_b",
4823 };
4824
4825 static const char * const pwm5_groups[] = {
4826     "pwm5_a",
4827     "pwm5_b",
4828 };
4829
4830 static const char * const pwm6_groups[] = {
4831     "pwm6_a",
4832     "pwm6_b",
4833 };
4834
4835 static const char * const qspi0_groups[] = {
4836     "qspi0_ctrl",
4837     "qspi0_data2",
4838     "qspi0_data4",
4839 };
4840
4841 static const char * const qspi1_groups[] = {
4842     "qspi1_ctrl",
4843     "qspi1_data2",
4844     "qspi1_data4",
4845 };
4846
4847 static const char * const scif0_groups[] = {
4848     "scif0_data",
4849     "scif0_clk",
4850     "scif0_ctrl",
4851 };
4852
4853 static const char * const scif1_groups[] = {
4854     "scif1_data_a",
4855     "scif1_clk",
4856     "scif1_ctrl",
4857     "scif1_data_b",
4858 };
4859
4860 static const char * const scif2_groups[] = {
4861     "scif2_data_a",
4862     "scif2_clk",
4863     "scif2_data_b",
4864 };
4865
4866 static const char * const scif3_groups[] = {
4867     "scif3_data_a",
4868     "scif3_clk",
4869     "scif3_ctrl",
4870     "scif3_data_b",
4871 };
4872
4873 static const char * const scif4_groups[] = {
4874     "scif4_data_a",
4875     "scif4_clk_a",
4876     "scif4_ctrl_a",
4877     "scif4_data_b",
4878     "scif4_clk_b",
4879     "scif4_ctrl_b",
4880     "scif4_data_c",
4881     "scif4_clk_c",
4882     "scif4_ctrl_c",
4883 };
4884
4885 static const char * const scif5_groups[] = {
4886     "scif5_data_a",
4887     "scif5_clk_a",
4888     "scif5_data_b",
4889     "scif5_clk_b",
4890 };
4891
4892 static const char * const scif_clk_groups[] = {
4893     "scif_clk_a",
4894     "scif_clk_b",
4895 };
4896
4897 static const char * const sdhi0_groups[] = {
4898     "sdhi0_data1",
4899     "sdhi0_data4",
4900     "sdhi0_ctrl",
4901     "sdhi0_cd",
4902     "sdhi0_wp",
4903 };
4904
4905 static const char * const sdhi1_groups[] = {
4906     "sdhi1_data1",
4907     "sdhi1_data4",
4908     "sdhi1_ctrl",
4909     "sdhi1_cd",
4910     "sdhi1_wp",
4911 };
4912
4913 static const char * const sdhi2_groups[] = {
4914     "sdhi2_data1",
4915     "sdhi2_data4",
4916     "sdhi2_data8",
4917     "sdhi2_ctrl",
4918     "sdhi2_cd_a",
4919     "sdhi2_wp_a",
4920     "sdhi2_cd_b",
4921     "sdhi2_wp_b",
4922     "sdhi2_ds",
4923 };
4924
4925 static const char * const sdhi3_groups[] = {
4926     "sdhi3_data1",
4927     "sdhi3_data4",
4928     "sdhi3_data8",
4929     "sdhi3_ctrl",
4930     "sdhi3_cd",
4931     "sdhi3_wp",
4932     "sdhi3_ds",
4933 };
4934
4935 static const char * const ssi_groups[] = {
4936     "ssi0_data",
4937     "ssi01239_ctrl",
4938     "ssi1_data_a",
4939     "ssi1_data_b",
4940     "ssi1_ctrl_a",
4941     "ssi1_ctrl_b",
4942     "ssi2_data_a",
4943     "ssi2_data_b",
4944     "ssi2_ctrl_a",
4945     "ssi2_ctrl_b",
4946     "ssi3_data",
4947     "ssi349_ctrl",
4948     "ssi4_data",
4949     "ssi4_ctrl",
4950     "ssi5_data",
4951     "ssi5_ctrl",
4952     "ssi6_data",
4953     "ssi6_ctrl",
4954     "ssi7_data",
4955     "ssi78_ctrl",
4956     "ssi8_data",
4957     "ssi9_data_a",
4958     "ssi9_data_b",
4959     "ssi9_ctrl_a",
4960     "ssi9_ctrl_b",
4961 };
4962
4963 static const char * const tmu_groups[] = {
4964     "tmu_tclk1_a",
4965     "tmu_tclk1_b",
4966     "tmu_tclk2_a",
4967     "tmu_tclk2_b",
4968 };
4969
4970 static const char * const tpu_groups[] = {
4971     "tpu_to0",
4972     "tpu_to1",
4973     "tpu_to2",
4974     "tpu_to3",
4975 };
4976
4977 static const char * const usb0_groups[] = {
4978     "usb0",
4979 };
4980
4981 static const char * const usb1_groups[] = {
4982     "usb1",
4983 };
4984
4985 static const char * const usb30_groups[] = {
4986     "usb30",
4987 };
4988
4989 static const char * const vin4_groups[] = {
4990     "vin4_data8_a",
4991     "vin4_data10_a",
4992     "vin4_data12_a",
4993     "vin4_data16_a",
4994     "vin4_data18_a",
4995     "vin4_data20_a",
4996     "vin4_data24_a",
4997     "vin4_data8_b",
4998     "vin4_data10_b",
4999     "vin4_data12_b",
5000     "vin4_data16_b",
5001     "vin4_data18_b",
5002     "vin4_data20_b",
5003     "vin4_data24_b",
5004     "vin4_g8",
5005     "vin4_sync",
5006     "vin4_field",
5007     "vin4_clkenb",
5008     "vin4_clk",
5009 };
5010
5011 static const char * const vin5_groups[] = {
5012     "vin5_data8",
5013     "vin5_data10",
5014     "vin5_data12",
5015     "vin5_data16",
5016     "vin5_high8",
5017     "vin5_sync",
5018     "vin5_field",
5019     "vin5_clkenb",
5020     "vin5_clk",
5021 };
5022
5023 static const struct {
5024     struct sh_pfc_function common[52];
5025 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
5026     struct sh_pfc_function automotive[5];
5027 #endif
5028 } pinmux_functions = {
5029     .common = {
5030         SH_PFC_FUNCTION(audio_clk),
5031         SH_PFC_FUNCTION(avb),
5032         SH_PFC_FUNCTION(can0),
5033         SH_PFC_FUNCTION(can1),
5034         SH_PFC_FUNCTION(can_clk),
5035         SH_PFC_FUNCTION(canfd0),
5036         SH_PFC_FUNCTION(canfd1),
5037         SH_PFC_FUNCTION(du),
5038         SH_PFC_FUNCTION(hscif0),
5039         SH_PFC_FUNCTION(hscif1),
5040         SH_PFC_FUNCTION(hscif2),
5041         SH_PFC_FUNCTION(hscif3),
5042         SH_PFC_FUNCTION(hscif4),
5043         SH_PFC_FUNCTION(i2c0),
5044         SH_PFC_FUNCTION(i2c1),
5045         SH_PFC_FUNCTION(i2c2),
5046         SH_PFC_FUNCTION(i2c3),
5047         SH_PFC_FUNCTION(i2c5),
5048         SH_PFC_FUNCTION(i2c6),
5049         SH_PFC_FUNCTION(intc_ex),
5050         SH_PFC_FUNCTION(msiof0),
5051         SH_PFC_FUNCTION(msiof1),
5052         SH_PFC_FUNCTION(msiof2),
5053         SH_PFC_FUNCTION(msiof3),
5054         SH_PFC_FUNCTION(pwm0),
5055         SH_PFC_FUNCTION(pwm1),
5056         SH_PFC_FUNCTION(pwm2),
5057         SH_PFC_FUNCTION(pwm3),
5058         SH_PFC_FUNCTION(pwm4),
5059         SH_PFC_FUNCTION(pwm5),
5060         SH_PFC_FUNCTION(pwm6),
5061         SH_PFC_FUNCTION(qspi0),
5062         SH_PFC_FUNCTION(qspi1),
5063         SH_PFC_FUNCTION(scif0),
5064         SH_PFC_FUNCTION(scif1),
5065         SH_PFC_FUNCTION(scif2),
5066         SH_PFC_FUNCTION(scif3),
5067         SH_PFC_FUNCTION(scif4),
5068         SH_PFC_FUNCTION(scif5),
5069         SH_PFC_FUNCTION(scif_clk),
5070         SH_PFC_FUNCTION(sdhi0),
5071         SH_PFC_FUNCTION(sdhi1),
5072         SH_PFC_FUNCTION(sdhi2),
5073         SH_PFC_FUNCTION(sdhi3),
5074         SH_PFC_FUNCTION(ssi),
5075         SH_PFC_FUNCTION(tmu),
5076         SH_PFC_FUNCTION(tpu),
5077         SH_PFC_FUNCTION(usb0),
5078         SH_PFC_FUNCTION(usb1),
5079         SH_PFC_FUNCTION(usb30),
5080         SH_PFC_FUNCTION(vin4),
5081         SH_PFC_FUNCTION(vin5),
5082     },
5083 #if defined(CONFIG_PINCTRL_PFC_R8A77960) || defined(CONFIG_PINCTRL_PFC_R8A77961)
5084     .automotive = {
5085         SH_PFC_FUNCTION(drif0),
5086         SH_PFC_FUNCTION(drif1),
5087         SH_PFC_FUNCTION(drif2),
5088         SH_PFC_FUNCTION(drif3),
5089         SH_PFC_FUNCTION(mlb_3pin),
5090     }
5091 #endif /* CONFIG_PINCTRL_PFC_R8A77960 || CONFIG_PINCTRL_PFC_R8A77961 */
5092 };
5093
5094 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5095 #define F_(x, y)    FN_##y
5096 #define FM(x)       FN_##x
5097     { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32,
5098                  GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5099                    1, 1, 1, 1, 1),
5100                  GROUP(
5101         /* GP0_31_16 RESERVED */
5102         GP_0_15_FN, GPSR0_15,
5103         GP_0_14_FN, GPSR0_14,
5104         GP_0_13_FN, GPSR0_13,
5105         GP_0_12_FN, GPSR0_12,
5106         GP_0_11_FN, GPSR0_11,
5107         GP_0_10_FN, GPSR0_10,
5108         GP_0_9_FN,  GPSR0_9,
5109         GP_0_8_FN,  GPSR0_8,
5110         GP_0_7_FN,  GPSR0_7,
5111         GP_0_6_FN,  GPSR0_6,
5112         GP_0_5_FN,  GPSR0_5,
5113         GP_0_4_FN,  GPSR0_4,
5114         GP_0_3_FN,  GPSR0_3,
5115         GP_0_2_FN,  GPSR0_2,
5116         GP_0_1_FN,  GPSR0_1,
5117         GP_0_0_FN,  GPSR0_0, ))
5118     },
5119     { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
5120         0, 0,
5121         0, 0,
5122         0, 0,
5123         GP_1_28_FN, GPSR1_28,
5124         GP_1_27_FN, GPSR1_27,
5125         GP_1_26_FN, GPSR1_26,
5126         GP_1_25_FN, GPSR1_25,
5127         GP_1_24_FN, GPSR1_24,
5128         GP_1_23_FN, GPSR1_23,
5129         GP_1_22_FN, GPSR1_22,
5130         GP_1_21_FN, GPSR1_21,
5131         GP_1_20_FN, GPSR1_20,
5132         GP_1_19_FN, GPSR1_19,
5133         GP_1_18_FN, GPSR1_18,
5134         GP_1_17_FN, GPSR1_17,
5135         GP_1_16_FN, GPSR1_16,
5136         GP_1_15_FN, GPSR1_15,
5137         GP_1_14_FN, GPSR1_14,
5138         GP_1_13_FN, GPSR1_13,
5139         GP_1_12_FN, GPSR1_12,
5140         GP_1_11_FN, GPSR1_11,
5141         GP_1_10_FN, GPSR1_10,
5142         GP_1_9_FN,  GPSR1_9,
5143         GP_1_8_FN,  GPSR1_8,
5144         GP_1_7_FN,  GPSR1_7,
5145         GP_1_6_FN,  GPSR1_6,
5146         GP_1_5_FN,  GPSR1_5,
5147         GP_1_4_FN,  GPSR1_4,
5148         GP_1_3_FN,  GPSR1_3,
5149         GP_1_2_FN,  GPSR1_2,
5150         GP_1_1_FN,  GPSR1_1,
5151         GP_1_0_FN,  GPSR1_0, ))
5152     },
5153     { PINMUX_CFG_REG_VAR("GPSR2", 0xe6060108, 32,
5154                  GROUP(-17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5155                    1, 1, 1, 1),
5156                  GROUP(
5157         /* GP2_31_15 RESERVED */
5158         GP_2_14_FN, GPSR2_14,
5159         GP_2_13_FN, GPSR2_13,
5160         GP_2_12_FN, GPSR2_12,
5161         GP_2_11_FN, GPSR2_11,
5162         GP_2_10_FN, GPSR2_10,
5163         GP_2_9_FN,  GPSR2_9,
5164         GP_2_8_FN,  GPSR2_8,
5165         GP_2_7_FN,  GPSR2_7,
5166         GP_2_6_FN,  GPSR2_6,
5167         GP_2_5_FN,  GPSR2_5,
5168         GP_2_4_FN,  GPSR2_4,
5169         GP_2_3_FN,  GPSR2_3,
5170         GP_2_2_FN,  GPSR2_2,
5171         GP_2_1_FN,  GPSR2_1,
5172         GP_2_0_FN,  GPSR2_0, ))
5173     },
5174     { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32,
5175                  GROUP(-16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5176                    1, 1, 1, 1, 1),
5177                  GROUP(
5178         /* GP3_31_16 RESERVED */
5179         GP_3_15_FN, GPSR3_15,
5180         GP_3_14_FN, GPSR3_14,
5181         GP_3_13_FN, GPSR3_13,
5182         GP_3_12_FN, GPSR3_12,
5183         GP_3_11_FN, GPSR3_11,
5184         GP_3_10_FN, GPSR3_10,
5185         GP_3_9_FN,  GPSR3_9,
5186         GP_3_8_FN,  GPSR3_8,
5187         GP_3_7_FN,  GPSR3_7,
5188         GP_3_6_FN,  GPSR3_6,
5189         GP_3_5_FN,  GPSR3_5,
5190         GP_3_4_FN,  GPSR3_4,
5191         GP_3_3_FN,  GPSR3_3,
5192         GP_3_2_FN,  GPSR3_2,
5193         GP_3_1_FN,  GPSR3_1,
5194         GP_3_0_FN,  GPSR3_0, ))
5195     },
5196     { PINMUX_CFG_REG_VAR("GPSR4", 0xe6060110, 32,
5197                  GROUP(-14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
5198                    1, 1, 1, 1, 1, 1, 1),
5199                  GROUP(
5200         /* GP4_31_18 RESERVED */
5201         GP_4_17_FN, GPSR4_17,
5202         GP_4_16_FN, GPSR4_16,
5203         GP_4_15_FN, GPSR4_15,
5204         GP_4_14_FN, GPSR4_14,
5205         GP_4_13_FN, GPSR4_13,
5206         GP_4_12_FN, GPSR4_12,
5207         GP_4_11_FN, GPSR4_11,
5208         GP_4_10_FN, GPSR4_10,
5209         GP_4_9_FN,  GPSR4_9,
5210         GP_4_8_FN,  GPSR4_8,
5211         GP_4_7_FN,  GPSR4_7,
5212         GP_4_6_FN,  GPSR4_6,
5213         GP_4_5_FN,  GPSR4_5,
5214         GP_4_4_FN,  GPSR4_4,
5215         GP_4_3_FN,  GPSR4_3,
5216         GP_4_2_FN,  GPSR4_2,
5217         GP_4_1_FN,  GPSR4_1,
5218         GP_4_0_FN,  GPSR4_0, ))
5219     },
5220     { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
5221         0, 0,
5222         0, 0,
5223         0, 0,
5224         0, 0,
5225         0, 0,
5226         0, 0,
5227         GP_5_25_FN, GPSR5_25,
5228         GP_5_24_FN, GPSR5_24,
5229         GP_5_23_FN, GPSR5_23,
5230         GP_5_22_FN, GPSR5_22,
5231         GP_5_21_FN, GPSR5_21,
5232         GP_5_20_FN, GPSR5_20,
5233         GP_5_19_FN, GPSR5_19,
5234         GP_5_18_FN, GPSR5_18,
5235         GP_5_17_FN, GPSR5_17,
5236         GP_5_16_FN, GPSR5_16,
5237         GP_5_15_FN, GPSR5_15,
5238         GP_5_14_FN, GPSR5_14,
5239         GP_5_13_FN, GPSR5_13,
5240         GP_5_12_FN, GPSR5_12,
5241         GP_5_11_FN, GPSR5_11,
5242         GP_5_10_FN, GPSR5_10,
5243         GP_5_9_FN,  GPSR5_9,
5244         GP_5_8_FN,  GPSR5_8,
5245         GP_5_7_FN,  GPSR5_7,
5246         GP_5_6_FN,  GPSR5_6,
5247         GP_5_5_FN,  GPSR5_5,
5248         GP_5_4_FN,  GPSR5_4,
5249         GP_5_3_FN,  GPSR5_3,
5250         GP_5_2_FN,  GPSR5_2,
5251         GP_5_1_FN,  GPSR5_1,
5252         GP_5_0_FN,  GPSR5_0, ))
5253     },
5254     { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
5255         GP_6_31_FN, GPSR6_31,
5256         GP_6_30_FN, GPSR6_30,
5257         GP_6_29_FN, GPSR6_29,
5258         GP_6_28_FN, GPSR6_28,
5259         GP_6_27_FN, GPSR6_27,
5260         GP_6_26_FN, GPSR6_26,
5261         GP_6_25_FN, GPSR6_25,
5262         GP_6_24_FN, GPSR6_24,
5263         GP_6_23_FN, GPSR6_23,
5264         GP_6_22_FN, GPSR6_22,
5265         GP_6_21_FN, GPSR6_21,
5266         GP_6_20_FN, GPSR6_20,
5267         GP_6_19_FN, GPSR6_19,
5268         GP_6_18_FN, GPSR6_18,
5269         GP_6_17_FN, GPSR6_17,
5270         GP_6_16_FN, GPSR6_16,
5271         GP_6_15_FN, GPSR6_15,
5272         GP_6_14_FN, GPSR6_14,
5273         GP_6_13_FN, GPSR6_13,
5274         GP_6_12_FN, GPSR6_12,
5275         GP_6_11_FN, GPSR6_11,
5276         GP_6_10_FN, GPSR6_10,
5277         GP_6_9_FN,  GPSR6_9,
5278         GP_6_8_FN,  GPSR6_8,
5279         GP_6_7_FN,  GPSR6_7,
5280         GP_6_6_FN,  GPSR6_6,
5281         GP_6_5_FN,  GPSR6_5,
5282         GP_6_4_FN,  GPSR6_4,
5283         GP_6_3_FN,  GPSR6_3,
5284         GP_6_2_FN,  GPSR6_2,
5285         GP_6_1_FN,  GPSR6_1,
5286         GP_6_0_FN,  GPSR6_0, ))
5287     },
5288     { PINMUX_CFG_REG_VAR("GPSR7", 0xe606011c, 32,
5289                  GROUP(-28, 1, 1, 1, 1),
5290                  GROUP(
5291         /* GP7_31_4 RESERVED */
5292         GP_7_3_FN, GPSR7_3,
5293         GP_7_2_FN, GPSR7_2,
5294         GP_7_1_FN, GPSR7_1,
5295         GP_7_0_FN, GPSR7_0, ))
5296     },
5297 #undef F_
5298 #undef FM
5299
5300 #define F_(x, y)    x,
5301 #define FM(x)       FN_##x,
5302     { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
5303         IP0_31_28
5304         IP0_27_24
5305         IP0_23_20
5306         IP0_19_16
5307         IP0_15_12
5308         IP0_11_8
5309         IP0_7_4
5310         IP0_3_0 ))
5311     },
5312     { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
5313         IP1_31_28
5314         IP1_27_24
5315         IP1_23_20
5316         IP1_19_16
5317         IP1_15_12
5318         IP1_11_8
5319         IP1_7_4
5320         IP1_3_0 ))
5321     },
5322     { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
5323         IP2_31_28
5324         IP2_27_24
5325         IP2_23_20
5326         IP2_19_16
5327         IP2_15_12
5328         IP2_11_8
5329         IP2_7_4
5330         IP2_3_0 ))
5331     },
5332     { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
5333         IP3_31_28
5334         IP3_27_24
5335         IP3_23_20
5336         IP3_19_16
5337         IP3_15_12
5338         IP3_11_8
5339         IP3_7_4
5340         IP3_3_0 ))
5341     },
5342     { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
5343         IP4_31_28
5344         IP4_27_24
5345         IP4_23_20
5346         IP4_19_16
5347         IP4_15_12
5348         IP4_11_8
5349         IP4_7_4
5350         IP4_3_0 ))
5351     },
5352     { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
5353         IP5_31_28
5354         IP5_27_24
5355         IP5_23_20
5356         IP5_19_16
5357         IP5_15_12
5358         IP5_11_8
5359         IP5_7_4
5360         IP5_3_0 ))
5361     },
5362     { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
5363         IP6_31_28
5364         IP6_27_24
5365         IP6_23_20
5366         IP6_19_16
5367         IP6_15_12
5368         IP6_11_8
5369         IP6_7_4
5370         IP6_3_0 ))
5371     },
5372     { PINMUX_CFG_REG_VAR("IPSR7", 0xe606021c, 32,
5373                  GROUP(4, 4, 4, 4, -4, 4, 4, 4),
5374                  GROUP(
5375         IP7_31_28
5376         IP7_27_24
5377         IP7_23_20
5378         IP7_19_16
5379         /* IP7_15_12 RESERVED */
5380         IP7_11_8
5381         IP7_7_4
5382         IP7_3_0 ))
5383     },
5384     { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
5385         IP8_31_28
5386         IP8_27_24
5387         IP8_23_20
5388         IP8_19_16
5389         IP8_15_12
5390         IP8_11_8
5391         IP8_7_4
5392         IP8_3_0 ))
5393     },
5394     { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
5395         IP9_31_28
5396         IP9_27_24
5397         IP9_23_20
5398         IP9_19_16
5399         IP9_15_12
5400         IP9_11_8
5401         IP9_7_4
5402         IP9_3_0 ))
5403     },
5404     { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
5405         IP10_31_28
5406         IP10_27_24
5407         IP10_23_20
5408         IP10_19_16
5409         IP10_15_12
5410         IP10_11_8
5411         IP10_7_4
5412         IP10_3_0 ))
5413     },
5414     { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
5415         IP11_31_28
5416         IP11_27_24
5417         IP11_23_20
5418         IP11_19_16
5419         IP11_15_12
5420         IP11_11_8
5421         IP11_7_4
5422         IP11_3_0 ))
5423     },
5424     { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
5425         IP12_31_28
5426         IP12_27_24
5427         IP12_23_20
5428         IP12_19_16
5429         IP12_15_12
5430         IP12_11_8
5431         IP12_7_4
5432         IP12_3_0 ))
5433     },
5434     { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
5435         IP13_31_28
5436         IP13_27_24
5437         IP13_23_20
5438         IP13_19_16
5439         IP13_15_12
5440         IP13_11_8
5441         IP13_7_4
5442         IP13_3_0 ))
5443     },
5444     { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
5445         IP14_31_28
5446         IP14_27_24
5447         IP14_23_20
5448         IP14_19_16
5449         IP14_15_12
5450         IP14_11_8
5451         IP14_7_4
5452         IP14_3_0 ))
5453     },
5454     { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
5455         IP15_31_28
5456         IP15_27_24
5457         IP15_23_20
5458         IP15_19_16
5459         IP15_15_12
5460         IP15_11_8
5461         IP15_7_4
5462         IP15_3_0 ))
5463     },
5464     { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
5465         IP16_31_28
5466         IP16_27_24
5467         IP16_23_20
5468         IP16_19_16
5469         IP16_15_12
5470         IP16_11_8
5471         IP16_7_4
5472         IP16_3_0 ))
5473     },
5474     { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
5475         IP17_31_28
5476         IP17_27_24
5477         IP17_23_20
5478         IP17_19_16
5479         IP17_15_12
5480         IP17_11_8
5481         IP17_7_4
5482         IP17_3_0 ))
5483     },
5484     { PINMUX_CFG_REG_VAR("IPSR18", 0xe6060248, 32,
5485                  GROUP(-24, 4, 4),
5486                  GROUP(
5487         /* IP18_31_8 RESERVED */
5488         IP18_7_4
5489         IP18_3_0 ))
5490     },
5491 #undef F_
5492 #undef FM
5493
5494 #define F_(x, y)    x,
5495 #define FM(x)       FN_##x,
5496     { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5497                  GROUP(3, 2, 3, 1, 1, 1, 1, 1, 2, 1, -1, 2,
5498                    1, 1, 1, 2, 2, 1, 2, -3),
5499                  GROUP(
5500         MOD_SEL0_31_30_29
5501         MOD_SEL0_28_27
5502         MOD_SEL0_26_25_24
5503         MOD_SEL0_23
5504         MOD_SEL0_22
5505         MOD_SEL0_21
5506         MOD_SEL0_20
5507         MOD_SEL0_19
5508         MOD_SEL0_18_17
5509         MOD_SEL0_16
5510         /* RESERVED 15 */
5511         MOD_SEL0_14_13
5512         MOD_SEL0_12
5513         MOD_SEL0_11
5514         MOD_SEL0_10
5515         MOD_SEL0_9_8
5516         MOD_SEL0_7_6
5517         MOD_SEL0_5
5518         MOD_SEL0_4_3
5519         /* RESERVED 2, 1, 0 */ ))
5520     },
5521     { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5522                  GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
5523                    1, 1, 1, -2, 1, 1, 1, 1, 1, 1, 1),
5524                  GROUP(
5525         MOD_SEL1_31_30
5526         MOD_SEL1_29_28_27
5527         MOD_SEL1_26
5528         MOD_SEL1_25_24
5529         MOD_SEL1_23_22_21
5530         MOD_SEL1_20
5531         MOD_SEL1_19
5532         MOD_SEL1_18_17
5533         MOD_SEL1_16
5534         MOD_SEL1_15_14
5535         MOD_SEL1_13
5536         MOD_SEL1_12
5537         MOD_SEL1_11
5538         MOD_SEL1_10
5539         MOD_SEL1_9
5540         /* RESERVED 8, 7 */
5541         MOD_SEL1_6
5542         MOD_SEL1_5
5543         MOD_SEL1_4
5544         MOD_SEL1_3
5545         MOD_SEL1_2
5546         MOD_SEL1_1
5547         MOD_SEL1_0 ))
5548     },
5549     { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5550                  GROUP(1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1,
5551                    -16, 1),
5552                  GROUP(
5553         MOD_SEL2_31
5554         MOD_SEL2_30
5555         MOD_SEL2_29
5556         MOD_SEL2_28_27
5557         MOD_SEL2_26
5558         MOD_SEL2_25_24_23
5559         MOD_SEL2_22
5560         MOD_SEL2_21
5561         MOD_SEL2_20
5562         MOD_SEL2_19
5563         MOD_SEL2_18
5564         MOD_SEL2_17
5565         /* RESERVED 16-1 */
5566         MOD_SEL2_0 ))
5567     },
5568     { },
5569 };
5570
5571 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5572     { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5573         { PIN_QSPI0_SPCLK,    28, 2 },  /* QSPI0_SPCLK */
5574         { PIN_QSPI0_MOSI_IO0, 24, 2 },  /* QSPI0_MOSI_IO0 */
5575         { PIN_QSPI0_MISO_IO1, 20, 2 },  /* QSPI0_MISO_IO1 */
5576         { PIN_QSPI0_IO2,      16, 2 },  /* QSPI0_IO2 */
5577         { PIN_QSPI0_IO3,      12, 2 },  /* QSPI0_IO3 */
5578         { PIN_QSPI0_SSL,       8, 2 },  /* QSPI0_SSL */
5579         { PIN_QSPI1_SPCLK,     4, 2 },  /* QSPI1_SPCLK */
5580         { PIN_QSPI1_MOSI_IO0,  0, 2 },  /* QSPI1_MOSI_IO0 */
5581     } },
5582     { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5583         { PIN_QSPI1_MISO_IO1, 28, 2 },  /* QSPI1_MISO_IO1 */
5584         { PIN_QSPI1_IO2,      24, 2 },  /* QSPI1_IO2 */
5585         { PIN_QSPI1_IO3,      20, 2 },  /* QSPI1_IO3 */
5586         { PIN_QSPI1_SSL,      16, 2 },  /* QSPI1_SSL */
5587         { PIN_RPC_INT_N,      12, 2 },  /* RPC_INT# */
5588         { PIN_RPC_WP_N,        8, 2 },  /* RPC_WP# */
5589         { PIN_RPC_RESET_N,     4, 2 },  /* RPC_RESET# */
5590         { PIN_AVB_RX_CTL,      0, 3 },  /* AVB_RX_CTL */
5591     } },
5592     { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5593         { PIN_AVB_RXC,        28, 3 },  /* AVB_RXC */
5594         { PIN_AVB_RD0,        24, 3 },  /* AVB_RD0 */
5595         { PIN_AVB_RD1,        20, 3 },  /* AVB_RD1 */
5596         { PIN_AVB_RD2,        16, 3 },  /* AVB_RD2 */
5597         { PIN_AVB_RD3,        12, 3 },  /* AVB_RD3 */
5598         { PIN_AVB_TX_CTL,      8, 3 },  /* AVB_TX_CTL */
5599         { PIN_AVB_TXC,         4, 3 },  /* AVB_TXC */
5600         { PIN_AVB_TD0,         0, 3 },  /* AVB_TD0 */
5601     } },
5602     { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5603         { PIN_AVB_TD1,        28, 3 },  /* AVB_TD1 */
5604         { PIN_AVB_TD2,        24, 3 },  /* AVB_TD2 */
5605         { PIN_AVB_TD3,        20, 3 },  /* AVB_TD3 */
5606         { PIN_AVB_TXCREFCLK,  16, 3 },  /* AVB_TXCREFCLK */
5607         { PIN_AVB_MDIO,       12, 3 },  /* AVB_MDIO */
5608         { RCAR_GP_PIN(2,  9),  8, 3 },  /* AVB_MDC */
5609         { RCAR_GP_PIN(2, 10),  4, 3 },  /* AVB_MAGIC */
5610         { RCAR_GP_PIN(2, 11),  0, 3 },  /* AVB_PHY_INT */
5611     } },
5612     { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5613         { RCAR_GP_PIN(2, 12), 28, 3 },  /* AVB_LINK */
5614         { RCAR_GP_PIN(2, 13), 24, 3 },  /* AVB_AVTP_MATCH */
5615         { RCAR_GP_PIN(2, 14), 20, 3 },  /* AVB_AVTP_CAPTURE */
5616         { RCAR_GP_PIN(2,  0), 16, 3 },  /* IRQ0 */
5617         { RCAR_GP_PIN(2,  1), 12, 3 },  /* IRQ1 */
5618         { RCAR_GP_PIN(2,  2),  8, 3 },  /* IRQ2 */
5619         { RCAR_GP_PIN(2,  3),  4, 3 },  /* IRQ3 */
5620         { RCAR_GP_PIN(2,  4),  0, 3 },  /* IRQ4 */
5621     } },
5622     { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5623         { RCAR_GP_PIN(2,  5), 28, 3 },  /* IRQ5 */
5624         { RCAR_GP_PIN(2,  6), 24, 3 },  /* PWM0 */
5625         { RCAR_GP_PIN(2,  7), 20, 3 },  /* PWM1 */
5626         { RCAR_GP_PIN(2,  8), 16, 3 },  /* PWM2 */
5627         { RCAR_GP_PIN(1,  0), 12, 3 },  /* A0 */
5628         { RCAR_GP_PIN(1,  1),  8, 3 },  /* A1 */
5629         { RCAR_GP_PIN(1,  2),  4, 3 },  /* A2 */
5630         { RCAR_GP_PIN(1,  3),  0, 3 },  /* A3 */
5631     } },
5632     { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5633         { RCAR_GP_PIN(1,  4), 28, 3 },  /* A4 */
5634         { RCAR_GP_PIN(1,  5), 24, 3 },  /* A5 */
5635         { RCAR_GP_PIN(1,  6), 20, 3 },  /* A6 */
5636         { RCAR_GP_PIN(1,  7), 16, 3 },  /* A7 */
5637         { RCAR_GP_PIN(1,  8), 12, 3 },  /* A8 */
5638         { RCAR_GP_PIN(1,  9),  8, 3 },  /* A9 */
5639         { RCAR_GP_PIN(1, 10),  4, 3 },  /* A10 */
5640         { RCAR_GP_PIN(1, 11),  0, 3 },  /* A11 */
5641     } },
5642     { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5643         { RCAR_GP_PIN(1, 12), 28, 3 },  /* A12 */
5644         { RCAR_GP_PIN(1, 13), 24, 3 },  /* A13 */
5645         { RCAR_GP_PIN(1, 14), 20, 3 },  /* A14 */
5646         { RCAR_GP_PIN(1, 15), 16, 3 },  /* A15 */
5647         { RCAR_GP_PIN(1, 16), 12, 3 },  /* A16 */
5648         { RCAR_GP_PIN(1, 17),  8, 3 },  /* A17 */
5649         { RCAR_GP_PIN(1, 18),  4, 3 },  /* A18 */
5650         { RCAR_GP_PIN(1, 19),  0, 3 },  /* A19 */
5651     } },
5652     { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
5653         { RCAR_GP_PIN(1, 28), 28, 3 },  /* CLKOUT */
5654         { RCAR_GP_PIN(1, 20), 24, 3 },  /* CS0 */
5655         { RCAR_GP_PIN(1, 21), 20, 3 },  /* CS1_A26 */
5656         { RCAR_GP_PIN(1, 22), 16, 3 },  /* BS */
5657         { RCAR_GP_PIN(1, 23), 12, 3 },  /* RD */
5658         { RCAR_GP_PIN(1, 24),  8, 3 },  /* RD_WR */
5659         { RCAR_GP_PIN(1, 25),  4, 3 },  /* WE0 */
5660         { RCAR_GP_PIN(1, 26),  0, 3 },  /* WE1 */
5661     } },
5662     { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5663         { RCAR_GP_PIN(1, 27), 28, 3 },  /* EX_WAIT0 */
5664         { PIN_PRESETOUT_N,    24, 3 },  /* PRESETOUT# */
5665         { RCAR_GP_PIN(0,  0), 20, 3 },  /* D0 */
5666         { RCAR_GP_PIN(0,  1), 16, 3 },  /* D1 */
5667         { RCAR_GP_PIN(0,  2), 12, 3 },  /* D2 */
5668         { RCAR_GP_PIN(0,  3),  8, 3 },  /* D3 */
5669         { RCAR_GP_PIN(0,  4),  4, 3 },  /* D4 */
5670         { RCAR_GP_PIN(0,  5),  0, 3 },  /* D5 */
5671     } },
5672     { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5673         { RCAR_GP_PIN(0,  6), 28, 3 },  /* D6 */
5674         { RCAR_GP_PIN(0,  7), 24, 3 },  /* D7 */
5675         { RCAR_GP_PIN(0,  8), 20, 3 },  /* D8 */
5676         { RCAR_GP_PIN(0,  9), 16, 3 },  /* D9 */
5677         { RCAR_GP_PIN(0, 10), 12, 3 },  /* D10 */
5678         { RCAR_GP_PIN(0, 11),  8, 3 },  /* D11 */
5679         { RCAR_GP_PIN(0, 12),  4, 3 },  /* D12 */
5680         { RCAR_GP_PIN(0, 13),  0, 3 },  /* D13 */
5681     } },
5682     { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5683         { RCAR_GP_PIN(0, 14), 28, 3 },  /* D14 */
5684         { RCAR_GP_PIN(0, 15), 24, 3 },  /* D15 */
5685         { RCAR_GP_PIN(7,  0), 20, 3 },  /* AVS1 */
5686         { RCAR_GP_PIN(7,  1), 16, 3 },  /* AVS2 */
5687         { RCAR_GP_PIN(7,  2), 12, 3 },  /* GP7_02 */
5688         { RCAR_GP_PIN(7,  3),  8, 3 },  /* GP7_03 */
5689         { PIN_DU_DOTCLKIN0,    4, 2 },  /* DU_DOTCLKIN0 */
5690         { PIN_DU_DOTCLKIN1,    0, 2 },  /* DU_DOTCLKIN1 */
5691     } },
5692     { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5693         { PIN_DU_DOTCLKIN2,   28, 2 },  /* DU_DOTCLKIN2 */
5694         { PIN_FSCLKST,        20, 2 },  /* FSCLKST */
5695         { PIN_TMS,             4, 2 },  /* TMS */
5696     } },
5697     { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5698         { PIN_TDO,            28, 2 },  /* TDO */
5699         { PIN_ASEBRK,         24, 2 },  /* ASEBRK */
5700         { RCAR_GP_PIN(3,  0), 20, 3 },  /* SD0_CLK */
5701         { RCAR_GP_PIN(3,  1), 16, 3 },  /* SD0_CMD */
5702         { RCAR_GP_PIN(3,  2), 12, 3 },  /* SD0_DAT0 */
5703         { RCAR_GP_PIN(3,  3),  8, 3 },  /* SD0_DAT1 */
5704         { RCAR_GP_PIN(3,  4),  4, 3 },  /* SD0_DAT2 */
5705         { RCAR_GP_PIN(3,  5),  0, 3 },  /* SD0_DAT3 */
5706     } },
5707     { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5708         { RCAR_GP_PIN(3,  6), 28, 3 },  /* SD1_CLK */
5709         { RCAR_GP_PIN(3,  7), 24, 3 },  /* SD1_CMD */
5710         { RCAR_GP_PIN(3,  8), 20, 3 },  /* SD1_DAT0 */
5711         { RCAR_GP_PIN(3,  9), 16, 3 },  /* SD1_DAT1 */
5712         { RCAR_GP_PIN(3, 10), 12, 3 },  /* SD1_DAT2 */
5713         { RCAR_GP_PIN(3, 11),  8, 3 },  /* SD1_DAT3 */
5714         { RCAR_GP_PIN(4,  0),  4, 3 },  /* SD2_CLK */
5715         { RCAR_GP_PIN(4,  1),  0, 3 },  /* SD2_CMD */
5716     } },
5717     { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5718         { RCAR_GP_PIN(4,  2), 28, 3 },  /* SD2_DAT0 */
5719         { RCAR_GP_PIN(4,  3), 24, 3 },  /* SD2_DAT1 */
5720         { RCAR_GP_PIN(4,  4), 20, 3 },  /* SD2_DAT2 */
5721         { RCAR_GP_PIN(4,  5), 16, 3 },  /* SD2_DAT3 */
5722         { RCAR_GP_PIN(4,  6), 12, 3 },  /* SD2_DS */
5723         { RCAR_GP_PIN(4,  7),  8, 3 },  /* SD3_CLK */
5724         { RCAR_GP_PIN(4,  8),  4, 3 },  /* SD3_CMD */
5725         { RCAR_GP_PIN(4,  9),  0, 3 },  /* SD3_DAT0 */
5726     } },
5727     { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5728         { RCAR_GP_PIN(4, 10), 28, 3 },  /* SD3_DAT1 */
5729         { RCAR_GP_PIN(4, 11), 24, 3 },  /* SD3_DAT2 */
5730         { RCAR_GP_PIN(4, 12), 20, 3 },  /* SD3_DAT3 */
5731         { RCAR_GP_PIN(4, 13), 16, 3 },  /* SD3_DAT4 */
5732         { RCAR_GP_PIN(4, 14), 12, 3 },  /* SD3_DAT5 */
5733         { RCAR_GP_PIN(4, 15),  8, 3 },  /* SD3_DAT6 */
5734         { RCAR_GP_PIN(4, 16),  4, 3 },  /* SD3_DAT7 */
5735         { RCAR_GP_PIN(4, 17),  0, 3 },  /* SD3_DS */
5736     } },
5737     { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5738         { RCAR_GP_PIN(3, 12), 28, 3 },  /* SD0_CD */
5739         { RCAR_GP_PIN(3, 13), 24, 3 },  /* SD0_WP */
5740         { RCAR_GP_PIN(3, 14), 20, 3 },  /* SD1_CD */
5741         { RCAR_GP_PIN(3, 15), 16, 3 },  /* SD1_WP */
5742         { RCAR_GP_PIN(5,  0), 12, 3 },  /* SCK0 */
5743         { RCAR_GP_PIN(5,  1),  8, 3 },  /* RX0 */
5744         { RCAR_GP_PIN(5,  2),  4, 3 },  /* TX0 */
5745         { RCAR_GP_PIN(5,  3),  0, 3 },  /* CTS0 */
5746     } },
5747     { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5748         { RCAR_GP_PIN(5,  4), 28, 3 },  /* RTS0 */
5749         { RCAR_GP_PIN(5,  5), 24, 3 },  /* RX1 */
5750         { RCAR_GP_PIN(5,  6), 20, 3 },  /* TX1 */
5751         { RCAR_GP_PIN(5,  7), 16, 3 },  /* CTS1 */
5752         { RCAR_GP_PIN(5,  8), 12, 3 },  /* RTS1 */
5753         { RCAR_GP_PIN(5,  9),  8, 3 },  /* SCK2 */
5754         { RCAR_GP_PIN(5, 10),  4, 3 },  /* TX2 */
5755         { RCAR_GP_PIN(5, 11),  0, 3 },  /* RX2 */
5756     } },
5757     { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5758         { RCAR_GP_PIN(5, 12), 28, 3 },  /* HSCK0 */
5759         { RCAR_GP_PIN(5, 13), 24, 3 },  /* HRX0 */
5760         { RCAR_GP_PIN(5, 14), 20, 3 },  /* HTX0 */
5761         { RCAR_GP_PIN(5, 15), 16, 3 },  /* HCTS0 */
5762         { RCAR_GP_PIN(5, 16), 12, 3 },  /* HRTS0 */
5763         { RCAR_GP_PIN(5, 17),  8, 3 },  /* MSIOF0_SCK */
5764         { RCAR_GP_PIN(5, 18),  4, 3 },  /* MSIOF0_SYNC */
5765         { RCAR_GP_PIN(5, 19),  0, 3 },  /* MSIOF0_SS1 */
5766     } },
5767     { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5768         { RCAR_GP_PIN(5, 20), 28, 3 },  /* MSIOF0_TXD */
5769         { RCAR_GP_PIN(5, 21), 24, 3 },  /* MSIOF0_SS2 */
5770         { RCAR_GP_PIN(5, 22), 20, 3 },  /* MSIOF0_RXD */
5771         { RCAR_GP_PIN(5, 23), 16, 3 },  /* MLB_CLK */
5772         { RCAR_GP_PIN(5, 24), 12, 3 },  /* MLB_SIG */
5773         { RCAR_GP_PIN(5, 25),  8, 3 },  /* MLB_DAT */
5774         { PIN_MLB_REF,         4, 3 },  /* MLB_REF */
5775         { RCAR_GP_PIN(6,  0),  0, 3 },  /* SSI_SCK01239 */
5776     } },
5777     { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5778         { RCAR_GP_PIN(6,  1), 28, 3 },  /* SSI_WS01239 */
5779         { RCAR_GP_PIN(6,  2), 24, 3 },  /* SSI_SDATA0 */
5780         { RCAR_GP_PIN(6,  3), 20, 3 },  /* SSI_SDATA1 */
5781         { RCAR_GP_PIN(6,  4), 16, 3 },  /* SSI_SDATA2 */
5782         { RCAR_GP_PIN(6,  5), 12, 3 },  /* SSI_SCK349 */
5783         { RCAR_GP_PIN(6,  6),  8, 3 },  /* SSI_WS349 */
5784         { RCAR_GP_PIN(6,  7),  4, 3 },  /* SSI_SDATA3 */
5785         { RCAR_GP_PIN(6,  8),  0, 3 },  /* SSI_SCK4 */
5786     } },
5787     { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5788         { RCAR_GP_PIN(6,  9), 28, 3 },  /* SSI_WS4 */
5789         { RCAR_GP_PIN(6, 10), 24, 3 },  /* SSI_SDATA4 */
5790         { RCAR_GP_PIN(6, 11), 20, 3 },  /* SSI_SCK5 */
5791         { RCAR_GP_PIN(6, 12), 16, 3 },  /* SSI_WS5 */
5792         { RCAR_GP_PIN(6, 13), 12, 3 },  /* SSI_SDATA5 */
5793         { RCAR_GP_PIN(6, 14),  8, 3 },  /* SSI_SCK6 */
5794         { RCAR_GP_PIN(6, 15),  4, 3 },  /* SSI_WS6 */
5795         { RCAR_GP_PIN(6, 16),  0, 3 },  /* SSI_SDATA6 */
5796     } },
5797     { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5798         { RCAR_GP_PIN(6, 17), 28, 3 },  /* SSI_SCK78 */
5799         { RCAR_GP_PIN(6, 18), 24, 3 },  /* SSI_WS78 */
5800         { RCAR_GP_PIN(6, 19), 20, 3 },  /* SSI_SDATA7 */
5801         { RCAR_GP_PIN(6, 20), 16, 3 },  /* SSI_SDATA8 */
5802         { RCAR_GP_PIN(6, 21), 12, 3 },  /* SSI_SDATA9 */
5803         { RCAR_GP_PIN(6, 22),  8, 3 },  /* AUDIO_CLKA */
5804         { RCAR_GP_PIN(6, 23),  4, 3 },  /* AUDIO_CLKB */
5805         { RCAR_GP_PIN(6, 24),  0, 3 },  /* USB0_PWEN */
5806     } },
5807     { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5808         { RCAR_GP_PIN(6, 25), 28, 3 },  /* USB0_OVC */
5809         { RCAR_GP_PIN(6, 26), 24, 3 },  /* USB1_PWEN */
5810         { RCAR_GP_PIN(6, 27), 20, 3 },  /* USB1_OVC */
5811         { RCAR_GP_PIN(6, 28), 16, 3 },  /* USB30_PWEN */
5812         { RCAR_GP_PIN(6, 29), 12, 3 },  /* USB30_OVC */
5813         { RCAR_GP_PIN(6, 30),  8, 3 },  /* GP6_30 */
5814         { RCAR_GP_PIN(6, 31),  4, 3 },  /* GP6_31 */
5815     } },
5816     { },
5817 };
5818
5819 enum ioctrl_regs {
5820     POCCTRL,
5821     TDSELCTRL,
5822 };
5823
5824 static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5825     [POCCTRL] = { 0xe6060380, },
5826     [TDSELCTRL] = { 0xe60603c0, },
5827     { /* sentinel */ },
5828 };
5829
5830 static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
5831 {
5832     int bit = -EINVAL;
5833
5834     *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
5835
5836     if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5837         bit = pin & 0x1f;
5838
5839     if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5840         bit = (pin & 0x1f) + 12;
5841
5842     return bit;
5843 }
5844
5845 static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5846     { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5847         [ 0] = PIN_QSPI0_SPCLK,     /* QSPI0_SPCLK */
5848         [ 1] = PIN_QSPI0_MOSI_IO0,  /* QSPI0_MOSI_IO0 */
5849         [ 2] = PIN_QSPI0_MISO_IO1,  /* QSPI0_MISO_IO1 */
5850         [ 3] = PIN_QSPI0_IO2,       /* QSPI0_IO2 */
5851         [ 4] = PIN_QSPI0_IO3,       /* QSPI0_IO3 */
5852         [ 5] = PIN_QSPI0_SSL,       /* QSPI0_SSL */
5853         [ 6] = PIN_QSPI1_SPCLK,     /* QSPI1_SPCLK */
5854         [ 7] = PIN_QSPI1_MOSI_IO0,  /* QSPI1_MOSI_IO0 */
5855         [ 8] = PIN_QSPI1_MISO_IO1,  /* QSPI1_MISO_IO1 */
5856         [ 9] = PIN_QSPI1_IO2,       /* QSPI1_IO2 */
5857         [10] = PIN_QSPI1_IO3,       /* QSPI1_IO3 */
5858         [11] = PIN_QSPI1_SSL,       /* QSPI1_SSL */
5859         [12] = PIN_RPC_INT_N,       /* RPC_INT# */
5860         [13] = PIN_RPC_WP_N,        /* RPC_WP# */
5861         [14] = PIN_RPC_RESET_N,     /* RPC_RESET# */
5862         [15] = PIN_AVB_RX_CTL,      /* AVB_RX_CTL */
5863         [16] = PIN_AVB_RXC,     /* AVB_RXC */
5864         [17] = PIN_AVB_RD0,     /* AVB_RD0 */
5865         [18] = PIN_AVB_RD1,     /* AVB_RD1 */
5866         [19] = PIN_AVB_RD2,     /* AVB_RD2 */
5867         [20] = PIN_AVB_RD3,     /* AVB_RD3 */
5868         [21] = PIN_AVB_TX_CTL,      /* AVB_TX_CTL */
5869         [22] = PIN_AVB_TXC,     /* AVB_TXC */
5870         [23] = PIN_AVB_TD0,     /* AVB_TD0 */
5871         [24] = PIN_AVB_TD1,     /* AVB_TD1 */
5872         [25] = PIN_AVB_TD2,     /* AVB_TD2 */
5873         [26] = PIN_AVB_TD3,     /* AVB_TD3 */
5874         [27] = PIN_AVB_TXCREFCLK,   /* AVB_TXCREFCLK */
5875         [28] = PIN_AVB_MDIO,        /* AVB_MDIO */
5876         [29] = RCAR_GP_PIN(2,  9),  /* AVB_MDC */
5877         [30] = RCAR_GP_PIN(2, 10),  /* AVB_MAGIC */
5878         [31] = RCAR_GP_PIN(2, 11),  /* AVB_PHY_INT */
5879     } },
5880     { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5881         [ 0] = RCAR_GP_PIN(2, 12),  /* AVB_LINK */
5882         [ 1] = RCAR_GP_PIN(2, 13),  /* AVB_AVTP_MATCH_A */
5883         [ 2] = RCAR_GP_PIN(2, 14),  /* AVB_AVTP_CAPTURE_A */
5884         [ 3] = RCAR_GP_PIN(2,  0),  /* IRQ0 */
5885         [ 4] = RCAR_GP_PIN(2,  1),  /* IRQ1 */
5886         [ 5] = RCAR_GP_PIN(2,  2),  /* IRQ2 */
5887         [ 6] = RCAR_GP_PIN(2,  3),  /* IRQ3 */
5888         [ 7] = RCAR_GP_PIN(2,  4),  /* IRQ4 */
5889         [ 8] = RCAR_GP_PIN(2,  5),  /* IRQ5 */
5890         [ 9] = RCAR_GP_PIN(2,  6),  /* PWM0 */
5891         [10] = RCAR_GP_PIN(2,  7),  /* PWM1_A */
5892         [11] = RCAR_GP_PIN(2,  8),  /* PWM2_A */
5893         [12] = RCAR_GP_PIN(1,  0),  /* A0 */
5894         [13] = RCAR_GP_PIN(1,  1),  /* A1 */
5895         [14] = RCAR_GP_PIN(1,  2),  /* A2 */
5896         [15] = RCAR_GP_PIN(1,  3),  /* A3 */
5897         [16] = RCAR_GP_PIN(1,  4),  /* A4 */
5898         [17] = RCAR_GP_PIN(1,  5),  /* A5 */
5899         [18] = RCAR_GP_PIN(1,  6),  /* A6 */
5900         [19] = RCAR_GP_PIN(1,  7),  /* A7 */
5901         [20] = RCAR_GP_PIN(1,  8),  /* A8 */
5902         [21] = RCAR_GP_PIN(1,  9),  /* A9 */
5903         [22] = RCAR_GP_PIN(1, 10),  /* A10 */
5904         [23] = RCAR_GP_PIN(1, 11),  /* A11 */
5905         [24] = RCAR_GP_PIN(1, 12),  /* A12 */
5906         [25] = RCAR_GP_PIN(1, 13),  /* A13 */
5907         [26] = RCAR_GP_PIN(1, 14),  /* A14 */
5908         [27] = RCAR_GP_PIN(1, 15),  /* A15 */
5909         [28] = RCAR_GP_PIN(1, 16),  /* A16 */
5910         [29] = RCAR_GP_PIN(1, 17),  /* A17 */
5911         [30] = RCAR_GP_PIN(1, 18),  /* A18 */
5912         [31] = RCAR_GP_PIN(1, 19),  /* A19 */
5913     } },
5914     { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5915         [ 0] = RCAR_GP_PIN(1, 28),  /* CLKOUT */
5916         [ 1] = RCAR_GP_PIN(1, 20),  /* CS0_N */
5917         [ 2] = RCAR_GP_PIN(1, 21),  /* CS1_N */
5918         [ 3] = RCAR_GP_PIN(1, 22),  /* BS_N */
5919         [ 4] = RCAR_GP_PIN(1, 23),  /* RD_N */
5920         [ 5] = RCAR_GP_PIN(1, 24),  /* RD_WR_N */
5921         [ 6] = RCAR_GP_PIN(1, 25),  /* WE0_N */
5922         [ 7] = RCAR_GP_PIN(1, 26),  /* WE1_N */
5923         [ 8] = RCAR_GP_PIN(1, 27),  /* EX_WAIT0_A */
5924         [ 9] = PIN_PRESETOUT_N,     /* PRESETOUT# */
5925         [10] = RCAR_GP_PIN(0,  0),  /* D0 */
5926         [11] = RCAR_GP_PIN(0,  1),  /* D1 */
5927         [12] = RCAR_GP_PIN(0,  2),  /* D2 */
5928         [13] = RCAR_GP_PIN(0,  3),  /* D3 */
5929         [14] = RCAR_GP_PIN(0,  4),  /* D4 */
5930         [15] = RCAR_GP_PIN(0,  5),  /* D5 */
5931         [16] = RCAR_GP_PIN(0,  6),  /* D6 */
5932         [17] = RCAR_GP_PIN(0,  7),  /* D7 */
5933         [18] = RCAR_GP_PIN(0,  8),  /* D8 */
5934         [19] = RCAR_GP_PIN(0,  9),  /* D9 */
5935         [20] = RCAR_GP_PIN(0, 10),  /* D10 */
5936         [21] = RCAR_GP_PIN(0, 11),  /* D11 */
5937         [22] = RCAR_GP_PIN(0, 12),  /* D12 */
5938         [23] = RCAR_GP_PIN(0, 13),  /* D13 */
5939         [24] = RCAR_GP_PIN(0, 14),  /* D14 */
5940         [25] = RCAR_GP_PIN(0, 15),  /* D15 */
5941         [26] = RCAR_GP_PIN(7,  0),  /* AVS1 */
5942         [27] = RCAR_GP_PIN(7,  1),  /* AVS2 */
5943         [28] = RCAR_GP_PIN(7,  2),  /* GP7_02 */
5944         [29] = RCAR_GP_PIN(7,  3),  /* GP7_03 */
5945         [30] = PIN_DU_DOTCLKIN0,    /* DU_DOTCLKIN0 */
5946         [31] = PIN_DU_DOTCLKIN1,    /* DU_DOTCLKIN1 */
5947     } },
5948     { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5949         [ 0] = PIN_DU_DOTCLKIN2,    /* DU_DOTCLKIN2 */
5950         [ 1] = SH_PFC_PIN_NONE,
5951         [ 2] = PIN_FSCLKST,     /* FSCLKST */
5952         [ 3] = PIN_EXTALR,      /* EXTALR*/
5953         [ 4] = PIN_TRST_N,      /* TRST# */
5954         [ 5] = PIN_TCK,         /* TCK */
5955         [ 6] = PIN_TMS,         /* TMS */
5956         [ 7] = PIN_TDI,         /* TDI */
5957         [ 8] = SH_PFC_PIN_NONE,
5958         [ 9] = PIN_ASEBRK,      /* ASEBRK */
5959         [10] = RCAR_GP_PIN(3,  0),  /* SD0_CLK */
5960         [11] = RCAR_GP_PIN(3,  1),  /* SD0_CMD */
5961         [12] = RCAR_GP_PIN(3,  2),  /* SD0_DAT0 */
5962         [13] = RCAR_GP_PIN(3,  3),  /* SD0_DAT1 */
5963         [14] = RCAR_GP_PIN(3,  4),  /* SD0_DAT2 */
5964         [15] = RCAR_GP_PIN(3,  5),  /* SD0_DAT3 */
5965         [16] = RCAR_GP_PIN(3,  6),  /* SD1_CLK */
5966         [17] = RCAR_GP_PIN(3,  7),  /* SD1_CMD */
5967         [18] = RCAR_GP_PIN(3,  8),  /* SD1_DAT0 */
5968         [19] = RCAR_GP_PIN(3,  9),  /* SD1_DAT1 */
5969         [20] = RCAR_GP_PIN(3, 10),  /* SD1_DAT2 */
5970         [21] = RCAR_GP_PIN(3, 11),  /* SD1_DAT3 */
5971         [22] = RCAR_GP_PIN(4,  0),  /* SD2_CLK */
5972         [23] = RCAR_GP_PIN(4,  1),  /* SD2_CMD */
5973         [24] = RCAR_GP_PIN(4,  2),  /* SD2_DAT0 */
5974         [25] = RCAR_GP_PIN(4,  3),  /* SD2_DAT1 */
5975         [26] = RCAR_GP_PIN(4,  4),  /* SD2_DAT2 */
5976         [27] = RCAR_GP_PIN(4,  5),  /* SD2_DAT3 */
5977         [28] = RCAR_GP_PIN(4,  6),  /* SD2_DS */
5978         [29] = RCAR_GP_PIN(4,  7),  /* SD3_CLK */
5979         [30] = RCAR_GP_PIN(4,  8),  /* SD3_CMD */
5980         [31] = RCAR_GP_PIN(4,  9),  /* SD3_DAT0 */
5981     } },
5982     { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5983         [ 0] = RCAR_GP_PIN(4, 10),  /* SD3_DAT1 */
5984         [ 1] = RCAR_GP_PIN(4, 11),  /* SD3_DAT2 */
5985         [ 2] = RCAR_GP_PIN(4, 12),  /* SD3_DAT3 */
5986         [ 3] = RCAR_GP_PIN(4, 13),  /* SD3_DAT4 */
5987         [ 4] = RCAR_GP_PIN(4, 14),  /* SD3_DAT5 */
5988         [ 5] = RCAR_GP_PIN(4, 15),  /* SD3_DAT6 */
5989         [ 6] = RCAR_GP_PIN(4, 16),  /* SD3_DAT7 */
5990         [ 7] = RCAR_GP_PIN(4, 17),  /* SD3_DS */
5991         [ 8] = RCAR_GP_PIN(3, 12),  /* SD0_CD */
5992         [ 9] = RCAR_GP_PIN(3, 13),  /* SD0_WP */
5993         [10] = RCAR_GP_PIN(3, 14),  /* SD1_CD */
5994         [11] = RCAR_GP_PIN(3, 15),  /* SD1_WP */
5995         [12] = RCAR_GP_PIN(5,  0),  /* SCK0 */
5996         [13] = RCAR_GP_PIN(5,  1),  /* RX0 */
5997         [14] = RCAR_GP_PIN(5,  2),  /* TX0 */
5998         [15] = RCAR_GP_PIN(5,  3),  /* CTS0_N */
5999         [16] = RCAR_GP_PIN(5,  4),  /* RTS0_N */
6000         [17] = RCAR_GP_PIN(5,  5),  /* RX1_A */
6001         [18] = RCAR_GP_PIN(5,  6),  /* TX1_A */
6002         [19] = RCAR_GP_PIN(5,  7),  /* CTS1_N */
6003         [20] = RCAR_GP_PIN(5,  8),  /* RTS1_N */
6004         [21] = RCAR_GP_PIN(5,  9),  /* SCK2 */
6005         [22] = RCAR_GP_PIN(5, 10),  /* TX2_A */
6006         [23] = RCAR_GP_PIN(5, 11),  /* RX2_A */
6007         [24] = RCAR_GP_PIN(5, 12),  /* HSCK0 */
6008         [25] = RCAR_GP_PIN(5, 13),  /* HRX0 */
6009         [26] = RCAR_GP_PIN(5, 14),  /* HTX0 */
6010         [27] = RCAR_GP_PIN(5, 15),  /* HCTS0_N */
6011         [28] = RCAR_GP_PIN(5, 16),  /* HRTS0_N */
6012         [29] = RCAR_GP_PIN(5, 17),  /* MSIOF0_SCK */
6013         [30] = RCAR_GP_PIN(5, 18),  /* MSIOF0_SYNC */
6014         [31] = RCAR_GP_PIN(5, 19),  /* MSIOF0_SS1 */
6015     } },
6016     { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6017         [ 0] = RCAR_GP_PIN(5, 20),  /* MSIOF0_TXD */
6018         [ 1] = RCAR_GP_PIN(5, 21),  /* MSIOF0_SS2 */
6019         [ 2] = RCAR_GP_PIN(5, 22),  /* MSIOF0_RXD */
6020         [ 3] = RCAR_GP_PIN(5, 23),  /* MLB_CLK */
6021         [ 4] = RCAR_GP_PIN(5, 24),  /* MLB_SIG */
6022         [ 5] = RCAR_GP_PIN(5, 25),  /* MLB_DAT */
6023         [ 6] = PIN_MLB_REF,     /* MLB_REF */
6024         [ 7] = RCAR_GP_PIN(6,  0),  /* SSI_SCK01239 */
6025         [ 8] = RCAR_GP_PIN(6,  1),  /* SSI_WS01239 */
6026         [ 9] = RCAR_GP_PIN(6,  2),  /* SSI_SDATA0 */
6027         [10] = RCAR_GP_PIN(6,  3),  /* SSI_SDATA1_A */
6028         [11] = RCAR_GP_PIN(6,  4),  /* SSI_SDATA2_A */
6029         [12] = RCAR_GP_PIN(6,  5),  /* SSI_SCK349 */
6030         [13] = RCAR_GP_PIN(6,  6),  /* SSI_WS349 */
6031         [14] = RCAR_GP_PIN(6,  7),  /* SSI_SDATA3 */
6032         [15] = RCAR_GP_PIN(6,  8),  /* SSI_SCK4 */
6033         [16] = RCAR_GP_PIN(6,  9),  /* SSI_WS4 */
6034         [17] = RCAR_GP_PIN(6, 10),  /* SSI_SDATA4 */
6035         [18] = RCAR_GP_PIN(6, 11),  /* SSI_SCK5 */
6036         [19] = RCAR_GP_PIN(6, 12),  /* SSI_WS5 */
6037         [20] = RCAR_GP_PIN(6, 13),  /* SSI_SDATA5 */
6038         [21] = RCAR_GP_PIN(6, 14),  /* SSI_SCK6 */
6039         [22] = RCAR_GP_PIN(6, 15),  /* SSI_WS6 */
6040         [23] = RCAR_GP_PIN(6, 16),  /* SSI_SDATA6 */
6041         [24] = RCAR_GP_PIN(6, 17),  /* SSI_SCK78 */
6042         [25] = RCAR_GP_PIN(6, 18),  /* SSI_WS78 */
6043         [26] = RCAR_GP_PIN(6, 19),  /* SSI_SDATA7 */
6044         [27] = RCAR_GP_PIN(6, 20),  /* SSI_SDATA8 */
6045         [28] = RCAR_GP_PIN(6, 21),  /* SSI_SDATA9_A */
6046         [29] = RCAR_GP_PIN(6, 22),  /* AUDIO_CLKA_A */
6047         [30] = RCAR_GP_PIN(6, 23),  /* AUDIO_CLKB_B */
6048         [31] = RCAR_GP_PIN(6, 24),  /* USB0_PWEN */
6049     } },
6050     { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6051         [ 0] = RCAR_GP_PIN(6, 25),  /* USB0_OVC */
6052         [ 1] = RCAR_GP_PIN(6, 26),  /* USB1_PWEN */
6053         [ 2] = RCAR_GP_PIN(6, 27),  /* USB1_OVC */
6054         [ 3] = RCAR_GP_PIN(6, 28),  /* USB30_PWEN */
6055         [ 4] = RCAR_GP_PIN(6, 29),  /* USB30_OVC */
6056         [ 5] = RCAR_GP_PIN(6, 30),  /* GP6_30 */
6057         [ 6] = RCAR_GP_PIN(6, 31),  /* GP6_31 */
6058         [ 7] = PIN_PRESET_N,        /* PRESET# */
6059         [ 8] = SH_PFC_PIN_NONE,
6060         [ 9] = SH_PFC_PIN_NONE,
6061         [10] = SH_PFC_PIN_NONE,
6062         [11] = SH_PFC_PIN_NONE,
6063         [12] = SH_PFC_PIN_NONE,
6064         [13] = SH_PFC_PIN_NONE,
6065         [14] = SH_PFC_PIN_NONE,
6066         [15] = SH_PFC_PIN_NONE,
6067         [16] = SH_PFC_PIN_NONE,
6068         [17] = SH_PFC_PIN_NONE,
6069         [18] = SH_PFC_PIN_NONE,
6070         [19] = SH_PFC_PIN_NONE,
6071         [20] = SH_PFC_PIN_NONE,
6072         [21] = SH_PFC_PIN_NONE,
6073         [22] = SH_PFC_PIN_NONE,
6074         [23] = SH_PFC_PIN_NONE,
6075         [24] = SH_PFC_PIN_NONE,
6076         [25] = SH_PFC_PIN_NONE,
6077         [26] = SH_PFC_PIN_NONE,
6078         [27] = SH_PFC_PIN_NONE,
6079         [28] = SH_PFC_PIN_NONE,
6080         [29] = SH_PFC_PIN_NONE,
6081         [30] = SH_PFC_PIN_NONE,
6082         [31] = SH_PFC_PIN_NONE,
6083     } },
6084     { /* sentinel */ },
6085 };
6086
6087 static const struct sh_pfc_soc_operations r8a7796_pfc_ops = {
6088     .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
6089     .get_bias = rcar_pinmux_get_bias,
6090     .set_bias = rcar_pinmux_set_bias,
6091 };
6092
6093 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
6094 const struct sh_pfc_soc_info r8a774a1_pinmux_info = {
6095     .name = "r8a774a1_pfc",
6096     .ops = &r8a7796_pfc_ops,
6097     .unlock_reg = 0xe6060000, /* PMMR */
6098
6099     .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6100
6101     .pins = pinmux_pins,
6102     .nr_pins = ARRAY_SIZE(pinmux_pins),
6103     .groups = pinmux_groups.common,
6104     .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6105     .functions = pinmux_functions.common,
6106     .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6107
6108     .cfg_regs = pinmux_config_regs,
6109     .drive_regs = pinmux_drive_regs,
6110     .bias_regs = pinmux_bias_regs,
6111     .ioctrl_regs = pinmux_ioctrl_regs,
6112
6113     .pinmux_data = pinmux_data,
6114     .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6115 };
6116 #endif
6117
6118 #ifdef CONFIG_PINCTRL_PFC_R8A77960
6119 const struct sh_pfc_soc_info r8a77960_pinmux_info = {
6120     .name = "r8a77960_pfc",
6121     .ops = &r8a7796_pfc_ops,
6122     .unlock_reg = 0xe6060000, /* PMMR */
6123
6124     .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6125
6126     .pins = pinmux_pins,
6127     .nr_pins = ARRAY_SIZE(pinmux_pins),
6128     .groups = pinmux_groups.common,
6129     .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6130         ARRAY_SIZE(pinmux_groups.automotive),
6131     .functions = pinmux_functions.common,
6132     .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6133         ARRAY_SIZE(pinmux_functions.automotive),
6134
6135     .cfg_regs = pinmux_config_regs,
6136     .drive_regs = pinmux_drive_regs,
6137     .bias_regs = pinmux_bias_regs,
6138     .ioctrl_regs = pinmux_ioctrl_regs,
6139
6140     .pinmux_data = pinmux_data,
6141     .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6142 };
6143 #endif
6144
6145 #ifdef CONFIG_PINCTRL_PFC_R8A77961
6146 const struct sh_pfc_soc_info r8a77961_pinmux_info = {
6147     .name = "r8a77961_pfc",
6148     .ops = &r8a7796_pfc_ops,
6149     .unlock_reg = 0xe6060000, /* PMMR */
6150
6151     .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6152
6153     .pins = pinmux_pins,
6154     .nr_pins = ARRAY_SIZE(pinmux_pins),
6155     .groups = pinmux_groups.common,
6156     .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6157         ARRAY_SIZE(pinmux_groups.automotive),
6158     .functions = pinmux_functions.common,
6159     .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6160         ARRAY_SIZE(pinmux_functions.automotive),
6161
6162     .cfg_regs = pinmux_config_regs,
6163     .drive_regs = pinmux_drive_regs,
6164     .bias_regs = pinmux_bias_regs,
6165     .ioctrl_regs = pinmux_ioctrl_regs,
6166
6167     .pinmux_data = pinmux_data,
6168     .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6169 };
6170 #endif