pinctrl/renesas/pfc-r8a7779.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * r8a7779 processor support - PFC hardware block
0004  *
0005  * Copyright (C) 2011, 2013  Renesas Solutions Corp.
0006  * Copyright (C) 2011  Magnus Damm
0007  * Copyright (C) 2013  Cogent Embedded, Inc.
0008  */
0009
0010 #include <linux/kernel.h>
0011
0012 #include "sh_pfc.h"
0013
0014 #define CPU_ALL_GP(fn, sfx)                     \
0015     PORT_GP_32(0, fn, sfx),                     \
0016     PORT_GP_32(1, fn, sfx),                     \
0017     PORT_GP_32(2, fn, sfx),                     \
0018     PORT_GP_32(3, fn, sfx),                     \
0019     PORT_GP_32(4, fn, sfx),                     \
0020     PORT_GP_32(5, fn, sfx),                     \
0021     PORT_GP_9(6, fn, sfx)
0022
0023 enum {
0024     PINMUX_RESERVED = 0,
0025
0026     PINMUX_DATA_BEGIN,
0027     GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
0028     PINMUX_DATA_END,
0029
0030     PINMUX_FUNCTION_BEGIN,
0031     GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
0032
0033     /* GPSR0 */
0034     FN_AVS1, FN_AVS2, FN_IP0_7_6, FN_A17,
0035     FN_A18, FN_A19, FN_IP0_9_8, FN_IP0_11_10,
0036     FN_IP0_13_12, FN_IP0_15_14, FN_IP0_18_16, FN_IP0_22_19,
0037     FN_IP0_24_23, FN_IP0_25, FN_IP0_27_26, FN_IP1_1_0,
0038     FN_IP1_3_2, FN_IP1_6_4, FN_IP1_10_7, FN_IP1_14_11,
0039     FN_IP1_18_15, FN_IP0_5_3, FN_IP0_30_28, FN_IP2_18_16,
0040     FN_IP2_21_19, FN_IP2_30_28, FN_IP3_2_0, FN_IP3_11_9,
0041     FN_IP3_14_12, FN_IP3_22_21, FN_IP3_26_24, FN_IP3_31_29,
0042
0043     /* GPSR1 */
0044     FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, FN_IP4_10_8,
0045     FN_IP4_11, FN_IP4_12, FN_IP4_13, FN_IP4_14,
0046     FN_IP4_15, FN_IP4_16, FN_IP4_19_17, FN_IP4_22_20,
0047     FN_IP4_23, FN_IP4_24, FN_IP4_25, FN_IP4_26,
0048     FN_IP4_27, FN_IP4_28, FN_IP4_31_29, FN_IP5_2_0,
0049     FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6,
0050     FN_IP5_7, FN_IP5_8, FN_IP5_10_9, FN_IP5_12_11,
0051     FN_IP5_14_13, FN_IP5_16_15, FN_IP5_20_17, FN_IP5_23_21,
0052
0053     /* GPSR2 */
0054     FN_IP5_27_24, FN_IP8_20, FN_IP8_22_21, FN_IP8_24_23,
0055     FN_IP8_27_25, FN_IP8_30_28, FN_IP9_1_0, FN_IP9_3_2,
0056     FN_IP9_4, FN_IP9_5, FN_IP9_6, FN_IP9_7,
0057     FN_IP9_9_8, FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14,
0058     FN_IP9_18_16, FN_IP9_21_19, FN_IP9_23_22, FN_IP9_25_24,
0059     FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
0060     FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
0061     FN_IP10_20_18, FN_IP10_23_21, FN_IP10_25_24, FN_IP10_28_26,
0062
0063     /* GPSR3 */
0064     FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
0065     FN_IP11_11_9, FN_IP11_14_12, FN_IP11_17_15, FN_IP11_20_18,
0066     FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
0067     FN_IP12_5_3, FN_IP12_8_6, FN_IP12_11_9, FN_IP12_14_12,
0068     FN_IP12_17_15, FN_IP7_16_15, FN_IP7_18_17, FN_IP7_28_27,
0069     FN_IP7_30_29, FN_IP7_20_19, FN_IP7_22_21, FN_IP7_24_23,
0070     FN_IP7_26_25, FN_IP1_20_19, FN_IP1_22_21, FN_IP1_24_23,
0071     FN_IP5_28, FN_IP5_30_29, FN_IP6_1_0, FN_IP6_3_2,
0072
0073     /* GPSR4 */
0074     FN_IP6_5_4, FN_IP6_7_6, FN_IP6_8, FN_IP6_11_9,
0075     FN_IP6_14_12, FN_IP6_17_15, FN_IP6_19_18, FN_IP6_22_20,
0076     FN_IP6_24_23, FN_IP6_26_25, FN_IP6_30_29, FN_IP7_1_0,
0077     FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
0078     FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
0079     FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
0080     FN_IP8_11_8, FN_IP8_15_12, FN_USB_PENC0, FN_USB_PENC1,
0081     FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
0082
0083     /* GPSR5 */
0084     FN_A1, FN_A2, FN_A3, FN_A4,
0085     FN_A5, FN_A6, FN_A7, FN_A8,
0086     FN_A9, FN_A10, FN_A11, FN_A12,
0087     FN_A13, FN_A14, FN_A15, FN_A16,
0088     FN_RD, FN_WE0, FN_WE1, FN_EX_WAIT0,
0089     FN_IP3_23, FN_IP3_27, FN_IP3_28, FN_IP2_22,
0090     FN_IP2_23, FN_IP2_24, FN_IP2_25, FN_IP2_26,
0091     FN_IP2_27, FN_IP3_3, FN_IP3_4, FN_IP3_5,
0092
0093     /* GPSR6 */
0094     FN_IP3_6, FN_IP3_7, FN_IP3_8, FN_IP3_15,
0095     FN_IP3_16, FN_IP3_17, FN_IP3_18, FN_IP3_19,
0096     FN_IP3_20,
0097
0098     /* IPSR0 */
0099     FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
0100     FN_HRTS1, FN_RX4_C,
0101     FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B,
0102     FN_CS0, FN_HSPI_CS2_B,
0103     FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B,
0104     FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
0105     FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
0106     FN_CTS0_B,
0107     FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
0108     FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B,
0109     FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
0110     FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
0111     FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B,
0112     FN_A20, FN_TX5_D, FN_HSPI_TX2_B,
0113     FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
0114     FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
0115     FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
0116     FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
0117     FN_SCIF_CLK, FN_TCLK0_C,
0118
0119     /* IPSR1 */
0120     FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6,
0121     FN_FD6, FN_EX_CS1, FN_MMC0_D7, FN_FD7,
0122     FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
0123     FN_ATACS00, FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD,
0124     FN_FRE, FN_ATACS10, FN_VI1_R4, FN_RX5_B,
0125     FN_HSCK1, FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9,
0126     FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
0127     FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
0128     FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, FN_EX_CS5,
0129     FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, FN_ATAWR0,
0130     FN_VI1_R6, FN_HRX1, FN_RX2_E, FN_RX0_B,
0131     FN_SSI_WS9, FN_MLB_CLK, FN_PWM2, FN_SCK4,
0132     FN_MLB_SIG, FN_PWM3, FN_TX4, FN_MLB_DAT,
0133     FN_PWM4, FN_RX4, FN_HTX0, FN_TX1,
0134     FN_SDATA, FN_CTS0_C, FN_SUB_TCK, FN_CC5_STATE2,
0135     FN_CC5_STATE10, FN_CC5_STATE18, FN_CC5_STATE26, FN_CC5_STATE34,
0136
0137     /* IPSR2 */
0138     FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
0139     FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
0140     FN_CC5_STATE27, FN_CC5_STATE35, FN_HSCK0, FN_SCK1,
0141     FN_MTS, FN_PWM5, FN_SCK0_C, FN_SSI_SDATA9_B,
0142     FN_SUB_TDO, FN_CC5_STATE0, FN_CC5_STATE8, FN_CC5_STATE16,
0143     FN_CC5_STATE24, FN_CC5_STATE32, FN_HCTS0, FN_CTS1,
0144     FN_STM, FN_PWM0_D, FN_RX0_C, FN_SCIF_CLK_C,
0145     FN_SUB_TRST, FN_TCLK1_B, FN_CC5_OSCOUT, FN_HRTS0,
0146     FN_RTS1_TANS, FN_MDATA, FN_TX0_C, FN_SUB_TMS,
0147     FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, FN_CC5_STATE25,
0148     FN_CC5_STATE33, FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0,
0149     FN_GPS_CLK_B, FN_AUDATA0, FN_TX5_C, FN_DU0_DR1,
0150     FN_LCDOUT1, FN_DACK0, FN_DRACK0, FN_GPS_SIGN_B,
0151     FN_AUDATA1, FN_RX5_C, FN_DU0_DR2, FN_LCDOUT2,
0152     FN_DU0_DR3, FN_LCDOUT3, FN_DU0_DR4, FN_LCDOUT4,
0153     FN_DU0_DR5, FN_LCDOUT5, FN_DU0_DR6, FN_LCDOUT6,
0154     FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8,
0155     FN_DREQ1, FN_SCL2, FN_AUDATA2,
0156
0157     /* IPSR3 */
0158     FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
0159     FN_AUDATA3, FN_DU0_DG2, FN_LCDOUT10, FN_DU0_DG3,
0160     FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, FN_DU0_DG5,
0161     FN_LCDOUT13, FN_DU0_DG6, FN_LCDOUT14, FN_DU0_DG7,
0162     FN_LCDOUT15, FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1,
0163     FN_SCL1, FN_TCLK1, FN_AUDATA4, FN_DU0_DB1,
0164     FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, FN_GPS_MAG_B,
0165     FN_AUDATA5, FN_SCK5_C, FN_DU0_DB2, FN_LCDOUT18,
0166     FN_DU0_DB3, FN_LCDOUT19, FN_DU0_DB4, FN_LCDOUT20,
0167     FN_DU0_DB5, FN_LCDOUT21, FN_DU0_DB6, FN_LCDOUT22,
0168     FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
0169     FN_TX3_D_IRDA_TX_D, FN_SCL3_B, FN_DU0_DOTCLKOUT0, FN_QCLK,
0170     FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
0171     FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, FN_DU0_EXHSYNC_DU0_HSYNC,
0172     FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
0173     FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX,
0174     FN_TX2_C, FN_SCL2_C, FN_REMOCON,
0175
0176     /* IPSR4 */
0177     FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C,
0178     FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
0179     FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, FN_DU1_DR0,
0180     FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, FN_TX3_E_IRDA_TX_E,
0181     FN_AUDCK, FN_PWMFSW0_B, FN_DU1_DR1, FN_VI2_DATA1_VI2_B1,
0182     FN_PWM0, FN_SD3_CMD, FN_RX3_E_IRDA_RX_E, FN_AUDSYNC,
0183     FN_CTS0_D, FN_DU1_DR2, FN_VI2_G0, FN_DU1_DR3,
0184     FN_VI2_G1, FN_DU1_DR4, FN_VI2_G2, FN_DU1_DR5,
0185     FN_VI2_G3, FN_DU1_DR6, FN_VI2_G4, FN_DU1_DR7,
0186     FN_VI2_G5, FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B,
0187     FN_SD3_DAT2, FN_SCK3_E, FN_AUDATA6, FN_TX0_D,
0188     FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
0189     FN_SCK5, FN_AUDATA7, FN_RX0_D, FN_DU1_DG2,
0190     FN_VI2_G6, FN_DU1_DG3, FN_VI2_G7, FN_DU1_DG4,
0191     FN_VI2_R0, FN_DU1_DG5, FN_VI2_R1, FN_DU1_DG6,
0192     FN_VI2_R2, FN_DU1_DG7, FN_VI2_R3, FN_DU1_DB0,
0193     FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, FN_TX5,
0194     FN_SCK0_D,
0195
0196     /* IPSR5 */
0197     FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
0198     FN_RX5, FN_RTS0_D_TANS_D, FN_DU1_DB2, FN_VI2_R4,
0199     FN_DU1_DB3, FN_VI2_R5, FN_DU1_DB4, FN_VI2_R6,
0200     FN_DU1_DB5, FN_VI2_R7, FN_DU1_DB6, FN_SCL2_D,
0201     FN_DU1_DB7, FN_SDA2_D, FN_DU1_DOTCLKIN, FN_VI2_CLKENB,
0202     FN_HSPI_CS1, FN_SCL1_D, FN_DU1_DOTCLKOUT, FN_VI2_FIELD,
0203     FN_SDA1_D, FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC,
0204     FN_VI3_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC,
0205     FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
0206     FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
0207     FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D,
0208     FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
0209     FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
0210     FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B,
0211     FN_SD3_WP, FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD,
0212     FN_AUDIO_CLKOUT, FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D,
0213     FN_AUDIO_CLKA, FN_CAN_TXCLK, FN_AUDIO_CLKB, FN_USB_OVC2,
0214     FN_CAN_DEBUGOUT0, FN_MOUT0,
0215
0216     /* IPSR6 */
0217     FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, FN_SSI_WS0129,
0218     FN_CAN_DEBUGOUT2, FN_MOUT2, FN_SSI_SDATA0, FN_CAN_DEBUGOUT3,
0219     FN_MOUT5, FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6,
0220     FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, FN_SSI_SCK34, FN_CAN_DEBUGOUT6,
0221     FN_CAN0_TX_B, FN_IERX, FN_SSI_SCK9_C, FN_SSI_WS34,
0222     FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, FN_SSI_WS9_C,
0223     FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
0224     FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, FN_SSI_SDATA4,
0225     FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, FN_SSI_SCK5, FN_ADICLK,
0226     FN_CAN_DEBUGOUT10, FN_SCK3, FN_TCLK0_D, FN_SSI_WS5,
0227     FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, FN_SSI_SDATA5,
0228     FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, FN_SSI_SCK6,
0229     FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
0230
0231     /* IPSR7 */
0232     FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B,
0233     FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
0234     FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
0235     FN_HSPI_CLK1_C, FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B,
0236     FN_SSI_WS9_B, FN_HSPI_CS1_C, FN_SSI_SDATA7, FN_CAN_DEBUGOUT15,
0237     FN_IRQ2_B, FN_TCLK1_C, FN_HSPI_TX1_C, FN_SSI_SDATA8,
0238     FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, FN_SD0_CLK,
0239     FN_ATACS01, FN_SCK1_B, FN_SD0_CMD, FN_ATACS11,
0240     FN_TX1_B, FN_CC5_TDO, FN_SD0_DAT0, FN_ATADIR1,
0241     FN_RX1_B, FN_CC5_TRST, FN_SD0_DAT1, FN_ATAG1,
0242     FN_SCK2_B, FN_CC5_TMS, FN_SD0_DAT2, FN_ATARD1,
0243     FN_TX2_B, FN_CC5_TCK, FN_SD0_DAT3, FN_ATAWR1,
0244     FN_RX2_B, FN_CC5_TDI, FN_SD0_CD, FN_DREQ2,
0245     FN_RTS1_B_TANS_B, FN_SD0_WP, FN_DACK2, FN_CTS1_B,
0246
0247     /* IPSR8 */
0248     FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
0249     FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
0250     FN_CC5_STATE36, FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1,
0251     FN_AD_DI, FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21,
0252     FN_CC5_STATE29, FN_CC5_STATE37, FN_HSPI_TX0, FN_TX0,
0253     FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, FN_CC5_STATE6, FN_CC5_STATE14,
0254     FN_CC5_STATE22, FN_CC5_STATE30, FN_CC5_STATE38, FN_HSPI_RX0,
0255     FN_RX0, FN_CAN_STEP0, FN_AD_NCS, FN_CC5_STATE7,
0256     FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, FN_CC5_STATE39,
0257     FN_FMCLK, FN_RDS_CLK, FN_PCMOE, FN_BPFCLK,
0258     FN_PCMWE, FN_FMIN, FN_RDS_DATA, FN_VI0_CLK,
0259     FN_MMC1_CLK, FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B,
0260     FN_MT1_SYNC, FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B,
0261     FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
0262     FN_MMC1_CMD, FN_HSCK1_B, FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B,
0263     FN_RTS1_C_TANS_C, FN_RX4_D, FN_PWMFSW0_C,
0264
0265     /* IPSR9 */
0266     FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, FN_VI0_DATA1_VI0_B1,
0267     FN_HCTS1_B, FN_MT1_PWM, FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
0268     FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
0269     FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, FN_VI0_DATA6_VI0_B6, FN_MMC1_D4,
0270     FN_ARM_TRACEDATA_0, FN_VI0_DATA7_VI0_B7, FN_MMC1_D5,
0271     FN_ARM_TRACEDATA_1, FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0,
0272     FN_ARM_TRACEDATA_2, FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1,
0273     FN_ARM_TRACEDATA_3, FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6,
0274     FN_ARM_TRACEDATA_4, FN_TS_SPSYNC0, FN_VI0_G3, FN_ETH_CRS_DV,
0275     FN_MMC1_D7, FN_ARM_TRACEDATA_5, FN_TS_SDAT0, FN_VI0_G4,
0276     FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, FN_VI0_G5,
0277     FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, FN_VI0_G6,
0278     FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, FN_VI0_G7,
0279     FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
0280
0281     /* IPSR10 */
0282     FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
0283     FN_ARM_TRACEDATA_10, FN_DREQ0_C, FN_VI0_R1, FN_SSI_SDATA8_C,
0284     FN_DACK1_B, FN_ARM_TRACEDATA_11, FN_DACK0_C, FN_DRACK0_C,
0285     FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
0286     FN_ARM_TRACEDATA_12, FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B,
0287     FN_IRQ3, FN_ARM_TRACEDATA_13, FN_VI0_R4, FN_ETH_REFCLK,
0288     FN_SD2_CD_B, FN_HSPI_CLK1_B, FN_ARM_TRACEDATA_14, FN_MT1_CLK,
0289     FN_TS_SCK0, FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
0290     FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, FN_VI0_R6,
0291     FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, FN_TRACECLK,
0292     FN_MT1_BEN, FN_PWMFSW0_D, FN_VI0_R7, FN_ETH_MDIO,
0293     FN_DACK2_C, FN_HSPI_RX1_B, FN_SCIF_CLK_D, FN_TRACECTL,
0294     FN_MT1_PEN, FN_VI1_CLK, FN_SIM_D, FN_SDA3,
0295     FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
0296     FN_PWMFSW0_E, FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4,
0297     FN_SIM_CLK, FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3,
0298
0299     /* IPSR11 */
0300     FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
0301     FN_ADICLK_B, FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK,
0302     FN_SPV_TMS, FN_ADICS_B_SAMP_B, FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2,
0303     FN_MT0_D, FN_SPVTDI, FN_ADIDATA_B, FN_VI1_DATA3_VI1_B3,
0304     FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, FN_ADICHS0_B,
0305     FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
0306     FN_HSPI_CLK1_D, FN_ADICHS1_B, FN_VI1_DATA5_VI1_B5, FN_SD2_CMD,
0307     FN_MT0_SYNC, FN_SPA_TCK, FN_HSPI_CS1_D, FN_ADICHS2_B,
0308     FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
0309     FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM,
0310     FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0,
0311     FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
0312     FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1,
0313     FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B,
0314
0315     /* IPSR12 */
0316     FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
0317     FN_SCK2, FN_HSCK0_B, FN_VI1_G3, FN_VI3_DATA3,
0318     FN_SSI_SCK2, FN_TS_SDAT1, FN_SCL1_C, FN_HTX0_B,
0319     FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
0320     FN_SIM_RST_B, FN_HRX0_B, FN_VI1_G5, FN_VI3_DATA5,
0321     FN_GPS_CLK, FN_FSE, FN_TX4_B, FN_SIM_D_B,
0322     FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
0323     FN_RX4_B, FN_SIM_CLK_B, FN_VI1_G7, FN_VI3_DATA7,
0324     FN_GPS_MAG, FN_FCE, FN_SCK4_B,
0325
0326     FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
0327     FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
0328     FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
0329     FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
0330     FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
0331     FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
0332     FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
0333     FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
0334     FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2,
0335     FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
0336     FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
0337     FN_SEL_VI0_0, FN_SEL_VI0_1,
0338     FN_SEL_SD2_0, FN_SEL_SD2_1,
0339     FN_SEL_INT3_0, FN_SEL_INT3_1,
0340     FN_SEL_INT2_0, FN_SEL_INT2_1,
0341     FN_SEL_INT1_0, FN_SEL_INT1_1,
0342     FN_SEL_INT0_0, FN_SEL_INT0_1,
0343     FN_SEL_IE_0, FN_SEL_IE_1,
0344     FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2,
0345     FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
0346     FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2,
0347
0348     FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2,
0349     FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
0350     FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
0351     FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
0352     FN_SEL_CAN0_0, FN_SEL_CAN0_1,
0353     FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
0354     FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
0355     FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
0356     FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4,
0357     FN_SEL_ADI_0, FN_SEL_ADI_1,
0358     FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
0359     FN_SEL_SIM_0, FN_SEL_SIM_1,
0360     FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
0361     FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
0362     FN_SEL_I2C3_0, FN_SEL_I2C3_1,
0363     FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
0364     FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
0365     PINMUX_FUNCTION_END,
0366
0367     PINMUX_MARK_BEGIN,
0368     AVS1_MARK, AVS2_MARK, A17_MARK, A18_MARK,
0369     A19_MARK,
0370
0371     RD_WR_MARK, FWE_MARK, ATAG0_MARK, VI1_R7_MARK,
0372     HRTS1_MARK, RX4_C_MARK,
0373     CS1_A26_MARK, HSPI_TX2_MARK, SDSELF_B_MARK,
0374     CS0_MARK, HSPI_CS2_B_MARK,
0375     CLKOUT_MARK, TX3C_IRDA_TX_C_MARK, PWM0_B_MARK,
0376     A25_MARK, SD1_WP_MARK, MMC0_D5_MARK, FD5_MARK,
0377     HSPI_RX2_MARK, VI1_R3_MARK, TX5_B_MARK, SSI_SDATA7_B_MARK, CTS0_B_MARK,
0378     A24_MARK, SD1_CD_MARK, MMC0_D4_MARK, FD4_MARK,
0379     HSPI_CS2_MARK, VI1_R2_MARK, SSI_WS78_B_MARK,
0380     A23_MARK, FCLE_MARK, HSPI_CLK2_MARK, VI1_R1_MARK,
0381     A22_MARK, RX5_D_MARK, HSPI_RX2_B_MARK, VI1_R0_MARK,
0382     A21_MARK, SCK5_D_MARK, HSPI_CLK2_B_MARK,
0383     A20_MARK, TX5_D_MARK, HSPI_TX2_B_MARK,
0384     A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
0385     BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
0386     ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
0387     USB_PENC0_MARK, USB_PENC1_MARK, USB_PENC2_MARK,
0388     SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
0389     SCIF_CLK_MARK, TCLK0_C_MARK,
0390
0391     EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
0392     FD6_MARK, EX_CS1_MARK, MMC0_D7_MARK, FD7_MARK,
0393     EX_CS2_MARK, SD1_CLK_MARK, MMC0_CLK_MARK, FALE_MARK,
0394     ATACS00_MARK, EX_CS3_MARK, SD1_CMD_MARK, MMC0_CMD_MARK,
0395     FRE_MARK, ATACS10_MARK, VI1_R4_MARK, RX5_B_MARK,
0396     HSCK1_MARK, SSI_SDATA8_B_MARK, RTS0_B_TANS_B_MARK, SSI_SDATA9_MARK,
0397     EX_CS4_MARK, SD1_DAT0_MARK, MMC0_D0_MARK, FD0_MARK,
0398     ATARD0_MARK, VI1_R5_MARK, SCK5_B_MARK, HTX1_MARK,
0399     TX2_E_MARK, TX0_B_MARK, SSI_SCK9_MARK, EX_CS5_MARK,
0400     SD1_DAT1_MARK, MMC0_D1_MARK, FD1_MARK, ATAWR0_MARK,
0401     VI1_R6_MARK, HRX1_MARK, RX2_E_MARK, RX0_B_MARK,
0402     SSI_WS9_MARK, MLB_CLK_MARK, PWM2_MARK, SCK4_MARK,
0403     MLB_SIG_MARK, PWM3_MARK, TX4_MARK, MLB_DAT_MARK,
0404     PWM4_MARK, RX4_MARK, HTX0_MARK, TX1_MARK,
0405     SDATA_MARK, CTS0_C_MARK, SUB_TCK_MARK, CC5_STATE2_MARK,
0406     CC5_STATE10_MARK, CC5_STATE18_MARK, CC5_STATE26_MARK, CC5_STATE34_MARK,
0407
0408     HRX0_MARK, RX1_MARK, SCKZ_MARK, RTS0_C_TANS_C_MARK,
0409     SUB_TDI_MARK, CC5_STATE3_MARK, CC5_STATE11_MARK, CC5_STATE19_MARK,
0410     CC5_STATE27_MARK, CC5_STATE35_MARK, HSCK0_MARK, SCK1_MARK,
0411     MTS_MARK, PWM5_MARK, SCK0_C_MARK, SSI_SDATA9_B_MARK,
0412     SUB_TDO_MARK, CC5_STATE0_MARK, CC5_STATE8_MARK, CC5_STATE16_MARK,
0413     CC5_STATE24_MARK, CC5_STATE32_MARK, HCTS0_MARK, CTS1_MARK,
0414     STM_MARK, PWM0_D_MARK, RX0_C_MARK, SCIF_CLK_C_MARK,
0415     SUB_TRST_MARK, TCLK1_B_MARK, CC5_OSCOUT_MARK, HRTS0_MARK,
0416     RTS1_TANS_MARK, MDATA_MARK, TX0_C_MARK, SUB_TMS_MARK,
0417     CC5_STATE1_MARK, CC5_STATE9_MARK, CC5_STATE17_MARK, CC5_STATE25_MARK,
0418     CC5_STATE33_MARK, DU0_DR0_MARK, LCDOUT0_MARK, DREQ0_MARK,
0419     GPS_CLK_B_MARK, AUDATA0_MARK, TX5_C_MARK, DU0_DR1_MARK,
0420     LCDOUT1_MARK, DACK0_MARK, DRACK0_MARK, GPS_SIGN_B_MARK,
0421     AUDATA1_MARK, RX5_C_MARK, DU0_DR2_MARK, LCDOUT2_MARK,
0422     DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK,
0423     DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK,
0424     DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK,
0425     DREQ1_MARK, SCL2_MARK, AUDATA2_MARK,
0426
0427     DU0_DG1_MARK, LCDOUT9_MARK, DACK1_MARK, SDA2_MARK,
0428     AUDATA3_MARK, DU0_DG2_MARK, LCDOUT10_MARK, DU0_DG3_MARK,
0429     LCDOUT11_MARK, DU0_DG4_MARK, LCDOUT12_MARK, DU0_DG5_MARK,
0430     LCDOUT13_MARK, DU0_DG6_MARK, LCDOUT14_MARK, DU0_DG7_MARK,
0431     LCDOUT15_MARK, DU0_DB0_MARK, LCDOUT16_MARK, EX_WAIT1_MARK,
0432     SCL1_MARK, TCLK1_MARK, AUDATA4_MARK, DU0_DB1_MARK,
0433     LCDOUT17_MARK, EX_WAIT2_MARK, SDA1_MARK, GPS_MAG_B_MARK,
0434     AUDATA5_MARK, SCK5_C_MARK, DU0_DB2_MARK, LCDOUT18_MARK,
0435     DU0_DB3_MARK, LCDOUT19_MARK, DU0_DB4_MARK, LCDOUT20_MARK,
0436     DU0_DB5_MARK, LCDOUT21_MARK, DU0_DB6_MARK, LCDOUT22_MARK,
0437     DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
0438     TX3_D_IRDA_TX_D_MARK, SCL3_B_MARK, DU0_DOTCLKOUT0_MARK, QCLK_MARK,
0439     DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, RX3_D_IRDA_RX_D_MARK, SDA3_B_MARK,
0440     SDA2_C_MARK, DACK0_B_MARK, DRACK0_B_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
0441     QSTH_QHS_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
0442     DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CAN1_TX_MARK,
0443     TX2_C_MARK, SCL2_C_MARK, REMOCON_MARK,
0444
0445     DU0_DISP_MARK, QPOLA_MARK, CAN_CLK_C_MARK, SCK2_C_MARK,
0446     DU0_CDE_MARK, QPOLB_MARK, CAN1_RX_MARK, RX2_C_MARK,
0447     DREQ0_B_MARK, SSI_SCK78_B_MARK, SCK0_B_MARK, DU1_DR0_MARK,
0448     VI2_DATA0_VI2_B0_MARK, PWM6_MARK, SD3_CLK_MARK, TX3_E_IRDA_TX_E_MARK,
0449     AUDCK_MARK, PWMFSW0_B_MARK, DU1_DR1_MARK, VI2_DATA1_VI2_B1_MARK,
0450     PWM0_MARK, SD3_CMD_MARK, RX3_E_IRDA_RX_E_MARK, AUDSYNC_MARK,
0451     CTS0_D_MARK, DU1_DR2_MARK, VI2_G0_MARK, DU1_DR3_MARK,
0452     VI2_G1_MARK, DU1_DR4_MARK, VI2_G2_MARK, DU1_DR5_MARK,
0453     VI2_G3_MARK, DU1_DR6_MARK, VI2_G4_MARK, DU1_DR7_MARK,
0454     VI2_G5_MARK, DU1_DG0_MARK, VI2_DATA2_VI2_B2_MARK, SCL1_B_MARK,
0455     SD3_DAT2_MARK, SCK3_E_MARK, AUDATA6_MARK, TX0_D_MARK,
0456     DU1_DG1_MARK, VI2_DATA3_VI2_B3_MARK, SDA1_B_MARK, SD3_DAT3_MARK,
0457     SCK5_MARK, AUDATA7_MARK, RX0_D_MARK, DU1_DG2_MARK,
0458     VI2_G6_MARK, DU1_DG3_MARK, VI2_G7_MARK, DU1_DG4_MARK,
0459     VI2_R0_MARK, DU1_DG5_MARK, VI2_R1_MARK, DU1_DG6_MARK,
0460     VI2_R2_MARK, DU1_DG7_MARK, VI2_R3_MARK, DU1_DB0_MARK,
0461     VI2_DATA4_VI2_B4_MARK, SCL2_B_MARK, SD3_DAT0_MARK, TX5_MARK,
0462     SCK0_D_MARK,
0463
0464     DU1_DB1_MARK, VI2_DATA5_VI2_B5_MARK, SDA2_B_MARK, SD3_DAT1_MARK,
0465     RX5_MARK, RTS0_D_TANS_D_MARK, DU1_DB2_MARK, VI2_R4_MARK,
0466     DU1_DB3_MARK, VI2_R5_MARK, DU1_DB4_MARK, VI2_R6_MARK,
0467     DU1_DB5_MARK, VI2_R7_MARK, DU1_DB6_MARK, SCL2_D_MARK,
0468     DU1_DB7_MARK, SDA2_D_MARK, DU1_DOTCLKIN_MARK, VI2_CLKENB_MARK,
0469     HSPI_CS1_MARK, SCL1_D_MARK, DU1_DOTCLKOUT_MARK, VI2_FIELD_MARK,
0470     SDA1_D_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, VI2_HSYNC_MARK,
0471     VI3_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, VI2_VSYNC_MARK,
0472     VI3_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, VI2_CLK_MARK,
0473     TX3_B_IRDA_TX_B_MARK, SD3_CD_MARK, HSPI_TX1_MARK, VI1_CLKENB_MARK,
0474     VI3_CLKENB_MARK, AUDIO_CLKC_MARK, TX2_D_MARK, SPEEDIN_MARK,
0475     GPS_SIGN_D_MARK, DU1_DISP_MARK, VI2_DATA6_VI2_B6_MARK, TCLK0_MARK,
0476     QSTVA_B_QVS_B_MARK, HSPI_CLK1_MARK, SCK2_D_MARK, AUDIO_CLKOUT_B_MARK,
0477     GPS_MAG_D_MARK, DU1_CDE_MARK, VI2_DATA7_VI2_B7_MARK,
0478     RX3_B_IRDA_RX_B_MARK, SD3_WP_MARK, HSPI_RX1_MARK, VI1_FIELD_MARK,
0479     VI3_FIELD_MARK, AUDIO_CLKOUT_MARK, RX2_D_MARK, GPS_CLK_C_MARK,
0480     GPS_CLK_D_MARK, AUDIO_CLKA_MARK, CAN_TXCLK_MARK, AUDIO_CLKB_MARK,
0481     USB_OVC2_MARK, CAN_DEBUGOUT0_MARK, MOUT0_MARK,
0482
0483     SSI_SCK0129_MARK, CAN_DEBUGOUT1_MARK, MOUT1_MARK, SSI_WS0129_MARK,
0484     CAN_DEBUGOUT2_MARK, MOUT2_MARK, SSI_SDATA0_MARK, CAN_DEBUGOUT3_MARK,
0485     MOUT5_MARK, SSI_SDATA1_MARK, CAN_DEBUGOUT4_MARK, MOUT6_MARK,
0486     SSI_SDATA2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK34_MARK,
0487     CAN_DEBUGOUT6_MARK, CAN0_TX_B_MARK, IERX_MARK, SSI_SCK9_C_MARK,
0488     SSI_WS34_MARK, CAN_DEBUGOUT7_MARK, CAN0_RX_B_MARK, IETX_MARK,
0489     SSI_WS9_C_MARK, SSI_SDATA3_MARK, PWM0_C_MARK, CAN_DEBUGOUT8_MARK,
0490     CAN_CLK_B_MARK, IECLK_MARK, SCIF_CLK_B_MARK, TCLK0_B_MARK,
0491     SSI_SDATA4_MARK, CAN_DEBUGOUT9_MARK, SSI_SDATA9_C_MARK, SSI_SCK5_MARK,
0492     ADICLK_MARK, CAN_DEBUGOUT10_MARK, SCK3_MARK, TCLK0_D_MARK,
0493     SSI_WS5_MARK, ADICS_SAMP_MARK, CAN_DEBUGOUT11_MARK, TX3_IRDA_TX_MARK,
0494     SSI_SDATA5_MARK, ADIDATA_MARK, CAN_DEBUGOUT12_MARK, RX3_IRDA_RX_MARK,
0495     SSI_SCK6_MARK, ADICHS0_MARK, CAN0_TX_MARK, IERX_B_MARK,
0496
0497     SSI_WS6_MARK, ADICHS1_MARK, CAN0_RX_MARK, IETX_B_MARK,
0498     SSI_SDATA6_MARK, ADICHS2_MARK, CAN_CLK_MARK, IECLK_B_MARK,
0499     SSI_SCK78_MARK, CAN_DEBUGOUT13_MARK, IRQ0_B_MARK, SSI_SCK9_B_MARK,
0500     HSPI_CLK1_C_MARK, SSI_WS78_MARK, CAN_DEBUGOUT14_MARK, IRQ1_B_MARK,
0501     SSI_WS9_B_MARK, HSPI_CS1_C_MARK, SSI_SDATA7_MARK, CAN_DEBUGOUT15_MARK,
0502     IRQ2_B_MARK, TCLK1_C_MARK, HSPI_TX1_C_MARK, SSI_SDATA8_MARK,
0503     VSP_MARK, IRQ3_B_MARK, HSPI_RX1_C_MARK, SD0_CLK_MARK,
0504     ATACS01_MARK, SCK1_B_MARK, SD0_CMD_MARK, ATACS11_MARK,
0505     TX1_B_MARK, CC5_TDO_MARK, SD0_DAT0_MARK, ATADIR1_MARK,
0506     RX1_B_MARK, CC5_TRST_MARK, SD0_DAT1_MARK, ATAG1_MARK,
0507     SCK2_B_MARK, CC5_TMS_MARK, SD0_DAT2_MARK, ATARD1_MARK,
0508     TX2_B_MARK, CC5_TCK_MARK, SD0_DAT3_MARK, ATAWR1_MARK,
0509     RX2_B_MARK, CC5_TDI_MARK, SD0_CD_MARK, DREQ2_MARK,
0510     RTS1_B_TANS_B_MARK, SD0_WP_MARK, DACK2_MARK, CTS1_B_MARK,
0511
0512     HSPI_CLK0_MARK, CTS0_MARK, USB_OVC0_MARK, AD_CLK_MARK,
0513     CC5_STATE4_MARK, CC5_STATE12_MARK, CC5_STATE20_MARK, CC5_STATE28_MARK,
0514     CC5_STATE36_MARK, HSPI_CS0_MARK, RTS0_TANS_MARK, USB_OVC1_MARK,
0515     AD_DI_MARK, CC5_STATE5_MARK, CC5_STATE13_MARK, CC5_STATE21_MARK,
0516     CC5_STATE29_MARK, CC5_STATE37_MARK, HSPI_TX0_MARK, TX0_MARK,
0517     CAN_DEBUG_HW_TRIGGER_MARK, AD_DO_MARK, CC5_STATE6_MARK,
0518     CC5_STATE14_MARK, CC5_STATE22_MARK, CC5_STATE30_MARK,
0519     CC5_STATE38_MARK, HSPI_RX0_MARK, RX0_MARK, CAN_STEP0_MARK,
0520     AD_NCS_MARK, CC5_STATE7_MARK, CC5_STATE15_MARK, CC5_STATE23_MARK,
0521     CC5_STATE31_MARK, CC5_STATE39_MARK, FMCLK_MARK, RDS_CLK_MARK,
0522     PCMOE_MARK, BPFCLK_MARK, PCMWE_MARK, FMIN_MARK, RDS_DATA_MARK,
0523     VI0_CLK_MARK, MMC1_CLK_MARK, VI0_CLKENB_MARK, TX1_C_MARK, HTX1_B_MARK,
0524     MT1_SYNC_MARK, VI0_FIELD_MARK, RX1_C_MARK, HRX1_B_MARK,
0525     VI0_HSYNC_MARK, VI0_DATA0_B_VI0_B0_B_MARK, CTS1_C_MARK, TX4_D_MARK,
0526     MMC1_CMD_MARK, HSCK1_B_MARK, VI0_VSYNC_MARK, VI0_DATA1_B_VI0_B1_B_MARK,
0527     RTS1_C_TANS_C_MARK, RX4_D_MARK, PWMFSW0_C_MARK,
0528
0529     VI0_DATA0_VI0_B0_MARK, HRTS1_B_MARK, MT1_VCXO_MARK,
0530     VI0_DATA1_VI0_B1_MARK, HCTS1_B_MARK, MT1_PWM_MARK,
0531     VI0_DATA2_VI0_B2_MARK, MMC1_D0_MARK, VI0_DATA3_VI0_B3_MARK,
0532     MMC1_D1_MARK, VI0_DATA4_VI0_B4_MARK, MMC1_D2_MARK,
0533     VI0_DATA5_VI0_B5_MARK, MMC1_D3_MARK, VI0_DATA6_VI0_B6_MARK,
0534     MMC1_D4_MARK, ARM_TRACEDATA_0_MARK, VI0_DATA7_VI0_B7_MARK,
0535     MMC1_D5_MARK, ARM_TRACEDATA_1_MARK, VI0_G0_MARK, SSI_SCK78_C_MARK,
0536     IRQ0_MARK, ARM_TRACEDATA_2_MARK, VI0_G1_MARK, SSI_WS78_C_MARK,
0537     IRQ1_MARK, ARM_TRACEDATA_3_MARK, VI0_G2_MARK, ETH_TXD1_MARK,
0538     MMC1_D6_MARK, ARM_TRACEDATA_4_MARK, TS_SPSYNC0_MARK, VI0_G3_MARK,
0539     ETH_CRS_DV_MARK, MMC1_D7_MARK, ARM_TRACEDATA_5_MARK, TS_SDAT0_MARK,
0540     VI0_G4_MARK, ETH_TX_EN_MARK, SD2_DAT0_B_MARK, ARM_TRACEDATA_6_MARK,
0541     VI0_G5_MARK, ETH_RX_ER_MARK, SD2_DAT1_B_MARK, ARM_TRACEDATA_7_MARK,
0542     VI0_G6_MARK, ETH_RXD0_MARK, SD2_DAT2_B_MARK, ARM_TRACEDATA_8_MARK,
0543     VI0_G7_MARK, ETH_RXD1_MARK, SD2_DAT3_B_MARK, ARM_TRACEDATA_9_MARK,
0544
0545     VI0_R0_MARK, SSI_SDATA7_C_MARK, SCK1_C_MARK, DREQ1_B_MARK,
0546     ARM_TRACEDATA_10_MARK, DREQ0_C_MARK, VI0_R1_MARK, SSI_SDATA8_C_MARK,
0547     DACK1_B_MARK, ARM_TRACEDATA_11_MARK, DACK0_C_MARK, DRACK0_C_MARK,
0548     VI0_R2_MARK, ETH_LINK_MARK, SD2_CLK_B_MARK, IRQ2_MARK,
0549     ARM_TRACEDATA_12_MARK, VI0_R3_MARK, ETH_MAGIC_MARK, SD2_CMD_B_MARK,
0550     IRQ3_MARK, ARM_TRACEDATA_13_MARK, VI0_R4_MARK, ETH_REFCLK_MARK,
0551     SD2_CD_B_MARK, HSPI_CLK1_B_MARK, ARM_TRACEDATA_14_MARK, MT1_CLK_MARK,
0552     TS_SCK0_MARK, VI0_R5_MARK, ETH_TXD0_MARK, SD2_WP_B_MARK,
0553     HSPI_CS1_B_MARK, ARM_TRACEDATA_15_MARK, MT1_D_MARK, TS_SDEN0_MARK,
0554     VI0_R6_MARK, ETH_MDC_MARK, DREQ2_C_MARK, HSPI_TX1_B_MARK,
0555     TRACECLK_MARK, MT1_BEN_MARK, PWMFSW0_D_MARK, VI0_R7_MARK,
0556     ETH_MDIO_MARK, DACK2_C_MARK, HSPI_RX1_B_MARK, SCIF_CLK_D_MARK,
0557     TRACECTL_MARK, MT1_PEN_MARK, VI1_CLK_MARK, SIM_D_MARK, SDA3_MARK,
0558     VI1_HSYNC_MARK, VI3_CLK_MARK, SSI_SCK4_MARK, GPS_SIGN_C_MARK,
0559     PWMFSW0_E_MARK, VI1_VSYNC_MARK, AUDIO_CLKOUT_C_MARK, SSI_WS4_MARK,
0560     SIM_CLK_MARK, GPS_MAG_C_MARK, SPV_TRST_MARK, SCL3_MARK,
0561
0562     VI1_DATA0_VI1_B0_MARK, SD2_DAT0_MARK, SIM_RST_MARK, SPV_TCK_MARK,
0563     ADICLK_B_MARK, VI1_DATA1_VI1_B1_MARK, SD2_DAT1_MARK, MT0_CLK_MARK,
0564     SPV_TMS_MARK, ADICS_B_SAMP_B_MARK, VI1_DATA2_VI1_B2_MARK,
0565     SD2_DAT2_MARK, MT0_D_MARK, SPVTDI_MARK, ADIDATA_B_MARK,
0566     VI1_DATA3_VI1_B3_MARK, SD2_DAT3_MARK, MT0_BEN_MARK, SPV_TDO_MARK,
0567     ADICHS0_B_MARK, VI1_DATA4_VI1_B4_MARK, SD2_CLK_MARK, MT0_PEN_MARK,
0568     SPA_TRST_MARK, HSPI_CLK1_D_MARK, ADICHS1_B_MARK,
0569     VI1_DATA5_VI1_B5_MARK, SD2_CMD_MARK, MT0_SYNC_MARK, SPA_TCK_MARK,
0570     HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK,
0571     MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK,
0572     SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK,
0573     VI1_G0_MARK, VI3_DATA0_MARK, TS_SCK1_MARK,
0574     DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK,
0575     VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK,
0576     DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK,
0577
0578     VI1_G2_MARK, VI3_DATA2_MARK, SSI_WS1_MARK, TS_SPSYNC1_MARK,
0579     SCK2_MARK, HSCK0_B_MARK, VI1_G3_MARK, VI3_DATA3_MARK,
0580     SSI_SCK2_MARK, TS_SDAT1_MARK, SCL1_C_MARK, HTX0_B_MARK,
0581     VI1_G4_MARK, VI3_DATA4_MARK, SSI_WS2_MARK, SDA1_C_MARK,
0582     SIM_RST_B_MARK, HRX0_B_MARK, VI1_G5_MARK, VI3_DATA5_MARK,
0583     GPS_CLK_MARK, FSE_MARK, TX4_B_MARK, SIM_D_B_MARK,
0584     VI1_G6_MARK, VI3_DATA6_MARK, GPS_SIGN_MARK, FRB_MARK,
0585     RX4_B_MARK, SIM_CLK_B_MARK, VI1_G7_MARK, VI3_DATA7_MARK,
0586     GPS_MAG_MARK, FCE_MARK, SCK4_B_MARK,
0587     PINMUX_MARK_END,
0588 };
0589
0590 static const u16 pinmux_data[] = {
0591     PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
0592
0593     PINMUX_SINGLE(AVS1),
0594     PINMUX_SINGLE(AVS1),
0595     PINMUX_SINGLE(A17),
0596     PINMUX_SINGLE(A18),
0597     PINMUX_SINGLE(A19),
0598
0599     PINMUX_SINGLE(USB_PENC0),
0600     PINMUX_SINGLE(USB_PENC1),
0601
0602     PINMUX_IPSR_GPSR(IP0_2_0, USB_PENC2),
0603     PINMUX_IPSR_MSEL(IP0_2_0, SCK0, SEL_SCIF0_0),
0604     PINMUX_IPSR_GPSR(IP0_2_0, PWM1),
0605     PINMUX_IPSR_MSEL(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
0606     PINMUX_IPSR_MSEL(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
0607     PINMUX_IPSR_MSEL(IP0_2_0, TCLK0_C, SEL_TMU0_2),
0608     PINMUX_IPSR_GPSR(IP0_5_3, BS),
0609     PINMUX_IPSR_GPSR(IP0_5_3, SD1_DAT2),
0610     PINMUX_IPSR_GPSR(IP0_5_3, MMC0_D2),
0611     PINMUX_IPSR_GPSR(IP0_5_3, FD2),
0612     PINMUX_IPSR_GPSR(IP0_5_3, ATADIR0),
0613     PINMUX_IPSR_GPSR(IP0_5_3, SDSELF),
0614     PINMUX_IPSR_MSEL(IP0_5_3, HCTS1, SEL_HSCIF1_0),
0615     PINMUX_IPSR_GPSR(IP0_5_3, TX4_C),
0616     PINMUX_IPSR_GPSR(IP0_7_6, A0),
0617     PINMUX_IPSR_GPSR(IP0_7_6, SD1_DAT3),
0618     PINMUX_IPSR_GPSR(IP0_7_6, MMC0_D3),
0619     PINMUX_IPSR_GPSR(IP0_7_6, FD3),
0620     PINMUX_IPSR_GPSR(IP0_9_8, A20),
0621     PINMUX_IPSR_GPSR(IP0_9_8, TX5_D),
0622     PINMUX_IPSR_GPSR(IP0_9_8, HSPI_TX2_B),
0623     PINMUX_IPSR_GPSR(IP0_11_10, A21),
0624     PINMUX_IPSR_MSEL(IP0_11_10, SCK5_D, SEL_SCIF5_3),
0625     PINMUX_IPSR_MSEL(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
0626     PINMUX_IPSR_GPSR(IP0_13_12, A22),
0627     PINMUX_IPSR_MSEL(IP0_13_12, RX5_D, SEL_SCIF5_3),
0628     PINMUX_IPSR_MSEL(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
0629     PINMUX_IPSR_GPSR(IP0_13_12, VI1_R0),
0630     PINMUX_IPSR_GPSR(IP0_15_14, A23),
0631     PINMUX_IPSR_GPSR(IP0_15_14, FCLE),
0632     PINMUX_IPSR_MSEL(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
0633     PINMUX_IPSR_GPSR(IP0_15_14, VI1_R1),
0634     PINMUX_IPSR_GPSR(IP0_18_16, A24),
0635     PINMUX_IPSR_GPSR(IP0_18_16, SD1_CD),
0636     PINMUX_IPSR_GPSR(IP0_18_16, MMC0_D4),
0637     PINMUX_IPSR_GPSR(IP0_18_16, FD4),
0638     PINMUX_IPSR_MSEL(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
0639     PINMUX_IPSR_GPSR(IP0_18_16, VI1_R2),
0640     PINMUX_IPSR_MSEL(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
0641     PINMUX_IPSR_GPSR(IP0_22_19, A25),
0642     PINMUX_IPSR_GPSR(IP0_22_19, SD1_WP),
0643     PINMUX_IPSR_GPSR(IP0_22_19, MMC0_D5),
0644     PINMUX_IPSR_GPSR(IP0_22_19, FD5),
0645     PINMUX_IPSR_MSEL(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
0646     PINMUX_IPSR_GPSR(IP0_22_19, VI1_R3),
0647     PINMUX_IPSR_GPSR(IP0_22_19, TX5_B),
0648     PINMUX_IPSR_MSEL(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
0649     PINMUX_IPSR_MSEL(IP0_22_19, CTS0_B, SEL_SCIF0_1),
0650     PINMUX_IPSR_GPSR(IP0_24_23, CLKOUT),
0651     PINMUX_IPSR_GPSR(IP0_24_23, TX3C_IRDA_TX_C),
0652     PINMUX_IPSR_GPSR(IP0_24_23, PWM0_B),
0653     PINMUX_IPSR_GPSR(IP0_25, CS0),
0654     PINMUX_IPSR_MSEL(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
0655     PINMUX_IPSR_GPSR(IP0_27_26, CS1_A26),
0656     PINMUX_IPSR_GPSR(IP0_27_26, HSPI_TX2),
0657     PINMUX_IPSR_GPSR(IP0_27_26, SDSELF_B),
0658     PINMUX_IPSR_GPSR(IP0_30_28, RD_WR),
0659     PINMUX_IPSR_GPSR(IP0_30_28, FWE),
0660     PINMUX_IPSR_GPSR(IP0_30_28, ATAG0),
0661     PINMUX_IPSR_GPSR(IP0_30_28, VI1_R7),
0662     PINMUX_IPSR_MSEL(IP0_30_28, HRTS1, SEL_HSCIF1_0),
0663     PINMUX_IPSR_MSEL(IP0_30_28, RX4_C, SEL_SCIF4_2),
0664
0665     PINMUX_IPSR_GPSR(IP1_1_0, EX_CS0),
0666     PINMUX_IPSR_MSEL(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
0667     PINMUX_IPSR_GPSR(IP1_1_0, MMC0_D6),
0668     PINMUX_IPSR_GPSR(IP1_1_0, FD6),
0669     PINMUX_IPSR_GPSR(IP1_3_2, EX_CS1),
0670     PINMUX_IPSR_GPSR(IP1_3_2, MMC0_D7),
0671     PINMUX_IPSR_GPSR(IP1_3_2, FD7),
0672     PINMUX_IPSR_GPSR(IP1_6_4, EX_CS2),
0673     PINMUX_IPSR_GPSR(IP1_6_4, SD1_CLK),
0674     PINMUX_IPSR_GPSR(IP1_6_4, MMC0_CLK),
0675     PINMUX_IPSR_GPSR(IP1_6_4, FALE),
0676     PINMUX_IPSR_GPSR(IP1_6_4, ATACS00),
0677     PINMUX_IPSR_GPSR(IP1_10_7, EX_CS3),
0678     PINMUX_IPSR_GPSR(IP1_10_7, SD1_CMD),
0679     PINMUX_IPSR_GPSR(IP1_10_7, MMC0_CMD),
0680     PINMUX_IPSR_GPSR(IP1_10_7, FRE),
0681     PINMUX_IPSR_GPSR(IP1_10_7, ATACS10),
0682     PINMUX_IPSR_GPSR(IP1_10_7, VI1_R4),
0683     PINMUX_IPSR_MSEL(IP1_10_7, RX5_B, SEL_SCIF5_1),
0684     PINMUX_IPSR_MSEL(IP1_10_7, HSCK1, SEL_HSCIF1_0),
0685     PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
0686     PINMUX_IPSR_MSEL(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
0687     PINMUX_IPSR_MSEL(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
0688     PINMUX_IPSR_GPSR(IP1_14_11, EX_CS4),
0689     PINMUX_IPSR_GPSR(IP1_14_11, SD1_DAT0),
0690     PINMUX_IPSR_GPSR(IP1_14_11, MMC0_D0),
0691     PINMUX_IPSR_GPSR(IP1_14_11, FD0),
0692     PINMUX_IPSR_GPSR(IP1_14_11, ATARD0),
0693     PINMUX_IPSR_GPSR(IP1_14_11, VI1_R5),
0694     PINMUX_IPSR_MSEL(IP1_14_11, SCK5_B, SEL_SCIF5_1),
0695     PINMUX_IPSR_GPSR(IP1_14_11, HTX1),
0696     PINMUX_IPSR_GPSR(IP1_14_11, TX2_E),
0697     PINMUX_IPSR_GPSR(IP1_14_11, TX0_B),
0698     PINMUX_IPSR_MSEL(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
0699     PINMUX_IPSR_GPSR(IP1_18_15, EX_CS5),
0700     PINMUX_IPSR_GPSR(IP1_18_15, SD1_DAT1),
0701     PINMUX_IPSR_GPSR(IP1_18_15, MMC0_D1),
0702     PINMUX_IPSR_GPSR(IP1_18_15, FD1),
0703     PINMUX_IPSR_GPSR(IP1_18_15, ATAWR0),
0704     PINMUX_IPSR_GPSR(IP1_18_15, VI1_R6),
0705     PINMUX_IPSR_MSEL(IP1_18_15, HRX1, SEL_HSCIF1_0),
0706     PINMUX_IPSR_MSEL(IP1_18_15, RX2_E, SEL_SCIF2_4),
0707     PINMUX_IPSR_MSEL(IP1_18_15, RX0_B, SEL_SCIF0_1),
0708     PINMUX_IPSR_MSEL(IP1_18_15, SSI_WS9, SEL_SSI9_0),
0709     PINMUX_IPSR_GPSR(IP1_20_19, MLB_CLK),
0710     PINMUX_IPSR_GPSR(IP1_20_19, PWM2),
0711     PINMUX_IPSR_MSEL(IP1_20_19, SCK4, SEL_SCIF4_0),
0712     PINMUX_IPSR_GPSR(IP1_22_21, MLB_SIG),
0713     PINMUX_IPSR_GPSR(IP1_22_21, PWM3),
0714     PINMUX_IPSR_GPSR(IP1_22_21, TX4),
0715     PINMUX_IPSR_GPSR(IP1_24_23, MLB_DAT),
0716     PINMUX_IPSR_GPSR(IP1_24_23, PWM4),
0717     PINMUX_IPSR_MSEL(IP1_24_23, RX4, SEL_SCIF4_0),
0718     PINMUX_IPSR_GPSR(IP1_28_25, HTX0),
0719     PINMUX_IPSR_GPSR(IP1_28_25, TX1),
0720     PINMUX_IPSR_GPSR(IP1_28_25, SDATA),
0721     PINMUX_IPSR_MSEL(IP1_28_25, CTS0_C, SEL_SCIF0_2),
0722     PINMUX_IPSR_GPSR(IP1_28_25, SUB_TCK),
0723     PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE2),
0724     PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE10),
0725     PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE18),
0726     PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE26),
0727     PINMUX_IPSR_GPSR(IP1_28_25, CC5_STATE34),
0728
0729     PINMUX_IPSR_MSEL(IP2_3_0, HRX0, SEL_HSCIF0_0),
0730     PINMUX_IPSR_MSEL(IP2_3_0, RX1, SEL_SCIF1_0),
0731     PINMUX_IPSR_GPSR(IP2_3_0, SCKZ),
0732     PINMUX_IPSR_MSEL(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
0733     PINMUX_IPSR_GPSR(IP2_3_0, SUB_TDI),
0734     PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE3),
0735     PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE11),
0736     PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE19),
0737     PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE27),
0738     PINMUX_IPSR_GPSR(IP2_3_0, CC5_STATE35),
0739     PINMUX_IPSR_MSEL(IP2_7_4, HSCK0, SEL_HSCIF0_0),
0740     PINMUX_IPSR_MSEL(IP2_7_4, SCK1, SEL_SCIF1_0),
0741     PINMUX_IPSR_GPSR(IP2_7_4, MTS),
0742     PINMUX_IPSR_GPSR(IP2_7_4, PWM5),
0743     PINMUX_IPSR_MSEL(IP2_7_4, SCK0_C, SEL_SCIF0_2),
0744     PINMUX_IPSR_MSEL(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
0745     PINMUX_IPSR_GPSR(IP2_7_4, SUB_TDO),
0746     PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE0),
0747     PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE8),
0748     PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE16),
0749     PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE24),
0750     PINMUX_IPSR_GPSR(IP2_7_4, CC5_STATE32),
0751     PINMUX_IPSR_MSEL(IP2_11_8, HCTS0, SEL_HSCIF0_0),
0752     PINMUX_IPSR_MSEL(IP2_11_8, CTS1, SEL_SCIF1_0),
0753     PINMUX_IPSR_GPSR(IP2_11_8, STM),
0754     PINMUX_IPSR_GPSR(IP2_11_8, PWM0_D),
0755     PINMUX_IPSR_MSEL(IP2_11_8, RX0_C, SEL_SCIF0_2),
0756     PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
0757     PINMUX_IPSR_GPSR(IP2_11_8, SUB_TRST),
0758     PINMUX_IPSR_MSEL(IP2_11_8, TCLK1_B, SEL_TMU1_1),
0759     PINMUX_IPSR_GPSR(IP2_11_8, CC5_OSCOUT),
0760     PINMUX_IPSR_MSEL(IP2_15_12, HRTS0, SEL_HSCIF0_0),
0761     PINMUX_IPSR_MSEL(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
0762     PINMUX_IPSR_GPSR(IP2_15_12, MDATA),
0763     PINMUX_IPSR_GPSR(IP2_15_12, TX0_C),
0764     PINMUX_IPSR_GPSR(IP2_15_12, SUB_TMS),
0765     PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE1),
0766     PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE9),
0767     PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE17),
0768     PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE25),
0769     PINMUX_IPSR_GPSR(IP2_15_12, CC5_STATE33),
0770     PINMUX_IPSR_GPSR(IP2_18_16, DU0_DR0),
0771     PINMUX_IPSR_GPSR(IP2_18_16, LCDOUT0),
0772     PINMUX_IPSR_MSEL(IP2_18_16, DREQ0, SEL_EXBUS0_0),
0773     PINMUX_IPSR_MSEL(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
0774     PINMUX_IPSR_GPSR(IP2_18_16, AUDATA0),
0775     PINMUX_IPSR_GPSR(IP2_18_16, TX5_C),
0776     PINMUX_IPSR_GPSR(IP2_21_19, DU0_DR1),
0777     PINMUX_IPSR_GPSR(IP2_21_19, LCDOUT1),
0778     PINMUX_IPSR_GPSR(IP2_21_19, DACK0),
0779     PINMUX_IPSR_GPSR(IP2_21_19, DRACK0),
0780     PINMUX_IPSR_MSEL(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
0781     PINMUX_IPSR_GPSR(IP2_21_19, AUDATA1),
0782     PINMUX_IPSR_MSEL(IP2_21_19, RX5_C, SEL_SCIF5_2),
0783     PINMUX_IPSR_GPSR(IP2_22, DU0_DR2),
0784     PINMUX_IPSR_GPSR(IP2_22, LCDOUT2),
0785     PINMUX_IPSR_GPSR(IP2_23, DU0_DR3),
0786     PINMUX_IPSR_GPSR(IP2_23, LCDOUT3),
0787     PINMUX_IPSR_GPSR(IP2_24, DU0_DR4),
0788     PINMUX_IPSR_GPSR(IP2_24, LCDOUT4),
0789     PINMUX_IPSR_GPSR(IP2_25, DU0_DR5),
0790     PINMUX_IPSR_GPSR(IP2_25, LCDOUT5),
0791     PINMUX_IPSR_GPSR(IP2_26, DU0_DR6),
0792     PINMUX_IPSR_GPSR(IP2_26, LCDOUT6),
0793     PINMUX_IPSR_GPSR(IP2_27, DU0_DR7),
0794     PINMUX_IPSR_GPSR(IP2_27, LCDOUT7),
0795     PINMUX_IPSR_GPSR(IP2_30_28, DU0_DG0),
0796     PINMUX_IPSR_GPSR(IP2_30_28, LCDOUT8),
0797     PINMUX_IPSR_MSEL(IP2_30_28, DREQ1, SEL_EXBUS1_0),
0798     PINMUX_IPSR_MSEL(IP2_30_28, SCL2, SEL_I2C2_0),
0799     PINMUX_IPSR_GPSR(IP2_30_28, AUDATA2),
0800
0801     PINMUX_IPSR_GPSR(IP3_2_0, DU0_DG1),
0802     PINMUX_IPSR_GPSR(IP3_2_0, LCDOUT9),
0803     PINMUX_IPSR_GPSR(IP3_2_0, DACK1),
0804     PINMUX_IPSR_MSEL(IP3_2_0, SDA2, SEL_I2C2_0),
0805     PINMUX_IPSR_GPSR(IP3_2_0, AUDATA3),
0806     PINMUX_IPSR_GPSR(IP3_3, DU0_DG2),
0807     PINMUX_IPSR_GPSR(IP3_3, LCDOUT10),
0808     PINMUX_IPSR_GPSR(IP3_4, DU0_DG3),
0809     PINMUX_IPSR_GPSR(IP3_4, LCDOUT11),
0810     PINMUX_IPSR_GPSR(IP3_5, DU0_DG4),
0811     PINMUX_IPSR_GPSR(IP3_5, LCDOUT12),
0812     PINMUX_IPSR_GPSR(IP3_6, DU0_DG5),
0813     PINMUX_IPSR_GPSR(IP3_6, LCDOUT13),
0814     PINMUX_IPSR_GPSR(IP3_7, DU0_DG6),
0815     PINMUX_IPSR_GPSR(IP3_7, LCDOUT14),
0816     PINMUX_IPSR_GPSR(IP3_8, DU0_DG7),
0817     PINMUX_IPSR_GPSR(IP3_8, LCDOUT15),
0818     PINMUX_IPSR_GPSR(IP3_11_9, DU0_DB0),
0819     PINMUX_IPSR_GPSR(IP3_11_9, LCDOUT16),
0820     PINMUX_IPSR_GPSR(IP3_11_9, EX_WAIT1),
0821     PINMUX_IPSR_MSEL(IP3_11_9, SCL1, SEL_I2C1_0),
0822     PINMUX_IPSR_MSEL(IP3_11_9, TCLK1, SEL_TMU1_0),
0823     PINMUX_IPSR_GPSR(IP3_11_9, AUDATA4),
0824     PINMUX_IPSR_GPSR(IP3_14_12, DU0_DB1),
0825     PINMUX_IPSR_GPSR(IP3_14_12, LCDOUT17),
0826     PINMUX_IPSR_GPSR(IP3_14_12, EX_WAIT2),
0827     PINMUX_IPSR_MSEL(IP3_14_12, SDA1, SEL_I2C1_0),
0828     PINMUX_IPSR_MSEL(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
0829     PINMUX_IPSR_GPSR(IP3_14_12, AUDATA5),
0830     PINMUX_IPSR_MSEL(IP3_14_12, SCK5_C, SEL_SCIF5_2),
0831     PINMUX_IPSR_GPSR(IP3_15, DU0_DB2),
0832     PINMUX_IPSR_GPSR(IP3_15, LCDOUT18),
0833     PINMUX_IPSR_GPSR(IP3_16, DU0_DB3),
0834     PINMUX_IPSR_GPSR(IP3_16, LCDOUT19),
0835     PINMUX_IPSR_GPSR(IP3_17, DU0_DB4),
0836     PINMUX_IPSR_GPSR(IP3_17, LCDOUT20),
0837     PINMUX_IPSR_GPSR(IP3_18, DU0_DB5),
0838     PINMUX_IPSR_GPSR(IP3_18, LCDOUT21),
0839     PINMUX_IPSR_GPSR(IP3_19, DU0_DB6),
0840     PINMUX_IPSR_GPSR(IP3_19, LCDOUT22),
0841     PINMUX_IPSR_GPSR(IP3_20, DU0_DB7),
0842     PINMUX_IPSR_GPSR(IP3_20, LCDOUT23),
0843     PINMUX_IPSR_GPSR(IP3_22_21, DU0_DOTCLKIN),
0844     PINMUX_IPSR_GPSR(IP3_22_21, QSTVA_QVS),
0845     PINMUX_IPSR_GPSR(IP3_22_21, TX3_D_IRDA_TX_D),
0846     PINMUX_IPSR_MSEL(IP3_22_21, SCL3_B, SEL_I2C3_1),
0847     PINMUX_IPSR_GPSR(IP3_23, DU0_DOTCLKOUT0),
0848     PINMUX_IPSR_GPSR(IP3_23, QCLK),
0849     PINMUX_IPSR_GPSR(IP3_26_24, DU0_DOTCLKOUT1),
0850     PINMUX_IPSR_GPSR(IP3_26_24, QSTVB_QVE),
0851     PINMUX_IPSR_MSEL(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
0852     PINMUX_IPSR_MSEL(IP3_26_24, SDA3_B, SEL_I2C3_1),
0853     PINMUX_IPSR_MSEL(IP3_26_24, SDA2_C, SEL_I2C2_2),
0854     PINMUX_IPSR_GPSR(IP3_26_24, DACK0_B),
0855     PINMUX_IPSR_GPSR(IP3_26_24, DRACK0_B),
0856     PINMUX_IPSR_GPSR(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
0857     PINMUX_IPSR_GPSR(IP3_27, QSTH_QHS),
0858     PINMUX_IPSR_GPSR(IP3_28, DU0_EXVSYNC_DU0_VSYNC),
0859     PINMUX_IPSR_GPSR(IP3_28, QSTB_QHE),
0860     PINMUX_IPSR_GPSR(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE),
0861     PINMUX_IPSR_GPSR(IP3_31_29, QCPV_QDE),
0862     PINMUX_IPSR_GPSR(IP3_31_29, CAN1_TX),
0863     PINMUX_IPSR_GPSR(IP3_31_29, TX2_C),
0864     PINMUX_IPSR_MSEL(IP3_31_29, SCL2_C, SEL_I2C2_2),
0865     PINMUX_IPSR_GPSR(IP3_31_29, REMOCON),
0866
0867     PINMUX_IPSR_GPSR(IP4_1_0, DU0_DISP),
0868     PINMUX_IPSR_GPSR(IP4_1_0, QPOLA),
0869     PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
0870     PINMUX_IPSR_MSEL(IP4_1_0, SCK2_C, SEL_SCIF2_2),
0871     PINMUX_IPSR_GPSR(IP4_4_2, DU0_CDE),
0872     PINMUX_IPSR_GPSR(IP4_4_2, QPOLB),
0873     PINMUX_IPSR_GPSR(IP4_4_2, CAN1_RX),
0874     PINMUX_IPSR_MSEL(IP4_4_2, RX2_C, SEL_SCIF2_2),
0875     PINMUX_IPSR_MSEL(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
0876     PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
0877     PINMUX_IPSR_MSEL(IP4_4_2, SCK0_B, SEL_SCIF0_1),
0878     PINMUX_IPSR_GPSR(IP4_7_5, DU1_DR0),
0879     PINMUX_IPSR_GPSR(IP4_7_5, VI2_DATA0_VI2_B0),
0880     PINMUX_IPSR_GPSR(IP4_7_5, PWM6),
0881     PINMUX_IPSR_GPSR(IP4_7_5, SD3_CLK),
0882     PINMUX_IPSR_GPSR(IP4_7_5, TX3_E_IRDA_TX_E),
0883     PINMUX_IPSR_GPSR(IP4_7_5, AUDCK),
0884     PINMUX_IPSR_MSEL(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
0885     PINMUX_IPSR_GPSR(IP4_10_8, DU1_DR1),
0886     PINMUX_IPSR_GPSR(IP4_10_8, VI2_DATA1_VI2_B1),
0887     PINMUX_IPSR_GPSR(IP4_10_8, PWM0),
0888     PINMUX_IPSR_GPSR(IP4_10_8, SD3_CMD),
0889     PINMUX_IPSR_MSEL(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
0890     PINMUX_IPSR_GPSR(IP4_10_8, AUDSYNC),
0891     PINMUX_IPSR_MSEL(IP4_10_8, CTS0_D, SEL_SCIF0_3),
0892     PINMUX_IPSR_GPSR(IP4_11, DU1_DR2),
0893     PINMUX_IPSR_GPSR(IP4_11, VI2_G0),
0894     PINMUX_IPSR_GPSR(IP4_12, DU1_DR3),
0895     PINMUX_IPSR_GPSR(IP4_12, VI2_G1),
0896     PINMUX_IPSR_GPSR(IP4_13, DU1_DR4),
0897     PINMUX_IPSR_GPSR(IP4_13, VI2_G2),
0898     PINMUX_IPSR_GPSR(IP4_14, DU1_DR5),
0899     PINMUX_IPSR_GPSR(IP4_14, VI2_G3),
0900     PINMUX_IPSR_GPSR(IP4_15, DU1_DR6),
0901     PINMUX_IPSR_GPSR(IP4_15, VI2_G4),
0902     PINMUX_IPSR_GPSR(IP4_16, DU1_DR7),
0903     PINMUX_IPSR_GPSR(IP4_16, VI2_G5),
0904     PINMUX_IPSR_GPSR(IP4_19_17, DU1_DG0),
0905     PINMUX_IPSR_GPSR(IP4_19_17, VI2_DATA2_VI2_B2),
0906     PINMUX_IPSR_MSEL(IP4_19_17, SCL1_B, SEL_I2C1_1),
0907     PINMUX_IPSR_GPSR(IP4_19_17, SD3_DAT2),
0908     PINMUX_IPSR_MSEL(IP4_19_17, SCK3_E, SEL_SCIF3_4),
0909     PINMUX_IPSR_GPSR(IP4_19_17, AUDATA6),
0910     PINMUX_IPSR_GPSR(IP4_19_17, TX0_D),
0911     PINMUX_IPSR_GPSR(IP4_22_20, DU1_DG1),
0912     PINMUX_IPSR_GPSR(IP4_22_20, VI2_DATA3_VI2_B3),
0913     PINMUX_IPSR_MSEL(IP4_22_20, SDA1_B, SEL_I2C1_1),
0914     PINMUX_IPSR_GPSR(IP4_22_20, SD3_DAT3),
0915     PINMUX_IPSR_MSEL(IP4_22_20, SCK5, SEL_SCIF5_0),
0916     PINMUX_IPSR_GPSR(IP4_22_20, AUDATA7),
0917     PINMUX_IPSR_MSEL(IP4_22_20, RX0_D, SEL_SCIF0_3),
0918     PINMUX_IPSR_GPSR(IP4_23, DU1_DG2),
0919     PINMUX_IPSR_GPSR(IP4_23, VI2_G6),
0920     PINMUX_IPSR_GPSR(IP4_24, DU1_DG3),
0921     PINMUX_IPSR_GPSR(IP4_24, VI2_G7),
0922     PINMUX_IPSR_GPSR(IP4_25, DU1_DG4),
0923     PINMUX_IPSR_GPSR(IP4_25, VI2_R0),
0924     PINMUX_IPSR_GPSR(IP4_26, DU1_DG5),
0925     PINMUX_IPSR_GPSR(IP4_26, VI2_R1),
0926     PINMUX_IPSR_GPSR(IP4_27, DU1_DG6),
0927     PINMUX_IPSR_GPSR(IP4_27, VI2_R2),
0928     PINMUX_IPSR_GPSR(IP4_28, DU1_DG7),
0929     PINMUX_IPSR_GPSR(IP4_28, VI2_R3),
0930     PINMUX_IPSR_GPSR(IP4_31_29, DU1_DB0),
0931     PINMUX_IPSR_GPSR(IP4_31_29, VI2_DATA4_VI2_B4),
0932     PINMUX_IPSR_MSEL(IP4_31_29, SCL2_B, SEL_I2C2_1),
0933     PINMUX_IPSR_GPSR(IP4_31_29, SD3_DAT0),
0934     PINMUX_IPSR_GPSR(IP4_31_29, TX5),
0935     PINMUX_IPSR_MSEL(IP4_31_29, SCK0_D, SEL_SCIF0_3),
0936
0937     PINMUX_IPSR_GPSR(IP5_2_0, DU1_DB1),
0938     PINMUX_IPSR_GPSR(IP5_2_0, VI2_DATA5_VI2_B5),
0939     PINMUX_IPSR_MSEL(IP5_2_0, SDA2_B, SEL_I2C2_1),
0940     PINMUX_IPSR_GPSR(IP5_2_0, SD3_DAT1),
0941     PINMUX_IPSR_MSEL(IP5_2_0, RX5, SEL_SCIF5_0),
0942     PINMUX_IPSR_MSEL(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
0943     PINMUX_IPSR_GPSR(IP5_3, DU1_DB2),
0944     PINMUX_IPSR_GPSR(IP5_3, VI2_R4),
0945     PINMUX_IPSR_GPSR(IP5_4, DU1_DB3),
0946     PINMUX_IPSR_GPSR(IP5_4, VI2_R5),
0947     PINMUX_IPSR_GPSR(IP5_5, DU1_DB4),
0948     PINMUX_IPSR_GPSR(IP5_5, VI2_R6),
0949     PINMUX_IPSR_GPSR(IP5_6, DU1_DB5),
0950     PINMUX_IPSR_GPSR(IP5_6, VI2_R7),
0951     PINMUX_IPSR_GPSR(IP5_7, DU1_DB6),
0952     PINMUX_IPSR_MSEL(IP5_7, SCL2_D, SEL_I2C2_3),
0953     PINMUX_IPSR_GPSR(IP5_8, DU1_DB7),
0954     PINMUX_IPSR_MSEL(IP5_8, SDA2_D, SEL_I2C2_3),
0955     PINMUX_IPSR_GPSR(IP5_10_9, DU1_DOTCLKIN),
0956     PINMUX_IPSR_GPSR(IP5_10_9, VI2_CLKENB),
0957     PINMUX_IPSR_MSEL(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
0958     PINMUX_IPSR_MSEL(IP5_10_9, SCL1_D, SEL_I2C1_3),
0959     PINMUX_IPSR_GPSR(IP5_12_11, DU1_DOTCLKOUT),
0960     PINMUX_IPSR_GPSR(IP5_12_11, VI2_FIELD),
0961     PINMUX_IPSR_MSEL(IP5_12_11, SDA1_D, SEL_I2C1_3),
0962     PINMUX_IPSR_GPSR(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
0963     PINMUX_IPSR_GPSR(IP5_14_13, VI2_HSYNC),
0964     PINMUX_IPSR_GPSR(IP5_14_13, VI3_HSYNC),
0965     PINMUX_IPSR_GPSR(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC),
0966     PINMUX_IPSR_GPSR(IP5_16_15, VI2_VSYNC),
0967     PINMUX_IPSR_GPSR(IP5_16_15, VI3_VSYNC),
0968     PINMUX_IPSR_GPSR(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE),
0969     PINMUX_IPSR_GPSR(IP5_20_17, VI2_CLK),
0970     PINMUX_IPSR_GPSR(IP5_20_17, TX3_B_IRDA_TX_B),
0971     PINMUX_IPSR_GPSR(IP5_20_17, SD3_CD),
0972     PINMUX_IPSR_GPSR(IP5_20_17, HSPI_TX1),
0973     PINMUX_IPSR_GPSR(IP5_20_17, VI1_CLKENB),
0974     PINMUX_IPSR_GPSR(IP5_20_17, VI3_CLKENB),
0975     PINMUX_IPSR_GPSR(IP5_20_17, AUDIO_CLKC),
0976     PINMUX_IPSR_GPSR(IP5_20_17, TX2_D),
0977     PINMUX_IPSR_GPSR(IP5_20_17, SPEEDIN),
0978     PINMUX_IPSR_MSEL(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
0979     PINMUX_IPSR_GPSR(IP5_23_21, DU1_DISP),
0980     PINMUX_IPSR_GPSR(IP5_23_21, VI2_DATA6_VI2_B6),
0981     PINMUX_IPSR_MSEL(IP5_23_21, TCLK0, SEL_TMU0_0),
0982     PINMUX_IPSR_GPSR(IP5_23_21, QSTVA_B_QVS_B),
0983     PINMUX_IPSR_MSEL(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
0984     PINMUX_IPSR_MSEL(IP5_23_21, SCK2_D, SEL_SCIF2_3),
0985     PINMUX_IPSR_GPSR(IP5_23_21, AUDIO_CLKOUT_B),
0986     PINMUX_IPSR_MSEL(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
0987     PINMUX_IPSR_GPSR(IP5_27_24, DU1_CDE),
0988     PINMUX_IPSR_GPSR(IP5_27_24, VI2_DATA7_VI2_B7),
0989     PINMUX_IPSR_MSEL(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
0990     PINMUX_IPSR_GPSR(IP5_27_24, SD3_WP),
0991     PINMUX_IPSR_MSEL(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
0992     PINMUX_IPSR_GPSR(IP5_27_24, VI1_FIELD),
0993     PINMUX_IPSR_GPSR(IP5_27_24, VI3_FIELD),
0994     PINMUX_IPSR_GPSR(IP5_27_24, AUDIO_CLKOUT),
0995     PINMUX_IPSR_MSEL(IP5_27_24, RX2_D, SEL_SCIF2_3),
0996     PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
0997     PINMUX_IPSR_MSEL(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
0998     PINMUX_IPSR_GPSR(IP5_28, AUDIO_CLKA),
0999     PINMUX_IPSR_GPSR(IP5_28, CAN_TXCLK),
1000     PINMUX_IPSR_GPSR(IP5_30_29, AUDIO_CLKB),
1001     PINMUX_IPSR_GPSR(IP5_30_29, USB_OVC2),
1002     PINMUX_IPSR_GPSR(IP5_30_29, CAN_DEBUGOUT0),
1003     PINMUX_IPSR_GPSR(IP5_30_29, MOUT0),
1004
1005     PINMUX_IPSR_GPSR(IP6_1_0, SSI_SCK0129),
1006     PINMUX_IPSR_GPSR(IP6_1_0, CAN_DEBUGOUT1),
1007     PINMUX_IPSR_GPSR(IP6_1_0, MOUT1),
1008     PINMUX_IPSR_GPSR(IP6_3_2, SSI_WS0129),
1009     PINMUX_IPSR_GPSR(IP6_3_2, CAN_DEBUGOUT2),
1010     PINMUX_IPSR_GPSR(IP6_3_2, MOUT2),
1011     PINMUX_IPSR_GPSR(IP6_5_4, SSI_SDATA0),
1012     PINMUX_IPSR_GPSR(IP6_5_4, CAN_DEBUGOUT3),
1013     PINMUX_IPSR_GPSR(IP6_5_4, MOUT5),
1014     PINMUX_IPSR_GPSR(IP6_7_6, SSI_SDATA1),
1015     PINMUX_IPSR_GPSR(IP6_7_6, CAN_DEBUGOUT4),
1016     PINMUX_IPSR_GPSR(IP6_7_6, MOUT6),
1017     PINMUX_IPSR_GPSR(IP6_8, SSI_SDATA2),
1018     PINMUX_IPSR_GPSR(IP6_8, CAN_DEBUGOUT5),
1019     PINMUX_IPSR_GPSR(IP6_11_9, SSI_SCK34),
1020     PINMUX_IPSR_GPSR(IP6_11_9, CAN_DEBUGOUT6),
1021     PINMUX_IPSR_GPSR(IP6_11_9, CAN0_TX_B),
1022     PINMUX_IPSR_MSEL(IP6_11_9, IERX, SEL_IE_0),
1023     PINMUX_IPSR_MSEL(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
1024     PINMUX_IPSR_GPSR(IP6_14_12, SSI_WS34),
1025     PINMUX_IPSR_GPSR(IP6_14_12, CAN_DEBUGOUT7),
1026     PINMUX_IPSR_MSEL(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
1027     PINMUX_IPSR_GPSR(IP6_14_12, IETX),
1028     PINMUX_IPSR_MSEL(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
1029     PINMUX_IPSR_GPSR(IP6_17_15, SSI_SDATA3),
1030     PINMUX_IPSR_GPSR(IP6_17_15, PWM0_C),
1031     PINMUX_IPSR_GPSR(IP6_17_15, CAN_DEBUGOUT8),
1032     PINMUX_IPSR_MSEL(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
1033     PINMUX_IPSR_MSEL(IP6_17_15, IECLK, SEL_IE_0),
1034     PINMUX_IPSR_MSEL(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
1035     PINMUX_IPSR_MSEL(IP6_17_15, TCLK0_B, SEL_TMU0_1),
1036     PINMUX_IPSR_GPSR(IP6_19_18, SSI_SDATA4),
1037     PINMUX_IPSR_GPSR(IP6_19_18, CAN_DEBUGOUT9),
1038     PINMUX_IPSR_MSEL(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
1039     PINMUX_IPSR_GPSR(IP6_22_20, SSI_SCK5),
1040     PINMUX_IPSR_GPSR(IP6_22_20, ADICLK),
1041     PINMUX_IPSR_GPSR(IP6_22_20, CAN_DEBUGOUT10),
1042     PINMUX_IPSR_MSEL(IP6_22_20, SCK3, SEL_SCIF3_0),
1043     PINMUX_IPSR_MSEL(IP6_22_20, TCLK0_D, SEL_TMU0_3),
1044     PINMUX_IPSR_GPSR(IP6_24_23, SSI_WS5),
1045     PINMUX_IPSR_MSEL(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
1046     PINMUX_IPSR_GPSR(IP6_24_23, CAN_DEBUGOUT11),
1047     PINMUX_IPSR_GPSR(IP6_24_23, TX3_IRDA_TX),
1048     PINMUX_IPSR_GPSR(IP6_26_25, SSI_SDATA5),
1049     PINMUX_IPSR_MSEL(IP6_26_25, ADIDATA, SEL_ADI_0),
1050     PINMUX_IPSR_GPSR(IP6_26_25, CAN_DEBUGOUT12),
1051     PINMUX_IPSR_MSEL(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
1052     PINMUX_IPSR_GPSR(IP6_30_29, SSI_SCK6),
1053     PINMUX_IPSR_GPSR(IP6_30_29, ADICHS0),
1054     PINMUX_IPSR_GPSR(IP6_30_29, CAN0_TX),
1055     PINMUX_IPSR_MSEL(IP6_30_29, IERX_B, SEL_IE_1),
1056
1057     PINMUX_IPSR_GPSR(IP7_1_0, SSI_WS6),
1058     PINMUX_IPSR_GPSR(IP7_1_0, ADICHS1),
1059     PINMUX_IPSR_MSEL(IP7_1_0, CAN0_RX, SEL_CAN0_0),
1060     PINMUX_IPSR_GPSR(IP7_1_0, IETX_B),
1061     PINMUX_IPSR_GPSR(IP7_3_2, SSI_SDATA6),
1062     PINMUX_IPSR_GPSR(IP7_3_2, ADICHS2),
1063     PINMUX_IPSR_MSEL(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
1064     PINMUX_IPSR_MSEL(IP7_3_2, IECLK_B, SEL_IE_1),
1065     PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
1066     PINMUX_IPSR_GPSR(IP7_6_4, CAN_DEBUGOUT13),
1067     PINMUX_IPSR_MSEL(IP7_6_4, IRQ0_B, SEL_INT0_1),
1068     PINMUX_IPSR_MSEL(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
1069     PINMUX_IPSR_MSEL(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
1070     PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS78, SEL_SSI7_0),
1071     PINMUX_IPSR_GPSR(IP7_9_7, CAN_DEBUGOUT14),
1072     PINMUX_IPSR_MSEL(IP7_9_7, IRQ1_B, SEL_INT1_1),
1073     PINMUX_IPSR_MSEL(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
1074     PINMUX_IPSR_MSEL(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
1075     PINMUX_IPSR_MSEL(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
1076     PINMUX_IPSR_GPSR(IP7_12_10, CAN_DEBUGOUT15),
1077     PINMUX_IPSR_MSEL(IP7_12_10, IRQ2_B, SEL_INT2_1),
1078     PINMUX_IPSR_MSEL(IP7_12_10, TCLK1_C, SEL_TMU1_2),
1079     PINMUX_IPSR_GPSR(IP7_12_10, HSPI_TX1_C),
1080     PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
1081     PINMUX_IPSR_GPSR(IP7_14_13, VSP),
1082     PINMUX_IPSR_MSEL(IP7_14_13, IRQ3_B, SEL_INT3_1),
1083     PINMUX_IPSR_MSEL(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
1084     PINMUX_IPSR_GPSR(IP7_16_15, SD0_CLK),
1085     PINMUX_IPSR_GPSR(IP7_16_15, ATACS01),
1086     PINMUX_IPSR_MSEL(IP7_16_15, SCK1_B, SEL_SCIF1_1),
1087     PINMUX_IPSR_GPSR(IP7_18_17, SD0_CMD),
1088     PINMUX_IPSR_GPSR(IP7_18_17, ATACS11),
1089     PINMUX_IPSR_GPSR(IP7_18_17, TX1_B),
1090     PINMUX_IPSR_GPSR(IP7_18_17, CC5_TDO),
1091     PINMUX_IPSR_GPSR(IP7_20_19, SD0_DAT0),
1092     PINMUX_IPSR_GPSR(IP7_20_19, ATADIR1),
1093     PINMUX_IPSR_MSEL(IP7_20_19, RX1_B, SEL_SCIF1_1),
1094     PINMUX_IPSR_GPSR(IP7_20_19, CC5_TRST),
1095     PINMUX_IPSR_GPSR(IP7_22_21, SD0_DAT1),
1096     PINMUX_IPSR_GPSR(IP7_22_21, ATAG1),
1097     PINMUX_IPSR_MSEL(IP7_22_21, SCK2_B, SEL_SCIF2_1),
1098     PINMUX_IPSR_GPSR(IP7_22_21, CC5_TMS),
1099     PINMUX_IPSR_GPSR(IP7_24_23, SD0_DAT2),
1100     PINMUX_IPSR_GPSR(IP7_24_23, ATARD1),
1101     PINMUX_IPSR_GPSR(IP7_24_23, TX2_B),
1102     PINMUX_IPSR_GPSR(IP7_24_23, CC5_TCK),
1103     PINMUX_IPSR_GPSR(IP7_26_25, SD0_DAT3),
1104     PINMUX_IPSR_GPSR(IP7_26_25, ATAWR1),
1105     PINMUX_IPSR_MSEL(IP7_26_25, RX2_B, SEL_SCIF2_1),
1106     PINMUX_IPSR_GPSR(IP7_26_25, CC5_TDI),
1107     PINMUX_IPSR_GPSR(IP7_28_27, SD0_CD),
1108     PINMUX_IPSR_MSEL(IP7_28_27, DREQ2, SEL_EXBUS2_0),
1109     PINMUX_IPSR_MSEL(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
1110     PINMUX_IPSR_GPSR(IP7_30_29, SD0_WP),
1111     PINMUX_IPSR_GPSR(IP7_30_29, DACK2),
1112     PINMUX_IPSR_MSEL(IP7_30_29, CTS1_B, SEL_SCIF1_1),
1113
1114     PINMUX_IPSR_GPSR(IP8_3_0, HSPI_CLK0),
1115     PINMUX_IPSR_MSEL(IP8_3_0, CTS0, SEL_SCIF0_0),
1116     PINMUX_IPSR_GPSR(IP8_3_0, USB_OVC0),
1117     PINMUX_IPSR_GPSR(IP8_3_0, AD_CLK),
1118     PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE4),
1119     PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE12),
1120     PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE20),
1121     PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE28),
1122     PINMUX_IPSR_GPSR(IP8_3_0, CC5_STATE36),
1123     PINMUX_IPSR_GPSR(IP8_7_4, HSPI_CS0),
1124     PINMUX_IPSR_MSEL(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
1125     PINMUX_IPSR_GPSR(IP8_7_4, USB_OVC1),
1126     PINMUX_IPSR_GPSR(IP8_7_4, AD_DI),
1127     PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE5),
1128     PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE13),
1129     PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE21),
1130     PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE29),
1131     PINMUX_IPSR_GPSR(IP8_7_4, CC5_STATE37),
1132     PINMUX_IPSR_GPSR(IP8_11_8, HSPI_TX0),
1133     PINMUX_IPSR_GPSR(IP8_11_8, TX0),
1134     PINMUX_IPSR_GPSR(IP8_11_8, CAN_DEBUG_HW_TRIGGER),
1135     PINMUX_IPSR_GPSR(IP8_11_8, AD_DO),
1136     PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE6),
1137     PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE14),
1138     PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE22),
1139     PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE30),
1140     PINMUX_IPSR_GPSR(IP8_11_8, CC5_STATE38),
1141     PINMUX_IPSR_GPSR(IP8_15_12, HSPI_RX0),
1142     PINMUX_IPSR_MSEL(IP8_15_12, RX0, SEL_SCIF0_0),
1143     PINMUX_IPSR_GPSR(IP8_15_12, CAN_STEP0),
1144     PINMUX_IPSR_GPSR(IP8_15_12, AD_NCS),
1145     PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE7),
1146     PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE15),
1147     PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE23),
1148     PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE31),
1149     PINMUX_IPSR_GPSR(IP8_15_12, CC5_STATE39),
1150     PINMUX_IPSR_GPSR(IP8_17_16, FMCLK),
1151     PINMUX_IPSR_GPSR(IP8_17_16, RDS_CLK),
1152     PINMUX_IPSR_GPSR(IP8_17_16, PCMOE),
1153     PINMUX_IPSR_GPSR(IP8_18, BPFCLK),
1154     PINMUX_IPSR_GPSR(IP8_18, PCMWE),
1155     PINMUX_IPSR_GPSR(IP8_19, FMIN),
1156     PINMUX_IPSR_GPSR(IP8_19, RDS_DATA),
1157     PINMUX_IPSR_GPSR(IP8_20, VI0_CLK),
1158     PINMUX_IPSR_GPSR(IP8_20, MMC1_CLK),
1159     PINMUX_IPSR_GPSR(IP8_22_21, VI0_CLKENB),
1160     PINMUX_IPSR_GPSR(IP8_22_21, TX1_C),
1161     PINMUX_IPSR_GPSR(IP8_22_21, HTX1_B),
1162     PINMUX_IPSR_GPSR(IP8_22_21, MT1_SYNC),
1163     PINMUX_IPSR_GPSR(IP8_24_23, VI0_FIELD),
1164     PINMUX_IPSR_MSEL(IP8_24_23, RX1_C, SEL_SCIF1_2),
1165     PINMUX_IPSR_MSEL(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
1166     PINMUX_IPSR_GPSR(IP8_27_25, VI0_HSYNC),
1167     PINMUX_IPSR_MSEL(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
1168     PINMUX_IPSR_MSEL(IP8_27_25, CTS1_C, SEL_SCIF1_2),
1169     PINMUX_IPSR_GPSR(IP8_27_25, TX4_D),
1170     PINMUX_IPSR_GPSR(IP8_27_25, MMC1_CMD),
1171     PINMUX_IPSR_MSEL(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
1172     PINMUX_IPSR_GPSR(IP8_30_28, VI0_VSYNC),
1173     PINMUX_IPSR_MSEL(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
1174     PINMUX_IPSR_MSEL(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
1175     PINMUX_IPSR_MSEL(IP8_30_28, RX4_D, SEL_SCIF4_3),
1176     PINMUX_IPSR_MSEL(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2),
1177
1178     PINMUX_IPSR_MSEL(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
1179     PINMUX_IPSR_MSEL(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
1180     PINMUX_IPSR_GPSR(IP9_1_0, MT1_VCXO),
1181     PINMUX_IPSR_MSEL(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
1182     PINMUX_IPSR_MSEL(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
1183     PINMUX_IPSR_GPSR(IP9_3_2, MT1_PWM),
1184     PINMUX_IPSR_GPSR(IP9_4, VI0_DATA2_VI0_B2),
1185     PINMUX_IPSR_GPSR(IP9_4, MMC1_D0),
1186     PINMUX_IPSR_GPSR(IP9_5, VI0_DATA3_VI0_B3),
1187     PINMUX_IPSR_GPSR(IP9_5, MMC1_D1),
1188     PINMUX_IPSR_GPSR(IP9_6, VI0_DATA4_VI0_B4),
1189     PINMUX_IPSR_GPSR(IP9_6, MMC1_D2),
1190     PINMUX_IPSR_GPSR(IP9_7, VI0_DATA5_VI0_B5),
1191     PINMUX_IPSR_GPSR(IP9_7, MMC1_D3),
1192     PINMUX_IPSR_GPSR(IP9_9_8, VI0_DATA6_VI0_B6),
1193     PINMUX_IPSR_GPSR(IP9_9_8, MMC1_D4),
1194     PINMUX_IPSR_GPSR(IP9_9_8, ARM_TRACEDATA_0),
1195     PINMUX_IPSR_GPSR(IP9_11_10, VI0_DATA7_VI0_B7),
1196     PINMUX_IPSR_GPSR(IP9_11_10, MMC1_D5),
1197     PINMUX_IPSR_GPSR(IP9_11_10, ARM_TRACEDATA_1),
1198     PINMUX_IPSR_GPSR(IP9_13_12, VI0_G0),
1199     PINMUX_IPSR_MSEL(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
1200     PINMUX_IPSR_MSEL(IP9_13_12, IRQ0, SEL_INT0_0),
1201     PINMUX_IPSR_GPSR(IP9_13_12, ARM_TRACEDATA_2),
1202     PINMUX_IPSR_GPSR(IP9_15_14, VI0_G1),
1203     PINMUX_IPSR_MSEL(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
1204     PINMUX_IPSR_MSEL(IP9_15_14, IRQ1, SEL_INT1_0),
1205     PINMUX_IPSR_GPSR(IP9_15_14, ARM_TRACEDATA_3),
1206     PINMUX_IPSR_GPSR(IP9_18_16, VI0_G2),
1207     PINMUX_IPSR_GPSR(IP9_18_16, ETH_TXD1),
1208     PINMUX_IPSR_GPSR(IP9_18_16, MMC1_D6),
1209     PINMUX_IPSR_GPSR(IP9_18_16, ARM_TRACEDATA_4),
1210     PINMUX_IPSR_GPSR(IP9_18_16, TS_SPSYNC0),
1211     PINMUX_IPSR_GPSR(IP9_21_19, VI0_G3),
1212     PINMUX_IPSR_GPSR(IP9_21_19, ETH_CRS_DV),
1213     PINMUX_IPSR_GPSR(IP9_21_19, MMC1_D7),
1214     PINMUX_IPSR_GPSR(IP9_21_19, ARM_TRACEDATA_5),
1215     PINMUX_IPSR_GPSR(IP9_21_19, TS_SDAT0),
1216     PINMUX_IPSR_GPSR(IP9_23_22, VI0_G4),
1217     PINMUX_IPSR_GPSR(IP9_23_22, ETH_TX_EN),
1218     PINMUX_IPSR_MSEL(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
1219     PINMUX_IPSR_GPSR(IP9_23_22, ARM_TRACEDATA_6),
1220     PINMUX_IPSR_GPSR(IP9_25_24, VI0_G5),
1221     PINMUX_IPSR_GPSR(IP9_25_24, ETH_RX_ER),
1222     PINMUX_IPSR_MSEL(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
1223     PINMUX_IPSR_GPSR(IP9_25_24, ARM_TRACEDATA_7),
1224     PINMUX_IPSR_GPSR(IP9_27_26, VI0_G6),
1225     PINMUX_IPSR_GPSR(IP9_27_26, ETH_RXD0),
1226     PINMUX_IPSR_MSEL(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
1227     PINMUX_IPSR_GPSR(IP9_27_26, ARM_TRACEDATA_8),
1228     PINMUX_IPSR_GPSR(IP9_29_28, VI0_G7),
1229     PINMUX_IPSR_GPSR(IP9_29_28, ETH_RXD1),
1230     PINMUX_IPSR_MSEL(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
1231     PINMUX_IPSR_GPSR(IP9_29_28, ARM_TRACEDATA_9),
1232
1233     PINMUX_IPSR_GPSR(IP10_2_0, VI0_R0),
1234     PINMUX_IPSR_MSEL(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
1235     PINMUX_IPSR_MSEL(IP10_2_0, SCK1_C, SEL_SCIF1_2),
1236     PINMUX_IPSR_MSEL(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
1237     PINMUX_IPSR_GPSR(IP10_2_0, ARM_TRACEDATA_10),
1238     PINMUX_IPSR_MSEL(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
1239     PINMUX_IPSR_GPSR(IP10_5_3, VI0_R1),
1240     PINMUX_IPSR_MSEL(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
1241     PINMUX_IPSR_GPSR(IP10_5_3, DACK1_B),
1242     PINMUX_IPSR_GPSR(IP10_5_3, ARM_TRACEDATA_11),
1243     PINMUX_IPSR_GPSR(IP10_5_3, DACK0_C),
1244     PINMUX_IPSR_GPSR(IP10_5_3, DRACK0_C),
1245     PINMUX_IPSR_GPSR(IP10_8_6, VI0_R2),
1246     PINMUX_IPSR_GPSR(IP10_8_6, ETH_LINK),
1247     PINMUX_IPSR_GPSR(IP10_8_6, SD2_CLK_B),
1248     PINMUX_IPSR_MSEL(IP10_8_6, IRQ2, SEL_INT2_0),
1249     PINMUX_IPSR_GPSR(IP10_8_6, ARM_TRACEDATA_12),
1250     PINMUX_IPSR_GPSR(IP10_11_9, VI0_R3),
1251     PINMUX_IPSR_GPSR(IP10_11_9, ETH_MAGIC),
1252     PINMUX_IPSR_MSEL(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
1253     PINMUX_IPSR_MSEL(IP10_11_9, IRQ3, SEL_INT3_0),
1254     PINMUX_IPSR_GPSR(IP10_11_9, ARM_TRACEDATA_13),
1255     PINMUX_IPSR_GPSR(IP10_14_12, VI0_R4),
1256     PINMUX_IPSR_GPSR(IP10_14_12, ETH_REFCLK),
1257     PINMUX_IPSR_MSEL(IP10_14_12, SD2_CD_B, SEL_SD2_1),
1258     PINMUX_IPSR_MSEL(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
1259     PINMUX_IPSR_GPSR(IP10_14_12, ARM_TRACEDATA_14),
1260     PINMUX_IPSR_GPSR(IP10_14_12, MT1_CLK),
1261     PINMUX_IPSR_GPSR(IP10_14_12, TS_SCK0),
1262     PINMUX_IPSR_GPSR(IP10_17_15, VI0_R5),
1263     PINMUX_IPSR_GPSR(IP10_17_15, ETH_TXD0),
1264     PINMUX_IPSR_MSEL(IP10_17_15, SD2_WP_B, SEL_SD2_1),
1265     PINMUX_IPSR_MSEL(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
1266     PINMUX_IPSR_GPSR(IP10_17_15, ARM_TRACEDATA_15),
1267     PINMUX_IPSR_GPSR(IP10_17_15, MT1_D),
1268     PINMUX_IPSR_GPSR(IP10_17_15, TS_SDEN0),
1269     PINMUX_IPSR_GPSR(IP10_20_18, VI0_R6),
1270     PINMUX_IPSR_GPSR(IP10_20_18, ETH_MDC),
1271     PINMUX_IPSR_MSEL(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
1272     PINMUX_IPSR_GPSR(IP10_20_18, HSPI_TX1_B),
1273     PINMUX_IPSR_GPSR(IP10_20_18, TRACECLK),
1274     PINMUX_IPSR_GPSR(IP10_20_18, MT1_BEN),
1275     PINMUX_IPSR_MSEL(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
1276     PINMUX_IPSR_GPSR(IP10_23_21, VI0_R7),
1277     PINMUX_IPSR_GPSR(IP10_23_21, ETH_MDIO),
1278     PINMUX_IPSR_GPSR(IP10_23_21, DACK2_C),
1279     PINMUX_IPSR_MSEL(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
1280     PINMUX_IPSR_MSEL(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
1281     PINMUX_IPSR_GPSR(IP10_23_21, TRACECTL),
1282     PINMUX_IPSR_GPSR(IP10_23_21, MT1_PEN),
1283     PINMUX_IPSR_GPSR(IP10_25_24, VI1_CLK),
1284     PINMUX_IPSR_MSEL(IP10_25_24, SIM_D, SEL_SIM_0),
1285     PINMUX_IPSR_MSEL(IP10_25_24, SDA3, SEL_I2C3_0),
1286     PINMUX_IPSR_GPSR(IP10_28_26, VI1_HSYNC),
1287     PINMUX_IPSR_GPSR(IP10_28_26, VI3_CLK),
1288     PINMUX_IPSR_GPSR(IP10_28_26, SSI_SCK4),
1289     PINMUX_IPSR_MSEL(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
1290     PINMUX_IPSR_MSEL(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
1291     PINMUX_IPSR_GPSR(IP10_31_29, VI1_VSYNC),
1292     PINMUX_IPSR_GPSR(IP10_31_29, AUDIO_CLKOUT_C),
1293     PINMUX_IPSR_GPSR(IP10_31_29, SSI_WS4),
1294     PINMUX_IPSR_GPSR(IP10_31_29, SIM_CLK),
1295     PINMUX_IPSR_MSEL(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
1296     PINMUX_IPSR_GPSR(IP10_31_29, SPV_TRST),
1297     PINMUX_IPSR_MSEL(IP10_31_29, SCL3, SEL_I2C3_0),
1298
1299     PINMUX_IPSR_GPSR(IP11_2_0, VI1_DATA0_VI1_B0),
1300     PINMUX_IPSR_MSEL(IP11_2_0, SD2_DAT0, SEL_SD2_0),
1301     PINMUX_IPSR_GPSR(IP11_2_0, SIM_RST),
1302     PINMUX_IPSR_GPSR(IP11_2_0, SPV_TCK),
1303     PINMUX_IPSR_GPSR(IP11_2_0, ADICLK_B),
1304     PINMUX_IPSR_GPSR(IP11_5_3, VI1_DATA1_VI1_B1),
1305     PINMUX_IPSR_MSEL(IP11_5_3, SD2_DAT1, SEL_SD2_0),
1306     PINMUX_IPSR_GPSR(IP11_5_3, MT0_CLK),
1307     PINMUX_IPSR_GPSR(IP11_5_3, SPV_TMS),
1308     PINMUX_IPSR_MSEL(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
1309     PINMUX_IPSR_GPSR(IP11_8_6, VI1_DATA2_VI1_B2),
1310     PINMUX_IPSR_MSEL(IP11_8_6, SD2_DAT2, SEL_SD2_0),
1311     PINMUX_IPSR_GPSR(IP11_8_6, MT0_D),
1312     PINMUX_IPSR_GPSR(IP11_8_6, SPVTDI),
1313     PINMUX_IPSR_MSEL(IP11_8_6, ADIDATA_B, SEL_ADI_1),
1314     PINMUX_IPSR_GPSR(IP11_11_9, VI1_DATA3_VI1_B3),
1315     PINMUX_IPSR_MSEL(IP11_11_9, SD2_DAT3, SEL_SD2_0),
1316     PINMUX_IPSR_GPSR(IP11_11_9, MT0_BEN),
1317     PINMUX_IPSR_GPSR(IP11_11_9, SPV_TDO),
1318     PINMUX_IPSR_GPSR(IP11_11_9, ADICHS0_B),
1319     PINMUX_IPSR_GPSR(IP11_14_12, VI1_DATA4_VI1_B4),
1320     PINMUX_IPSR_GPSR(IP11_14_12, SD2_CLK),
1321     PINMUX_IPSR_GPSR(IP11_14_12, MT0_PEN),
1322     PINMUX_IPSR_GPSR(IP11_14_12, SPA_TRST),
1323     PINMUX_IPSR_MSEL(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
1324     PINMUX_IPSR_GPSR(IP11_14_12, ADICHS1_B),
1325     PINMUX_IPSR_GPSR(IP11_17_15, VI1_DATA5_VI1_B5),
1326     PINMUX_IPSR_MSEL(IP11_17_15, SD2_CMD, SEL_SD2_0),
1327     PINMUX_IPSR_GPSR(IP11_17_15, MT0_SYNC),
1328     PINMUX_IPSR_GPSR(IP11_17_15, SPA_TCK),
1329     PINMUX_IPSR_MSEL(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
1330     PINMUX_IPSR_GPSR(IP11_17_15, ADICHS2_B),
1331     PINMUX_IPSR_GPSR(IP11_20_18, VI1_DATA6_VI1_B6),
1332     PINMUX_IPSR_MSEL(IP11_20_18, SD2_CD, SEL_SD2_0),
1333     PINMUX_IPSR_GPSR(IP11_20_18, MT0_VCXO),
1334     PINMUX_IPSR_GPSR(IP11_20_18, SPA_TMS),
1335     PINMUX_IPSR_GPSR(IP11_20_18, HSPI_TX1_D),
1336     PINMUX_IPSR_GPSR(IP11_23_21, VI1_DATA7_VI1_B7),
1337     PINMUX_IPSR_MSEL(IP11_23_21, SD2_WP, SEL_SD2_0),
1338     PINMUX_IPSR_GPSR(IP11_23_21, MT0_PWM),
1339     PINMUX_IPSR_GPSR(IP11_23_21, SPA_TDI),
1340     PINMUX_IPSR_MSEL(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
1341     PINMUX_IPSR_GPSR(IP11_26_24, VI1_G0),
1342     PINMUX_IPSR_GPSR(IP11_26_24, VI3_DATA0),
1343     PINMUX_IPSR_GPSR(IP11_26_24, TS_SCK1),
1344     PINMUX_IPSR_MSEL(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
1345     PINMUX_IPSR_GPSR(IP11_26_24, TX2),
1346     PINMUX_IPSR_GPSR(IP11_26_24, SPA_TDO),
1347     PINMUX_IPSR_MSEL(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
1348     PINMUX_IPSR_GPSR(IP11_29_27, VI1_G1),
1349     PINMUX_IPSR_GPSR(IP11_29_27, VI3_DATA1),
1350     PINMUX_IPSR_GPSR(IP11_29_27, SSI_SCK1),
1351     PINMUX_IPSR_GPSR(IP11_29_27, TS_SDEN1),
1352     PINMUX_IPSR_GPSR(IP11_29_27, DACK2_B),
1353     PINMUX_IPSR_MSEL(IP11_29_27, RX2, SEL_SCIF2_0),
1354     PINMUX_IPSR_MSEL(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
1355
1356     PINMUX_IPSR_GPSR(IP12_2_0, VI1_G2),
1357     PINMUX_IPSR_GPSR(IP12_2_0, VI3_DATA2),
1358     PINMUX_IPSR_GPSR(IP12_2_0, SSI_WS1),
1359     PINMUX_IPSR_GPSR(IP12_2_0, TS_SPSYNC1),
1360     PINMUX_IPSR_MSEL(IP12_2_0, SCK2, SEL_SCIF2_0),
1361     PINMUX_IPSR_MSEL(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
1362     PINMUX_IPSR_GPSR(IP12_5_3, VI1_G3),
1363     PINMUX_IPSR_GPSR(IP12_5_3, VI3_DATA3),
1364     PINMUX_IPSR_GPSR(IP12_5_3, SSI_SCK2),
1365     PINMUX_IPSR_GPSR(IP12_5_3, TS_SDAT1),
1366     PINMUX_IPSR_MSEL(IP12_5_3, SCL1_C, SEL_I2C1_2),
1367     PINMUX_IPSR_GPSR(IP12_5_3, HTX0_B),
1368     PINMUX_IPSR_GPSR(IP12_8_6, VI1_G4),
1369     PINMUX_IPSR_GPSR(IP12_8_6, VI3_DATA4),
1370     PINMUX_IPSR_GPSR(IP12_8_6, SSI_WS2),
1371     PINMUX_IPSR_MSEL(IP12_8_6, SDA1_C, SEL_I2C1_2),
1372     PINMUX_IPSR_GPSR(IP12_8_6, SIM_RST_B),
1373     PINMUX_IPSR_MSEL(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
1374     PINMUX_IPSR_GPSR(IP12_11_9, VI1_G5),
1375     PINMUX_IPSR_GPSR(IP12_11_9, VI3_DATA5),
1376     PINMUX_IPSR_MSEL(IP12_11_9, GPS_CLK, SEL_GPS_0),
1377     PINMUX_IPSR_GPSR(IP12_11_9, FSE),
1378     PINMUX_IPSR_GPSR(IP12_11_9, TX4_B),
1379     PINMUX_IPSR_MSEL(IP12_11_9, SIM_D_B, SEL_SIM_1),
1380     PINMUX_IPSR_GPSR(IP12_14_12, VI1_G6),
1381     PINMUX_IPSR_GPSR(IP12_14_12, VI3_DATA6),
1382     PINMUX_IPSR_MSEL(IP12_14_12, GPS_SIGN, SEL_GPS_0),
1383     PINMUX_IPSR_GPSR(IP12_14_12, FRB),
1384     PINMUX_IPSR_MSEL(IP12_14_12, RX4_B, SEL_SCIF4_1),
1385     PINMUX_IPSR_GPSR(IP12_14_12, SIM_CLK_B),
1386     PINMUX_IPSR_GPSR(IP12_17_15, VI1_G7),
1387     PINMUX_IPSR_GPSR(IP12_17_15, VI3_DATA7),
1388     PINMUX_IPSR_MSEL(IP12_17_15, GPS_MAG, SEL_GPS_0),
1389     PINMUX_IPSR_GPSR(IP12_17_15, FCE),
1390     PINMUX_IPSR_MSEL(IP12_17_15, SCK4_B, SEL_SCIF4_1),
1391 };
1392
1393 static const struct sh_pfc_pin pinmux_pins[] = {
1394     PINMUX_GPIO_GP_ALL(),
1395 };
1396
1397 /* - DU0 -------------------------------------------------------------------- */
1398 static const unsigned int du0_rgb666_pins[] = {
1399     /* R[7:2], G[7:2], B[7:2] */
1400     RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
1401     RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
1402     RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),
1403     RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29),
1404     RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),  RCAR_GP_PIN(6, 6),
1405     RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),  RCAR_GP_PIN(6, 3),
1406 };
1407 static const unsigned int du0_rgb666_mux[] = {
1408     DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1409     DU0_DR3_MARK, DU0_DR2_MARK,
1410     DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1411     DU0_DG3_MARK, DU0_DG2_MARK,
1412     DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1413     DU0_DB3_MARK, DU0_DB2_MARK,
1414 };
1415 static const unsigned int du0_rgb888_pins[] = {
1416     /* R[7:0], G[7:0], B[7:0] */
1417     RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
1418     RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
1419     RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), RCAR_GP_PIN(6, 2),
1420     RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),  RCAR_GP_PIN(5, 31),
1421     RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), RCAR_GP_PIN(0, 26),
1422     RCAR_GP_PIN(0, 25), RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),
1423     RCAR_GP_PIN(6, 6),  RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),
1424     RCAR_GP_PIN(6, 3),  RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 27),
1425 };
1426 static const unsigned int du0_rgb888_mux[] = {
1427     DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1428     DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
1429     DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1430     DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
1431     DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1432     DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1433 };
1434 static const unsigned int du0_clk_in_pins[] = {
1435     /* CLKIN */
1436     RCAR_GP_PIN(0, 29),
1437 };
1438 static const unsigned int du0_clk_in_mux[] = {
1439     DU0_DOTCLKIN_MARK,
1440 };
1441 static const unsigned int du0_clk_out_0_pins[] = {
1442     /* CLKOUT */
1443     RCAR_GP_PIN(5, 20),
1444 };
1445 static const unsigned int du0_clk_out_0_mux[] = {
1446     DU0_DOTCLKOUT0_MARK,
1447 };
1448 static const unsigned int du0_clk_out_1_pins[] = {
1449     /* CLKOUT */
1450     RCAR_GP_PIN(0, 30),
1451 };
1452 static const unsigned int du0_clk_out_1_mux[] = {
1453     DU0_DOTCLKOUT1_MARK,
1454 };
1455 static const unsigned int du0_sync_0_pins[] = {
1456     /* VSYNC, HSYNC, DISP */
1457     RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(0, 31),
1458 };
1459 static const unsigned int du0_sync_0_mux[] = {
1460     DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
1461     DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
1462 };
1463 static const unsigned int du0_sync_1_pins[] = {
1464     /* VSYNC, HSYNC, DISP */
1465     RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(1, 0),
1466 };
1467 static const unsigned int du0_sync_1_mux[] = {
1468     DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
1469     DU0_DISP_MARK
1470 };
1471 static const unsigned int du0_oddf_pins[] = {
1472     /* ODDF */
1473     RCAR_GP_PIN(0, 31),
1474 };
1475 static const unsigned int du0_oddf_mux[] = {
1476     DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
1477 };
1478 static const unsigned int du0_cde_pins[] = {
1479     /* CDE */
1480     RCAR_GP_PIN(1, 1),
1481 };
1482 static const unsigned int du0_cde_mux[] = {
1483     DU0_CDE_MARK
1484 };
1485 /* - DU1 -------------------------------------------------------------------- */
1486 static const unsigned int du1_rgb666_pins[] = {
1487     /* R[7:2], G[7:2], B[7:2] */
1488     RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
1489     RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
1490     RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
1491     RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
1492     RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
1493     RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 20),
1494 };
1495 static const unsigned int du1_rgb666_mux[] = {
1496     DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1497     DU1_DR3_MARK, DU1_DR2_MARK,
1498     DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1499     DU1_DG3_MARK, DU1_DG2_MARK,
1500     DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1501     DU1_DB3_MARK, DU1_DB2_MARK,
1502 };
1503 static const unsigned int du1_rgb888_pins[] = {
1504     /* R[7:0], G[7:0], B[7:0] */
1505     RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
1506     RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
1507     RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 17),
1508     RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
1509     RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11),
1510     RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24),
1511     RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
1512     RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1513 };
1514 static const unsigned int du1_rgb888_mux[] = {
1515     DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1516     DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1517     DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1518     DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1519     DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1520     DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1521 };
1522 static const unsigned int du1_clk_in_pins[] = {
1523     /* CLKIN */
1524     RCAR_GP_PIN(1, 26),
1525 };
1526 static const unsigned int du1_clk_in_mux[] = {
1527     DU1_DOTCLKIN_MARK,
1528 };
1529 static const unsigned int du1_clk_out_pins[] = {
1530     /* CLKOUT */
1531     RCAR_GP_PIN(1, 27),
1532 };
1533 static const unsigned int du1_clk_out_mux[] = {
1534     DU1_DOTCLKOUT_MARK,
1535 };
1536 static const unsigned int du1_sync_0_pins[] = {
1537     /* VSYNC, HSYNC, DISP */
1538     RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 30),
1539 };
1540 static const unsigned int du1_sync_0_mux[] = {
1541     DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
1542     DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
1543 };
1544 static const unsigned int du1_sync_1_pins[] = {
1545     /* VSYNC, HSYNC, DISP */
1546     RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 31),
1547 };
1548 static const unsigned int du1_sync_1_mux[] = {
1549     DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
1550     DU1_DISP_MARK
1551 };
1552 static const unsigned int du1_oddf_pins[] = {
1553     /* ODDF */
1554     RCAR_GP_PIN(1, 30),
1555 };
1556 static const unsigned int du1_oddf_mux[] = {
1557     DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
1558 };
1559 static const unsigned int du1_cde_pins[] = {
1560     /* CDE */
1561     RCAR_GP_PIN(2, 0),
1562 };
1563 static const unsigned int du1_cde_mux[] = {
1564     DU1_CDE_MARK
1565 };
1566 /* - Ether ------------------------------------------------------------------ */
1567 static const unsigned int ether_rmii_pins[] = {
1568     /*
1569      * ETH_TXD0, ETH_TXD1, ETH_TX_EN,  ETH_REFCLK,
1570      * ETH_RXD0, ETH_RXD1, ETH_CRS_DV, ETH_RX_ER,
1571      * ETH_MDIO, ETH_MDC
1572      */
1573     RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 18),
1574     RCAR_GP_PIN(2, 26),
1575     RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 17),
1576     RCAR_GP_PIN(2, 19),
1577     RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 28),
1578 };
1579 static const unsigned int ether_rmii_mux[] = {
1580     ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REFCLK_MARK,
1581     ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
1582     ETH_MDIO_MARK, ETH_MDC_MARK,
1583 };
1584 static const unsigned int ether_link_pins[] = {
1585     /* ETH_LINK */
1586     RCAR_GP_PIN(2, 24),
1587 };
1588 static const unsigned int ether_link_mux[] = {
1589     ETH_LINK_MARK,
1590 };
1591 static const unsigned int ether_magic_pins[] = {
1592     /* ETH_MAGIC */
1593     RCAR_GP_PIN(2, 25),
1594 };
1595 static const unsigned int ether_magic_mux[] = {
1596     ETH_MAGIC_MARK,
1597 };
1598 /* - HSCIF0 ----------------------------------------------------------------- */
1599 static const unsigned int hscif0_data_pins[] = {
1600     /* TX, RX */
1601     RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21)
1602 };
1603 static const unsigned int hscif0_data_mux[] = {
1604     HTX0_MARK, HRX0_MARK
1605 };
1606 static const unsigned int hscif0_data_b_pins[] = {
1607     /* TX, RX */
1608     RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13)
1609 };
1610 static const unsigned int hscif0_data_b_mux[] = {
1611     HTX0_B_MARK, HRX0_B_MARK
1612 };
1613 static const unsigned int hscif0_ctrl_pins[] = {
1614     /* CTS, RTS */
1615     RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19)
1616 };
1617 static const unsigned int hscif0_ctrl_mux[] = {
1618     HCTS0_MARK, HRTS0_MARK
1619 };
1620 static const unsigned int hscif0_ctrl_b_pins[] = {
1621     /* CTS, RTS */
1622     RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10)
1623 };
1624 static const unsigned int hscif0_ctrl_b_mux[] = {
1625     HCTS0_B_MARK, HRTS0_B_MARK
1626 };
1627 static const unsigned int hscif0_clk_pins[] = {
1628     /* SCK */
1629     RCAR_GP_PIN(4, 17)
1630 };
1631 static const unsigned int hscif0_clk_mux[] = {
1632     HSCK0_MARK
1633 };
1634 static const unsigned int hscif0_clk_b_pins[] = {
1635     /* SCK */
1636     RCAR_GP_PIN(3, 11)
1637 };
1638 static const unsigned int hscif0_clk_b_mux[] = {
1639     HSCK0_B_MARK
1640 };
1641 /* - HSCIF1 ----------------------------------------------------------------- */
1642 static const unsigned int hscif1_data_pins[] = {
1643     /* TX, RX */
1644     RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20)
1645 };
1646 static const unsigned int hscif1_data_mux[] = {
1647     HTX1_MARK, HRX1_MARK
1648 };
1649 static const unsigned int hscif1_data_b_pins[] = {
1650     /* TX, RX */
1651     RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3)
1652 };
1653 static const unsigned int hscif1_data_b_mux[] = {
1654     HTX1_B_MARK, HRX1_B_MARK
1655 };
1656 static const unsigned int hscif1_ctrl_pins[] = {
1657     /* CTS, RTS */
1658     RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22)
1659 };
1660 static const unsigned int hscif1_ctrl_mux[] = {
1661     HCTS1_MARK, HRTS1_MARK
1662 };
1663 static const unsigned int hscif1_ctrl_b_pins[] = {
1664     /* CTS, RTS */
1665     RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6)
1666 };
1667 static const unsigned int hscif1_ctrl_b_mux[] = {
1668     HCTS1_B_MARK, HRTS1_B_MARK
1669 };
1670 static const unsigned int hscif1_clk_pins[] = {
1671     /* SCK */
1672     RCAR_GP_PIN(0, 18)
1673 };
1674 static const unsigned int hscif1_clk_mux[] = {
1675     HSCK1_MARK
1676 };
1677 static const unsigned int hscif1_clk_b_pins[] = {
1678     /* SCK */
1679     RCAR_GP_PIN(2, 4)
1680 };
1681 static const unsigned int hscif1_clk_b_mux[] = {
1682     HSCK1_B_MARK
1683 };
1684 /* - HSPI0 ------------------------------------------------------------------ */
1685 static const unsigned int hspi0_pins[] = {
1686     /* CLK, CS, RX, TX */
1687     RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 25),
1688     RCAR_GP_PIN(4, 24),
1689 };
1690 static const unsigned int hspi0_mux[] = {
1691     HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK,
1692 };
1693 /* - HSPI1 ------------------------------------------------------------------ */
1694 static const unsigned int hspi1_pins[] = {
1695     /* CLK, CS, RX, TX */
1696     RCAR_GP_PIN(1, 31), RCAR_GP_PIN(1, 26), RCAR_GP_PIN(2, 0),
1697     RCAR_GP_PIN(1, 30),
1698 };
1699 static const unsigned int hspi1_mux[] = {
1700     HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK,
1701 };
1702 static const unsigned int hspi1_b_pins[] = {
1703     /* CLK, CS, RX, TX */
1704     RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 29),
1705     RCAR_GP_PIN(2, 28),
1706 };
1707 static const unsigned int hspi1_b_mux[] = {
1708     HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK,
1709 };
1710 static const unsigned int hspi1_c_pins[] = {
1711     /* CLK, CS, RX, TX */
1712     RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 16),
1713     RCAR_GP_PIN(4, 15),
1714 };
1715 static const unsigned int hspi1_c_mux[] = {
1716     HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK,
1717 };
1718 static const unsigned int hspi1_d_pins[] = {
1719     /* CLK, CS, RX, TX */
1720     RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 8),
1721     RCAR_GP_PIN(3, 7),
1722 };
1723 static const unsigned int hspi1_d_mux[] = {
1724     HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK,
1725 };
1726 /* - HSPI2 ------------------------------------------------------------------ */
1727 static const unsigned int hspi2_pins[] = {
1728     /* CLK, CS, RX, TX */
1729     RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
1730     RCAR_GP_PIN(0, 14),
1731 };
1732 static const unsigned int hspi2_mux[] = {
1733     HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK,
1734 };
1735 static const unsigned int hspi2_b_pins[] = {
1736     /* CLK, CS, RX, TX */
1737     RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 8),
1738     RCAR_GP_PIN(0, 6),
1739 };
1740 static const unsigned int hspi2_b_mux[] = {
1741     HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
1742 };
1743 /* - I2C1 ------------------------------------------------------------------ */
1744 static const unsigned int i2c1_pins[] = {
1745     /* SCL, SDA, */
1746     RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
1747 };
1748 static const unsigned int i2c1_mux[] = {
1749     SCL1_MARK, SDA1_MARK,
1750 };
1751 static const unsigned int i2c1_b_pins[] = {
1752     /* SCL, SDA, */
1753     RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
1754 };
1755 static const unsigned int i2c1_b_mux[] = {
1756     SCL1_B_MARK, SDA1_B_MARK,
1757 };
1758 static const unsigned int i2c1_c_pins[] = {
1759     /* SCL, SDA, */
1760     RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
1761 };
1762 static const unsigned int i2c1_c_mux[] = {
1763     SCL1_C_MARK, SDA1_C_MARK,
1764 };
1765 static const unsigned int i2c1_d_pins[] = {
1766     /* SCL, SDA, */
1767     RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 27),
1768 };
1769 static const unsigned int i2c1_d_mux[] = {
1770     SCL1_D_MARK, SDA1_D_MARK,
1771 };
1772 /* - I2C2 ------------------------------------------------------------------ */
1773 static const unsigned int i2c2_pins[] = {
1774     /* SCL, SDA, */
1775     RCAR_GP_PIN(0, 25), RCAR_GP_PIN(0, 26),
1776 };
1777 static const unsigned int i2c2_mux[] = {
1778     SCL2_MARK, SDA2_MARK,
1779 };
1780 static const unsigned int i2c2_b_pins[] = {
1781     /* SCL, SDA, */
1782     RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
1783 };
1784 static const unsigned int i2c2_b_mux[] = {
1785     SCL2_B_MARK, SDA2_B_MARK,
1786 };
1787 static const unsigned int i2c2_c_pins[] = {
1788     /* SCL, SDA */
1789     RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 30),
1790 };
1791 static const unsigned int i2c2_c_mux[] = {
1792     SCL2_C_MARK, SDA2_C_MARK,
1793 };
1794 static const unsigned int i2c2_d_pins[] = {
1795     /* SCL, SDA */
1796     RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
1797 };
1798 static const unsigned int i2c2_d_mux[] = {
1799     SCL2_D_MARK, SDA2_D_MARK,
1800 };
1801 /* - I2C3 ------------------------------------------------------------------ */
1802 static const unsigned int i2c3_pins[] = {
1803     /* SCL, SDA, */
1804     RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 30),
1805 };
1806 static const unsigned int i2c3_mux[] = {
1807     SCL3_MARK, SDA3_MARK,
1808 };
1809 static const unsigned int i2c3_b_pins[] = {
1810     /* SCL, SDA, */
1811     RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30),
1812 };
1813 static const unsigned int i2c3_b_mux[] = {
1814     SCL3_B_MARK, SDA3_B_MARK,
1815 };
1816 /* - INTC ------------------------------------------------------------------- */
1817 static const unsigned int intc_irq0_pins[] = {
1818     /* IRQ */
1819     RCAR_GP_PIN(2, 14),
1820 };
1821 static const unsigned int intc_irq0_mux[] = {
1822     IRQ0_MARK,
1823 };
1824 static const unsigned int intc_irq0_b_pins[] = {
1825     /* IRQ */
1826     RCAR_GP_PIN(4, 13),
1827 };
1828 static const unsigned int intc_irq0_b_mux[] = {
1829     IRQ0_B_MARK,
1830 };
1831 static const unsigned int intc_irq1_pins[] = {
1832     /* IRQ */
1833     RCAR_GP_PIN(2, 15),
1834 };
1835 static const unsigned int intc_irq1_mux[] = {
1836     IRQ1_MARK,
1837 };
1838 static const unsigned int intc_irq1_b_pins[] = {
1839     /* IRQ */
1840     RCAR_GP_PIN(4, 14),
1841 };
1842 static const unsigned int intc_irq1_b_mux[] = {
1843     IRQ1_B_MARK,
1844 };
1845 static const unsigned int intc_irq2_pins[] = {
1846     /* IRQ */
1847     RCAR_GP_PIN(2, 24),
1848 };
1849 static const unsigned int intc_irq2_mux[] = {
1850     IRQ2_MARK,
1851 };
1852 static const unsigned int intc_irq2_b_pins[] = {
1853     /* IRQ */
1854     RCAR_GP_PIN(4, 15),
1855 };
1856 static const unsigned int intc_irq2_b_mux[] = {
1857     IRQ2_B_MARK,
1858 };
1859 static const unsigned int intc_irq3_pins[] = {
1860     /* IRQ */
1861     RCAR_GP_PIN(2, 25),
1862 };
1863 static const unsigned int intc_irq3_mux[] = {
1864     IRQ3_MARK,
1865 };
1866 static const unsigned int intc_irq3_b_pins[] = {
1867     /* IRQ */
1868     RCAR_GP_PIN(4, 16),
1869 };
1870 static const unsigned int intc_irq3_b_mux[] = {
1871     IRQ3_B_MARK,
1872 };
1873 /* - LSBC ------------------------------------------------------------------- */
1874 static const unsigned int lbsc_cs0_pins[] = {
1875     /* CS */
1876     RCAR_GP_PIN(0, 13),
1877 };
1878 static const unsigned int lbsc_cs0_mux[] = {
1879     CS0_MARK,
1880 };
1881 static const unsigned int lbsc_cs1_pins[] = {
1882     /* CS */
1883     RCAR_GP_PIN(0, 14),
1884 };
1885 static const unsigned int lbsc_cs1_mux[] = {
1886     CS1_A26_MARK,
1887 };
1888 static const unsigned int lbsc_ex_cs0_pins[] = {
1889     /* CS */
1890     RCAR_GP_PIN(0, 15),
1891 };
1892 static const unsigned int lbsc_ex_cs0_mux[] = {
1893     EX_CS0_MARK,
1894 };
1895 static const unsigned int lbsc_ex_cs1_pins[] = {
1896     /* CS */
1897     RCAR_GP_PIN(0, 16),
1898 };
1899 static const unsigned int lbsc_ex_cs1_mux[] = {
1900     EX_CS1_MARK,
1901 };
1902 static const unsigned int lbsc_ex_cs2_pins[] = {
1903     /* CS */
1904     RCAR_GP_PIN(0, 17),
1905 };
1906 static const unsigned int lbsc_ex_cs2_mux[] = {
1907     EX_CS2_MARK,
1908 };
1909 static const unsigned int lbsc_ex_cs3_pins[] = {
1910     /* CS */
1911     RCAR_GP_PIN(0, 18),
1912 };
1913 static const unsigned int lbsc_ex_cs3_mux[] = {
1914     EX_CS3_MARK,
1915 };
1916 static const unsigned int lbsc_ex_cs4_pins[] = {
1917     /* CS */
1918     RCAR_GP_PIN(0, 19),
1919 };
1920 static const unsigned int lbsc_ex_cs4_mux[] = {
1921     EX_CS4_MARK,
1922 };
1923 static const unsigned int lbsc_ex_cs5_pins[] = {
1924     /* CS */
1925     RCAR_GP_PIN(0, 20),
1926 };
1927 static const unsigned int lbsc_ex_cs5_mux[] = {
1928     EX_CS5_MARK,
1929 };
1930 /* - MMCIF ------------------------------------------------------------------ */
1931 static const unsigned int mmc0_data_pins[] = {
1932     /* D[0:7] */
1933     RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
1934     RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
1935     RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
1936 };
1937 static const unsigned int mmc0_data_mux[] = {
1938     MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1939     MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
1940 };
1941 static const unsigned int mmc0_ctrl_pins[] = {
1942     /* CMD, CLK */
1943     RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
1944 };
1945 static const unsigned int mmc0_ctrl_mux[] = {
1946     MMC0_CMD_MARK, MMC0_CLK_MARK,
1947 };
1948 static const unsigned int mmc1_data_pins[] = {
1949     /* D[0:7] */
1950     RCAR_GP_PIN(2, 8),  RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10),
1951     RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
1952     RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
1953 };
1954 static const unsigned int mmc1_data_mux[] = {
1955     MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1956     MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
1957 };
1958 static const unsigned int mmc1_ctrl_pins[] = {
1959     /* CMD, CLK */
1960     RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 1),
1961 };
1962 static const unsigned int mmc1_ctrl_mux[] = {
1963     MMC1_CMD_MARK, MMC1_CLK_MARK,
1964 };
1965 /* - SCIF0 ------------------------------------------------------------------ */
1966 static const unsigned int scif0_data_pins[] = {
1967     /* RXD, TXD */
1968     RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
1969 };
1970 static const unsigned int scif0_data_mux[] = {
1971     RX0_MARK, TX0_MARK,
1972 };
1973 static const unsigned int scif0_clk_pins[] = {
1974     /* SCK */
1975     RCAR_GP_PIN(4, 28),
1976 };
1977 static const unsigned int scif0_clk_mux[] = {
1978     SCK0_MARK,
1979 };
1980 static const unsigned int scif0_ctrl_pins[] = {
1981     /* RTS, CTS */
1982     RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22),
1983 };
1984 static const unsigned int scif0_ctrl_mux[] = {
1985     RTS0_TANS_MARK, CTS0_MARK,
1986 };
1987 static const unsigned int scif0_data_b_pins[] = {
1988     /* RXD, TXD */
1989     RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
1990 };
1991 static const unsigned int scif0_data_b_mux[] = {
1992     RX0_B_MARK, TX0_B_MARK,
1993 };
1994 static const unsigned int scif0_clk_b_pins[] = {
1995     /* SCK */
1996     RCAR_GP_PIN(1, 1),
1997 };
1998 static const unsigned int scif0_clk_b_mux[] = {
1999     SCK0_B_MARK,
2000 };
2001 static const unsigned int scif0_ctrl_b_pins[] = {
2002     /* RTS, CTS */
2003     RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
2004 };
2005 static const unsigned int scif0_ctrl_b_mux[] = {
2006     RTS0_B_TANS_B_MARK, CTS0_B_MARK,
2007 };
2008 static const unsigned int scif0_data_c_pins[] = {
2009     /* RXD, TXD */
2010     RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
2011 };
2012 static const unsigned int scif0_data_c_mux[] = {
2013     RX0_C_MARK, TX0_C_MARK,
2014 };
2015 static const unsigned int scif0_clk_c_pins[] = {
2016     /* SCK */
2017     RCAR_GP_PIN(4, 17),
2018 };
2019 static const unsigned int scif0_clk_c_mux[] = {
2020     SCK0_C_MARK,
2021 };
2022 static const unsigned int scif0_ctrl_c_pins[] = {
2023     /* RTS, CTS */
2024     RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
2025 };
2026 static const unsigned int scif0_ctrl_c_mux[] = {
2027     RTS0_C_TANS_C_MARK, CTS0_C_MARK,
2028 };
2029 static const unsigned int scif0_data_d_pins[] = {
2030     /* RXD, TXD */
2031     RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
2032 };
2033 static const unsigned int scif0_data_d_mux[] = {
2034     RX0_D_MARK, TX0_D_MARK,
2035 };
2036 static const unsigned int scif0_clk_d_pins[] = {
2037     /* SCK */
2038     RCAR_GP_PIN(1, 18),
2039 };
2040 static const unsigned int scif0_clk_d_mux[] = {
2041     SCK0_D_MARK,
2042 };
2043 static const unsigned int scif0_ctrl_d_pins[] = {
2044     /* RTS, CTS */
2045     RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 3),
2046 };
2047 static const unsigned int scif0_ctrl_d_mux[] = {
2048     RTS0_D_TANS_D_MARK, CTS0_D_MARK,
2049 };
2050 /* - SCIF1 ------------------------------------------------------------------ */
2051 static const unsigned int scif1_data_pins[] = {
2052     /* RXD, TXD */
2053     RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
2054 };
2055 static const unsigned int scif1_data_mux[] = {
2056     RX1_MARK, TX1_MARK,
2057 };
2058 static const unsigned int scif1_clk_pins[] = {
2059     /* SCK */
2060     RCAR_GP_PIN(4, 17),
2061 };
2062 static const unsigned int scif1_clk_mux[] = {
2063     SCK1_MARK,
2064 };
2065 static const unsigned int scif1_ctrl_pins[] = {
2066     /* RTS, CTS */
2067     RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
2068 };
2069 static const unsigned int scif1_ctrl_mux[] = {
2070     RTS1_TANS_MARK, CTS1_MARK,
2071 };
2072 static const unsigned int scif1_data_b_pins[] = {
2073     /* RXD, TXD */
2074     RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 18),
2075 };
2076 static const unsigned int scif1_data_b_mux[] = {
2077     RX1_B_MARK, TX1_B_MARK,
2078 };
2079 static const unsigned int scif1_clk_b_pins[] = {
2080     /* SCK */
2081     RCAR_GP_PIN(3, 17),
2082 };
2083 static const unsigned int scif1_clk_b_mux[] = {
2084     SCK1_B_MARK,
2085 };
2086 static const unsigned int scif1_ctrl_b_pins[] = {
2087     /* RTS, CTS */
2088     RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
2089 };
2090 static const unsigned int scif1_ctrl_b_mux[] = {
2091     RTS1_B_TANS_B_MARK, CTS1_B_MARK,
2092 };
2093 static const unsigned int scif1_data_c_pins[] = {
2094     /* RXD, TXD */
2095     RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
2096 };
2097 static const unsigned int scif1_data_c_mux[] = {
2098     RX1_C_MARK, TX1_C_MARK,
2099 };
2100 static const unsigned int scif1_clk_c_pins[] = {
2101     /* SCK */
2102     RCAR_GP_PIN(2, 22),
2103 };
2104 static const unsigned int scif1_clk_c_mux[] = {
2105     SCK1_C_MARK,
2106 };
2107 static const unsigned int scif1_ctrl_c_pins[] = {
2108     /* RTS, CTS */
2109     RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2110 };
2111 static const unsigned int scif1_ctrl_c_mux[] = {
2112     RTS1_C_TANS_C_MARK, CTS1_C_MARK,
2113 };
2114 /* - SCIF2 ------------------------------------------------------------------ */
2115 static const unsigned int scif2_data_pins[] = {
2116     /* RXD, TXD */
2117     RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 9),
2118 };
2119 static const unsigned int scif2_data_mux[] = {
2120     RX2_MARK, TX2_MARK,
2121 };
2122 static const unsigned int scif2_clk_pins[] = {
2123     /* SCK */
2124     RCAR_GP_PIN(3, 11),
2125 };
2126 static const unsigned int scif2_clk_mux[] = {
2127     SCK2_MARK,
2128 };
2129 static const unsigned int scif2_data_b_pins[] = {
2130     /* RXD, TXD */
2131     RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 23),
2132 };
2133 static const unsigned int scif2_data_b_mux[] = {
2134     RX2_B_MARK, TX2_B_MARK,
2135 };
2136 static const unsigned int scif2_clk_b_pins[] = {
2137     /* SCK */
2138     RCAR_GP_PIN(3, 22),
2139 };
2140 static const unsigned int scif2_clk_b_mux[] = {
2141     SCK2_B_MARK,
2142 };
2143 static const unsigned int scif2_data_c_pins[] = {
2144     /* RXD, TXD */
2145     RCAR_GP_PIN(1, 1), RCAR_GP_PIN(0, 31),
2146 };
2147 static const unsigned int scif2_data_c_mux[] = {
2148     RX2_C_MARK, TX2_C_MARK,
2149 };
2150 static const unsigned int scif2_clk_c_pins[] = {
2151     /* SCK */
2152     RCAR_GP_PIN(1, 0),
2153 };
2154 static const unsigned int scif2_clk_c_mux[] = {
2155     SCK2_C_MARK,
2156 };
2157 static const unsigned int scif2_data_d_pins[] = {
2158     /* RXD, TXD */
2159     RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
2160 };
2161 static const unsigned int scif2_data_d_mux[] = {
2162     RX2_D_MARK, TX2_D_MARK,
2163 };
2164 static const unsigned int scif2_clk_d_pins[] = {
2165     /* SCK */
2166     RCAR_GP_PIN(1, 31),
2167 };
2168 static const unsigned int scif2_clk_d_mux[] = {
2169     SCK2_D_MARK,
2170 };
2171 static const unsigned int scif2_data_e_pins[] = {
2172     /* RXD, TXD */
2173     RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
2174 };
2175 static const unsigned int scif2_data_e_mux[] = {
2176     RX2_E_MARK, TX2_E_MARK,
2177 };
2178 /* - SCIF3 ------------------------------------------------------------------ */
2179 static const unsigned int scif3_data_pins[] = {
2180     /* RXD, TXD */
2181     RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8),
2182 };
2183 static const unsigned int scif3_data_mux[] = {
2184     RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK,
2185 };
2186 static const unsigned int scif3_clk_pins[] = {
2187     /* SCK */
2188     RCAR_GP_PIN(4, 7),
2189 };
2190 static const unsigned int scif3_clk_mux[] = {
2191     SCK3_MARK,
2192 };
2193
2194 static const unsigned int scif3_data_b_pins[] = {
2195     /* RXD, TXD */
2196     RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
2197 };
2198 static const unsigned int scif3_data_b_mux[] = {
2199     RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK,
2200 };
2201 static const unsigned int scif3_data_c_pins[] = {
2202     /* RXD, TXD */
2203     RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 12),
2204 };
2205 static const unsigned int scif3_data_c_mux[] = {
2206     RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK,
2207 };
2208 static const unsigned int scif3_data_d_pins[] = {
2209     /* RXD, TXD */
2210     RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 29),
2211 };
2212 static const unsigned int scif3_data_d_mux[] = {
2213     RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK,
2214 };
2215 static const unsigned int scif3_data_e_pins[] = {
2216     /* RXD, TXD */
2217     RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2218 };
2219 static const unsigned int scif3_data_e_mux[] = {
2220     RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK,
2221 };
2222 static const unsigned int scif3_clk_e_pins[] = {
2223     /* SCK */
2224     RCAR_GP_PIN(1, 10),
2225 };
2226 static const unsigned int scif3_clk_e_mux[] = {
2227     SCK3_E_MARK,
2228 };
2229 /* - SCIF4 ------------------------------------------------------------------ */
2230 static const unsigned int scif4_data_pins[] = {
2231     /* RXD, TXD */
2232     RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 26),
2233 };
2234 static const unsigned int scif4_data_mux[] = {
2235     RX4_MARK, TX4_MARK,
2236 };
2237 static const unsigned int scif4_clk_pins[] = {
2238     /* SCK */
2239     RCAR_GP_PIN(3, 25),
2240 };
2241 static const unsigned int scif4_clk_mux[] = {
2242     SCK4_MARK,
2243 };
2244 static const unsigned int scif4_data_b_pins[] = {
2245     /* RXD, TXD */
2246     RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
2247 };
2248 static const unsigned int scif4_data_b_mux[] = {
2249     RX4_B_MARK, TX4_B_MARK,
2250 };
2251 static const unsigned int scif4_clk_b_pins[] = {
2252     /* SCK */
2253     RCAR_GP_PIN(3, 16),
2254 };
2255 static const unsigned int scif4_clk_b_mux[] = {
2256     SCK4_B_MARK,
2257 };
2258 static const unsigned int scif4_data_c_pins[] = {
2259     /* RXD, TXD */
2260     RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
2261 };
2262 static const unsigned int scif4_data_c_mux[] = {
2263     RX4_C_MARK, TX4_C_MARK,
2264 };
2265 static const unsigned int scif4_data_d_pins[] = {
2266     /* RXD, TXD */
2267     RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2268 };
2269 static const unsigned int scif4_data_d_mux[] = {
2270     RX4_D_MARK, TX4_D_MARK,
2271 };
2272 /* - SCIF5 ------------------------------------------------------------------ */
2273 static const unsigned int scif5_data_pins[] = {
2274     /* RXD, TXD */
2275     RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2276 };
2277 static const unsigned int scif5_data_mux[] = {
2278     RX5_MARK, TX5_MARK,
2279 };
2280 static const unsigned int scif5_clk_pins[] = {
2281     /* SCK */
2282     RCAR_GP_PIN(1, 11),
2283 };
2284 static const unsigned int scif5_clk_mux[] = {
2285     SCK5_MARK,
2286 };
2287 static const unsigned int scif5_data_b_pins[] = {
2288     /* RXD, TXD */
2289     RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
2290 };
2291 static const unsigned int scif5_data_b_mux[] = {
2292     RX5_B_MARK, TX5_B_MARK,
2293 };
2294 static const unsigned int scif5_clk_b_pins[] = {
2295     /* SCK */
2296     RCAR_GP_PIN(0, 19),
2297 };
2298 static const unsigned int scif5_clk_b_mux[] = {
2299     SCK5_B_MARK,
2300 };
2301 static const unsigned int scif5_data_c_pins[] = {
2302     /* RXD, TXD */
2303     RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23),
2304 };
2305 static const unsigned int scif5_data_c_mux[] = {
2306     RX5_C_MARK, TX5_C_MARK,
2307 };
2308 static const unsigned int scif5_clk_c_pins[] = {
2309     /* SCK */
2310     RCAR_GP_PIN(0, 28),
2311 };
2312 static const unsigned int scif5_clk_c_mux[] = {
2313     SCK5_C_MARK,
2314 };
2315 static const unsigned int scif5_data_d_pins[] = {
2316     /* RXD, TXD */
2317     RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6),
2318 };
2319 static const unsigned int scif5_data_d_mux[] = {
2320     RX5_D_MARK, TX5_D_MARK,
2321 };
2322 static const unsigned int scif5_clk_d_pins[] = {
2323     /* SCK */
2324     RCAR_GP_PIN(0, 7),
2325 };
2326 static const unsigned int scif5_clk_d_mux[] = {
2327     SCK5_D_MARK,
2328 };
2329 /* - SCIF Clock ------------------------------------------------------------- */
2330 static const unsigned int scif_clk_pins[] = {
2331     /* SCIF_CLK */
2332     RCAR_GP_PIN(4, 28),
2333 };
2334 static const unsigned int scif_clk_mux[] = {
2335     SCIF_CLK_MARK,
2336 };
2337 static const unsigned int scif_clk_b_pins[] = {
2338     /* SCIF_CLK */
2339     RCAR_GP_PIN(4, 5),
2340 };
2341 static const unsigned int scif_clk_b_mux[] = {
2342     SCIF_CLK_B_MARK,
2343 };
2344 static const unsigned int scif_clk_c_pins[] = {
2345     /* SCIF_CLK */
2346     RCAR_GP_PIN(4, 18),
2347 };
2348 static const unsigned int scif_clk_c_mux[] = {
2349     SCIF_CLK_C_MARK,
2350 };
2351 static const unsigned int scif_clk_d_pins[] = {
2352     /* SCIF_CLK */
2353     RCAR_GP_PIN(2, 29),
2354 };
2355 static const unsigned int scif_clk_d_mux[] = {
2356     SCIF_CLK_D_MARK,
2357 };
2358 /* - SDHI0 ------------------------------------------------------------------ */
2359 static const unsigned int sdhi0_data_pins[] = {
2360     /* D[0:3] */
2361     RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2362     RCAR_GP_PIN(3, 24),
2363 };
2364 static const unsigned int sdhi0_data_mux[] = {
2365     SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
2366 };
2367 static const unsigned int sdhi0_ctrl_pins[] = {
2368     /* CMD, CLK */
2369     RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 17),
2370 };
2371 static const unsigned int sdhi0_ctrl_mux[] = {
2372     SD0_CMD_MARK, SD0_CLK_MARK,
2373 };
2374 static const unsigned int sdhi0_cd_pins[] = {
2375     /* CD */
2376     RCAR_GP_PIN(3, 19),
2377 };
2378 static const unsigned int sdhi0_cd_mux[] = {
2379     SD0_CD_MARK,
2380 };
2381 static const unsigned int sdhi0_wp_pins[] = {
2382     /* WP */
2383     RCAR_GP_PIN(3, 20),
2384 };
2385 static const unsigned int sdhi0_wp_mux[] = {
2386     SD0_WP_MARK,
2387 };
2388 /* - SDHI1 ------------------------------------------------------------------ */
2389 static const unsigned int sdhi1_data_pins[] = {
2390     /* D[0:3] */
2391     RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
2392     RCAR_GP_PIN(0, 2),
2393 };
2394 static const unsigned int sdhi1_data_mux[] = {
2395     SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
2396 };
2397 static const unsigned int sdhi1_ctrl_pins[] = {
2398     /* CMD, CLK */
2399     RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
2400 };
2401 static const unsigned int sdhi1_ctrl_mux[] = {
2402     SD1_CMD_MARK, SD1_CLK_MARK,
2403 };
2404 static const unsigned int sdhi1_cd_pins[] = {
2405     /* CD */
2406     RCAR_GP_PIN(0, 10),
2407 };
2408 static const unsigned int sdhi1_cd_mux[] = {
2409     SD1_CD_MARK,
2410 };
2411 static const unsigned int sdhi1_wp_pins[] = {
2412     /* WP */
2413     RCAR_GP_PIN(0, 11),
2414 };
2415 static const unsigned int sdhi1_wp_mux[] = {
2416     SD1_WP_MARK,
2417 };
2418 /* - SDHI2 ------------------------------------------------------------------ */
2419 static const unsigned int sdhi2_data_pins[] = {
2420     /* D[0:3] */
2421     RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2422     RCAR_GP_PIN(3, 4),
2423 };
2424 static const unsigned int sdhi2_data_mux[] = {
2425     SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
2426 };
2427 static const unsigned int sdhi2_ctrl_pins[] = {
2428     /* CMD, CLK */
2429     RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
2430 };
2431 static const unsigned int sdhi2_ctrl_mux[] = {
2432     SD2_CMD_MARK, SD2_CLK_MARK,
2433 };
2434 static const unsigned int sdhi2_cd_pins[] = {
2435     /* CD */
2436     RCAR_GP_PIN(3, 7),
2437 };
2438 static const unsigned int sdhi2_cd_mux[] = {
2439     SD2_CD_MARK,
2440 };
2441 static const unsigned int sdhi2_wp_pins[] = {
2442     /* WP */
2443     RCAR_GP_PIN(3, 8),
2444 };
2445 static const unsigned int sdhi2_wp_mux[] = {
2446     SD2_WP_MARK,
2447 };
2448 /* - SDHI3 ------------------------------------------------------------------ */
2449 static const unsigned int sdhi3_data_pins[] = {
2450     /* D[0:3] */
2451     RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20),
2452     RCAR_GP_PIN(1, 21),
2453 };
2454 static const unsigned int sdhi3_data_mux[] = {
2455     SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
2456 };
2457 static const unsigned int sdhi3_ctrl_pins[] = {
2458     /* CMD, CLK */
2459     RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2460 };
2461 static const unsigned int sdhi3_ctrl_mux[] = {
2462     SD3_CMD_MARK, SD3_CLK_MARK,
2463 };
2464 static const unsigned int sdhi3_cd_pins[] = {
2465     /* CD */
2466     RCAR_GP_PIN(1, 30),
2467 };
2468 static const unsigned int sdhi3_cd_mux[] = {
2469     SD3_CD_MARK,
2470 };
2471 static const unsigned int sdhi3_wp_pins[] = {
2472     /* WP */
2473     RCAR_GP_PIN(2, 0),
2474 };
2475 static const unsigned int sdhi3_wp_mux[] = {
2476     SD3_WP_MARK,
2477 };
2478 /* - USB0 ------------------------------------------------------------------- */
2479 static const unsigned int usb0_pins[] = {
2480     /* PENC */
2481     RCAR_GP_PIN(4, 26),
2482 };
2483 static const unsigned int usb0_mux[] = {
2484     USB_PENC0_MARK,
2485 };
2486 static const unsigned int usb0_ovc_pins[] = {
2487     /* USB_OVC */
2488     RCAR_GP_PIN(4, 22),
2489 };
2490 static const unsigned int usb0_ovc_mux[] = {
2491     USB_OVC0_MARK,
2492 };
2493 /* - USB1 ------------------------------------------------------------------- */
2494 static const unsigned int usb1_pins[] = {
2495     /* PENC */
2496     RCAR_GP_PIN(4, 27),
2497 };
2498 static const unsigned int usb1_mux[] = {
2499     USB_PENC1_MARK,
2500 };
2501 static const unsigned int usb1_ovc_pins[] = {
2502     /* USB_OVC */
2503     RCAR_GP_PIN(4, 24),
2504 };
2505 static const unsigned int usb1_ovc_mux[] = {
2506     USB_OVC1_MARK,
2507 };
2508 /* - USB2 ------------------------------------------------------------------- */
2509 static const unsigned int usb2_pins[] = {
2510     /* PENC */
2511     RCAR_GP_PIN(4, 28),
2512 };
2513 static const unsigned int usb2_mux[] = {
2514     USB_PENC2_MARK,
2515 };
2516 static const unsigned int usb2_ovc_pins[] = {
2517     /* USB_OVC */
2518     RCAR_GP_PIN(3, 29),
2519 };
2520 static const unsigned int usb2_ovc_mux[] = {
2521     USB_OVC2_MARK,
2522 };
2523 /* - VIN0 ------------------------------------------------------------------- */
2524 static const unsigned int vin0_data8_pins[] = {
2525     /* D[0:7] */
2526     RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 8),
2527     RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
2528     RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
2529 };
2530 static const unsigned int vin0_data8_mux[] = {
2531     VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK,
2532     VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2533     VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2534 };
2535 static const unsigned int vin0_clk_pins[] = {
2536     /* CLK */
2537     RCAR_GP_PIN(2, 1),
2538 };
2539 static const unsigned int vin0_clk_mux[] = {
2540     VI0_CLK_MARK,
2541 };
2542 static const unsigned int vin0_sync_pins[] = {
2543     /* HSYNC, VSYNC */
2544     RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2545 };
2546 static const unsigned int vin0_sync_mux[] = {
2547     VI0_HSYNC_MARK, VI0_VSYNC_MARK,
2548 };
2549 /* - VIN1 ------------------------------------------------------------------- */
2550 static const unsigned int vin1_data8_pins[] = {
2551     /* D[0:7] */
2552     RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2553     RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
2554     RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
2555 };
2556 static const unsigned int vin1_data8_mux[] = {
2557     VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK,
2558     VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
2559     VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
2560 };
2561 static const unsigned int vin1_clk_pins[] = {
2562     /* CLK */
2563     RCAR_GP_PIN(2, 30),
2564 };
2565 static const unsigned int vin1_clk_mux[] = {
2566     VI1_CLK_MARK,
2567 };
2568 static const unsigned int vin1_sync_pins[] = {
2569     /* HSYNC, VSYNC */
2570     RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0),
2571 };
2572 static const unsigned int vin1_sync_mux[] = {
2573     VI1_HSYNC_MARK, VI1_VSYNC_MARK,
2574 };
2575 /* - VIN2 ------------------------------------------------------------------- */
2576 static const unsigned int vin2_data8_pins[] = {
2577     /* D[0:7] */
2578     RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
2579     RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
2580     RCAR_GP_PIN(1, 31), RCAR_GP_PIN(2, 0),
2581 };
2582 static const unsigned int vin2_data8_mux[] = {
2583     VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK,
2584     VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
2585     VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
2586 };
2587 static const unsigned int vin2_clk_pins[] = {
2588     /* CLK */
2589     RCAR_GP_PIN(1, 30),
2590 };
2591 static const unsigned int vin2_clk_mux[] = {
2592     VI2_CLK_MARK,
2593 };
2594 static const unsigned int vin2_sync_pins[] = {
2595     /* HSYNC, VSYNC */
2596     RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
2597 };
2598 static const unsigned int vin2_sync_mux[] = {
2599     VI2_HSYNC_MARK, VI2_VSYNC_MARK,
2600 };
2601 /* - VIN3 ------------------------------------------------------------------- */
2602 static const unsigned int vin3_data8_pins[] = {
2603     /* D[0:7] */
2604     RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2605     RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
2606     RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
2607 };
2608 static const unsigned int vin3_data8_mux[] = {
2609     VI3_DATA0_MARK, VI3_DATA1_MARK, VI3_DATA2_MARK,
2610     VI3_DATA3_MARK, VI3_DATA4_MARK, VI3_DATA5_MARK,
2611     VI3_DATA6_MARK, VI3_DATA7_MARK,
2612 };
2613 static const unsigned int vin3_clk_pins[] = {
2614     /* CLK */
2615     RCAR_GP_PIN(2, 31),
2616 };
2617 static const unsigned int vin3_clk_mux[] = {
2618     VI3_CLK_MARK,
2619 };
2620 static const unsigned int vin3_sync_pins[] = {
2621     /* HSYNC, VSYNC */
2622     RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
2623 };
2624 static const unsigned int vin3_sync_mux[] = {
2625     VI3_HSYNC_MARK, VI3_VSYNC_MARK,
2626 };
2627
2628 static const struct sh_pfc_pin_group pinmux_groups[] = {
2629     SH_PFC_PIN_GROUP(du0_rgb666),
2630     SH_PFC_PIN_GROUP(du0_rgb888),
2631     SH_PFC_PIN_GROUP(du0_clk_in),
2632     SH_PFC_PIN_GROUP(du0_clk_out_0),
2633     SH_PFC_PIN_GROUP(du0_clk_out_1),
2634     SH_PFC_PIN_GROUP(du0_sync_0),
2635     SH_PFC_PIN_GROUP(du0_sync_1),
2636     SH_PFC_PIN_GROUP(du0_oddf),
2637     SH_PFC_PIN_GROUP(du0_cde),
2638     SH_PFC_PIN_GROUP(du1_rgb666),
2639     SH_PFC_PIN_GROUP(du1_rgb888),
2640     SH_PFC_PIN_GROUP(du1_clk_in),
2641     SH_PFC_PIN_GROUP(du1_clk_out),
2642     SH_PFC_PIN_GROUP(du1_sync_0),
2643     SH_PFC_PIN_GROUP(du1_sync_1),
2644     SH_PFC_PIN_GROUP(du1_oddf),
2645     SH_PFC_PIN_GROUP(du1_cde),
2646     SH_PFC_PIN_GROUP(ether_rmii),
2647     SH_PFC_PIN_GROUP(ether_link),
2648     SH_PFC_PIN_GROUP(ether_magic),
2649     SH_PFC_PIN_GROUP(hscif0_data),
2650     SH_PFC_PIN_GROUP(hscif0_data_b),
2651     SH_PFC_PIN_GROUP(hscif0_ctrl),
2652     SH_PFC_PIN_GROUP(hscif0_ctrl_b),
2653     SH_PFC_PIN_GROUP(hscif0_clk),
2654     SH_PFC_PIN_GROUP(hscif0_clk_b),
2655     SH_PFC_PIN_GROUP(hscif1_data),
2656     SH_PFC_PIN_GROUP(hscif1_data_b),
2657     SH_PFC_PIN_GROUP(hscif1_ctrl),
2658     SH_PFC_PIN_GROUP(hscif1_ctrl_b),
2659     SH_PFC_PIN_GROUP(hscif1_clk),
2660     SH_PFC_PIN_GROUP(hscif1_clk_b),
2661     SH_PFC_PIN_GROUP(hspi0),
2662     SH_PFC_PIN_GROUP(hspi1),
2663     SH_PFC_PIN_GROUP(hspi1_b),
2664     SH_PFC_PIN_GROUP(hspi1_c),
2665     SH_PFC_PIN_GROUP(hspi1_d),
2666     SH_PFC_PIN_GROUP(hspi2),
2667     SH_PFC_PIN_GROUP(hspi2_b),
2668     SH_PFC_PIN_GROUP(i2c1),
2669     SH_PFC_PIN_GROUP(i2c1_b),
2670     SH_PFC_PIN_GROUP(i2c1_c),
2671     SH_PFC_PIN_GROUP(i2c1_d),
2672     SH_PFC_PIN_GROUP(i2c2),
2673     SH_PFC_PIN_GROUP(i2c2_b),
2674     SH_PFC_PIN_GROUP(i2c2_c),
2675     SH_PFC_PIN_GROUP(i2c2_d),
2676     SH_PFC_PIN_GROUP(i2c3),
2677     SH_PFC_PIN_GROUP(i2c3_b),
2678     SH_PFC_PIN_GROUP(intc_irq0),
2679     SH_PFC_PIN_GROUP(intc_irq0_b),
2680     SH_PFC_PIN_GROUP(intc_irq1),
2681     SH_PFC_PIN_GROUP(intc_irq1_b),
2682     SH_PFC_PIN_GROUP(intc_irq2),
2683     SH_PFC_PIN_GROUP(intc_irq2_b),
2684     SH_PFC_PIN_GROUP(intc_irq3),
2685     SH_PFC_PIN_GROUP(intc_irq3_b),
2686     SH_PFC_PIN_GROUP(lbsc_cs0),
2687     SH_PFC_PIN_GROUP(lbsc_cs1),
2688     SH_PFC_PIN_GROUP(lbsc_ex_cs0),
2689     SH_PFC_PIN_GROUP(lbsc_ex_cs1),
2690     SH_PFC_PIN_GROUP(lbsc_ex_cs2),
2691     SH_PFC_PIN_GROUP(lbsc_ex_cs3),
2692     SH_PFC_PIN_GROUP(lbsc_ex_cs4),
2693     SH_PFC_PIN_GROUP(lbsc_ex_cs5),
2694     BUS_DATA_PIN_GROUP(mmc0_data, 1),
2695     BUS_DATA_PIN_GROUP(mmc0_data, 4),
2696     BUS_DATA_PIN_GROUP(mmc0_data, 8),
2697     SH_PFC_PIN_GROUP(mmc0_ctrl),
2698     BUS_DATA_PIN_GROUP(mmc1_data, 1),
2699     BUS_DATA_PIN_GROUP(mmc1_data, 4),
2700     BUS_DATA_PIN_GROUP(mmc1_data, 8),
2701     SH_PFC_PIN_GROUP(mmc1_ctrl),
2702     SH_PFC_PIN_GROUP(scif0_data),
2703     SH_PFC_PIN_GROUP(scif0_clk),
2704     SH_PFC_PIN_GROUP(scif0_ctrl),
2705     SH_PFC_PIN_GROUP(scif0_data_b),
2706     SH_PFC_PIN_GROUP(scif0_clk_b),
2707     SH_PFC_PIN_GROUP(scif0_ctrl_b),
2708     SH_PFC_PIN_GROUP(scif0_data_c),
2709     SH_PFC_PIN_GROUP(scif0_clk_c),
2710     SH_PFC_PIN_GROUP(scif0_ctrl_c),
2711     SH_PFC_PIN_GROUP(scif0_data_d),
2712     SH_PFC_PIN_GROUP(scif0_clk_d),
2713     SH_PFC_PIN_GROUP(scif0_ctrl_d),
2714     SH_PFC_PIN_GROUP(scif1_data),
2715     SH_PFC_PIN_GROUP(scif1_clk),
2716     SH_PFC_PIN_GROUP(scif1_ctrl),
2717     SH_PFC_PIN_GROUP(scif1_data_b),
2718     SH_PFC_PIN_GROUP(scif1_clk_b),
2719     SH_PFC_PIN_GROUP(scif1_ctrl_b),
2720     SH_PFC_PIN_GROUP(scif1_data_c),
2721     SH_PFC_PIN_GROUP(scif1_clk_c),
2722     SH_PFC_PIN_GROUP(scif1_ctrl_c),
2723     SH_PFC_PIN_GROUP(scif2_data),
2724     SH_PFC_PIN_GROUP(scif2_clk),
2725     SH_PFC_PIN_GROUP(scif2_data_b),
2726     SH_PFC_PIN_GROUP(scif2_clk_b),
2727     SH_PFC_PIN_GROUP(scif2_data_c),
2728     SH_PFC_PIN_GROUP(scif2_clk_c),
2729     SH_PFC_PIN_GROUP(scif2_data_d),
2730     SH_PFC_PIN_GROUP(scif2_clk_d),
2731     SH_PFC_PIN_GROUP(scif2_data_e),
2732     SH_PFC_PIN_GROUP(scif3_data),
2733     SH_PFC_PIN_GROUP(scif3_clk),
2734     SH_PFC_PIN_GROUP(scif3_data_b),
2735     SH_PFC_PIN_GROUP(scif3_data_c),
2736     SH_PFC_PIN_GROUP(scif3_data_d),
2737     SH_PFC_PIN_GROUP(scif3_data_e),
2738     SH_PFC_PIN_GROUP(scif3_clk_e),
2739     SH_PFC_PIN_GROUP(scif4_data),
2740     SH_PFC_PIN_GROUP(scif4_clk),
2741     SH_PFC_PIN_GROUP(scif4_data_b),
2742     SH_PFC_PIN_GROUP(scif4_clk_b),
2743     SH_PFC_PIN_GROUP(scif4_data_c),
2744     SH_PFC_PIN_GROUP(scif4_data_d),
2745     SH_PFC_PIN_GROUP(scif5_data),
2746     SH_PFC_PIN_GROUP(scif5_clk),
2747     SH_PFC_PIN_GROUP(scif5_data_b),
2748     SH_PFC_PIN_GROUP(scif5_clk_b),
2749     SH_PFC_PIN_GROUP(scif5_data_c),
2750     SH_PFC_PIN_GROUP(scif5_clk_c),
2751     SH_PFC_PIN_GROUP(scif5_data_d),
2752     SH_PFC_PIN_GROUP(scif5_clk_d),
2753     SH_PFC_PIN_GROUP(scif_clk),
2754     SH_PFC_PIN_GROUP(scif_clk_b),
2755     SH_PFC_PIN_GROUP(scif_clk_c),
2756     SH_PFC_PIN_GROUP(scif_clk_d),
2757     BUS_DATA_PIN_GROUP(sdhi0_data, 1),
2758     BUS_DATA_PIN_GROUP(sdhi0_data, 4),
2759     SH_PFC_PIN_GROUP(sdhi0_ctrl),
2760     SH_PFC_PIN_GROUP(sdhi0_cd),
2761     SH_PFC_PIN_GROUP(sdhi0_wp),
2762     BUS_DATA_PIN_GROUP(sdhi1_data, 1),
2763     BUS_DATA_PIN_GROUP(sdhi1_data, 4),
2764     SH_PFC_PIN_GROUP(sdhi1_ctrl),
2765     SH_PFC_PIN_GROUP(sdhi1_cd),
2766     SH_PFC_PIN_GROUP(sdhi1_wp),
2767     BUS_DATA_PIN_GROUP(sdhi2_data, 1),
2768     BUS_DATA_PIN_GROUP(sdhi2_data, 4),
2769     SH_PFC_PIN_GROUP(sdhi2_ctrl),
2770     SH_PFC_PIN_GROUP(sdhi2_cd),
2771     SH_PFC_PIN_GROUP(sdhi2_wp),
2772     BUS_DATA_PIN_GROUP(sdhi3_data, 1),
2773     BUS_DATA_PIN_GROUP(sdhi3_data, 4),
2774     SH_PFC_PIN_GROUP(sdhi3_ctrl),
2775     SH_PFC_PIN_GROUP(sdhi3_cd),
2776     SH_PFC_PIN_GROUP(sdhi3_wp),
2777     SH_PFC_PIN_GROUP(usb0),
2778     SH_PFC_PIN_GROUP(usb0_ovc),
2779     SH_PFC_PIN_GROUP(usb1),
2780     SH_PFC_PIN_GROUP(usb1_ovc),
2781     SH_PFC_PIN_GROUP(usb2),
2782     SH_PFC_PIN_GROUP(usb2_ovc),
2783     SH_PFC_PIN_GROUP(vin0_data8),
2784     SH_PFC_PIN_GROUP(vin0_clk),
2785     SH_PFC_PIN_GROUP(vin0_sync),
2786     SH_PFC_PIN_GROUP(vin1_data8),
2787     SH_PFC_PIN_GROUP(vin1_clk),
2788     SH_PFC_PIN_GROUP(vin1_sync),
2789     SH_PFC_PIN_GROUP(vin2_data8),
2790     SH_PFC_PIN_GROUP(vin2_clk),
2791     SH_PFC_PIN_GROUP(vin2_sync),
2792     SH_PFC_PIN_GROUP(vin3_data8),
2793     SH_PFC_PIN_GROUP(vin3_clk),
2794     SH_PFC_PIN_GROUP(vin3_sync),
2795 };
2796
2797 static const char * const du0_groups[] = {
2798     "du0_rgb666",
2799     "du0_rgb888",
2800     "du0_clk_in",
2801     "du0_clk_out_0",
2802     "du0_clk_out_1",
2803     "du0_sync_0",
2804     "du0_sync_1",
2805     "du0_oddf",
2806     "du0_cde",
2807 };
2808
2809 static const char * const du1_groups[] = {
2810     "du1_rgb666",
2811     "du1_rgb888",
2812     "du1_clk_in",
2813     "du1_clk_out",
2814     "du1_sync_0",
2815     "du1_sync_1",
2816     "du1_oddf",
2817     "du1_cde",
2818 };
2819
2820 static const char * const ether_groups[] = {
2821     "ether_rmii",
2822     "ether_link",
2823     "ether_magic",
2824 };
2825
2826 static const char * const hscif0_groups[] = {
2827     "hscif0_data",
2828     "hscif0_data_b",
2829     "hscif0_ctrl",
2830     "hscif0_ctrl_b",
2831     "hscif0_clk",
2832     "hscif0_clk_b",
2833 };
2834
2835 static const char * const hscif1_groups[] = {
2836     "hscif1_data",
2837     "hscif1_data_b",
2838     "hscif1_ctrl",
2839     "hscif1_ctrl_b",
2840     "hscif1_clk",
2841     "hscif1_clk_b",
2842 };
2843
2844 static const char * const hspi0_groups[] = {
2845     "hspi0",
2846 };
2847
2848 static const char * const hspi1_groups[] = {
2849     "hspi1",
2850     "hspi1_b",
2851     "hspi1_c",
2852     "hspi1_d",
2853 };
2854
2855 static const char * const hspi2_groups[] = {
2856     "hspi2",
2857     "hspi2_b",
2858 };
2859
2860 static const char * const i2c1_groups[] = {
2861     "i2c1",
2862     "i2c1_b",
2863     "i2c1_c",
2864     "i2c1_d",
2865 };
2866
2867 static const char * const i2c2_groups[] = {
2868     "i2c2",
2869     "i2c2_b",
2870     "i2c2_c",
2871     "i2c2_d",
2872 };
2873
2874 static const char * const i2c3_groups[] = {
2875     "i2c3",
2876     "i2c3_b",
2877 };
2878
2879 static const char * const intc_groups[] = {
2880     "intc_irq0",
2881     "intc_irq0_b",
2882     "intc_irq1",
2883     "intc_irq1_b",
2884     "intc_irq2",
2885     "intc_irq2_b",
2886     "intc_irq3",
2887     "intc_irq3_b",
2888 };
2889
2890 static const char * const lbsc_groups[] = {
2891     "lbsc_cs0",
2892     "lbsc_cs1",
2893     "lbsc_ex_cs0",
2894     "lbsc_ex_cs1",
2895     "lbsc_ex_cs2",
2896     "lbsc_ex_cs3",
2897     "lbsc_ex_cs4",
2898     "lbsc_ex_cs5",
2899 };
2900
2901 static const char * const mmc0_groups[] = {
2902     "mmc0_data1",
2903     "mmc0_data4",
2904     "mmc0_data8",
2905     "mmc0_ctrl",
2906 };
2907
2908 static const char * const mmc1_groups[] = {
2909     "mmc1_data1",
2910     "mmc1_data4",
2911     "mmc1_data8",
2912     "mmc1_ctrl",
2913 };
2914
2915 static const char * const scif0_groups[] = {
2916     "scif0_data",
2917     "scif0_clk",
2918     "scif0_ctrl",
2919     "scif0_data_b",
2920     "scif0_clk_b",
2921     "scif0_ctrl_b",
2922     "scif0_data_c",
2923     "scif0_clk_c",
2924     "scif0_ctrl_c",
2925     "scif0_data_d",
2926     "scif0_clk_d",
2927     "scif0_ctrl_d",
2928 };
2929
2930 static const char * const scif1_groups[] = {
2931     "scif1_data",
2932     "scif1_clk",
2933     "scif1_ctrl",
2934     "scif1_data_b",
2935     "scif1_clk_b",
2936     "scif1_ctrl_b",
2937     "scif1_data_c",
2938     "scif1_clk_c",
2939     "scif1_ctrl_c",
2940 };
2941
2942 static const char * const scif2_groups[] = {
2943     "scif2_data",
2944     "scif2_clk",
2945     "scif2_data_b",
2946     "scif2_clk_b",
2947     "scif2_data_c",
2948     "scif2_clk_c",
2949     "scif2_data_d",
2950     "scif2_clk_d",
2951     "scif2_data_e",
2952 };
2953
2954 static const char * const scif3_groups[] = {
2955     "scif3_data",
2956     "scif3_clk",
2957     "scif3_data_b",
2958     "scif3_data_c",
2959     "scif3_data_d",
2960     "scif3_data_e",
2961     "scif3_clk_e",
2962 };
2963
2964 static const char * const scif4_groups[] = {
2965     "scif4_data",
2966     "scif4_clk",
2967     "scif4_data_b",
2968     "scif4_clk_b",
2969     "scif4_data_c",
2970     "scif4_data_d",
2971 };
2972
2973 static const char * const scif5_groups[] = {
2974     "scif5_data",
2975     "scif5_clk",
2976     "scif5_data_b",
2977     "scif5_clk_b",
2978     "scif5_data_c",
2979     "scif5_clk_c",
2980     "scif5_data_d",
2981     "scif5_clk_d",
2982 };
2983
2984 static const char * const scif_clk_groups[] = {
2985     "scif_clk",
2986     "scif_clk_b",
2987     "scif_clk_c",
2988     "scif_clk_d",
2989 };
2990
2991 static const char * const sdhi0_groups[] = {
2992     "sdhi0_data1",
2993     "sdhi0_data4",
2994     "sdhi0_ctrl",
2995     "sdhi0_cd",
2996     "sdhi0_wp",
2997 };
2998
2999 static const char * const sdhi1_groups[] = {
3000     "sdhi1_data1",
3001     "sdhi1_data4",
3002     "sdhi1_ctrl",
3003     "sdhi1_cd",
3004     "sdhi1_wp",
3005 };
3006
3007 static const char * const sdhi2_groups[] = {
3008     "sdhi2_data1",
3009     "sdhi2_data4",
3010     "sdhi2_ctrl",
3011     "sdhi2_cd",
3012     "sdhi2_wp",
3013 };
3014
3015 static const char * const sdhi3_groups[] = {
3016     "sdhi3_data1",
3017     "sdhi3_data4",
3018     "sdhi3_ctrl",
3019     "sdhi3_cd",
3020     "sdhi3_wp",
3021 };
3022
3023 static const char * const usb0_groups[] = {
3024     "usb0",
3025     "usb0_ovc",
3026 };
3027
3028 static const char * const usb1_groups[] = {
3029     "usb1",
3030     "usb1_ovc",
3031 };
3032
3033 static const char * const usb2_groups[] = {
3034     "usb2",
3035     "usb2_ovc",
3036 };
3037
3038 static const char * const vin0_groups[] = {
3039     "vin0_data8",
3040     "vin0_clk",
3041     "vin0_sync",
3042 };
3043
3044 static const char * const vin1_groups[] = {
3045     "vin1_data8",
3046     "vin1_clk",
3047     "vin1_sync",
3048 };
3049
3050 static const char * const vin2_groups[] = {
3051     "vin2_data8",
3052     "vin2_clk",
3053     "vin2_sync",
3054 };
3055
3056 static const char * const vin3_groups[] = {
3057     "vin3_data8",
3058     "vin3_clk",
3059     "vin3_sync",
3060 };
3061
3062 static const struct sh_pfc_function pinmux_functions[] = {
3063     SH_PFC_FUNCTION(du0),
3064     SH_PFC_FUNCTION(du1),
3065     SH_PFC_FUNCTION(ether),
3066     SH_PFC_FUNCTION(hscif0),
3067     SH_PFC_FUNCTION(hscif1),
3068     SH_PFC_FUNCTION(hspi0),
3069     SH_PFC_FUNCTION(hspi1),
3070     SH_PFC_FUNCTION(hspi2),
3071     SH_PFC_FUNCTION(i2c1),
3072     SH_PFC_FUNCTION(i2c2),
3073     SH_PFC_FUNCTION(i2c3),
3074     SH_PFC_FUNCTION(intc),
3075     SH_PFC_FUNCTION(lbsc),
3076     SH_PFC_FUNCTION(mmc0),
3077     SH_PFC_FUNCTION(mmc1),
3078     SH_PFC_FUNCTION(scif0),
3079     SH_PFC_FUNCTION(scif1),
3080     SH_PFC_FUNCTION(scif2),
3081     SH_PFC_FUNCTION(scif3),
3082     SH_PFC_FUNCTION(scif4),
3083     SH_PFC_FUNCTION(scif5),
3084     SH_PFC_FUNCTION(scif_clk),
3085     SH_PFC_FUNCTION(sdhi0),
3086     SH_PFC_FUNCTION(sdhi1),
3087     SH_PFC_FUNCTION(sdhi2),
3088     SH_PFC_FUNCTION(sdhi3),
3089     SH_PFC_FUNCTION(usb0),
3090     SH_PFC_FUNCTION(usb1),
3091     SH_PFC_FUNCTION(usb2),
3092     SH_PFC_FUNCTION(vin0),
3093     SH_PFC_FUNCTION(vin1),
3094     SH_PFC_FUNCTION(vin2),
3095     SH_PFC_FUNCTION(vin3),
3096 };
3097
3098 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3099     { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1, GROUP(
3100         GP_0_31_FN, FN_IP3_31_29,
3101         GP_0_30_FN, FN_IP3_26_24,
3102         GP_0_29_FN, FN_IP3_22_21,
3103         GP_0_28_FN, FN_IP3_14_12,
3104         GP_0_27_FN, FN_IP3_11_9,
3105         GP_0_26_FN, FN_IP3_2_0,
3106         GP_0_25_FN, FN_IP2_30_28,
3107         GP_0_24_FN, FN_IP2_21_19,
3108         GP_0_23_FN, FN_IP2_18_16,
3109         GP_0_22_FN, FN_IP0_30_28,
3110         GP_0_21_FN, FN_IP0_5_3,
3111         GP_0_20_FN, FN_IP1_18_15,
3112         GP_0_19_FN, FN_IP1_14_11,
3113         GP_0_18_FN, FN_IP1_10_7,
3114         GP_0_17_FN, FN_IP1_6_4,
3115         GP_0_16_FN, FN_IP1_3_2,
3116         GP_0_15_FN, FN_IP1_1_0,
3117         GP_0_14_FN, FN_IP0_27_26,
3118         GP_0_13_FN, FN_IP0_25,
3119         GP_0_12_FN, FN_IP0_24_23,
3120         GP_0_11_FN, FN_IP0_22_19,
3121         GP_0_10_FN, FN_IP0_18_16,
3122         GP_0_9_FN, FN_IP0_15_14,
3123         GP_0_8_FN, FN_IP0_13_12,
3124         GP_0_7_FN, FN_IP0_11_10,
3125         GP_0_6_FN, FN_IP0_9_8,
3126         GP_0_5_FN, FN_A19,
3127         GP_0_4_FN, FN_A18,
3128         GP_0_3_FN, FN_A17,
3129         GP_0_2_FN, FN_IP0_7_6,
3130         GP_0_1_FN, FN_AVS2,
3131         GP_0_0_FN, FN_AVS1 ))
3132     },
3133     { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1, GROUP(
3134         GP_1_31_FN, FN_IP5_23_21,
3135         GP_1_30_FN, FN_IP5_20_17,
3136         GP_1_29_FN, FN_IP5_16_15,
3137         GP_1_28_FN, FN_IP5_14_13,
3138         GP_1_27_FN, FN_IP5_12_11,
3139         GP_1_26_FN, FN_IP5_10_9,
3140         GP_1_25_FN, FN_IP5_8,
3141         GP_1_24_FN, FN_IP5_7,
3142         GP_1_23_FN, FN_IP5_6,
3143         GP_1_22_FN, FN_IP5_5,
3144         GP_1_21_FN, FN_IP5_4,
3145         GP_1_20_FN, FN_IP5_3,
3146         GP_1_19_FN, FN_IP5_2_0,
3147         GP_1_18_FN, FN_IP4_31_29,
3148         GP_1_17_FN, FN_IP4_28,
3149         GP_1_16_FN, FN_IP4_27,
3150         GP_1_15_FN, FN_IP4_26,
3151         GP_1_14_FN, FN_IP4_25,
3152         GP_1_13_FN, FN_IP4_24,
3153         GP_1_12_FN, FN_IP4_23,
3154         GP_1_11_FN, FN_IP4_22_20,
3155         GP_1_10_FN, FN_IP4_19_17,
3156         GP_1_9_FN, FN_IP4_16,
3157         GP_1_8_FN, FN_IP4_15,
3158         GP_1_7_FN, FN_IP4_14,
3159         GP_1_6_FN, FN_IP4_13,
3160         GP_1_5_FN, FN_IP4_12,
3161         GP_1_4_FN, FN_IP4_11,
3162         GP_1_3_FN, FN_IP4_10_8,
3163         GP_1_2_FN, FN_IP4_7_5,
3164         GP_1_1_FN, FN_IP4_4_2,
3165         GP_1_0_FN, FN_IP4_1_0 ))
3166     },
3167     { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1, GROUP(
3168         GP_2_31_FN, FN_IP10_28_26,
3169         GP_2_30_FN, FN_IP10_25_24,
3170         GP_2_29_FN, FN_IP10_23_21,
3171         GP_2_28_FN, FN_IP10_20_18,
3172         GP_2_27_FN, FN_IP10_17_15,
3173         GP_2_26_FN, FN_IP10_14_12,
3174         GP_2_25_FN, FN_IP10_11_9,
3175         GP_2_24_FN, FN_IP10_8_6,
3176         GP_2_23_FN, FN_IP10_5_3,
3177         GP_2_22_FN, FN_IP10_2_0,
3178         GP_2_21_FN, FN_IP9_29_28,
3179         GP_2_20_FN, FN_IP9_27_26,
3180         GP_2_19_FN, FN_IP9_25_24,
3181         GP_2_18_FN, FN_IP9_23_22,
3182         GP_2_17_FN, FN_IP9_21_19,
3183         GP_2_16_FN, FN_IP9_18_16,
3184         GP_2_15_FN, FN_IP9_15_14,
3185         GP_2_14_FN, FN_IP9_13_12,
3186         GP_2_13_FN, FN_IP9_11_10,
3187         GP_2_12_FN, FN_IP9_9_8,
3188         GP_2_11_FN, FN_IP9_7,
3189         GP_2_10_FN, FN_IP9_6,
3190         GP_2_9_FN, FN_IP9_5,
3191         GP_2_8_FN, FN_IP9_4,
3192         GP_2_7_FN, FN_IP9_3_2,
3193         GP_2_6_FN, FN_IP9_1_0,
3194         GP_2_5_FN, FN_IP8_30_28,
3195         GP_2_4_FN, FN_IP8_27_25,
3196         GP_2_3_FN, FN_IP8_24_23,
3197         GP_2_2_FN, FN_IP8_22_21,
3198         GP_2_1_FN, FN_IP8_20,
3199         GP_2_0_FN, FN_IP5_27_24 ))
3200     },
3201     { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1, GROUP(
3202         GP_3_31_FN, FN_IP6_3_2,
3203         GP_3_30_FN, FN_IP6_1_0,
3204         GP_3_29_FN, FN_IP5_30_29,
3205         GP_3_28_FN, FN_IP5_28,
3206         GP_3_27_FN, FN_IP1_24_23,
3207         GP_3_26_FN, FN_IP1_22_21,
3208         GP_3_25_FN, FN_IP1_20_19,
3209         GP_3_24_FN, FN_IP7_26_25,
3210         GP_3_23_FN, FN_IP7_24_23,
3211         GP_3_22_FN, FN_IP7_22_21,
3212         GP_3_21_FN, FN_IP7_20_19,
3213         GP_3_20_FN, FN_IP7_30_29,
3214         GP_3_19_FN, FN_IP7_28_27,
3215         GP_3_18_FN, FN_IP7_18_17,
3216         GP_3_17_FN, FN_IP7_16_15,
3217         GP_3_16_FN, FN_IP12_17_15,
3218         GP_3_15_FN, FN_IP12_14_12,
3219         GP_3_14_FN, FN_IP12_11_9,
3220         GP_3_13_FN, FN_IP12_8_6,
3221         GP_3_12_FN, FN_IP12_5_3,
3222         GP_3_11_FN, FN_IP12_2_0,
3223         GP_3_10_FN, FN_IP11_29_27,
3224         GP_3_9_FN, FN_IP11_26_24,
3225         GP_3_8_FN, FN_IP11_23_21,
3226         GP_3_7_FN, FN_IP11_20_18,
3227         GP_3_6_FN, FN_IP11_17_15,
3228         GP_3_5_FN, FN_IP11_14_12,
3229         GP_3_4_FN, FN_IP11_11_9,
3230         GP_3_3_FN, FN_IP11_8_6,
3231         GP_3_2_FN, FN_IP11_5_3,
3232         GP_3_1_FN, FN_IP11_2_0,
3233         GP_3_0_FN, FN_IP10_31_29 ))
3234     },
3235     { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1, GROUP(
3236         GP_4_31_FN, FN_IP8_19,
3237         GP_4_30_FN, FN_IP8_18,
3238         GP_4_29_FN, FN_IP8_17_16,
3239         GP_4_28_FN, FN_IP0_2_0,
3240         GP_4_27_FN, FN_USB_PENC1,
3241         GP_4_26_FN, FN_USB_PENC0,
3242         GP_4_25_FN, FN_IP8_15_12,
3243         GP_4_24_FN, FN_IP8_11_8,
3244         GP_4_23_FN, FN_IP8_7_4,
3245         GP_4_22_FN, FN_IP8_3_0,
3246         GP_4_21_FN, FN_IP2_3_0,
3247         GP_4_20_FN, FN_IP1_28_25,
3248         GP_4_19_FN, FN_IP2_15_12,
3249         GP_4_18_FN, FN_IP2_11_8,
3250         GP_4_17_FN, FN_IP2_7_4,
3251         GP_4_16_FN, FN_IP7_14_13,
3252         GP_4_15_FN, FN_IP7_12_10,
3253         GP_4_14_FN, FN_IP7_9_7,
3254         GP_4_13_FN, FN_IP7_6_4,
3255         GP_4_12_FN, FN_IP7_3_2,
3256         GP_4_11_FN, FN_IP7_1_0,
3257         GP_4_10_FN, FN_IP6_30_29,
3258         GP_4_9_FN, FN_IP6_26_25,
3259         GP_4_8_FN, FN_IP6_24_23,
3260         GP_4_7_FN, FN_IP6_22_20,
3261         GP_4_6_FN, FN_IP6_19_18,
3262         GP_4_5_FN, FN_IP6_17_15,
3263         GP_4_4_FN, FN_IP6_14_12,
3264         GP_4_3_FN, FN_IP6_11_9,
3265         GP_4_2_FN, FN_IP6_8,
3266         GP_4_1_FN, FN_IP6_7_6,
3267         GP_4_0_FN, FN_IP6_5_4 ))
3268     },
3269     { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1, GROUP(
3270         GP_5_31_FN, FN_IP3_5,
3271         GP_5_30_FN, FN_IP3_4,
3272         GP_5_29_FN, FN_IP3_3,
3273         GP_5_28_FN, FN_IP2_27,
3274         GP_5_27_FN, FN_IP2_26,
3275         GP_5_26_FN, FN_IP2_25,
3276         GP_5_25_FN, FN_IP2_24,
3277         GP_5_24_FN, FN_IP2_23,
3278         GP_5_23_FN, FN_IP2_22,
3279         GP_5_22_FN, FN_IP3_28,
3280         GP_5_21_FN, FN_IP3_27,
3281         GP_5_20_FN, FN_IP3_23,
3282         GP_5_19_FN, FN_EX_WAIT0,
3283         GP_5_18_FN, FN_WE1,
3284         GP_5_17_FN, FN_WE0,
3285         GP_5_16_FN, FN_RD,
3286         GP_5_15_FN, FN_A16,
3287         GP_5_14_FN, FN_A15,
3288         GP_5_13_FN, FN_A14,
3289         GP_5_12_FN, FN_A13,
3290         GP_5_11_FN, FN_A12,
3291         GP_5_10_FN, FN_A11,
3292         GP_5_9_FN, FN_A10,
3293         GP_5_8_FN, FN_A9,
3294         GP_5_7_FN, FN_A8,
3295         GP_5_6_FN, FN_A7,
3296         GP_5_5_FN, FN_A6,
3297         GP_5_4_FN, FN_A5,
3298         GP_5_3_FN, FN_A4,
3299         GP_5_2_FN, FN_A3,
3300         GP_5_1_FN, FN_A2,
3301         GP_5_0_FN, FN_A1 ))
3302     },
3303     { PINMUX_CFG_REG_VAR("GPSR6", 0xfffc001c, 32,
3304                  GROUP(-23, 1, 1, 1, 1, 1, 1, 1, 1, 1),
3305                  GROUP(
3306         /* GP6_31_9 RESERVED */
3307         GP_6_8_FN, FN_IP3_20,
3308         GP_6_7_FN, FN_IP3_19,
3309         GP_6_6_FN, FN_IP3_18,
3310         GP_6_5_FN, FN_IP3_17,
3311         GP_6_4_FN, FN_IP3_16,
3312         GP_6_3_FN, FN_IP3_15,
3313         GP_6_2_FN, FN_IP3_8,
3314         GP_6_1_FN, FN_IP3_7,
3315         GP_6_0_FN, FN_IP3_6 ))
3316     },
3317
3318     { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
3319                  GROUP(-1, 3, 2, 1, 2, 4, 3, 2, 2, 2, 2, 2, 3, 3),
3320                  GROUP(
3321         /* IP0_31 [1] RESERVED */
3322         /* IP0_30_28 [3] */
3323         FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
3324         FN_HRTS1, FN_RX4_C, 0, 0,
3325         /* IP0_27_26 [2] */
3326         FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B, 0,
3327         /* IP0_25 [1] */
3328         FN_CS0, FN_HSPI_CS2_B,
3329         /* IP0_24_23 [2] */
3330         FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B, 0,
3331         /* IP0_22_19 [4] */
3332         FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
3333         FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
3334         FN_CTS0_B, 0, 0, 0,
3335         0, 0, 0, 0,
3336         /* IP0_18_16 [3] */
3337         FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
3338         FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B, 0,
3339         /* IP0_15_14 [2] */
3340         FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
3341         /* IP0_13_12 [2] */
3342         FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
3343         /* IP0_11_10 [2] */
3344         FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B, 0,
3345         /* IP0_9_8 [2] */
3346         FN_A20, FN_TX5_D, FN_HSPI_TX2_B, 0,
3347         /* IP0_7_6 [2] */
3348         FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
3349         /* IP0_5_3 [3] */
3350         FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
3351         FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
3352         /* IP0_2_0 [3] */
3353         FN_USB_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
3354         FN_SCIF_CLK, FN_TCLK0_C, 0, 0 ))
3355     },
3356     { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
3357                  GROUP(-3, 4, 2, 2, 2, 4, 4, 4, 3, 2, 2),
3358                  GROUP(
3359         /* IP1_31_29 [3] RESERVED */
3360         /* IP1_28_25 [4] */
3361         FN_HTX0, FN_TX1, FN_SDATA, FN_CTS0_C,
3362         FN_SUB_TCK, FN_CC5_STATE2, FN_CC5_STATE10, FN_CC5_STATE18,
3363         FN_CC5_STATE26, FN_CC5_STATE34, 0, 0,
3364         0, 0, 0, 0,
3365         /* IP1_24_23 [2] */
3366         FN_MLB_DAT, FN_PWM4, FN_RX4, 0,
3367         /* IP1_22_21 [2] */
3368         FN_MLB_SIG, FN_PWM3, FN_TX4, 0,
3369         /* IP1_20_19 [2] */
3370         FN_MLB_CLK, FN_PWM2, FN_SCK4, 0,
3371         /* IP1_18_15 [4] */
3372         FN_EX_CS5, FN_SD1_DAT1, FN_MMC0_D1, FN_FD1,
3373         FN_ATAWR0, FN_VI1_R6, FN_HRX1, FN_RX2_E,
3374         FN_RX0_B, FN_SSI_WS9, 0, 0,
3375         0, 0, 0, 0,
3376         /* IP1_14_11 [4] */
3377         FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
3378         FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
3379         FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, 0,
3380         0, 0, 0, 0,
3381         /* IP1_10_7 [4] */
3382         FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD, FN_FRE,
3383         FN_ATACS10, FN_VI1_R4, FN_RX5_B, FN_HSCK1,
3384         FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9, 0,
3385         0, 0, 0, 0,
3386         /* IP1_6_4 [3] */
3387         FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
3388         FN_ATACS00, 0, 0, 0,
3389         /* IP1_3_2 [2] */
3390         FN_EX_CS1, FN_MMC0_D7, FN_FD7, 0,
3391         /* IP1_1_0 [2] */
3392         FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6, FN_FD6 ))
3393     },
3394     { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
3395                  GROUP(-1, 3, 1, 1, 1, 1, 1, 1, 3, 3, 4, 4, 4, 4),
3396                  GROUP(
3397         /* IP2_31 [1] RESERVED */
3398         /* IP2_30_28 [3] */
3399         FN_DU0_DG0, FN_LCDOUT8, FN_DREQ1, FN_SCL2,
3400         FN_AUDATA2, 0, 0, 0,
3401         /* IP2_27 [1] */
3402         FN_DU0_DR7, FN_LCDOUT7,
3403         /* IP2_26 [1] */
3404         FN_DU0_DR6, FN_LCDOUT6,
3405         /* IP2_25 [1] */
3406         FN_DU0_DR5, FN_LCDOUT5,
3407         /* IP2_24 [1] */
3408         FN_DU0_DR4, FN_LCDOUT4,
3409         /* IP2_23 [1] */
3410         FN_DU0_DR3, FN_LCDOUT3,
3411         /* IP2_22 [1] */
3412         FN_DU0_DR2, FN_LCDOUT2,
3413         /* IP2_21_19 [3] */
3414         FN_DU0_DR1, FN_LCDOUT1, FN_DACK0, FN_DRACK0,
3415         FN_GPS_SIGN_B, FN_AUDATA1, FN_RX5_C, 0,
3416         /* IP2_18_16 [3] */
3417         FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0, FN_GPS_CLK_B,
3418         FN_AUDATA0, FN_TX5_C, 0, 0,
3419         /* IP2_15_12 [4] */
3420         FN_HRTS0, FN_RTS1_TANS, FN_MDATA, FN_TX0_C,
3421         FN_SUB_TMS, FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17,
3422         FN_CC5_STATE25, FN_CC5_STATE33, 0, 0,
3423         0, 0, 0, 0,
3424         /* IP2_11_8 [4] */
3425         FN_HCTS0, FN_CTS1, FN_STM, FN_PWM0_D,
3426         FN_RX0_C, FN_SCIF_CLK_C, FN_SUB_TRST, FN_TCLK1_B,
3427         FN_CC5_OSCOUT, 0, 0, 0,
3428         0, 0, 0, 0,
3429         /* IP2_7_4 [4] */
3430         FN_HSCK0, FN_SCK1, FN_MTS, FN_PWM5,
3431         FN_SCK0_C, FN_SSI_SDATA9_B, FN_SUB_TDO, FN_CC5_STATE0,
3432         FN_CC5_STATE8, FN_CC5_STATE16, FN_CC5_STATE24, FN_CC5_STATE32,
3433         0, 0, 0, 0,
3434         /* IP2_3_0 [4] */
3435         FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
3436         FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
3437         FN_CC5_STATE27, FN_CC5_STATE35, 0, 0,
3438         0, 0, 0, 0 ))
3439     },
3440     { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
3441                  GROUP(3, 1, 1, 3, 1, 2, 1, 1, 1, 1, 1, 1,
3442                    3, 3, 1, 1, 1, 1, 1, 1, 3),
3443                  GROUP(
3444         /* IP3_31_29 [3] */
3445         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX, FN_TX2_C,
3446         FN_SCL2_C, FN_REMOCON, 0, 0,
3447         /* IP3_28 [1] */
3448         FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
3449         /* IP3_27 [1] */
3450         FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
3451         /* IP3_26_24 [3] */
3452         FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
3453         FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, 0,
3454         /* IP3_23 [1] */
3455         FN_DU0_DOTCLKOUT0, FN_QCLK,
3456         /* IP3_22_21 [2] */
3457         FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_TX3_D_IRDA_TX_D, FN_SCL3_B,
3458         /* IP3_20 [1] */
3459         FN_DU0_DB7, FN_LCDOUT23,
3460         /* IP3_19 [1] */
3461         FN_DU0_DB6, FN_LCDOUT22,
3462         /* IP3_18 [1] */
3463         FN_DU0_DB5, FN_LCDOUT21,
3464         /* IP3_17 [1] */
3465         FN_DU0_DB4, FN_LCDOUT20,
3466         /* IP3_16 [1] */
3467         FN_DU0_DB3, FN_LCDOUT19,
3468         /* IP3_15 [1] */
3469         FN_DU0_DB2, FN_LCDOUT18,
3470         /* IP3_14_12 [3] */
3471         FN_DU0_DB1, FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1,
3472         FN_GPS_MAG_B, FN_AUDATA5, FN_SCK5_C, 0,
3473         /* IP3_11_9 [3] */
3474         FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1, FN_SCL1,
3475         FN_TCLK1, FN_AUDATA4, 0, 0,
3476         /* IP3_8 [1] */
3477         FN_DU0_DG7, FN_LCDOUT15,
3478         /* IP3_7 [1] */
3479         FN_DU0_DG6, FN_LCDOUT14,
3480         /* IP3_6 [1] */
3481         FN_DU0_DG5, FN_LCDOUT13,
3482         /* IP3_5 [1] */
3483         FN_DU0_DG4, FN_LCDOUT12,
3484         /* IP3_4 [1] */
3485         FN_DU0_DG3, FN_LCDOUT11,
3486         /* IP3_3 [1] */
3487         FN_DU0_DG2, FN_LCDOUT10,
3488         /* IP3_2_0 [3] */
3489         FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
3490         FN_AUDATA3, 0, 0, 0 ))
3491     },
3492     { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
3493                  GROUP(3, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
3494                    1, 1, 1, 3, 3, 3, 2),
3495                  GROUP(
3496         /* IP4_31_29 [3] */
3497         FN_DU1_DB0, FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0,
3498         FN_TX5, FN_SCK0_D, 0, 0,
3499         /* IP4_28 [1] */
3500         FN_DU1_DG7, FN_VI2_R3,
3501         /* IP4_27 [1] */
3502         FN_DU1_DG6, FN_VI2_R2,
3503         /* IP4_26 [1] */
3504         FN_DU1_DG5, FN_VI2_R1,
3505         /* IP4_25 [1] */
3506         FN_DU1_DG4, FN_VI2_R0,
3507         /* IP4_24 [1] */
3508         FN_DU1_DG3, FN_VI2_G7,
3509         /* IP4_23 [1] */
3510         FN_DU1_DG2, FN_VI2_G6,
3511         /* IP4_22_20 [3] */
3512         FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
3513         FN_SCK5, FN_AUDATA7, FN_RX0_D, 0,
3514         /* IP4_19_17 [3] */
3515         FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B, FN_SD3_DAT2,
3516         FN_SCK3_E, FN_AUDATA6, FN_TX0_D, 0,
3517         /* IP4_16 [1] */
3518         FN_DU1_DR7, FN_VI2_G5,
3519         /* IP4_15 [1] */
3520         FN_DU1_DR6, FN_VI2_G4,
3521         /* IP4_14 [1] */
3522         FN_DU1_DR5, FN_VI2_G3,
3523         /* IP4_13 [1] */
3524         FN_DU1_DR4, FN_VI2_G2,
3525         /* IP4_12 [1] */
3526         FN_DU1_DR3, FN_VI2_G1,
3527         /* IP4_11 [1] */
3528         FN_DU1_DR2, FN_VI2_G0,
3529         /* IP4_10_8 [3] */
3530         FN_DU1_DR1, FN_VI2_DATA1_VI2_B1, FN_PWM0, FN_SD3_CMD,
3531         FN_RX3_E_IRDA_RX_E, FN_AUDSYNC, FN_CTS0_D, 0,
3532         /* IP4_7_5 [3] */
3533         FN_DU1_DR0, FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK,
3534         FN_TX3_E_IRDA_TX_E, FN_AUDCK, FN_PWMFSW0_B, 0,
3535         /* IP4_4_2 [3] */
3536         FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
3537         FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, 0,
3538         /* IP4_1_0 [2] */
3539         FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C ))
3540     },
3541     { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
3542                  GROUP(-1, 2, 1, 4, 3, 4, 2, 2, 2, 2, 1, 1,
3543                    1, 1, 1, 1, 3),
3544                  GROUP(
3545         /* IP5_31 [1] RESERVED */
3546         /* IP5_30_29 [2] */
3547         FN_AUDIO_CLKB, FN_USB_OVC2, FN_CAN_DEBUGOUT0, FN_MOUT0,
3548         /* IP5_28 [1] */
3549         FN_AUDIO_CLKA, FN_CAN_TXCLK,
3550         /* IP5_27_24 [4] */
3551         FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B, FN_SD3_WP,
3552         FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD, FN_AUDIO_CLKOUT,
3553         FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D, 0,
3554         0, 0, 0, 0,
3555         /* IP5_23_21 [3] */
3556         FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
3557         FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
3558         /* IP5_20_17 [4] */
3559         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
3560         FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
3561         FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D, 0,
3562         0, 0, 0, 0,
3563         /* IP5_16_15 [2] */
3564         FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC, 0,
3565         /* IP5_14_13 [2] */
3566         FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC, FN_VI3_HSYNC, 0,
3567         /* IP5_12_11 [2] */
3568         FN_DU1_DOTCLKOUT, FN_VI2_FIELD, FN_SDA1_D, 0,
3569         /* IP5_10_9 [2] */
3570         FN_DU1_DOTCLKIN, FN_VI2_CLKENB, FN_HSPI_CS1, FN_SCL1_D,
3571         /* IP5_8 [1] */
3572         FN_DU1_DB7, FN_SDA2_D,
3573         /* IP5_7 [1] */
3574         FN_DU1_DB6, FN_SCL2_D,
3575         /* IP5_6 [1] */
3576         FN_DU1_DB5, FN_VI2_R7,
3577         /* IP5_5 [1] */
3578         FN_DU1_DB4, FN_VI2_R6,
3579         /* IP5_4 [1] */
3580         FN_DU1_DB3, FN_VI2_R5,
3581         /* IP5_3 [1] */
3582         FN_DU1_DB2, FN_VI2_R4,
3583         /* IP5_2_0 [3] */
3584         FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
3585         FN_RX5, FN_RTS0_D_TANS_D, 0, 0 ))
3586     },
3587     { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
3588                  GROUP(-1, 2, -2, 2, 2, 3, 2, 3, 3, 3, 1, 2,
3589                    2, 2, 2),
3590                  GROUP(
3591         /* IP6_31 [1] RESERVED */
3592         /* IP6_30_29 [2] */
3593         FN_SSI_SCK6, FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
3594         /* IP_28_27 [2] RESERVED */
3595         /* IP6_26_25 [2] */
3596         FN_SSI_SDATA5, FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX,
3597         /* IP6_24_23 [2] */
3598         FN_SSI_WS5, FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX,
3599         /* IP6_22_20 [3] */
3600         FN_SSI_SCK5, FN_ADICLK, FN_CAN_DEBUGOUT10, FN_SCK3,
3601         FN_TCLK0_D, 0, 0, 0,
3602         /* IP6_19_18 [2] */
3603         FN_SSI_SDATA4, FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, 0,
3604         /* IP6_17_15 [3] */
3605         FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
3606         FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, 0,
3607         /* IP6_14_12 [3] */
3608         FN_SSI_WS34, FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX,
3609         FN_SSI_WS9_C, 0, 0, 0,
3610         /* IP6_11_9 [3] */
3611         FN_SSI_SCK34, FN_CAN_DEBUGOUT6, FN_CAN0_TX_B, FN_IERX,
3612         FN_SSI_SCK9_C, 0, 0, 0,
3613         /* IP6_8 [1] */
3614         FN_SSI_SDATA2, FN_CAN_DEBUGOUT5,
3615         /* IP6_7_6 [2] */
3616         FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6, 0,
3617         /* IP6_5_4 [2] */
3618         FN_SSI_SDATA0, FN_CAN_DEBUGOUT3, FN_MOUT5, 0,
3619         /* IP6_3_2 [2] */
3620         FN_SSI_WS0129, FN_CAN_DEBUGOUT2, FN_MOUT2, 0,
3621         /* IP6_1_0 [2] */
3622         FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, 0 ))
3623     },
3624     { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
3625                  GROUP(-1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
3626                    3, 2, 2),
3627                  GROUP(
3628         /* IP7_31 [1] RESERVED */
3629         /* IP7_30_29 [2] */
3630         FN_SD0_WP, FN_DACK2, FN_CTS1_B, 0,
3631         /* IP7_28_27 [2] */
3632         FN_SD0_CD, FN_DREQ2, FN_RTS1_B_TANS_B, 0,
3633         /* IP7_26_25 [2] */
3634         FN_SD0_DAT3, FN_ATAWR1, FN_RX2_B, FN_CC5_TDI,
3635         /* IP7_24_23 [2] */
3636         FN_SD0_DAT2, FN_ATARD1, FN_TX2_B, FN_CC5_TCK,
3637         /* IP7_22_21 [2] */
3638         FN_SD0_DAT1, FN_ATAG1, FN_SCK2_B, FN_CC5_TMS,
3639         /* IP7_20_19 [2] */
3640         FN_SD0_DAT0, FN_ATADIR1, FN_RX1_B, FN_CC5_TRST,
3641         /* IP7_18_17 [2] */
3642         FN_SD0_CMD, FN_ATACS11, FN_TX1_B, FN_CC5_TDO,
3643         /* IP7_16_15 [2] */
3644         FN_SD0_CLK, FN_ATACS01, FN_SCK1_B, 0,
3645         /* IP7_14_13 [2] */
3646         FN_SSI_SDATA8, FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C,
3647         /* IP7_12_10 [3] */
3648         FN_SSI_SDATA7, FN_CAN_DEBUGOUT15, FN_IRQ2_B, FN_TCLK1_C,
3649         FN_HSPI_TX1_C, 0, 0, 0,
3650         /* IP7_9_7 [3] */
3651         FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B, FN_SSI_WS9_B,
3652         FN_HSPI_CS1_C, 0, 0, 0,
3653         /* IP7_6_4 [3] */
3654         FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
3655         FN_HSPI_CLK1_C, 0, 0, 0,
3656         /* IP7_3_2 [2] */
3657         FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
3658         /* IP7_1_0 [2] */
3659         FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B ))
3660     },
3661     { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
3662                  GROUP(-1, 3, 3, 2, 2, 1, 1, 1, 2, 4, 4, 4, 4),
3663                  GROUP(
3664         /* IP8_31 [1] RESERVED */
3665         /* IP8_30_28 [3] */
3666         FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B, FN_RTS1_C_TANS_C, FN_RX4_D,
3667         FN_PWMFSW0_C, 0, 0, 0,
3668         /* IP8_27_25 [3] */
3669         FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
3670         FN_MMC1_CMD, FN_HSCK1_B, 0, 0,
3671         /* IP8_24_23 [2] */
3672         FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B, 0,
3673         /* IP8_22_21 [2] */
3674         FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B, FN_MT1_SYNC,
3675         /* IP8_20 [1] */
3676         FN_VI0_CLK, FN_MMC1_CLK,
3677         /* IP8_19 [1] */
3678         FN_FMIN, FN_RDS_DATA,
3679         /* IP8_18 [1] */
3680         FN_BPFCLK, FN_PCMWE,
3681         /* IP8_17_16 [2] */
3682         FN_FMCLK, FN_RDS_CLK, FN_PCMOE, 0,
3683         /* IP8_15_12 [4] */
3684         FN_HSPI_RX0, FN_RX0, FN_CAN_STEP0, FN_AD_NCS,
3685         FN_CC5_STATE7, FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31,
3686         FN_CC5_STATE39, 0, 0, 0,
3687         0, 0, 0, 0,
3688         /* IP8_11_8 [4] */
3689         FN_HSPI_TX0, FN_TX0, FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO,
3690         FN_CC5_STATE6, FN_CC5_STATE14, FN_CC5_STATE22, FN_CC5_STATE30,
3691         FN_CC5_STATE38, 0, 0, 0,
3692         0, 0, 0, 0,
3693         /* IP8_7_4 [4] */
3694         FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1, FN_AD_DI,
3695         FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21, FN_CC5_STATE29,
3696         FN_CC5_STATE37, 0, 0, 0,
3697         0, 0, 0, 0,
3698         /* IP8_3_0 [4] */
3699         FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
3700         FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
3701         FN_CC5_STATE36, 0, 0, 0,
3702         0, 0, 0, 0 ))
3703     },
3704     { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
3705                  GROUP(-2, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 1,
3706                    1, 1, 1, 2, 2),
3707                  GROUP(
3708         /* IP9_31_30 [2] RESERVED */
3709         /* IP9_29_28 [2] */
3710         FN_VI0_G7, FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
3711         /* IP9_27_26 [2] */
3712         FN_VI0_G6, FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8,
3713         /* IP9_25_24 [2] */
3714         FN_VI0_G5, FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7,
3715         /* IP9_23_22 [2] */
3716         FN_VI0_G4, FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6,
3717         /* IP9_21_19 [3] */
3718         FN_VI0_G3, FN_ETH_CRS_DV, FN_MMC1_D7, FN_ARM_TRACEDATA_5,
3719         FN_TS_SDAT0, 0, 0, 0,
3720         /* IP9_18_16 [3] */
3721         FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6, FN_ARM_TRACEDATA_4,
3722         FN_TS_SPSYNC0, 0, 0, 0,
3723         /* IP9_15_14 [2] */
3724         FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1, FN_ARM_TRACEDATA_3,
3725         /* IP9_13_12 [2] */
3726         FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0, FN_ARM_TRACEDATA_2,
3727         /* IP9_11_10 [2] */
3728         FN_VI0_DATA7_VI0_B7, FN_MMC1_D5, FN_ARM_TRACEDATA_1, 0,
3729         /* IP9_9_8 [2] */
3730         FN_VI0_DATA6_VI0_B6, FN_MMC1_D4, FN_ARM_TRACEDATA_0, 0,
3731         /* IP9_7 [1] */
3732         FN_VI0_DATA5_VI0_B5, FN_MMC1_D3,
3733         /* IP9_6 [1] */
3734         FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
3735         /* IP9_5 [1] */
3736         FN_VI0_DATA3_VI0_B3, FN_MMC1_D1,
3737         /* IP9_4 [1] */
3738         FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
3739         /* IP9_3_2 [2] */
3740         FN_VI0_DATA1_VI0_B1, FN_HCTS1_B, FN_MT1_PWM, 0,
3741         /* IP9_1_0 [2] */
3742         FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, 0 ))
3743     },
3744     { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
3745                  GROUP(3, 3, 2, 3, 3, 3, 3, 3, 3, 3, 3),
3746                  GROUP(
3747         /* IP10_31_29 [3] */
3748         FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4, FN_SIM_CLK,
3749         FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3, 0,
3750         /* IP10_28_26 [3] */
3751         FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
3752         FN_PWMFSW0_E, 0, 0, 0,
3753         /* IP10_25_24 [2] */
3754         FN_VI1_CLK, FN_SIM_D, FN_SDA3, 0,
3755         /* IP10_23_21 [3] */
3756         FN_VI0_R7, FN_ETH_MDIO, FN_DACK2_C, FN_HSPI_RX1_B,
3757         FN_SCIF_CLK_D, FN_TRACECTL, FN_MT1_PEN, 0,
3758         /* IP10_20_18 [3] */
3759         FN_VI0_R6, FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B,
3760         FN_TRACECLK, FN_MT1_BEN, FN_PWMFSW0_D, 0,
3761         /* IP10_17_15 [3] */
3762         FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
3763         FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, 0,
3764         /* IP10_14_12 [3] */
3765         FN_VI0_R4, FN_ETH_REFCLK, FN_SD2_CD_B, FN_HSPI_CLK1_B,
3766         FN_ARM_TRACEDATA_14, FN_MT1_CLK, FN_TS_SCK0, 0,
3767         /* IP10_11_9 [3] */
3768         FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B, FN_IRQ3,
3769         FN_ARM_TRACEDATA_13, 0, 0, 0,
3770         /* IP10_8_6 [3] */
3771         FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
3772         FN_ARM_TRACEDATA_12, 0, 0, 0,
3773         /* IP10_5_3 [3] */
3774         FN_VI0_R1, FN_SSI_SDATA8_C, FN_DACK1_B, FN_ARM_TRACEDATA_11,
3775         FN_DACK0_C, FN_DRACK0_C, 0, 0,
3776         /* IP10_2_0 [3] */
3777         FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
3778         FN_ARM_TRACEDATA_10, FN_DREQ0_C, 0, 0 ))
3779     },
3780     { PINMUX_CFG_REG_VAR("IPSR11", 0xfffc004c, 32,
3781                  GROUP(-2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
3782                  GROUP(
3783         /* IP11_31_30 [2] RESERVED */
3784         /* IP11_29_27 [3] */
3785         FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
3786         FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
3787         /* IP11_26_24 [3] */
3788         FN_VI1_G0, FN_VI3_DATA0, 0, FN_TS_SCK1,
3789         FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B,
3790         /* IP11_23_21 [3] */
3791         FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI,
3792         FN_HSPI_RX1_D, 0, 0, 0,
3793         /* IP11_20_18 [3] */
3794         FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
3795         FN_HSPI_TX1_D, 0, 0, 0,
3796         /* IP11_17_15 [3] */
3797         FN_VI1_DATA5_VI1_B5, FN_SD2_CMD, FN_MT0_SYNC, FN_SPA_TCK,
3798         FN_HSPI_CS1_D, FN_ADICHS2_B, 0, 0,
3799         /* IP11_14_12 [3] */
3800         FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
3801         FN_HSPI_CLK1_D, FN_ADICHS1_B, 0, 0,
3802         /* IP11_11_9 [3] */
3803         FN_VI1_DATA3_VI1_B3, FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO,
3804         FN_ADICHS0_B, 0, 0, 0,
3805         /* IP11_8_6 [3] */
3806         FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2, FN_MT0_D, FN_SPVTDI,
3807         FN_ADIDATA_B, 0, 0, 0,
3808         /* IP11_5_3 [3] */
3809         FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK, FN_SPV_TMS,
3810         FN_ADICS_B_SAMP_B, 0, 0, 0,
3811         /* IP11_2_0 [3] */
3812         FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
3813         FN_ADICLK_B, 0, 0, 0 ))
3814     },
3815     { PINMUX_CFG_REG_VAR("IPSR12", 0xfffc0050, 32,
3816                  GROUP(-14, 3, 3, 3, 3, 3, 3),
3817                  GROUP(
3818         /* IP12_31_18 [14] RESERVED */
3819         /* IP12_17_15 [3] */
3820         FN_VI1_G7, FN_VI3_DATA7, FN_GPS_MAG, FN_FCE,
3821         FN_SCK4_B, 0, 0, 0,
3822         /* IP12_14_12 [3] */
3823         FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
3824         FN_RX4_B, FN_SIM_CLK_B, 0, 0,
3825         /* IP12_11_9 [3] */
3826         FN_VI1_G5, FN_VI3_DATA5, FN_GPS_CLK, FN_FSE,
3827         FN_TX4_B, FN_SIM_D_B, 0, 0,
3828         /* IP12_8_6 [3] */
3829         FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
3830         FN_SIM_RST_B, FN_HRX0_B, 0, 0,
3831         /* IP12_5_3 [3] */
3832         FN_VI1_G3, FN_VI3_DATA3, FN_SSI_SCK2, FN_TS_SDAT1,
3833         FN_SCL1_C, FN_HTX0_B, 0, 0,
3834         /* IP12_2_0 [3] */
3835         FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
3836         FN_SCK2, FN_HSCK0_B, 0, 0 ))
3837     },
3838     { PINMUX_CFG_REG_VAR("MOD_SEL", 0xfffc0090, 32,
3839                  GROUP(2, 2, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1,
3840                    1, 1, 1, 1, 2, 1, 2),
3841                  GROUP(
3842         /* SEL_SCIF5 [2] */
3843         FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
3844         /* SEL_SCIF4 [2] */
3845         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
3846         /* SEL_SCIF3 [3] */
3847         FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
3848         FN_SEL_SCIF3_4, 0, 0, 0,
3849         /* SEL_SCIF2 [3] */
3850         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
3851         FN_SEL_SCIF2_4, 0, 0, 0,
3852         /* SEL_SCIF1 [2] */
3853         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
3854         /* SEL_SCIF0 [2] */
3855         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
3856         /* SEL_SSI9 [2] */
3857         FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2, 0,
3858         /* SEL_SSI8 [2] */
3859         FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0,
3860         /* SEL_SSI7 [2] */
3861         FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
3862         /* SEL_VI0 [1] */
3863         FN_SEL_VI0_0, FN_SEL_VI0_1,
3864         /* SEL_SD2 [1] */
3865         FN_SEL_SD2_0, FN_SEL_SD2_1,
3866         /* SEL_INT3 [1] */
3867         FN_SEL_INT3_0, FN_SEL_INT3_1,
3868         /* SEL_INT2 [1] */
3869         FN_SEL_INT2_0, FN_SEL_INT2_1,
3870         /* SEL_INT1 [1] */
3871         FN_SEL_INT1_0, FN_SEL_INT1_1,
3872         /* SEL_INT0 [1] */
3873         FN_SEL_INT0_0, FN_SEL_INT0_1,
3874         /* SEL_IE [1] */
3875         FN_SEL_IE_0, FN_SEL_IE_1,
3876         /* SEL_EXBUS2 [2] */
3877         FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2, 0,
3878         /* SEL_EXBUS1 [1] */
3879         FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
3880         /* SEL_EXBUS0 [2] */
3881         FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2, 0 ))
3882     },
3883     { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xfffc0094, 32,
3884                  GROUP(2, 2, 2, 2, 1, 1, 1, 3, 1, -6,
3885                    2, 1, 1, 2, 1, 2, 2),
3886                  GROUP(
3887         /* SEL_TMU1 [2] */
3888         FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2, 0,
3889         /* SEL_TMU0 [2] */
3890         FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
3891         /* SEL_SCIF [2] */
3892         FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
3893         /* SEL_CANCLK [2] */
3894         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 0,
3895         /* SEL_CAN0 [1] */
3896         FN_SEL_CAN0_0, FN_SEL_CAN0_1,
3897         /* SEL_HSCIF1 [1] */
3898         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
3899         /* SEL_HSCIF0 [1] */
3900         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
3901         /* SEL_PWMFSW [3] */
3902         FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
3903         FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4, 0, 0, 0,
3904         /* SEL_ADI [1] */
3905         FN_SEL_ADI_0, FN_SEL_ADI_1,
3906         /* [6] RESERVED */
3907         /* SEL_GPS [2] */
3908         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
3909         /* SEL_SIM [1] */
3910         FN_SEL_SIM_0, FN_SEL_SIM_1,
3911         /* SEL_HSPI2 [1] */
3912         FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
3913         /* SEL_HSPI1 [2] */
3914         FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
3915         /* SEL_I2C3 [1] */
3916         FN_SEL_I2C3_0, FN_SEL_I2C3_1,
3917         /* SEL_I2C2 [2] */
3918         FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
3919         /* SEL_I2C1 [2] */
3920         FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 ))
3921     },
3922     { },
3923 };
3924
3925 const struct sh_pfc_soc_info r8a7779_pinmux_info = {
3926     .name = "r8a7779_pfc",
3927
3928     .unlock_reg = 0xfffc0000, /* PMMR */
3929
3930     .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3931
3932     .pins = pinmux_pins,
3933     .nr_pins = ARRAY_SIZE(pinmux_pins),
3934     .groups = pinmux_groups,
3935     .nr_groups = ARRAY_SIZE(pinmux_groups),
3936     .functions = pinmux_functions,
3937     .nr_functions = ARRAY_SIZE(pinmux_functions),
3938
3939     .cfg_regs = pinmux_config_regs,
3940
3941     .pinmux_data = pinmux_data,
3942     .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3943 };