Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Pin Function Controller Support
0004  *
0005  * Copyright (C) 2015 Niklas Söderlund
0006  */
0007 #include <linux/kernel.h>
0008 
0009 #include "sh_pfc.h"
0010 
0011 #define CPU_ALL_PORT(fn, pfx, sfx)                  \
0012     PORT_10(0,  fn, pfx, sfx),  PORT_90(0,  fn, pfx, sfx),  \
0013     PORT_10(100, fn, pfx##10, sfx), PORT_10(110, fn, pfx##11, sfx), \
0014     PORT_10(120, fn, pfx##12, sfx), PORT_10(130, fn, pfx##13, sfx), \
0015     PORT_10(140, fn, pfx##14, sfx), PORT_1(150, fn, pfx##150, sfx), \
0016     PORT_1(151, fn, pfx##151, sfx), PORT_1(152, fn, pfx##152, sfx), \
0017     PORT_1(153, fn, pfx##153, sfx), PORT_1(154, fn, pfx##154, sfx), \
0018     PORT_1(155, fn, pfx##155, sfx), PORT_1(156, fn, pfx##156, sfx), \
0019     PORT_1(157, fn, pfx##157, sfx), PORT_1(158, fn, pfx##158, sfx)
0020 
0021 #define CPU_ALL_NOGP(fn)        \
0022     PIN_NOGP(LCD3_B2, "B15", fn),   \
0023     PIN_NOGP(LCD3_B3, "C15", fn),   \
0024     PIN_NOGP(LCD3_B4, "D15", fn),   \
0025     PIN_NOGP(LCD3_B5, "B14", fn),   \
0026     PIN_NOGP(LCD3_B6, "C14", fn),   \
0027     PIN_NOGP(LCD3_B7, "D14", fn),   \
0028     PIN_NOGP(LCD3_G2, "B17", fn),   \
0029     PIN_NOGP(LCD3_G3, "C17", fn),   \
0030     PIN_NOGP(LCD3_G4, "D17", fn),   \
0031     PIN_NOGP(LCD3_G5, "B16", fn),   \
0032     PIN_NOGP(LCD3_G6, "C16", fn),   \
0033     PIN_NOGP(LCD3_G7, "D16", fn)
0034 
0035 enum {
0036     PINMUX_RESERVED = 0,
0037 
0038     PINMUX_DATA_BEGIN,
0039     PORT_ALL(DATA),
0040     PINMUX_DATA_END,
0041 
0042     PINMUX_FUNCTION_BEGIN,
0043     PORT_ALL(FN),
0044 
0045     /* GPSR0 */
0046     FN_LCD3_1_0_PORT18, FN_LCD3_1_0_PORT20, FN_LCD3_1_0_PORT21,
0047     FN_LCD3_1_0_PORT22, FN_LCD3_1_0_PORT23,
0048     FN_JT_SEL, FN_ERR_RST_REQB, FN_REF_CLKO, FN_EXT_CLKI, FN_LCD3_PXCLKB,
0049 
0050     /* GPSR1 */
0051     FN_LCD3_9_8_PORT38, FN_LCD3_9_8_PORT39, FN_LCD3_11_10_PORT40,
0052     FN_LCD3_11_10_PORT41, FN_LCD3_11_10_PORT42, FN_LCD3_11_10_PORT43,
0053     FN_IIC_1_0_PORT46, FN_IIC_1_0_PORT47,
0054     FN_LCD3_R0, FN_LCD3_R1, FN_LCD3_R2, FN_LCD3_R3, FN_LCD3_R4, FN_LCD3_R5,
0055     FN_IIC0_SCL, FN_IIC0_SDA, FN_SD_CKI, FN_SDI0_CKO, FN_SDI0_CKI,
0056     FN_SDI0_CMD, FN_SDI0_DATA0, FN_SDI0_DATA1, FN_SDI0_DATA2,
0057     FN_SDI0_DATA3, FN_SDI0_DATA4, FN_SDI0_DATA5, FN_SDI0_DATA6,
0058     FN_SDI0_DATA7, FN_SDI1_CKO, FN_SDI1_CKI, FN_SDI1_CMD,
0059 
0060     /* GPSR2 */
0061     FN_AB_1_0_PORT71, FN_AB_1_0_PORT72, FN_AB_1_0_PORT73,
0062     FN_AB_1_0_PORT74, FN_AB_1_0_PORT75, FN_AB_1_0_PORT76,
0063     FN_AB_1_0_PORT77, FN_AB_1_0_PORT78, FN_AB_1_0_PORT79,
0064     FN_AB_1_0_PORT80, FN_AB_1_0_PORT81, FN_AB_1_0_PORT82,
0065     FN_AB_1_0_PORT83, FN_AB_1_0_PORT84, FN_AB_3_2_PORT85,
0066     FN_AB_3_2_PORT86, FN_AB_3_2_PORT87, FN_AB_3_2_PORT88,
0067     FN_AB_5_4_PORT89, FN_AB_5_4_PORT90, FN_AB_7_6_PORT91,
0068     FN_AB_7_6_PORT92, FN_AB_1_0_PORT93, FN_AB_1_0_PORT94,
0069     FN_AB_1_0_PORT95,
0070     FN_SDI1_DATA0, FN_SDI1_DATA1, FN_SDI1_DATA2, FN_SDI1_DATA3,
0071     FN_AB_CLK, FN_AB_CSB0, FN_AB_CSB1,
0072 
0073     /* GPSR3 */
0074     FN_AB_13_12_PORT104, FN_AB_13_12_PORT103, FN_AB_11_10_PORT102,
0075     FN_AB_11_10_PORT101, FN_AB_11_10_PORT100, FN_AB_9_8_PORT99,
0076     FN_AB_9_8_PORT98, FN_AB_9_8_PORT97,
0077     FN_USI_1_0_PORT109, FN_USI_1_0_PORT110, FN_USI_1_0_PORT111,
0078     FN_USI_1_0_PORT112, FN_USI_3_2_PORT113, FN_USI_3_2_PORT114,
0079     FN_USI_5_4_PORT115, FN_USI_5_4_PORT116, FN_USI_5_4_PORT117,
0080     FN_USI_5_4_PORT118, FN_USI_7_6_PORT119, FN_USI_9_8_PORT120,
0081     FN_USI_9_8_PORT121,
0082     FN_AB_A20, FN_USI0_CS1, FN_USI0_CS2, FN_USI1_DI,
0083     FN_USI1_DO,
0084     FN_NTSC_CLK, FN_NTSC_DATA0, FN_NTSC_DATA1, FN_NTSC_DATA2,
0085     FN_NTSC_DATA3, FN_NTSC_DATA4,
0086 
0087     /* GPRS4 */
0088     FN_HSI_1_0_PORT143, FN_HSI_1_0_PORT144, FN_HSI_1_0_PORT145,
0089     FN_HSI_1_0_PORT146, FN_HSI_1_0_PORT147, FN_HSI_1_0_PORT148,
0090     FN_HSI_1_0_PORT149, FN_HSI_1_0_PORT150,
0091     FN_UART_1_0_PORT157, FN_UART_1_0_PORT158,
0092     FN_NTSC_DATA5, FN_NTSC_DATA6, FN_NTSC_DATA7, FN_CAM_CLKO,
0093     FN_CAM_CLKI, FN_CAM_VS, FN_CAM_HS, FN_CAM_YUV0,
0094     FN_CAM_YUV1, FN_CAM_YUV2, FN_CAM_YUV3, FN_CAM_YUV4,
0095     FN_CAM_YUV5, FN_CAM_YUV6, FN_CAM_YUV7,
0096     FN_JT_TDO, FN_JT_TDOEN, FN_LOWPWR, FN_USB_VBUS, FN_UART1_RX,
0097     FN_UART1_TX,
0098 
0099     /* CHG_PINSEL_LCD3 */
0100     FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01,
0101     FN_SEL_LCD3_9_8_00, FN_SEL_LCD3_9_8_10,
0102     FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01, FN_SEL_LCD3_11_10_10,
0103 
0104     /* CHG_PINSEL_IIC */
0105     FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01,
0106 
0107     /* CHG_PINSEL_AB */
0108     FN_SEL_AB_1_0_00, FN_SEL_AB_1_0_10, FN_SEL_AB_3_2_00,
0109     FN_SEL_AB_3_2_01, FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11,
0110     FN_SEL_AB_5_4_00, FN_SEL_AB_5_4_01, FN_SEL_AB_5_4_10,
0111     FN_SEL_AB_5_4_11, FN_SEL_AB_7_6_00, FN_SEL_AB_7_6_01,
0112     FN_SEL_AB_7_6_10,
0113     FN_SEL_AB_9_8_00, FN_SEL_AB_9_8_01, FN_SEL_AB_9_8_10,
0114     FN_SEL_AB_11_10_00, FN_SEL_AB_11_10_10,
0115     FN_SEL_AB_13_12_00, FN_SEL_AB_13_12_10,
0116 
0117     /* CHG_PINSEL_USI */
0118     FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01,
0119     FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01,
0120     FN_SEL_USI_5_4_00, FN_SEL_USI_5_4_01,
0121     FN_SEL_USI_7_6_00, FN_SEL_USI_7_6_01,
0122     FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01,
0123 
0124     /* CHG_PINSEL_HSI */
0125     FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01,
0126 
0127     /* CHG_PINSEL_UART */
0128     FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01,
0129 
0130     PINMUX_FUNCTION_END,
0131 
0132     PINMUX_MARK_BEGIN,
0133 
0134     /* GPSR0 */
0135     JT_SEL_MARK, ERR_RST_REQB_MARK, REF_CLKO_MARK, EXT_CLKI_MARK,
0136     LCD3_PXCLKB_MARK, SD_CKI_MARK,
0137 
0138     /* GPSR1 */
0139     LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK, LCD3_R4_MARK,
0140     LCD3_R5_MARK, IIC0_SCL_MARK, IIC0_SDA_MARK, SDI0_CKO_MARK,
0141     SDI0_CKI_MARK, SDI0_CMD_MARK, SDI0_DATA0_MARK, SDI0_DATA1_MARK,
0142     SDI0_DATA2_MARK, SDI0_DATA3_MARK, SDI0_DATA4_MARK, SDI0_DATA5_MARK,
0143     SDI0_DATA6_MARK, SDI0_DATA7_MARK, SDI1_CKO_MARK, SDI1_CKI_MARK,
0144     SDI1_CMD_MARK,
0145 
0146     /* GPSR2 */
0147     SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK,
0148     AB_CLK_MARK, AB_CSB0_MARK, AB_CSB1_MARK,
0149 
0150     /* GPSR3 */
0151     AB_A20_MARK, USI0_CS1_MARK, USI0_CS2_MARK, USI1_DI_MARK,
0152     USI1_DO_MARK,
0153     NTSC_CLK_MARK, NTSC_DATA0_MARK, NTSC_DATA1_MARK, NTSC_DATA2_MARK,
0154     NTSC_DATA3_MARK, NTSC_DATA4_MARK,
0155 
0156     /* GPSR3 */
0157     NTSC_DATA5_MARK, NTSC_DATA6_MARK, NTSC_DATA7_MARK, CAM_CLKO_MARK,
0158     CAM_CLKI_MARK, CAM_VS_MARK, CAM_HS_MARK, CAM_YUV0_MARK,
0159     CAM_YUV1_MARK, CAM_YUV2_MARK, CAM_YUV3_MARK, CAM_YUV4_MARK,
0160     CAM_YUV5_MARK, CAM_YUV6_MARK, CAM_YUV7_MARK,
0161     JT_TDO_MARK, JT_TDOEN_MARK, USB_VBUS_MARK, LOWPWR_MARK,
0162     UART1_RX_MARK, UART1_TX_MARK,
0163 
0164     /* CHG_PINSEL_LCD3 */
0165     LCD3_PXCLK_MARK, LCD3_CLK_I_MARK, LCD3_HS_MARK, LCD3_VS_MARK,
0166     LCD3_DE_MARK, LCD3_R6_MARK, LCD3_R7_MARK, LCD3_G0_MARK, LCD3_G1_MARK,
0167     LCD3_G2_MARK, LCD3_G3_MARK, LCD3_G4_MARK, LCD3_G5_MARK, LCD3_G6_MARK,
0168     LCD3_G7_MARK, LCD3_B0_MARK, LCD3_B1_MARK, LCD3_B2_MARK, LCD3_B3_MARK,
0169     LCD3_B4_MARK, LCD3_B5_MARK, LCD3_B6_MARK, LCD3_B7_MARK,
0170     YUV3_CLK_O_MARK, YUV3_CLK_I_MARK, YUV3_HS_MARK, YUV3_VS_MARK,
0171     YUV3_DE_MARK, YUV3_D0_MARK, YUV3_D1_MARK, YUV3_D2_MARK, YUV3_D3_MARK,
0172     YUV3_D4_MARK, YUV3_D5_MARK, YUV3_D6_MARK, YUV3_D7_MARK, YUV3_D8_MARK,
0173     YUV3_D9_MARK, YUV3_D10_MARK, YUV3_D11_MARK, YUV3_D12_MARK,
0174     YUV3_D13_MARK, YUV3_D14_MARK, YUV3_D15_MARK,
0175     TP33_CLK_MARK, TP33_CTRL_MARK, TP33_DATA0_MARK, TP33_DATA1_MARK,
0176     TP33_DATA2_MARK, TP33_DATA3_MARK, TP33_DATA4_MARK, TP33_DATA5_MARK,
0177     TP33_DATA6_MARK, TP33_DATA7_MARK, TP33_DATA8_MARK, TP33_DATA9_MARK,
0178     TP33_DATA10_MARK, TP33_DATA11_MARK, TP33_DATA12_MARK, TP33_DATA13_MARK,
0179     TP33_DATA14_MARK, TP33_DATA15_MARK,
0180 
0181     /* CHG_PINSEL_IIC */
0182     IIC1_SCL_MARK, IIC1_SDA_MARK, UART3_RX_MARK, UART3_TX_MARK,
0183 
0184     /* CHG_PINSEL_AB */
0185     AB_CSB2_MARK, AB_CSB3_MARK, AB_RDB_MARK, AB_WRB_MARK,
0186     AB_WAIT_MARK, AB_ADV_MARK, AB_AD0_MARK, AB_AD1_MARK,
0187     AB_AD2_MARK, AB_AD3_MARK, AB_AD4_MARK, AB_AD5_MARK,
0188     AB_AD6_MARK, AB_AD7_MARK, AB_AD8_MARK, AB_AD9_MARK,
0189     AB_AD10_MARK, AB_AD11_MARK, AB_AD12_MARK, AB_AD13_MARK,
0190     AB_AD14_MARK, AB_AD15_MARK, AB_A17_MARK, AB_A18_MARK,
0191     AB_A19_MARK, AB_A21_MARK, AB_A22_MARK, AB_A23_MARK,
0192     AB_A24_MARK, AB_A25_MARK, AB_A26_MARK, AB_A27_MARK,
0193     AB_A28_MARK, AB_BEN0_MARK, AB_BEN1_MARK,
0194     DTV_BCLK_A_MARK, DTV_PSYNC_A_MARK, DTV_VALID_A_MARK,
0195     DTV_DATA_A_MARK,
0196     SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK,
0197     SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK,
0198     SDI2_DATA3_MARK,
0199     CF_CSB0_MARK, CF_CSB1_MARK, CF_IORDB_MARK,
0200     CF_IOWRB_MARK, CF_IORDY_MARK, CF_RESET_MARK,
0201     CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
0202     CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
0203     CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK,
0204     CF_D12_MARK, CF_D13_MARK, CF_D14_MARK, CF_D15_MARK,
0205     CF_A00_MARK, CF_A01_MARK, CF_A02_MARK,
0206     CF_INTRQ_MARK, CF_INPACKB_MARK, CF_CDB1_MARK, CF_CDB2_MARK,
0207     USI5_CLK_A_MARK, USI5_DI_A_MARK, USI5_DO_A_MARK,
0208     USI5_CS0_A_MARK, USI5_CS1_A_MARK, USI5_CS2_A_MARK,
0209 
0210     /* CHG_PINSEL_USI */
0211     USI0_CS3_MARK, USI0_CS4_MARK, USI0_CS5_MARK,
0212     USI0_CS6_MARK,
0213     USI2_CLK_MARK, USI2_DI_MARK, USI2_DO_MARK,
0214     USI2_CS0_MARK, USI2_CS1_MARK, USI2_CS2_MARK,
0215     USI3_CLK_MARK, USI3_DI_MARK, USI3_DO_MARK,
0216     USI3_CS0_MARK,
0217     USI4_CLK_MARK, USI4_DI_MARK, USI4_DO_MARK,
0218     USI4_CS0_MARK, USI4_CS1_MARK,
0219     PWM0_MARK, PWM1_MARK,
0220     DTV_BCLK_B_MARK, DTV_PSYNC_B_MARK, DTV_VALID_B_MARK,
0221     DTV_DATA_B_MARK,
0222 
0223     /* CHG_PINSEL_HSI */
0224     USI5_CLK_B_MARK, USI5_DO_B_MARK, USI5_CS0_B_MARK, USI5_CS1_B_MARK,
0225     USI5_CS2_B_MARK, USI5_CS3_B_MARK, USI5_CS4_B_MARK, USI5_DI_B_MARK,
0226 
0227     /* CHG_PINSEL_UART */
0228     UART1_CTSB_MARK, UART1_RTSB_MARK,
0229     UART2_RX_MARK, UART2_TX_MARK,
0230 
0231     PINMUX_MARK_END,
0232 };
0233 
0234 /*
0235  * Pins not associated with a GPIO port.
0236  */
0237 enum {
0238     PORT_ASSIGN_LAST(),
0239     NOGP_ALL(),
0240 };
0241 
0242 /* Expand to a list of sh_pfc_pin entries (named PORT#).
0243  * NOTE: No config are recorded since the driver do not handle pinconf. */
0244 #define __PIN_CFG(pn, pfx, sfx)  SH_PFC_PIN_CFG(pfx, 0)
0245 #define PINMUX_EMEV_GPIO_ALL()    CPU_ALL_PORT(__PIN_CFG, , unused)
0246 
0247 static const struct sh_pfc_pin pinmux_pins[] = {
0248     PINMUX_EMEV_GPIO_ALL(),
0249     PINMUX_NOGP_ALL(),
0250 };
0251 
0252 /* Expand to a list of name_DATA, name_FN marks */
0253 #define __PORT_DATA(pn, pfx, sfx)  PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN)
0254 #define PINMUX_EMEV_DATA_ALL()    CPU_ALL_PORT(__PORT_DATA, , unused)
0255 
0256 static const u16 pinmux_data[] = {
0257     PINMUX_EMEV_DATA_ALL(), /* PINMUX_DATA(PORTN_DATA, PORTN_FN), */
0258 
0259     /* GPSR0 */
0260     /* V9 */
0261     PINMUX_SINGLE(JT_SEL),
0262     /* U9 */
0263     PINMUX_SINGLE(ERR_RST_REQB),
0264     /* V8 */
0265     PINMUX_SINGLE(REF_CLKO),
0266     /* U8 */
0267     PINMUX_SINGLE(EXT_CLKI),
0268     /* B22*/
0269     PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, LCD3_PXCLK, SEL_LCD3_1_0_00),
0270     PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, YUV3_CLK_O, SEL_LCD3_1_0_01),
0271     /* C21 */
0272     PINMUX_SINGLE(LCD3_PXCLKB),
0273     /* A21 */
0274     PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, LCD3_CLK_I, SEL_LCD3_1_0_00),
0275     PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, YUV3_CLK_I, SEL_LCD3_1_0_01),
0276     /* B21 */
0277     PINMUX_IPSR_NOFN(LCD3_1_0_PORT21, LCD3_HS, SEL_LCD3_1_0_00),
0278     PINMUX_IPSR_NOFN(LCD3_1_0_PORT21, YUV3_HS, SEL_LCD3_1_0_01),
0279     /* C20 */
0280     PINMUX_IPSR_NOFN(LCD3_1_0_PORT22, LCD3_VS, SEL_LCD3_1_0_00),
0281     PINMUX_IPSR_NOFN(LCD3_1_0_PORT22, YUV3_VS, SEL_LCD3_1_0_01),
0282     /* D19 */
0283     PINMUX_IPSR_NOFN(LCD3_1_0_PORT23, LCD3_DE, SEL_LCD3_1_0_00),
0284     PINMUX_IPSR_NOFN(LCD3_1_0_PORT23, YUV3_DE, SEL_LCD3_1_0_01),
0285 
0286     /* GPSR1 */
0287     /* A20 */
0288     PINMUX_SINGLE(LCD3_R0),
0289     /* B20 */
0290     PINMUX_SINGLE(LCD3_R1),
0291     /* A19 */
0292     PINMUX_SINGLE(LCD3_R2),
0293     /* B19 */
0294     PINMUX_SINGLE(LCD3_R3),
0295     /* C19 */
0296     PINMUX_SINGLE(LCD3_R4),
0297     /* B18 */
0298     PINMUX_SINGLE(LCD3_R5),
0299     /* C18 */
0300     PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, LCD3_R6, SEL_LCD3_9_8_00),
0301     PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, TP33_CLK, SEL_LCD3_9_8_10),
0302     /* D18 */
0303     PINMUX_IPSR_NOFN(LCD3_9_8_PORT39, LCD3_R7, SEL_LCD3_9_8_00),
0304     PINMUX_IPSR_NOFN(LCD3_9_8_PORT39, TP33_CTRL, SEL_LCD3_9_8_10),
0305     /* A18 */
0306     PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, LCD3_G0, SEL_LCD3_11_10_00),
0307     PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, YUV3_D0, SEL_LCD3_11_10_01),
0308     PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, TP33_DATA0, SEL_LCD3_11_10_10),
0309     /* A17 */
0310     PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, LCD3_G1, SEL_LCD3_11_10_00),
0311     PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, YUV3_D1, SEL_LCD3_11_10_01),
0312     PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, TP33_DATA1, SEL_LCD3_11_10_10),
0313     /* B17 */
0314     PINMUX_DATA(LCD3_G2_MARK, FN_SEL_LCD3_11_10_00),
0315     PINMUX_DATA(YUV3_D2_MARK, FN_SEL_LCD3_11_10_01),
0316     PINMUX_DATA(TP33_DATA2_MARK, FN_SEL_LCD3_11_10_10),
0317     /* C17 */
0318     PINMUX_DATA(LCD3_G3_MARK, FN_SEL_LCD3_11_10_00),
0319     PINMUX_DATA(YUV3_D3_MARK, FN_SEL_LCD3_11_10_01),
0320     PINMUX_DATA(TP33_DATA3_MARK, FN_SEL_LCD3_11_10_10),
0321     /* D17 */
0322     PINMUX_DATA(LCD3_G4_MARK, FN_SEL_LCD3_11_10_00),
0323     PINMUX_DATA(YUV3_D4_MARK, FN_SEL_LCD3_11_10_01),
0324     PINMUX_DATA(TP33_DATA4_MARK, FN_SEL_LCD3_11_10_10),
0325     /* B16 */
0326     PINMUX_DATA(LCD3_G5_MARK, FN_SEL_LCD3_11_10_00),
0327     PINMUX_DATA(YUV3_D5_MARK, FN_SEL_LCD3_11_10_01),
0328     PINMUX_DATA(TP33_DATA5_MARK, FN_SEL_LCD3_11_10_10),
0329     /* C16 */
0330     PINMUX_DATA(LCD3_G6_MARK, FN_SEL_LCD3_11_10_00),
0331     PINMUX_DATA(YUV3_D6_MARK, FN_SEL_LCD3_11_10_01),
0332     PINMUX_DATA(TP33_DATA6_MARK, FN_SEL_LCD3_11_10_10),
0333     /* D16 */
0334     PINMUX_DATA(LCD3_G7_MARK, FN_SEL_LCD3_11_10_00),
0335     PINMUX_DATA(YUV3_D7_MARK, FN_SEL_LCD3_11_10_01),
0336     PINMUX_DATA(TP33_DATA7_MARK, FN_SEL_LCD3_11_10_10),
0337     /* A16 */
0338     PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, LCD3_B0, SEL_LCD3_11_10_00),
0339     PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, YUV3_D8, SEL_LCD3_11_10_01),
0340     PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, TP33_DATA8, SEL_LCD3_11_10_10),
0341     /* A15 */
0342     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B1, SEL_LCD3_11_10_00),
0343     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D9, SEL_LCD3_11_10_01),
0344     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA9, SEL_LCD3_11_10_10),
0345     /* B15 */
0346     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B2, SEL_LCD3_11_10_00),
0347     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D10, SEL_LCD3_11_10_01),
0348     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA10, SEL_LCD3_11_10_10),
0349     /* C15 */
0350     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B3, SEL_LCD3_11_10_00),
0351     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D11, SEL_LCD3_11_10_01),
0352     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA11, SEL_LCD3_11_10_10),
0353     /* D15 */
0354     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B4, SEL_LCD3_11_10_00),
0355     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D12, SEL_LCD3_11_10_01),
0356     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA12, SEL_LCD3_11_10_10),
0357     /* B14 */
0358     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B5, SEL_LCD3_11_10_00),
0359     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D13, SEL_LCD3_11_10_01),
0360     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA13, SEL_LCD3_11_10_10),
0361     /* C14 */
0362     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B6, SEL_LCD3_11_10_00),
0363     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D14, SEL_LCD3_11_10_01),
0364     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA14, SEL_LCD3_11_10_10),
0365     /* D14 */
0366     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B7, SEL_LCD3_11_10_00),
0367     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D15, SEL_LCD3_11_10_01),
0368     PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA15, SEL_LCD3_11_10_10),
0369     /* AA9 */
0370     PINMUX_SINGLE(IIC0_SCL),
0371     /* AA8 */
0372     PINMUX_SINGLE(IIC0_SDA),
0373     /* Y9 */
0374     PINMUX_IPSR_NOFN(IIC_1_0_PORT46, IIC1_SCL, SEL_IIC_1_0_00),
0375     PINMUX_IPSR_NOFN(IIC_1_0_PORT46, UART3_RX, SEL_IIC_1_0_01),
0376     /* Y8 */
0377     PINMUX_IPSR_NOFN(IIC_1_0_PORT47, IIC1_SDA, SEL_IIC_1_0_00),
0378     PINMUX_IPSR_NOFN(IIC_1_0_PORT47, UART3_TX, SEL_IIC_1_0_01),
0379     /* AC19 */
0380     PINMUX_SINGLE(SD_CKI),
0381     /* AB18 */
0382     PINMUX_SINGLE(SDI0_CKO),
0383     /* AC18 */
0384     PINMUX_SINGLE(SDI0_CKI),
0385     /* Y12 */
0386     PINMUX_SINGLE(SDI0_CMD),
0387     /* AA13 */
0388     PINMUX_SINGLE(SDI0_DATA0),
0389     /* Y13 */
0390     PINMUX_SINGLE(SDI0_DATA1),
0391     /* AA14 */
0392     PINMUX_SINGLE(SDI0_DATA2),
0393     /* Y14 */
0394     PINMUX_SINGLE(SDI0_DATA3),
0395     /* AA15 */
0396     PINMUX_SINGLE(SDI0_DATA4),
0397     /* Y15 */
0398     PINMUX_SINGLE(SDI0_DATA5),
0399     /* AA16 */
0400     PINMUX_SINGLE(SDI0_DATA6),
0401     /* Y16 */
0402     PINMUX_SINGLE(SDI0_DATA7),
0403     /* AB22 */
0404     PINMUX_SINGLE(SDI1_CKO),
0405     /* AA23 */
0406     PINMUX_SINGLE(SDI1_CKI),
0407     /* AC21 */
0408     PINMUX_SINGLE(SDI1_CMD),
0409 
0410     /* GPSR2 */
0411     /* AB21 */
0412     PINMUX_SINGLE(SDI1_DATA0),
0413     /* AB20 */
0414     PINMUX_SINGLE(SDI1_DATA1),
0415     /* AB19 */
0416     PINMUX_SINGLE(SDI1_DATA2),
0417     /* AA19 */
0418     PINMUX_SINGLE(SDI1_DATA3),
0419     /* J23 */
0420     PINMUX_SINGLE(AB_CLK),
0421     /* D21 */
0422     PINMUX_SINGLE(AB_CSB0),
0423     /* E21 */
0424     PINMUX_SINGLE(AB_CSB1),
0425     /* F20 */
0426     PINMUX_IPSR_NOFN(AB_1_0_PORT71, AB_CSB2, SEL_AB_1_0_00),
0427     PINMUX_IPSR_NOFN(AB_1_0_PORT71, CF_CSB0, SEL_AB_1_0_10),
0428     /* G20 */
0429     PINMUX_IPSR_NOFN(AB_1_0_PORT72, AB_CSB3, SEL_AB_1_0_00),
0430     PINMUX_IPSR_NOFN(AB_1_0_PORT72, CF_CSB1, SEL_AB_1_0_10),
0431     /* J20 */
0432     PINMUX_IPSR_NOFN(AB_1_0_PORT73, AB_RDB, SEL_AB_1_0_00),
0433     PINMUX_IPSR_NOFN(AB_1_0_PORT73, CF_IORDB, SEL_AB_1_0_10),
0434     /* H20 */
0435     PINMUX_IPSR_NOFN(AB_1_0_PORT74, AB_WRB, SEL_AB_1_0_00),
0436     PINMUX_IPSR_NOFN(AB_1_0_PORT74, CF_IOWRB, SEL_AB_1_0_10),
0437     /* L20 */
0438     PINMUX_IPSR_NOFN(AB_1_0_PORT75, AB_WAIT, SEL_AB_1_0_00),
0439     PINMUX_IPSR_NOFN(AB_1_0_PORT75, CF_IORDY, SEL_AB_1_0_10),
0440     /* K20 */
0441     PINMUX_IPSR_NOFN(AB_1_0_PORT76, AB_ADV, SEL_AB_1_0_00),
0442     PINMUX_IPSR_NOFN(AB_1_0_PORT76, CF_RESET, SEL_AB_1_0_10),
0443     /* C23 */
0444     PINMUX_IPSR_NOFN(AB_1_0_PORT77, AB_AD0, SEL_AB_1_0_00),
0445     PINMUX_IPSR_NOFN(AB_1_0_PORT77, CF_D00, SEL_AB_1_0_10),
0446     /* C22 */
0447     PINMUX_IPSR_NOFN(AB_1_0_PORT78, AB_AD1, SEL_AB_1_0_00),
0448     PINMUX_IPSR_NOFN(AB_1_0_PORT78, CF_D01, SEL_AB_1_0_10),
0449     /* D23 */
0450     PINMUX_IPSR_NOFN(AB_1_0_PORT79, AB_AD2, SEL_AB_1_0_00),
0451     PINMUX_IPSR_NOFN(AB_1_0_PORT79, CF_D02, SEL_AB_1_0_10),
0452     /* D22 */
0453     PINMUX_IPSR_NOFN(AB_1_0_PORT80, AB_AD3, SEL_AB_1_0_00),
0454     PINMUX_IPSR_NOFN(AB_1_0_PORT80, CF_D03, SEL_AB_1_0_10),
0455     /* E23 */
0456     PINMUX_IPSR_NOFN(AB_1_0_PORT81, AB_AD4, SEL_AB_1_0_00),
0457     PINMUX_IPSR_NOFN(AB_1_0_PORT81, CF_D04, SEL_AB_1_0_10),
0458     /* E22 */
0459     PINMUX_IPSR_NOFN(AB_1_0_PORT82, AB_AD5, SEL_AB_1_0_00),
0460     PINMUX_IPSR_NOFN(AB_1_0_PORT82, CF_D05, SEL_AB_1_0_10),
0461     /* F23 */
0462     PINMUX_IPSR_NOFN(AB_1_0_PORT83, AB_AD6, SEL_AB_1_0_00),
0463     PINMUX_IPSR_NOFN(AB_1_0_PORT83, CF_D06, SEL_AB_1_0_10),
0464     /* F22 */
0465     PINMUX_IPSR_NOFN(AB_1_0_PORT84, AB_AD7, SEL_AB_1_0_00),
0466     PINMUX_IPSR_NOFN(AB_1_0_PORT84, CF_D07, SEL_AB_1_0_10),
0467     /* F21 */
0468     PINMUX_IPSR_NOFN(AB_3_2_PORT85, AB_AD8, SEL_AB_3_2_00),
0469     PINMUX_IPSR_NOFN(AB_3_2_PORT85, DTV_BCLK_A, SEL_AB_3_2_01),
0470     PINMUX_IPSR_NOFN(AB_3_2_PORT85, CF_D08, SEL_AB_3_2_10),
0471     PINMUX_IPSR_NOFN(AB_3_2_PORT85, USI5_CLK_A, SEL_AB_3_2_11),
0472     /* G23 */
0473     PINMUX_IPSR_NOFN(AB_3_2_PORT86, AB_AD9, SEL_AB_3_2_00),
0474     PINMUX_IPSR_NOFN(AB_3_2_PORT86, DTV_PSYNC_A, SEL_AB_3_2_01),
0475     PINMUX_IPSR_NOFN(AB_3_2_PORT86, CF_D09, SEL_AB_3_2_10),
0476     PINMUX_IPSR_NOFN(AB_3_2_PORT86, USI5_DI_A, SEL_AB_3_2_11),
0477     /* G22 */
0478     PINMUX_IPSR_NOFN(AB_3_2_PORT87, AB_AD10, SEL_AB_3_2_00),
0479     PINMUX_IPSR_NOFN(AB_3_2_PORT87, DTV_VALID_A, SEL_AB_3_2_01),
0480     PINMUX_IPSR_NOFN(AB_3_2_PORT87, CF_D10, SEL_AB_3_2_10),
0481     PINMUX_IPSR_NOFN(AB_3_2_PORT87, USI5_DO_A, SEL_AB_3_2_11),
0482     /* G21 */
0483     PINMUX_IPSR_NOFN(AB_3_2_PORT88, AB_AD11, SEL_AB_3_2_00),
0484     PINMUX_IPSR_NOFN(AB_3_2_PORT88, DTV_DATA_A, SEL_AB_3_2_01),
0485     PINMUX_IPSR_NOFN(AB_3_2_PORT88, CF_D11, SEL_AB_3_2_10),
0486     PINMUX_IPSR_NOFN(AB_3_2_PORT88, USI5_CS0_A, SEL_AB_3_2_11),
0487     /* H23 */
0488     PINMUX_IPSR_NOFN(AB_5_4_PORT89, AB_AD12, SEL_AB_5_4_00),
0489     PINMUX_IPSR_NOFN(AB_5_4_PORT89, SDI2_DATA0, SEL_AB_5_4_01),
0490     PINMUX_IPSR_NOFN(AB_5_4_PORT89, CF_D12, SEL_AB_5_4_10),
0491     PINMUX_IPSR_NOFN(AB_5_4_PORT89, USI5_CS1_A, SEL_AB_5_4_11),
0492     /* H22 */
0493     PINMUX_IPSR_NOFN(AB_5_4_PORT90, AB_AD13, SEL_AB_5_4_00),
0494     PINMUX_IPSR_NOFN(AB_5_4_PORT90, SDI2_DATA1, SEL_AB_5_4_01),
0495     PINMUX_IPSR_NOFN(AB_5_4_PORT90, CF_D13, SEL_AB_5_4_10),
0496     PINMUX_IPSR_NOFN(AB_5_4_PORT90, USI5_CS2_A, SEL_AB_5_4_11),
0497     /* H21 */
0498     PINMUX_IPSR_NOFN(AB_7_6_PORT91, AB_AD14, SEL_AB_7_6_00),
0499     PINMUX_IPSR_NOFN(AB_7_6_PORT91, SDI2_DATA2, SEL_AB_7_6_01),
0500     PINMUX_IPSR_NOFN(AB_7_6_PORT91, CF_D14, SEL_AB_7_6_10),
0501     /* J22 */
0502     PINMUX_IPSR_NOFN(AB_7_6_PORT92, AB_AD15, SEL_AB_7_6_00),
0503     PINMUX_IPSR_NOFN(AB_7_6_PORT92, SDI2_DATA3, SEL_AB_7_6_01),
0504     PINMUX_IPSR_NOFN(AB_7_6_PORT92, CF_D15, SEL_AB_7_6_10),
0505     /* J21 */
0506     PINMUX_IPSR_NOFN(AB_1_0_PORT93, AB_A17, SEL_AB_1_0_00),
0507     PINMUX_IPSR_NOFN(AB_1_0_PORT93, CF_A00, SEL_AB_1_0_10),
0508     /* K21 */
0509     PINMUX_IPSR_NOFN(AB_1_0_PORT94, AB_A18, SEL_AB_1_0_00),
0510     PINMUX_IPSR_NOFN(AB_1_0_PORT94, CF_A01, SEL_AB_1_0_10),
0511     /* L21 */
0512     PINMUX_IPSR_NOFN(AB_1_0_PORT95, AB_A19, SEL_AB_1_0_00),
0513     PINMUX_IPSR_NOFN(AB_1_0_PORT95, CF_A02, SEL_AB_1_0_10),
0514 
0515     /* GPSR3 */
0516     /* M21 */
0517     PINMUX_SINGLE(AB_A20),
0518     /* N21 */
0519     PINMUX_IPSR_NOFN(AB_9_8_PORT97, AB_A21, SEL_AB_9_8_00),
0520     PINMUX_IPSR_NOFN(AB_9_8_PORT97, SDI2_CKO, SEL_AB_9_8_01),
0521     PINMUX_IPSR_NOFN(AB_9_8_PORT97, CF_INTRQ, SEL_AB_9_8_10),
0522     /* M20 */
0523     PINMUX_IPSR_NOFN(AB_9_8_PORT98, AB_A22, SEL_AB_9_8_00),
0524     PINMUX_IPSR_NOFN(AB_9_8_PORT98, SDI2_CKI, SEL_AB_9_8_01),
0525     /* N20 */
0526     PINMUX_IPSR_NOFN(AB_9_8_PORT99, AB_A23, SEL_AB_9_8_00),
0527     PINMUX_IPSR_NOFN(AB_9_8_PORT99, SDI2_CMD, SEL_AB_9_8_01),
0528     /* L18 */
0529     PINMUX_IPSR_NOFN(AB_11_10_PORT100, AB_A24, SEL_AB_11_10_00),
0530     PINMUX_IPSR_NOFN(AB_11_10_PORT100, CF_INPACKB, SEL_AB_11_10_10),
0531     /* M18 */
0532     PINMUX_IPSR_NOFN(AB_11_10_PORT101, AB_A25, SEL_AB_11_10_00),
0533     PINMUX_IPSR_NOFN(AB_11_10_PORT101, CF_CDB1, SEL_AB_11_10_10),
0534     /* N18 */
0535     PINMUX_IPSR_NOFN(AB_11_10_PORT102, AB_A26, SEL_AB_11_10_00),
0536     PINMUX_IPSR_NOFN(AB_11_10_PORT102, CF_CDB2, SEL_AB_11_10_10),
0537     /* L17 */
0538     PINMUX_IPSR_NOFN(AB_13_12_PORT103, AB_A27, SEL_AB_13_12_00),
0539     PINMUX_IPSR_NOFN(AB_13_12_PORT103, AB_BEN0, SEL_AB_13_12_10),
0540     /* M17 */
0541     PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_A28, SEL_AB_13_12_00),
0542     PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_BEN1, SEL_AB_13_12_10),
0543     /* B8 */
0544     PINMUX_SINGLE(USI0_CS1),
0545     /* B9 */
0546     PINMUX_SINGLE(USI0_CS2),
0547     /* C10 */
0548     PINMUX_SINGLE(USI1_DI),
0549     /* D10 */
0550     PINMUX_SINGLE(USI1_DO),
0551     /* AB5 */
0552     PINMUX_IPSR_NOFN(USI_1_0_PORT109, USI2_CLK, SEL_USI_1_0_00),
0553     PINMUX_IPSR_NOFN(USI_1_0_PORT109, DTV_BCLK_B, SEL_USI_1_0_01),
0554     /* AA6 */
0555     PINMUX_IPSR_NOFN(USI_1_0_PORT110, USI2_DI, SEL_USI_1_0_00),
0556     PINMUX_IPSR_NOFN(USI_1_0_PORT110, DTV_PSYNC_B, SEL_USI_1_0_01),
0557     /* AA5 */
0558     PINMUX_IPSR_NOFN(USI_1_0_PORT111, USI2_DO, SEL_USI_1_0_00),
0559     PINMUX_IPSR_NOFN(USI_1_0_PORT111, DTV_VALID_B, SEL_USI_1_0_01),
0560     /* Y7 */
0561     PINMUX_IPSR_NOFN(USI_1_0_PORT112, USI2_CS0, SEL_USI_1_0_00),
0562     PINMUX_IPSR_NOFN(USI_1_0_PORT112, DTV_DATA_B, SEL_USI_1_0_01),
0563     /* AA7 */
0564     PINMUX_IPSR_NOFN(USI_3_2_PORT113, USI2_CS1, SEL_USI_3_2_00),
0565     PINMUX_IPSR_NOFN(USI_3_2_PORT113, USI4_CS0, SEL_USI_3_2_01),
0566     /* Y6 */
0567     PINMUX_IPSR_NOFN(USI_3_2_PORT114, USI2_CS2, SEL_USI_3_2_00),
0568     PINMUX_IPSR_NOFN(USI_3_2_PORT114, USI4_CS1, SEL_USI_3_2_01),
0569     /* AC5 */
0570     PINMUX_IPSR_NOFN(USI_5_4_PORT115, USI3_CLK, SEL_USI_5_4_00),
0571     PINMUX_IPSR_NOFN(USI_5_4_PORT115, USI0_CS3, SEL_USI_5_4_01),
0572     /* AC4 */
0573     PINMUX_IPSR_NOFN(USI_5_4_PORT116, USI3_DI, SEL_USI_5_4_00),
0574     PINMUX_IPSR_NOFN(USI_5_4_PORT116, USI0_CS4, SEL_USI_5_4_01),
0575     /* AC3 */
0576     PINMUX_IPSR_NOFN(USI_5_4_PORT117, USI3_DO, SEL_USI_5_4_00),
0577     PINMUX_IPSR_NOFN(USI_5_4_PORT117, USI0_CS5, SEL_USI_5_4_01),
0578     /* AB4 */
0579     PINMUX_IPSR_NOFN(USI_5_4_PORT118, USI3_CS0, SEL_USI_5_4_00),
0580     PINMUX_IPSR_NOFN(USI_5_4_PORT118, USI0_CS6, SEL_USI_5_4_01),
0581     /* AB3 */
0582     PINMUX_IPSR_NOFN(USI_7_6_PORT119, USI4_CLK, SEL_USI_7_6_01),
0583     /* AA4 */
0584     PINMUX_IPSR_NOFN(USI_9_8_PORT120, PWM0, SEL_USI_9_8_00),
0585     PINMUX_IPSR_NOFN(USI_9_8_PORT120, USI4_DI, SEL_USI_9_8_01),
0586     /* Y5 */
0587     PINMUX_IPSR_NOFN(USI_9_8_PORT121, PWM1, SEL_USI_9_8_00),
0588     PINMUX_IPSR_NOFN(USI_9_8_PORT121, USI4_DO, SEL_USI_9_8_01),
0589     /* V20 */
0590     PINMUX_SINGLE(NTSC_CLK),
0591     /* P20 */
0592     PINMUX_SINGLE(NTSC_DATA0),
0593     /* P18 */
0594     PINMUX_SINGLE(NTSC_DATA1),
0595     /* R20 */
0596     PINMUX_SINGLE(NTSC_DATA2),
0597     /* R18 */
0598     PINMUX_SINGLE(NTSC_DATA3),
0599     /* T20 */
0600     PINMUX_SINGLE(NTSC_DATA4),
0601 
0602     /* GPRS3 */
0603     /* T18 */
0604     PINMUX_SINGLE(NTSC_DATA5),
0605     /* U20 */
0606     PINMUX_SINGLE(NTSC_DATA6),
0607     /* U18 */
0608     PINMUX_SINGLE(NTSC_DATA7),
0609     /* W23 */
0610     PINMUX_SINGLE(CAM_CLKO),
0611     /* Y23 */
0612     PINMUX_SINGLE(CAM_CLKI),
0613     /* W22 */
0614     PINMUX_SINGLE(CAM_VS),
0615     /* V21 */
0616     PINMUX_SINGLE(CAM_HS),
0617     /* T21 */
0618     PINMUX_SINGLE(CAM_YUV0),
0619     /* T22 */
0620     PINMUX_SINGLE(CAM_YUV1),
0621     /* T23 */
0622     PINMUX_SINGLE(CAM_YUV2),
0623     /* U21 */
0624     PINMUX_SINGLE(CAM_YUV3),
0625     /* U22 */
0626     PINMUX_SINGLE(CAM_YUV4),
0627     /* U23 */
0628     PINMUX_SINGLE(CAM_YUV5),
0629     /* V22 */
0630     PINMUX_SINGLE(CAM_YUV6),
0631     /* V23 */
0632     PINMUX_SINGLE(CAM_YUV7),
0633     /* K22 */
0634     PINMUX_IPSR_NOFN(HSI_1_0_PORT143, USI5_CLK_B, SEL_HSI_1_0_01),
0635     /* K23 */
0636     PINMUX_IPSR_NOFN(HSI_1_0_PORT144, USI5_DO_B, SEL_HSI_1_0_01),
0637     /* L23 */
0638     PINMUX_IPSR_NOFN(HSI_1_0_PORT145, USI5_CS0_B, SEL_HSI_1_0_01),
0639     /* L22 */
0640     PINMUX_IPSR_NOFN(HSI_1_0_PORT146, USI5_CS1_B, SEL_HSI_1_0_01),
0641     /* N22 */
0642     PINMUX_IPSR_NOFN(HSI_1_0_PORT147, USI5_CS2_B, SEL_HSI_1_0_01),
0643     /* N23 */
0644     PINMUX_IPSR_NOFN(HSI_1_0_PORT148, USI5_CS3_B, SEL_HSI_1_0_01),
0645     /* M23 */
0646     PINMUX_IPSR_NOFN(HSI_1_0_PORT149, USI5_CS4_B, SEL_HSI_1_0_01),
0647     /* M22 */
0648     PINMUX_IPSR_NOFN(HSI_1_0_PORT150, USI5_DI_B, SEL_HSI_1_0_01),
0649     /* D13 */
0650     PINMUX_SINGLE(JT_TDO),
0651     /* F13 */
0652     PINMUX_SINGLE(JT_TDOEN),
0653     /* AA12 */
0654     PINMUX_SINGLE(USB_VBUS),
0655     /* A12 */
0656     PINMUX_SINGLE(LOWPWR),
0657     /* Y11 */
0658     PINMUX_SINGLE(UART1_RX),
0659     /* Y10 */
0660     PINMUX_SINGLE(UART1_TX),
0661     /* AA10 */
0662     PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART1_CTSB, SEL_UART_1_0_00),
0663     PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART2_RX, SEL_UART_1_0_01),
0664     /* AB10 */
0665     PINMUX_IPSR_NOFN(UART_1_0_PORT158, UART1_RTSB, SEL_UART_1_0_00),
0666     PINMUX_IPSR_NOFN(UART_1_0_PORT158, UART2_TX, SEL_UART_1_0_01),
0667 };
0668 
0669 
0670 #define EMEV_MUX_PIN(name, pin, mark) \
0671     static const unsigned int name##_pins[] = { pin }; \
0672     static const unsigned int name##_mux[] = { mark##_MARK }
0673 
0674 /* = [ System ] =========== */
0675 EMEV_MUX_PIN(err_rst_reqb, 3, ERR_RST_REQB);
0676 EMEV_MUX_PIN(ref_clko, 4, REF_CLKO);
0677 EMEV_MUX_PIN(ext_clki, 5, EXT_CLKI);
0678 EMEV_MUX_PIN(lowpwr, 154, LOWPWR);
0679 
0680 /* = [ External Memory] === */
0681 static const unsigned int ab_main_pins[] = {
0682     /* AB_RDB, AB_WRB */
0683     73, 74,
0684     /* AB_AD[0:15] */
0685     77, 78, 79, 80,
0686     81, 82, 83, 84,
0687     85, 86, 87, 88,
0688     89, 90, 91, 92,
0689 };
0690 static const unsigned int ab_main_mux[] = {
0691     AB_RDB_MARK, AB_WRB_MARK,
0692     AB_AD0_MARK, AB_AD1_MARK, AB_AD2_MARK, AB_AD3_MARK,
0693     AB_AD4_MARK, AB_AD5_MARK, AB_AD6_MARK, AB_AD7_MARK,
0694     AB_AD8_MARK, AB_AD9_MARK, AB_AD10_MARK, AB_AD11_MARK,
0695     AB_AD12_MARK, AB_AD13_MARK, AB_AD14_MARK, AB_AD15_MARK,
0696 };
0697 
0698 EMEV_MUX_PIN(ab_clk, 68, AB_CLK);
0699 EMEV_MUX_PIN(ab_csb0, 69, AB_CSB0);
0700 EMEV_MUX_PIN(ab_csb1, 70, AB_CSB1);
0701 EMEV_MUX_PIN(ab_csb2, 71, AB_CSB2);
0702 EMEV_MUX_PIN(ab_csb3, 72, AB_CSB3);
0703 EMEV_MUX_PIN(ab_wait, 75, AB_WAIT);
0704 EMEV_MUX_PIN(ab_adv, 76, AB_ADV);
0705 EMEV_MUX_PIN(ab_a17, 93, AB_A17);
0706 EMEV_MUX_PIN(ab_a18, 94, AB_A18);
0707 EMEV_MUX_PIN(ab_a19, 95, AB_A19);
0708 EMEV_MUX_PIN(ab_a20, 96, AB_A20);
0709 EMEV_MUX_PIN(ab_a21, 97, AB_A21);
0710 EMEV_MUX_PIN(ab_a22, 98, AB_A22);
0711 EMEV_MUX_PIN(ab_a23, 99, AB_A23);
0712 EMEV_MUX_PIN(ab_a24, 100, AB_A24);
0713 EMEV_MUX_PIN(ab_a25, 101, AB_A25);
0714 EMEV_MUX_PIN(ab_a26, 102, AB_A26);
0715 EMEV_MUX_PIN(ab_a27, 103, AB_A27);
0716 EMEV_MUX_PIN(ab_a28, 104, AB_A28);
0717 EMEV_MUX_PIN(ab_ben0, 103, AB_BEN0);
0718 EMEV_MUX_PIN(ab_ben1, 104, AB_BEN1);
0719 
0720 /* = [ CAM ] ============== */
0721 EMEV_MUX_PIN(cam_clko, 131, CAM_CLKO);
0722 static const unsigned int cam_pins[] = {
0723     /* CLKI, VS, HS */
0724     132, 133, 134,
0725     /* CAM_YUV[0:7] */
0726     135, 136, 137, 138,
0727     139, 140, 141, 142,
0728 };
0729 static const unsigned int cam_mux[] = {
0730     CAM_CLKI_MARK, CAM_VS_MARK, CAM_HS_MARK,
0731     CAM_YUV0_MARK, CAM_YUV1_MARK, CAM_YUV2_MARK, CAM_YUV3_MARK,
0732     CAM_YUV4_MARK, CAM_YUV5_MARK, CAM_YUV6_MARK, CAM_YUV7_MARK,
0733 };
0734 
0735 /* = [ CF ] -============== */
0736 static const unsigned int cf_ctrl_pins[] = {
0737     /* CSB0, CSB1, IORDB, IOWRB, IORDY, RESET,
0738      * A00, A01, A02, INTRQ, INPACKB, CDB1, CDB2 */
0739     71, 72, 73, 74,
0740     75, 76, 93, 94,
0741     95, 97, 100, 101,
0742     102,
0743 };
0744 static const unsigned int cf_ctrl_mux[] = {
0745     CF_CSB0_MARK, CF_CSB1_MARK, CF_IORDB_MARK, CF_IOWRB_MARK,
0746     CF_IORDY_MARK, CF_RESET_MARK, CF_A00_MARK, CF_A01_MARK,
0747     CF_A02_MARK, CF_INTRQ_MARK, CF_INPACKB_MARK, CF_CDB1_MARK,
0748     CF_CDB2_MARK,
0749 };
0750 
0751 static const unsigned int cf_data_pins[] = {
0752     /* CF_D[0:15] */
0753     77, 78, 79, 80,
0754     81, 82, 83, 84,
0755     85, 86, 87, 88,
0756     89, 90, 91, 92,
0757 };
0758 static const unsigned int cf_data_mux[] = {
0759     CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
0760     CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
0761     CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK,
0762     CF_D12_MARK, CF_D13_MARK, CF_D14_MARK, CF_D15_MARK,
0763 };
0764 
0765 /* = [ DTV ] ============== */
0766 static const unsigned int dtv_a_pins[] = {
0767     /* BCLK, PSYNC, VALID, DATA */
0768     85, 86, 87, 88,
0769 };
0770 static const unsigned int dtv_a_mux[] = {
0771     DTV_BCLK_A_MARK, DTV_PSYNC_A_MARK, DTV_VALID_A_MARK, DTV_DATA_A_MARK,
0772 };
0773 
0774 static const unsigned int dtv_b_pins[] = {
0775     /* BCLK, PSYNC, VALID, DATA */
0776     109, 110, 111, 112,
0777 };
0778 static const unsigned int dtv_b_mux[] = {
0779     DTV_BCLK_B_MARK, DTV_PSYNC_B_MARK, DTV_VALID_B_MARK, DTV_DATA_B_MARK,
0780 };
0781 
0782 /* = [ IIC0 ] ============= */
0783 static const unsigned int iic0_pins[] = {
0784     /* SCL, SDA */
0785     44, 45,
0786 };
0787 static const unsigned int iic0_mux[] = {
0788     IIC0_SCL_MARK, IIC0_SDA_MARK,
0789 };
0790 
0791 /* = [ IIC1 ] ============= */
0792 static const unsigned int iic1_pins[] = {
0793     /* SCL, SDA */
0794     46, 47,
0795 };
0796 static const unsigned int iic1_mux[] = {
0797     IIC1_SCL_MARK, IIC1_SDA_MARK,
0798 };
0799 
0800 /* = [ JTAG ] ============= */
0801 static const unsigned int jtag_pins[] = {
0802     /* SEL, TDO, TDOEN */
0803     2, 151, 152,
0804 };
0805 static const unsigned int jtag_mux[] = {
0806     JT_SEL_MARK, JT_TDO_MARK, JT_TDOEN_MARK,
0807 };
0808 
0809 /* = [ LCD/YUV ] ========== */
0810 EMEV_MUX_PIN(lcd3_pxclk, 18, LCD3_PXCLK);
0811 EMEV_MUX_PIN(lcd3_pxclkb, 19, LCD3_PXCLKB);
0812 EMEV_MUX_PIN(lcd3_clk_i, 20, LCD3_CLK_I);
0813 
0814 static const unsigned int lcd3_sync_pins[] = {
0815     /* HS, VS, DE */
0816     21, 22, 23,
0817 };
0818 static const unsigned int lcd3_sync_mux[] = {
0819     LCD3_HS_MARK, LCD3_VS_MARK, LCD3_DE_MARK,
0820 };
0821 
0822 static const unsigned int lcd3_rgb888_pins[] = {
0823     /* R[0:7], G[0:7], B[0:7] */
0824     32, 33, 34, 35,
0825     36, 37, 38, 39,
0826     40, 41, PIN_LCD3_G2, PIN_LCD3_G3,
0827     PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7,
0828     42, 43, PIN_LCD3_B2, PIN_LCD3_B3,
0829     PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7
0830 };
0831 static const unsigned int lcd3_rgb888_mux[] = {
0832     LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK,
0833     LCD3_R4_MARK, LCD3_R5_MARK, LCD3_R6_MARK, LCD3_R7_MARK,
0834     LCD3_G0_MARK, LCD3_G1_MARK, LCD3_G2_MARK, LCD3_G3_MARK,
0835     LCD3_G4_MARK, LCD3_G5_MARK, LCD3_G6_MARK, LCD3_G7_MARK,
0836     LCD3_B0_MARK, LCD3_B1_MARK, LCD3_B2_MARK, LCD3_B3_MARK,
0837     LCD3_B4_MARK, LCD3_B5_MARK, LCD3_B6_MARK, LCD3_B7_MARK,
0838 };
0839 
0840 EMEV_MUX_PIN(yuv3_clk_i, 20, YUV3_CLK_I);
0841 static const unsigned int yuv3_pins[] = {
0842     /* CLK_O, HS, VS, DE */
0843     18, 21, 22, 23,
0844     /* YUV3_D[0:15] */
0845     40, 41, PIN_LCD3_G2, PIN_LCD3_G3,
0846     PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7,
0847     42, 43, PIN_LCD3_B2, PIN_LCD3_B3,
0848     PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7,
0849 };
0850 static const unsigned int yuv3_mux[] = {
0851     YUV3_CLK_O_MARK, YUV3_HS_MARK, YUV3_VS_MARK, YUV3_DE_MARK,
0852     YUV3_D0_MARK, YUV3_D1_MARK, YUV3_D2_MARK, YUV3_D3_MARK,
0853     YUV3_D4_MARK, YUV3_D5_MARK, YUV3_D6_MARK, YUV3_D7_MARK,
0854     YUV3_D8_MARK, YUV3_D9_MARK, YUV3_D10_MARK, YUV3_D11_MARK,
0855     YUV3_D12_MARK, YUV3_D13_MARK, YUV3_D14_MARK, YUV3_D15_MARK,
0856 };
0857 
0858 /* = [ NTSC ] ============= */
0859 EMEV_MUX_PIN(ntsc_clk, 122, NTSC_CLK);
0860 static const unsigned int ntsc_data_pins[] = {
0861     /* NTSC_DATA[0:7] */
0862     123, 124, 125, 126,
0863     127, 128, 129, 130,
0864 };
0865 static const unsigned int ntsc_data_mux[] = {
0866     NTSC_DATA0_MARK, NTSC_DATA1_MARK, NTSC_DATA2_MARK, NTSC_DATA3_MARK,
0867     NTSC_DATA4_MARK, NTSC_DATA5_MARK, NTSC_DATA6_MARK, NTSC_DATA7_MARK,
0868 };
0869 
0870 /* = [ PWM0 ] ============= */
0871 EMEV_MUX_PIN(pwm0, 120, PWM0);
0872 
0873 /* = [ PWM1 ] ============= */
0874 EMEV_MUX_PIN(pwm1, 121, PWM1);
0875 
0876 /* = [ SD ] =============== */
0877 EMEV_MUX_PIN(sd_cki, 48, SD_CKI);
0878 
0879 /* = [ SDIO0 ] ============ */
0880 static const unsigned int sdi0_ctrl_pins[] = {
0881     /* CKO, CKI, CMD */
0882     50, 51, 52,
0883 };
0884 static const unsigned int sdi0_ctrl_mux[] = {
0885     SDI0_CKO_MARK, SDI0_CKI_MARK, SDI0_CMD_MARK,
0886 };
0887 
0888 static const unsigned int sdi0_data_pins[] = {
0889     /* SDI0_DATA[0:7] */
0890     53, 54, 55, 56,
0891     57, 58, 59, 60
0892 };
0893 static const unsigned int sdi0_data_mux[] = {
0894     SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
0895     SDI0_DATA4_MARK, SDI0_DATA5_MARK, SDI0_DATA6_MARK, SDI0_DATA7_MARK,
0896 };
0897 
0898 /* = [ SDIO1 ] ============ */
0899 static const unsigned int sdi1_ctrl_pins[] = {
0900     /* CKO, CKI, CMD */
0901     61, 62, 63,
0902 };
0903 static const unsigned int sdi1_ctrl_mux[] = {
0904     SDI1_CKO_MARK, SDI1_CKI_MARK, SDI1_CMD_MARK,
0905 };
0906 
0907 static const unsigned int sdi1_data_pins[] = {
0908     /* SDI1_DATA[0:3] */
0909     64, 65, 66, 67,
0910 };
0911 static const unsigned int sdi1_data_mux[] = {
0912     SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK,
0913 };
0914 
0915 /* = [ SDIO2 ] ============ */
0916 static const unsigned int sdi2_ctrl_pins[] = {
0917     /* CKO, CKI, CMD */
0918     97, 98, 99,
0919 };
0920 static const unsigned int sdi2_ctrl_mux[] = {
0921     SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK,
0922 };
0923 
0924 static const unsigned int sdi2_data_pins[] = {
0925     /* SDI2_DATA[0:3] */
0926     89, 90, 91, 92,
0927 };
0928 static const unsigned int sdi2_data_mux[] = {
0929     SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK, SDI2_DATA3_MARK,
0930 };
0931 
0932 /* = [ TP33 ] ============= */
0933 static const unsigned int tp33_pins[] = {
0934     /* CLK, CTRL */
0935     38, 39,
0936     /* TP33_DATA[0:15] */
0937     40, 41, PIN_LCD3_G2, PIN_LCD3_G3,
0938     PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7,
0939     42, 43, PIN_LCD3_B2, PIN_LCD3_B3,
0940     PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7,
0941 };
0942 static const unsigned int tp33_mux[] = {
0943     TP33_CLK_MARK, TP33_CTRL_MARK,
0944     TP33_DATA0_MARK, TP33_DATA1_MARK, TP33_DATA2_MARK, TP33_DATA3_MARK,
0945     TP33_DATA4_MARK, TP33_DATA5_MARK, TP33_DATA6_MARK, TP33_DATA7_MARK,
0946     TP33_DATA8_MARK, TP33_DATA9_MARK, TP33_DATA10_MARK, TP33_DATA11_MARK,
0947     TP33_DATA12_MARK, TP33_DATA13_MARK, TP33_DATA14_MARK, TP33_DATA15_MARK,
0948 };
0949 
0950 /* = [ UART1 ] ============ */
0951 static const unsigned int uart1_data_pins[] = {
0952     /* RX, TX */
0953     155, 156,
0954 };
0955 static const unsigned int uart1_data_mux[] = {
0956     UART1_RX_MARK, UART1_TX_MARK,
0957 };
0958 
0959 static const unsigned int uart1_ctrl_pins[] = {
0960     /* CTSB, RTSB */
0961     157, 158,
0962 };
0963 static const unsigned int uart1_ctrl_mux[] = {
0964     UART1_CTSB_MARK, UART1_RTSB_MARK,
0965 };
0966 
0967 /* = [ UART2 ] ============ */
0968 static const unsigned int uart2_data_pins[] = {
0969     /* RX, TX */
0970     157, 158,
0971 };
0972 static const unsigned int uart2_data_mux[] = {
0973     UART2_RX_MARK, UART2_TX_MARK,
0974 };
0975 
0976 /* = [ UART3 ] ============ */
0977 static const unsigned int uart3_data_pins[] = {
0978     /* RX, TX */
0979     46, 47,
0980 };
0981 static const unsigned int uart3_data_mux[] = {
0982     UART3_RX_MARK, UART3_TX_MARK,
0983 };
0984 
0985 /* = [ USB ] ============== */
0986 EMEV_MUX_PIN(usb_vbus, 153, USB_VBUS);
0987 
0988 /* = [ USI0 ] ============== */
0989 EMEV_MUX_PIN(usi0_cs1, 105, USI0_CS1);
0990 EMEV_MUX_PIN(usi0_cs2, 106, USI0_CS2);
0991 EMEV_MUX_PIN(usi0_cs3, 115, USI0_CS3);
0992 EMEV_MUX_PIN(usi0_cs4, 116, USI0_CS4);
0993 EMEV_MUX_PIN(usi0_cs5, 117, USI0_CS5);
0994 EMEV_MUX_PIN(usi0_cs6, 118, USI0_CS6);
0995 
0996 /* = [ USI1 ] ============== */
0997 static const unsigned int usi1_pins[] = {
0998     /* DI, DO*/
0999     107, 108,
1000 };
1001 static const unsigned int usi1_mux[] = {
1002     USI1_DI_MARK, USI1_DO_MARK,
1003 };
1004 
1005 /* = [ USI2 ] ============== */
1006 static const unsigned int usi2_pins[] = {
1007     /* CLK, DI, DO*/
1008     109, 110, 111,
1009 };
1010 static const unsigned int usi2_mux[] = {
1011     USI2_CLK_MARK, USI2_DI_MARK, USI2_DO_MARK,
1012 };
1013 EMEV_MUX_PIN(usi2_cs0, 112, USI2_CS0);
1014 EMEV_MUX_PIN(usi2_cs1, 113, USI2_CS1);
1015 EMEV_MUX_PIN(usi2_cs2, 114, USI2_CS2);
1016 
1017 /* = [ USI3 ] ============== */
1018 static const unsigned int usi3_pins[] = {
1019     /* CLK, DI, DO*/
1020     115, 116, 117,
1021 };
1022 static const unsigned int usi3_mux[] = {
1023     USI3_CLK_MARK, USI3_DI_MARK, USI3_DO_MARK,
1024 };
1025 EMEV_MUX_PIN(usi3_cs0, 118, USI3_CS0);
1026 
1027 /* = [ USI4 ] ============== */
1028 static const unsigned int usi4_pins[] = {
1029     /* CLK, DI, DO*/
1030     119, 120, 121,
1031 };
1032 static const unsigned int usi4_mux[] = {
1033     USI4_CLK_MARK, USI4_DI_MARK, USI4_DO_MARK,
1034 };
1035 EMEV_MUX_PIN(usi4_cs0, 113, USI4_CS0);
1036 EMEV_MUX_PIN(usi4_cs1, 114, USI4_CS1);
1037 
1038 /* = [ USI5 ] ============== */
1039 static const unsigned int usi5_a_pins[] = {
1040     /* CLK, DI, DO*/
1041     85, 86, 87,
1042 };
1043 static const unsigned int usi5_a_mux[] = {
1044     USI5_CLK_A_MARK, USI5_DI_A_MARK, USI5_DO_A_MARK,
1045 };
1046 EMEV_MUX_PIN(usi5_cs0_a, 88, USI5_CS0_A);
1047 EMEV_MUX_PIN(usi5_cs1_a, 89, USI5_CS1_A);
1048 EMEV_MUX_PIN(usi5_cs2_a, 90, USI5_CS2_A);
1049 
1050 static const unsigned int usi5_b_pins[] = {
1051     /* CLK, DI, DO*/
1052     143, 144, 150,
1053 };
1054 static const unsigned int usi5_b_mux[] = {
1055     USI5_CLK_B_MARK, USI5_DI_B_MARK, USI5_DO_B_MARK,
1056 };
1057 EMEV_MUX_PIN(usi5_cs0_b, 145, USI5_CS0_B);
1058 EMEV_MUX_PIN(usi5_cs1_b, 146, USI5_CS1_B);
1059 EMEV_MUX_PIN(usi5_cs2_b, 147, USI5_CS2_B);
1060 EMEV_MUX_PIN(usi5_cs3_b, 148, USI5_CS3_B);
1061 EMEV_MUX_PIN(usi5_cs4_b, 149, USI5_CS4_B);
1062 
1063 static const struct sh_pfc_pin_group pinmux_groups[] = {
1064     SH_PFC_PIN_GROUP(err_rst_reqb),
1065     SH_PFC_PIN_GROUP(ref_clko),
1066     SH_PFC_PIN_GROUP(ext_clki),
1067     SH_PFC_PIN_GROUP(lowpwr),
1068 
1069     SH_PFC_PIN_GROUP(ab_main),
1070     SH_PFC_PIN_GROUP(ab_clk),
1071     SH_PFC_PIN_GROUP(ab_csb0),
1072     SH_PFC_PIN_GROUP(ab_csb1),
1073     SH_PFC_PIN_GROUP(ab_csb2),
1074     SH_PFC_PIN_GROUP(ab_csb3),
1075     SH_PFC_PIN_GROUP(ab_wait),
1076     SH_PFC_PIN_GROUP(ab_adv),
1077     SH_PFC_PIN_GROUP(ab_a17),
1078     SH_PFC_PIN_GROUP(ab_a18),
1079     SH_PFC_PIN_GROUP(ab_a19),
1080     SH_PFC_PIN_GROUP(ab_a20),
1081     SH_PFC_PIN_GROUP(ab_a21),
1082     SH_PFC_PIN_GROUP(ab_a22),
1083     SH_PFC_PIN_GROUP(ab_a23),
1084     SH_PFC_PIN_GROUP(ab_a24),
1085     SH_PFC_PIN_GROUP(ab_a25),
1086     SH_PFC_PIN_GROUP(ab_a26),
1087     SH_PFC_PIN_GROUP(ab_a27),
1088     SH_PFC_PIN_GROUP(ab_a28),
1089     SH_PFC_PIN_GROUP(ab_ben0),
1090     SH_PFC_PIN_GROUP(ab_ben1),
1091 
1092     SH_PFC_PIN_GROUP(cam_clko),
1093     SH_PFC_PIN_GROUP(cam),
1094 
1095     SH_PFC_PIN_GROUP(cf_ctrl),
1096     BUS_DATA_PIN_GROUP(cf_data, 8),
1097     BUS_DATA_PIN_GROUP(cf_data, 16),
1098 
1099     SH_PFC_PIN_GROUP(dtv_a),
1100     SH_PFC_PIN_GROUP(dtv_b),
1101 
1102     SH_PFC_PIN_GROUP(iic0),
1103 
1104     SH_PFC_PIN_GROUP(iic1),
1105 
1106     SH_PFC_PIN_GROUP(jtag),
1107 
1108     SH_PFC_PIN_GROUP(lcd3_pxclk),
1109     SH_PFC_PIN_GROUP(lcd3_pxclkb),
1110     SH_PFC_PIN_GROUP(lcd3_clk_i),
1111     SH_PFC_PIN_GROUP(lcd3_sync),
1112     SH_PFC_PIN_GROUP(lcd3_rgb888),
1113     SH_PFC_PIN_GROUP(yuv3_clk_i),
1114     SH_PFC_PIN_GROUP(yuv3),
1115 
1116     SH_PFC_PIN_GROUP(ntsc_clk),
1117     SH_PFC_PIN_GROUP(ntsc_data),
1118 
1119     SH_PFC_PIN_GROUP(pwm0),
1120 
1121     SH_PFC_PIN_GROUP(pwm1),
1122 
1123     SH_PFC_PIN_GROUP(sd_cki),
1124 
1125     SH_PFC_PIN_GROUP(sdi0_ctrl),
1126     BUS_DATA_PIN_GROUP(sdi0_data, 1),
1127     BUS_DATA_PIN_GROUP(sdi0_data, 4),
1128     BUS_DATA_PIN_GROUP(sdi0_data, 8),
1129 
1130     SH_PFC_PIN_GROUP(sdi1_ctrl),
1131     BUS_DATA_PIN_GROUP(sdi1_data, 1),
1132     BUS_DATA_PIN_GROUP(sdi1_data, 4),
1133 
1134     SH_PFC_PIN_GROUP(sdi2_ctrl),
1135     BUS_DATA_PIN_GROUP(sdi2_data, 1),
1136     BUS_DATA_PIN_GROUP(sdi2_data, 4),
1137 
1138     SH_PFC_PIN_GROUP(tp33),
1139 
1140     SH_PFC_PIN_GROUP(uart1_data),
1141     SH_PFC_PIN_GROUP(uart1_ctrl),
1142 
1143     SH_PFC_PIN_GROUP(uart2_data),
1144 
1145     SH_PFC_PIN_GROUP(uart3_data),
1146 
1147     SH_PFC_PIN_GROUP(usb_vbus),
1148 
1149     SH_PFC_PIN_GROUP(usi0_cs1),
1150     SH_PFC_PIN_GROUP(usi0_cs2),
1151     SH_PFC_PIN_GROUP(usi0_cs3),
1152     SH_PFC_PIN_GROUP(usi0_cs4),
1153     SH_PFC_PIN_GROUP(usi0_cs5),
1154     SH_PFC_PIN_GROUP(usi0_cs6),
1155 
1156     SH_PFC_PIN_GROUP(usi1),
1157 
1158     SH_PFC_PIN_GROUP(usi2),
1159     SH_PFC_PIN_GROUP(usi2_cs0),
1160     SH_PFC_PIN_GROUP(usi2_cs1),
1161     SH_PFC_PIN_GROUP(usi2_cs2),
1162 
1163     SH_PFC_PIN_GROUP(usi3),
1164     SH_PFC_PIN_GROUP(usi3_cs0),
1165 
1166     SH_PFC_PIN_GROUP(usi4),
1167     SH_PFC_PIN_GROUP(usi4_cs0),
1168     SH_PFC_PIN_GROUP(usi4_cs1),
1169 
1170     SH_PFC_PIN_GROUP(usi5_a),
1171     SH_PFC_PIN_GROUP(usi5_cs0_a),
1172     SH_PFC_PIN_GROUP(usi5_cs1_a),
1173     SH_PFC_PIN_GROUP(usi5_cs2_a),
1174     SH_PFC_PIN_GROUP(usi5_b),
1175     SH_PFC_PIN_GROUP(usi5_cs0_b),
1176     SH_PFC_PIN_GROUP(usi5_cs1_b),
1177     SH_PFC_PIN_GROUP(usi5_cs2_b),
1178     SH_PFC_PIN_GROUP(usi5_cs3_b),
1179     SH_PFC_PIN_GROUP(usi5_cs4_b),
1180 };
1181 
1182 static const char * const ab_groups[] = {
1183     "ab_main",
1184     "ab_clk",
1185     "ab_csb0",
1186     "ab_csb1",
1187     "ab_csb2",
1188     "ab_csb3",
1189     "ab_wait",
1190     "ab_adv",
1191     "ab_a17",
1192     "ab_a18",
1193     "ab_a19",
1194     "ab_a20",
1195     "ab_a21",
1196     "ab_a22",
1197     "ab_a23",
1198     "ab_a24",
1199     "ab_a25",
1200     "ab_a26",
1201     "ab_a27",
1202     "ab_a28",
1203     "ab_ben0",
1204     "ab_ben1",
1205 };
1206 
1207 static const char * const cam_groups[] = {
1208     "cam_clko",
1209     "cam",
1210 };
1211 
1212 static const char * const cf_groups[] = {
1213     "cf_ctrl",
1214     "cf_data8",
1215     "cf_data16",
1216 };
1217 
1218 static const char * const dtv_groups[] = {
1219     "dtv_a",
1220     "dtv_b",
1221 };
1222 
1223 static const char * const err_rst_reqb_groups[] = {
1224     "err_rst_reqb",
1225 };
1226 
1227 static const char * const ext_clki_groups[] = {
1228     "ext_clki",
1229 };
1230 
1231 static const char * const iic0_groups[] = {
1232     "iic0",
1233 };
1234 
1235 static const char * const iic1_groups[] = {
1236     "iic1",
1237 };
1238 
1239 static const char * const jtag_groups[] = {
1240     "jtag",
1241 };
1242 
1243 static const char * const lcd_groups[] = {
1244     "lcd3_pxclk",
1245     "lcd3_pxclkb",
1246     "lcd3_clk_i",
1247     "lcd3_sync",
1248     "lcd3_rgb888",
1249     "yuv3_clk_i",
1250     "yuv3",
1251 };
1252 
1253 static const char * const lowpwr_groups[] = {
1254     "lowpwr",
1255 };
1256 
1257 static const char * const ntsc_groups[] = {
1258     "ntsc_clk",
1259     "ntsc_data",
1260 };
1261 
1262 static const char * const pwm0_groups[] = {
1263     "pwm0",
1264 };
1265 
1266 static const char * const pwm1_groups[] = {
1267     "pwm1",
1268 };
1269 
1270 static const char * const ref_clko_groups[] = {
1271     "ref_clko",
1272 };
1273 
1274 static const char * const sd_groups[] = {
1275     "sd_cki",
1276 };
1277 
1278 static const char * const sdi0_groups[] = {
1279     "sdi0_ctrl",
1280     "sdi0_data1",
1281     "sdi0_data4",
1282     "sdi0_data8",
1283 };
1284 
1285 static const char * const sdi1_groups[] = {
1286     "sdi1_ctrl",
1287     "sdi1_data1",
1288     "sdi1_data4",
1289 };
1290 
1291 static const char * const sdi2_groups[] = {
1292     "sdi2_ctrl",
1293     "sdi2_data1",
1294     "sdi2_data4",
1295 };
1296 
1297 static const char * const tp33_groups[] = {
1298     "tp33",
1299 };
1300 
1301 static const char * const uart1_groups[] = {
1302     "uart1_data",
1303     "uart1_ctrl",
1304 };
1305 
1306 static const char * const uart2_groups[] = {
1307     "uart2_data",
1308 };
1309 
1310 static const char * const uart3_groups[] = {
1311     "uart3_data",
1312 };
1313 
1314 static const char * const usb_groups[] = {
1315     "usb_vbus",
1316 };
1317 
1318 static const char * const usi0_groups[] = {
1319     "usi0_cs1",
1320     "usi0_cs2",
1321     "usi0_cs3",
1322     "usi0_cs4",
1323     "usi0_cs5",
1324     "usi0_cs6",
1325 };
1326 
1327 static const char * const usi1_groups[] = {
1328     "usi1",
1329 };
1330 
1331 static const char * const usi2_groups[] = {
1332     "usi2",
1333     "usi2_cs0",
1334     "usi2_cs1",
1335     "usi2_cs2",
1336 };
1337 
1338 static const char * const usi3_groups[] = {
1339     "usi3",
1340     "usi3_cs0",
1341 };
1342 
1343 static const char * const usi4_groups[] = {
1344     "usi4",
1345     "usi4_cs0",
1346     "usi4_cs1",
1347 };
1348 
1349 static const char * const usi5_groups[] = {
1350     "usi5_a",
1351     "usi5_cs0_a",
1352     "usi5_cs1_a",
1353     "usi5_cs2_a",
1354     "usi5_b",
1355     "usi5_cs0_b",
1356     "usi5_cs1_b",
1357     "usi5_cs2_b",
1358     "usi5_cs3_b",
1359     "usi5_cs4_b",
1360 };
1361 
1362 static const struct sh_pfc_function pinmux_functions[] = {
1363     SH_PFC_FUNCTION(ab),
1364     SH_PFC_FUNCTION(cam),
1365     SH_PFC_FUNCTION(cf),
1366     SH_PFC_FUNCTION(dtv),
1367     SH_PFC_FUNCTION(err_rst_reqb),
1368     SH_PFC_FUNCTION(ext_clki),
1369     SH_PFC_FUNCTION(iic0),
1370     SH_PFC_FUNCTION(iic1),
1371     SH_PFC_FUNCTION(jtag),
1372     SH_PFC_FUNCTION(lcd),
1373     SH_PFC_FUNCTION(lowpwr),
1374     SH_PFC_FUNCTION(ntsc),
1375     SH_PFC_FUNCTION(pwm0),
1376     SH_PFC_FUNCTION(pwm1),
1377     SH_PFC_FUNCTION(ref_clko),
1378     SH_PFC_FUNCTION(sd),
1379     SH_PFC_FUNCTION(sdi0),
1380     SH_PFC_FUNCTION(sdi1),
1381     SH_PFC_FUNCTION(sdi2),
1382     SH_PFC_FUNCTION(tp33),
1383     SH_PFC_FUNCTION(uart1),
1384     SH_PFC_FUNCTION(uart2),
1385     SH_PFC_FUNCTION(uart3),
1386     SH_PFC_FUNCTION(usb),
1387     SH_PFC_FUNCTION(usi0),
1388     SH_PFC_FUNCTION(usi1),
1389     SH_PFC_FUNCTION(usi2),
1390     SH_PFC_FUNCTION(usi3),
1391     SH_PFC_FUNCTION(usi4),
1392     SH_PFC_FUNCTION(usi5),
1393 };
1394 
1395 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1396     { PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1, GROUP(
1397         0, PORT31_FN,               /* PIN: J18  */
1398         0, PORT30_FN,               /* PIN: H18  */
1399         0, PORT29_FN,               /* PIN: G18  */
1400         0, PORT28_FN,               /* PIN: F18  */
1401         0, PORT27_FN,               /* PIN: F17  */
1402         0, PORT26_FN,               /* PIN: F16  */
1403         0, PORT25_FN,               /* PIN: E20  */
1404         0, PORT24_FN,               /* PIN: D20  */
1405         FN_LCD3_1_0_PORT23, PORT23_FN,      /* PIN: D19  */
1406         FN_LCD3_1_0_PORT22, PORT22_FN,      /* PIN: C20  */
1407         FN_LCD3_1_0_PORT21, PORT21_FN,      /* PIN: B21  */
1408         FN_LCD3_1_0_PORT20, PORT20_FN,      /* PIN: A21  */
1409         FN_LCD3_PXCLKB, PORT19_FN,      /* PIN: C21  */
1410         FN_LCD3_1_0_PORT18, PORT18_FN,      /* PIN: B22  */
1411         0, PORT17_FN,               /* PIN: W20  */
1412         0, PORT16_FN,               /* PIN: W21  */
1413         0, PORT15_FN,               /* PIN: Y19  */
1414         0, PORT14_FN,               /* PIN: Y20  */
1415         0, PORT13_FN,               /* PIN: Y21  */
1416         0, PORT12_FN,               /* PIN: AA20 */
1417         0, PORT11_FN,               /* PIN: AA21 */
1418         0, PORT10_FN,               /* PIN: AA22 */
1419         0, PORT9_FN,                /* PIN: V15  */
1420         0, PORT8_FN,                /* PIN: V16  */
1421         0, PORT7_FN,                /* PIN: V17  */
1422         0, PORT6_FN,                /* PIN: V18  */
1423         FN_EXT_CLKI, PORT5_FN,          /* PIN: U8   */
1424         FN_REF_CLKO, PORT4_FN,          /* PIN: V8   */
1425         FN_ERR_RST_REQB, PORT3_FN,      /* PIN: U9   */
1426         FN_JT_SEL, PORT2_FN,            /* PIN: V9   */
1427         0, PORT1_FN,                /* PIN: U10  */
1428         0, PORT0_FN,                /* PIN: V10  */
1429         ))
1430     },
1431     { PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1, GROUP(
1432         FN_SDI1_CMD, PORT63_FN,         /* PIN: AC21 */
1433         FN_SDI1_CKI, PORT62_FN,         /* PIN: AA23 */
1434         FN_SDI1_CKO, PORT61_FN,         /* PIN: AB22 */
1435         FN_SDI0_DATA7, PORT60_FN,       /* PIN: Y16  */
1436         FN_SDI0_DATA6, PORT59_FN,       /* PIN: AA16 */
1437         FN_SDI0_DATA5, PORT58_FN,       /* PIN: Y15  */
1438         FN_SDI0_DATA4, PORT57_FN,       /* PIN: AA15 */
1439         FN_SDI0_DATA3, PORT56_FN,       /* PIN: Y14  */
1440         FN_SDI0_DATA2, PORT55_FN,       /* PIN: AA14 */
1441         FN_SDI0_DATA1, PORT54_FN,       /* PIN: Y13  */
1442         FN_SDI0_DATA0, PORT53_FN,       /* PIN: AA13 */
1443         FN_SDI0_CMD, PORT52_FN,         /* PIN: Y12  */
1444         FN_SDI0_CKI, PORT51_FN,         /* PIN: AC18 */
1445         FN_SDI0_CKO, PORT50_FN,         /* PIN: AB18 */
1446         0, PORT49_FN,               /* PIN: AB16 */
1447         FN_SD_CKI, PORT48_FN,           /* PIN: AC19 */
1448         FN_IIC_1_0_PORT47, PORT47_FN,       /* PIN: Y8   */
1449         FN_IIC_1_0_PORT46, PORT46_FN,       /* PIN: Y9   */
1450         FN_IIC0_SDA, PORT45_FN,         /* PIN: AA8  */
1451         FN_IIC0_SCL, PORT44_FN,         /* PIN: AA9  */
1452         FN_LCD3_11_10_PORT43, PORT43_FN,    /* PIN: A15  */
1453         FN_LCD3_11_10_PORT42, PORT42_FN,    /* PIN: A16  */
1454         FN_LCD3_11_10_PORT41, PORT41_FN,    /* PIN: A17  */
1455         FN_LCD3_11_10_PORT40, PORT40_FN,    /* PIN: A18  */
1456         FN_LCD3_9_8_PORT39, PORT39_FN,      /* PIN: D18  */
1457         FN_LCD3_9_8_PORT38, PORT38_FN,      /* PIN: C18  */
1458         FN_LCD3_R5, PORT37_FN,          /* PIN: B18  */
1459         FN_LCD3_R4, PORT36_FN,          /* PIN: C19  */
1460         FN_LCD3_R3, PORT35_FN,          /* PIN: B19  */
1461         FN_LCD3_R2, PORT34_FN,          /* PIN: A19  */
1462         FN_LCD3_R1, PORT33_FN,          /* PIN: B20  */
1463         FN_LCD3_R0, PORT32_FN,          /* PIN: A20  */
1464         ))
1465     },
1466     { PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1, GROUP(
1467         FN_AB_1_0_PORT95, PORT95_FN,        /* PIN: L21  */
1468         FN_AB_1_0_PORT94, PORT94_FN,        /* PIN: K21  */
1469         FN_AB_1_0_PORT93, PORT93_FN,        /* PIN: J21  */
1470         FN_AB_7_6_PORT92, PORT92_FN,        /* PIN: J22  */
1471         FN_AB_7_6_PORT91, PORT91_FN,        /* PIN: H21  */
1472         FN_AB_5_4_PORT90, PORT90_FN,        /* PIN: H22  */
1473         FN_AB_5_4_PORT89, PORT89_FN,        /* PIN: H23  */
1474         FN_AB_3_2_PORT88, PORT88_FN,        /* PIN: G21  */
1475         FN_AB_3_2_PORT87, PORT87_FN,        /* PIN: G22  */
1476         FN_AB_3_2_PORT86, PORT86_FN,        /* PIN: G23  */
1477         FN_AB_3_2_PORT85, PORT85_FN,        /* PIN: F21  */
1478         FN_AB_1_0_PORT84, PORT84_FN,        /* PIN: F22  */
1479         FN_AB_1_0_PORT83, PORT83_FN,        /* PIN: F23  */
1480         FN_AB_1_0_PORT82, PORT82_FN,        /* PIN: E22  */
1481         FN_AB_1_0_PORT81, PORT81_FN,        /* PIN: E23  */
1482         FN_AB_1_0_PORT80, PORT80_FN,        /* PIN: D22  */
1483         FN_AB_1_0_PORT79, PORT79_FN,        /* PIN: D23  */
1484         FN_AB_1_0_PORT78, PORT78_FN,        /* PIN: C22  */
1485         FN_AB_1_0_PORT77, PORT77_FN,        /* PIN: C23  */
1486         FN_AB_1_0_PORT76, PORT76_FN,        /* PIN: K20  */
1487         FN_AB_1_0_PORT75, PORT75_FN,        /* PIN: L20  */
1488         FN_AB_1_0_PORT74, PORT74_FN,        /* PIN: H20  */
1489         FN_AB_1_0_PORT73, PORT73_FN,        /* PIN: J20  */
1490         FN_AB_1_0_PORT72, PORT72_FN,        /* PIN: G20  */
1491         FN_AB_1_0_PORT71, PORT71_FN,        /* PIN: F20  */
1492         FN_AB_CSB1, PORT70_FN,          /* PIN: E21  */
1493         FN_AB_CSB0, PORT69_FN,          /* PIN: D21  */
1494         FN_AB_CLK, PORT68_FN,           /* PIN: J23  */
1495         FN_SDI1_DATA3, PORT67_FN,       /* PIN: AA19 */
1496         FN_SDI1_DATA2, PORT66_FN,       /* PIN: AB19 */
1497         FN_SDI1_DATA1, PORT65_FN,       /* PIN: AB20 */
1498         FN_SDI1_DATA0, PORT64_FN,       /* PIN: AB21 */
1499         ))
1500     },
1501     { PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1, GROUP(
1502         FN_NTSC_DATA4, PORT127_FN,      /* PIN: T20  */
1503         FN_NTSC_DATA3, PORT126_FN,      /* PIN: R18  */
1504         FN_NTSC_DATA2, PORT125_FN,      /* PIN: R20  */
1505         FN_NTSC_DATA1, PORT124_FN,      /* PIN: P18  */
1506         FN_NTSC_DATA0, PORT123_FN,      /* PIN: P20  */
1507         FN_NTSC_CLK, PORT122_FN,        /* PIN: V20  */
1508         FN_USI_9_8_PORT121, PORT121_FN,     /* PIN: Y5   */
1509         FN_USI_9_8_PORT120, PORT120_FN,     /* PIN: AA4  */
1510         FN_USI_7_6_PORT119, PORT119_FN,     /* PIN: AB3  */
1511         FN_USI_5_4_PORT118, PORT118_FN,     /* PIN: AB4  */
1512         FN_USI_5_4_PORT117, PORT117_FN,     /* PIN: AC3  */
1513         FN_USI_5_4_PORT116, PORT116_FN,     /* PIN: AC4  */
1514         FN_USI_5_4_PORT115, PORT115_FN,     /* PIN: AC5  */
1515         FN_USI_3_2_PORT114, PORT114_FN,     /* PIN: Y6   */
1516         FN_USI_3_2_PORT113, PORT113_FN,     /* PIN: AA7  */
1517         FN_USI_1_0_PORT112, PORT112_FN,     /* PIN: Y7   */
1518         FN_USI_1_0_PORT111, PORT111_FN,     /* PIN: AA5  */
1519         FN_USI_1_0_PORT110, PORT110_FN,     /* PIN: AA6  */
1520         FN_USI_1_0_PORT109, PORT109_FN,     /* PIN: AB5  */
1521         FN_USI1_DO, PORT108_FN,         /* PIN: D10  */
1522         FN_USI1_DI, PORT107_FN,         /* PIN: C10  */
1523         FN_USI0_CS2, PORT106_FN,        /* PIN: B9   */
1524         FN_USI0_CS1, PORT105_FN,        /* PIN: B8   */
1525         FN_AB_13_12_PORT104, PORT104_FN,    /* PIN: M17  */
1526         FN_AB_13_12_PORT103, PORT103_FN,    /* PIN: L17  */
1527         FN_AB_11_10_PORT102, PORT102_FN,    /* PIN: N18  */
1528         FN_AB_11_10_PORT101, PORT101_FN,    /* PIN: M18  */
1529         FN_AB_11_10_PORT100, PORT100_FN,    /* PIN: L18  */
1530         FN_AB_9_8_PORT99, PORT99_FN,        /* PIN: N20  */
1531         FN_AB_9_8_PORT98, PORT98_FN,        /* PIN: M20  */
1532         FN_AB_9_8_PORT97, PORT97_FN,        /* PIN: N21  */
1533         FN_AB_A20, PORT96_FN,           /* PIN: M21  */
1534         ))
1535     },
1536     { PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1, GROUP(
1537         0, 0,
1538         FN_UART_1_0_PORT158, PORT158_FN,    /* PIN: AB10 */
1539         FN_UART_1_0_PORT157, PORT157_FN,    /* PIN: AA10 */
1540         FN_UART1_TX, PORT156_FN,        /* PIN: Y10  */
1541         FN_UART1_RX, PORT155_FN,        /* PIN: Y11  */
1542         FN_LOWPWR, PORT154_FN,          /* PIN: A12  */
1543         FN_USB_VBUS, PORT153_FN,        /* PIN: AA12 */
1544         FN_JT_TDOEN, PORT152_FN,        /* PIN: F13  */
1545         FN_JT_TDO, PORT151_FN,          /* PIN: D13  */
1546         FN_HSI_1_0_PORT150, PORT150_FN,     /* PIN: M22  */
1547         FN_HSI_1_0_PORT149, PORT149_FN,     /* PIN: M23  */
1548         FN_HSI_1_0_PORT148, PORT148_FN,     /* PIN: N23  */
1549         FN_HSI_1_0_PORT147, PORT147_FN,     /* PIN: N22  */
1550         FN_HSI_1_0_PORT146, PORT146_FN,     /* PIN: L22  */
1551         FN_HSI_1_0_PORT145, PORT145_FN,     /* PIN: L23  */
1552         FN_HSI_1_0_PORT144, PORT144_FN,     /* PIN: K23  */
1553         FN_HSI_1_0_PORT143, PORT143_FN,     /* PIN: K22  */
1554         FN_CAM_YUV7, PORT142_FN,        /* PIN: V23  */
1555         FN_CAM_YUV6, PORT141_FN,        /* PIN: V22  */
1556         FN_CAM_YUV5, PORT140_FN,        /* PIN: U23  */
1557         FN_CAM_YUV4, PORT139_FN,        /* PIN: U22  */
1558         FN_CAM_YUV3, PORT138_FN,        /* PIN: U21  */
1559         FN_CAM_YUV2, PORT137_FN,        /* PIN: T23  */
1560         FN_CAM_YUV1, PORT136_FN,        /* PIN: T22  */
1561         FN_CAM_YUV0, PORT135_FN,        /* PIN: T21  */
1562         FN_CAM_HS, PORT134_FN,          /* PIN: V21  */
1563         FN_CAM_VS, PORT133_FN,          /* PIN: W22  */
1564         FN_CAM_CLKI, PORT132_FN,        /* PIN: Y23  */
1565         FN_CAM_CLKO, PORT131_FN,        /* PIN: W23  */
1566         FN_NTSC_DATA7, PORT130_FN,      /* PIN: U18  */
1567         FN_NTSC_DATA6, PORT129_FN,      /* PIN: U20  */
1568         FN_NTSC_DATA5, PORT128_FN,      /* PIN: T18  */
1569         ))
1570     },
1571     { PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,
1572                  GROUP(-20, 2, 2, -6, 2),
1573                  GROUP(
1574         /* 31 - 12 RESERVED */
1575         /* 11 - 10 */
1576         FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01,
1577         FN_SEL_LCD3_11_10_10, 0,
1578         /* 9 - 8 */
1579         FN_SEL_LCD3_9_8_00, 0, FN_SEL_LCD3_9_8_10, 0,
1580         /* 7 - 2 RESERVED */
1581         /* 1 - 0 */
1582         FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01, 0, 0,
1583         ))
1584     },
1585     { PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,
1586                  GROUP(-30, 2),
1587                  GROUP(
1588         /* 31 - 2 RESERVED */
1589         /* 1 - 0 */
1590         FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01, 0, 0,
1591         ))
1592     },
1593     { PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,
1594                  GROUP(-30, 2),
1595                  GROUP(
1596         /* 31 - 2 RESERVED */
1597         /* 1 - 0 */
1598         FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01, 0, 0,
1599         ))
1600     },
1601     { PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,
1602                  GROUP(-18, 2, 2, 2, 2, 2, 2, 2),
1603                  GROUP(
1604         /* 31 - 14 RESERVED */
1605         /* 13 - 12 */
1606         FN_SEL_AB_13_12_00, 0, FN_SEL_AB_13_12_10, 0,
1607         /* 11 - 10 */
1608         FN_SEL_AB_11_10_00, 0, FN_SEL_AB_11_10_10, 0,
1609         /* 9 - 8 */
1610         FN_SEL_AB_9_8_00, FN_SEL_AB_9_8_01, FN_SEL_AB_9_8_10, 0,
1611         /* 7 - 6 */
1612         FN_SEL_AB_7_6_00, FN_SEL_AB_7_6_01, FN_SEL_AB_7_6_10, 0,
1613         /* 5 - 4 */
1614         FN_SEL_AB_5_4_00, FN_SEL_AB_5_4_01,
1615         FN_SEL_AB_5_4_10, FN_SEL_AB_5_4_11,
1616         /* 3 - 2 */
1617         FN_SEL_AB_3_2_00, FN_SEL_AB_3_2_01,
1618         FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11,
1619         /* 1 - 0 */
1620         FN_SEL_AB_1_0_00, 0, FN_SEL_AB_1_0_10, 0,
1621         ))
1622     },
1623     { PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,
1624                  GROUP(-22, 2, 2, 2, 2, 2),
1625                  GROUP(
1626         /* 31 - 10 RESERVED */
1627         /* 9 - 8 */
1628         FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01, 0, 0,
1629         /* 7 - 6 */
1630         FN_SEL_USI_7_6_00, FN_SEL_USI_7_6_01, 0, 0,
1631         /* 5 - 4 */
1632         FN_SEL_USI_5_4_00, FN_SEL_USI_5_4_01, 0, 0,
1633         /* 3 - 2 */
1634         FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01, 0, 0,
1635         /* 1 - 0 */
1636         FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01, 0, 0,
1637         ))
1638     },
1639     { PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,
1640                  GROUP(-30, 2),
1641                  GROUP(
1642         /* 31 - 2 RESERVED */
1643         /* 1 - 0 */
1644         FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0,
1645         ))
1646     },
1647     { },
1648 };
1649 
1650 const struct sh_pfc_soc_info emev2_pinmux_info = {
1651     .name       = "emev2_pfc",
1652 
1653     .function   = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1654 
1655     .pins       = pinmux_pins,
1656     .nr_pins    = ARRAY_SIZE(pinmux_pins),
1657     .groups     = pinmux_groups,
1658     .nr_groups  = ARRAY_SIZE(pinmux_groups),
1659     .functions  = pinmux_functions,
1660     .nr_functions   = ARRAY_SIZE(pinmux_functions),
1661 
1662     .cfg_regs   = pinmux_config_regs,
1663 
1664     .pinmux_data    = pinmux_data,
1665     .pinmux_data_size = ARRAY_SIZE(pinmux_data),
1666 };
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!