pinctrl/renesas/gpio.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * SuperH Pin Function Controller GPIO driver.
0004  *
0005  * Copyright (C) 2008 Magnus Damm
0006  * Copyright (C) 2009 - 2012 Paul Mundt
0007  */
0008
0009 #include <linux/device.h>
0010 #include <linux/gpio/driver.h>
0011 #include <linux/module.h>
0012 #include <linux/pinctrl/consumer.h>
0013 #include <linux/slab.h>
0014 #include <linux/spinlock.h>
0015
0016 #include "core.h"
0017
0018 struct sh_pfc_gpio_data_reg {
0019     const struct pinmux_data_reg *info;
0020     u32 shadow;
0021 };
0022
0023 struct sh_pfc_gpio_pin {
0024     u8 dbit;
0025     u8 dreg;
0026 };
0027
0028 struct sh_pfc_chip {
0029     struct sh_pfc           *pfc;
0030     struct gpio_chip        gpio_chip;
0031
0032     struct sh_pfc_window        *mem;
0033     struct sh_pfc_gpio_data_reg *regs;
0034     struct sh_pfc_gpio_pin      *pins;
0035 };
0036
0037 static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
0038 {
0039     struct sh_pfc_chip *chip = gpiochip_get_data(gc);
0040     return chip->pfc;
0041 }
0042
0043 static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset,
0044                   struct sh_pfc_gpio_data_reg **reg,
0045                   unsigned int *bit)
0046 {
0047     int idx = sh_pfc_get_pin_index(chip->pfc, offset);
0048     struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
0049
0050     *reg = &chip->regs[gpio_pin->dreg];
0051     *bit = gpio_pin->dbit;
0052 }
0053
0054 static u32 gpio_read_data_reg(struct sh_pfc_chip *chip,
0055                   const struct pinmux_data_reg *dreg)
0056 {
0057     phys_addr_t address = dreg->reg;
0058     void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
0059
0060     return sh_pfc_read_raw_reg(mem, dreg->reg_width);
0061 }
0062
0063 static void gpio_write_data_reg(struct sh_pfc_chip *chip,
0064                 const struct pinmux_data_reg *dreg, u32 value)
0065 {
0066     phys_addr_t address = dreg->reg;
0067     void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
0068
0069     sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
0070 }
0071
0072 static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx)
0073 {
0074     struct sh_pfc *pfc = chip->pfc;
0075     struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
0076     const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
0077     const struct pinmux_data_reg *dreg;
0078     unsigned int bit;
0079     unsigned int i;
0080
0081     for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
0082         for (bit = 0; bit < dreg->reg_width; bit++) {
0083             if (dreg->enum_ids[bit] == pin->enum_id) {
0084                 gpio_pin->dreg = i;
0085                 gpio_pin->dbit = bit;
0086                 return;
0087             }
0088         }
0089     }
0090
0091     BUG();
0092 }
0093
0094 static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
0095 {
0096     struct sh_pfc *pfc = chip->pfc;
0097     const struct pinmux_data_reg *dreg;
0098     unsigned int i;
0099
0100     /* Count the number of data registers, allocate memory and initialize
0101      * them.
0102      */
0103     for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
0104         ;
0105
0106     chip->regs = devm_kcalloc(pfc->dev, i, sizeof(*chip->regs),
0107                   GFP_KERNEL);
0108     if (chip->regs == NULL)
0109         return -ENOMEM;
0110
0111     for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
0112         chip->regs[i].info = dreg;
0113         chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
0114     }
0115
0116     for (i = 0; i < pfc->info->nr_pins; i++) {
0117         if (pfc->info->pins[i].enum_id == 0)
0118             continue;
0119
0120         gpio_setup_data_reg(chip, i);
0121     }
0122
0123     return 0;
0124 }
0125
0126 /* -----------------------------------------------------------------------------
0127  * Pin GPIOs
0128  */
0129
0130 static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
0131 {
0132     struct sh_pfc *pfc = gpio_to_pfc(gc);
0133     int idx = sh_pfc_get_pin_index(pfc, offset);
0134
0135     if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
0136         return -EINVAL;
0137
0138     return pinctrl_gpio_request(offset);
0139 }
0140
0141 static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
0142 {
0143     return pinctrl_gpio_free(offset);
0144 }
0145
0146 static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
0147                    int value)
0148 {
0149     struct sh_pfc_gpio_data_reg *reg;
0150     unsigned int bit;
0151     unsigned int pos;
0152
0153     gpio_get_data_reg(chip, offset, &reg, &bit);
0154
0155     pos = reg->info->reg_width - (bit + 1);
0156
0157     if (value)
0158         reg->shadow |= BIT(pos);
0159     else
0160         reg->shadow &= ~BIT(pos);
0161
0162     gpio_write_data_reg(chip, reg->info, reg->shadow);
0163 }
0164
0165 static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
0166 {
0167     return pinctrl_gpio_direction_input(offset);
0168 }
0169
0170 static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
0171                     int value)
0172 {
0173     gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
0174
0175     return pinctrl_gpio_direction_output(offset);
0176 }
0177
0178 static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
0179 {
0180     struct sh_pfc_chip *chip = gpiochip_get_data(gc);
0181     struct sh_pfc_gpio_data_reg *reg;
0182     unsigned int bit;
0183     unsigned int pos;
0184
0185     gpio_get_data_reg(chip, offset, &reg, &bit);
0186
0187     pos = reg->info->reg_width - (bit + 1);
0188
0189     return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
0190 }
0191
0192 static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
0193 {
0194     gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
0195 }
0196
0197 static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
0198 {
0199     struct sh_pfc *pfc = gpio_to_pfc(gc);
0200     unsigned int i, k;
0201
0202     for (i = 0; i < pfc->info->gpio_irq_size; i++) {
0203         const short *gpios = pfc->info->gpio_irq[i].gpios;
0204
0205         for (k = 0; gpios[k] >= 0; k++) {
0206             if (gpios[k] == offset)
0207                 return pfc->irqs[i];
0208         }
0209     }
0210
0211     return 0;
0212 }
0213
0214 static int gpio_pin_setup(struct sh_pfc_chip *chip)
0215 {
0216     struct sh_pfc *pfc = chip->pfc;
0217     struct gpio_chip *gc = &chip->gpio_chip;
0218     int ret;
0219
0220     chip->pins = devm_kcalloc(pfc->dev,
0221                   pfc->info->nr_pins, sizeof(*chip->pins),
0222                   GFP_KERNEL);
0223     if (chip->pins == NULL)
0224         return -ENOMEM;
0225
0226     ret = gpio_setup_data_regs(chip);
0227     if (ret < 0)
0228         return ret;
0229
0230     gc->request = gpio_pin_request;
0231     gc->free = gpio_pin_free;
0232     gc->direction_input = gpio_pin_direction_input;
0233     gc->get = gpio_pin_get;
0234     gc->direction_output = gpio_pin_direction_output;
0235     gc->set = gpio_pin_set;
0236     gc->to_irq = gpio_pin_to_irq;
0237
0238     gc->label = pfc->info->name;
0239     gc->parent = pfc->dev;
0240     gc->owner = THIS_MODULE;
0241     gc->base = 0;
0242     gc->ngpio = pfc->nr_gpio_pins;
0243
0244     return 0;
0245 }
0246
0247 /* -----------------------------------------------------------------------------
0248  * Function GPIOs
0249  */
0250
0251 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
0252 static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
0253 {
0254     struct sh_pfc *pfc = gpio_to_pfc(gc);
0255     unsigned int mark = pfc->info->func_gpios[offset].enum_id;
0256     unsigned long flags;
0257     int ret;
0258
0259     dev_notice_once(pfc->dev,
0260             "Use of GPIO API for function requests is deprecated, convert to pinctrl\n");
0261
0262     if (mark == 0)
0263         return -EINVAL;
0264
0265     spin_lock_irqsave(&pfc->lock, flags);
0266     ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION);
0267     spin_unlock_irqrestore(&pfc->lock, flags);
0268
0269     return ret;
0270 }
0271
0272 static int gpio_function_setup(struct sh_pfc_chip *chip)
0273 {
0274     struct sh_pfc *pfc = chip->pfc;
0275     struct gpio_chip *gc = &chip->gpio_chip;
0276
0277     gc->request = gpio_function_request;
0278
0279     gc->label = pfc->info->name;
0280     gc->owner = THIS_MODULE;
0281     gc->base = pfc->nr_gpio_pins;
0282     gc->ngpio = pfc->info->nr_func_gpios;
0283
0284     return 0;
0285 }
0286 #endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
0287
0288 /* -----------------------------------------------------------------------------
0289  * Register/unregister
0290  */
0291
0292 static struct sh_pfc_chip *
0293 sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
0294             struct sh_pfc_window *mem)
0295 {
0296     struct sh_pfc_chip *chip;
0297     int ret;
0298
0299     chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
0300     if (unlikely(!chip))
0301         return ERR_PTR(-ENOMEM);
0302
0303     chip->mem = mem;
0304     chip->pfc = pfc;
0305
0306     ret = setup(chip);
0307     if (ret < 0)
0308         return ERR_PTR(ret);
0309
0310     ret = devm_gpiochip_add_data(pfc->dev, &chip->gpio_chip, chip);
0311     if (unlikely(ret < 0))
0312         return ERR_PTR(ret);
0313
0314     dev_info(pfc->dev, "%s handling gpio %u -> %u\n",
0315          chip->gpio_chip.label, chip->gpio_chip.base,
0316          chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
0317
0318     return chip;
0319 }
0320
0321 int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
0322 {
0323     struct sh_pfc_chip *chip;
0324     phys_addr_t address;
0325     unsigned int i;
0326
0327     if (pfc->info->data_regs == NULL)
0328         return 0;
0329
0330     /* Find the memory window that contains the GPIO registers. Boards that
0331      * register a separate GPIO device will not supply a memory resource
0332      * that covers the data registers. In that case don't try to handle
0333      * GPIOs.
0334      */
0335     address = pfc->info->data_regs[0].reg;
0336     for (i = 0; i < pfc->num_windows; ++i) {
0337         struct sh_pfc_window *window = &pfc->windows[i];
0338
0339         if (address >= window->phys &&
0340             address < window->phys + window->size)
0341             break;
0342     }
0343
0344     if (i == pfc->num_windows)
0345         return 0;
0346
0347     /* If we have IRQ resources make sure their number is correct. */
0348     if (pfc->num_irqs != pfc->info->gpio_irq_size) {
0349         dev_err(pfc->dev, "invalid number of IRQ resources\n");
0350         return -EINVAL;
0351     }
0352
0353     /* Register the real GPIOs chip. */
0354     chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]);
0355     if (IS_ERR(chip))
0356         return PTR_ERR(chip);
0357
0358     pfc->gpio = chip;
0359
0360     if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node)
0361         return 0;
0362
0363 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
0364     /*
0365      * Register the GPIO to pin mappings. As pins with GPIO ports
0366      * must come first in the ranges, skip the pins without GPIO
0367      * ports by stopping at the first range that contains such a
0368      * pin.
0369      */
0370     for (i = 0; i < pfc->nr_ranges; ++i) {
0371         const struct sh_pfc_pin_range *range = &pfc->ranges[i];
0372         int ret;
0373
0374         if (range->start >= pfc->nr_gpio_pins)
0375             break;
0376
0377         ret = gpiochip_add_pin_range(&chip->gpio_chip,
0378             dev_name(pfc->dev), range->start, range->start,
0379             range->end - range->start + 1);
0380         if (ret < 0)
0381             return ret;
0382     }
0383
0384     /* Register the function GPIOs chip. */
0385     if (pfc->info->nr_func_gpios) {
0386         chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
0387         if (IS_ERR(chip))
0388             return PTR_ERR(chip);
0389     }
0390 #endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
0391
0392     return 0;
0393 }