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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Pin Control and GPIO driver for SuperH Pin Function Controller.
0004  *
0005  * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
0006  *
0007  * Copyright (C) 2008 Magnus Damm
0008  * Copyright (C) 2009 - 2012 Paul Mundt
0009  */
0010 
0011 #define DRV_NAME "sh-pfc"
0012 
0013 #include <linux/bitops.h>
0014 #include <linux/err.h>
0015 #include <linux/errno.h>
0016 #include <linux/init.h>
0017 #include <linux/io.h>
0018 #include <linux/ioport.h>
0019 #include <linux/kernel.h>
0020 #include <linux/math.h>
0021 #include <linux/of.h>
0022 #include <linux/of_device.h>
0023 #include <linux/pinctrl/machine.h>
0024 #include <linux/platform_device.h>
0025 #include <linux/psci.h>
0026 #include <linux/slab.h>
0027 #include <linux/sys_soc.h>
0028 
0029 #include "core.h"
0030 
0031 static int sh_pfc_map_resources(struct sh_pfc *pfc,
0032                 struct platform_device *pdev)
0033 {
0034     struct sh_pfc_window *windows;
0035     unsigned int *irqs = NULL;
0036     unsigned int num_windows;
0037     struct resource *res;
0038     unsigned int i;
0039     int num_irqs;
0040 
0041     /* Count the MEM and IRQ resources. */
0042     for (num_windows = 0;; num_windows++) {
0043         res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows);
0044         if (!res)
0045             break;
0046     }
0047     if (num_windows == 0)
0048         return -EINVAL;
0049 
0050     num_irqs = platform_irq_count(pdev);
0051     if (num_irqs < 0)
0052         return num_irqs;
0053 
0054     /* Allocate memory windows and IRQs arrays. */
0055     windows = devm_kcalloc(pfc->dev, num_windows, sizeof(*windows),
0056                    GFP_KERNEL);
0057     if (windows == NULL)
0058         return -ENOMEM;
0059 
0060     pfc->num_windows = num_windows;
0061     pfc->windows = windows;
0062 
0063     if (num_irqs) {
0064         irqs = devm_kcalloc(pfc->dev, num_irqs, sizeof(*irqs),
0065                     GFP_KERNEL);
0066         if (irqs == NULL)
0067             return -ENOMEM;
0068 
0069         pfc->num_irqs = num_irqs;
0070         pfc->irqs = irqs;
0071     }
0072 
0073     /* Fill them. */
0074     for (i = 0; i < num_windows; i++) {
0075         windows->virt = devm_platform_get_and_ioremap_resource(pdev, i, &res);
0076         if (IS_ERR(windows->virt))
0077             return -ENOMEM;
0078         windows->phys = res->start;
0079         windows->size = resource_size(res);
0080         windows++;
0081     }
0082     for (i = 0; i < num_irqs; i++)
0083         *irqs++ = platform_get_irq(pdev, i);
0084 
0085     return 0;
0086 }
0087 
0088 static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
0089 {
0090     struct sh_pfc_window *window;
0091     phys_addr_t address = reg;
0092     unsigned int i;
0093 
0094     /* scan through physical windows and convert address */
0095     for (i = 0; i < pfc->num_windows; i++) {
0096         window = pfc->windows + i;
0097 
0098         if (address < window->phys)
0099             continue;
0100 
0101         if (address >= (window->phys + window->size))
0102             continue;
0103 
0104         return window->virt + (address - window->phys);
0105     }
0106 
0107     BUG();
0108     return NULL;
0109 }
0110 
0111 int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
0112 {
0113     unsigned int offset;
0114     unsigned int i;
0115 
0116     for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
0117         const struct sh_pfc_pin_range *range = &pfc->ranges[i];
0118 
0119         if (pin <= range->end)
0120             return pin >= range->start
0121                  ? offset + pin - range->start : -1;
0122 
0123         offset += range->end - range->start + 1;
0124     }
0125 
0126     return -EINVAL;
0127 }
0128 
0129 static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
0130 {
0131     if (enum_id < r->begin)
0132         return 0;
0133 
0134     if (enum_id > r->end)
0135         return 0;
0136 
0137     return 1;
0138 }
0139 
0140 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
0141 {
0142     switch (reg_width) {
0143     case 8:
0144         return ioread8(mapped_reg);
0145     case 16:
0146         return ioread16(mapped_reg);
0147     case 32:
0148         return ioread32(mapped_reg);
0149     }
0150 
0151     BUG();
0152     return 0;
0153 }
0154 
0155 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
0156               u32 data)
0157 {
0158     switch (reg_width) {
0159     case 8:
0160         iowrite8(data, mapped_reg);
0161         return;
0162     case 16:
0163         iowrite16(data, mapped_reg);
0164         return;
0165     case 32:
0166         iowrite32(data, mapped_reg);
0167         return;
0168     }
0169 
0170     BUG();
0171 }
0172 
0173 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
0174 {
0175     return sh_pfc_read_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32);
0176 }
0177 
0178 static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data)
0179 {
0180     u32 unlock;
0181 
0182     if (!pfc->info->unlock_reg)
0183         return;
0184 
0185     if (pfc->info->unlock_reg >= 0x80000000UL)
0186         unlock = pfc->info->unlock_reg;
0187     else
0188         /* unlock_reg is a mask */
0189         unlock = reg & ~pfc->info->unlock_reg;
0190 
0191     sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, unlock), 32, ~data);
0192 }
0193 
0194 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
0195 {
0196     sh_pfc_unlock_reg(pfc, reg, data);
0197     sh_pfc_write_raw_reg(sh_pfc_phys_to_virt(pfc, reg), 32, data);
0198 }
0199 
0200 static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
0201                      const struct pinmux_cfg_reg *crp,
0202                      unsigned int in_pos,
0203                      void __iomem **mapped_regp, u32 *maskp,
0204                      unsigned int *posp)
0205 {
0206     unsigned int k;
0207 
0208     *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
0209 
0210     if (crp->field_width) {
0211         *maskp = (1 << crp->field_width) - 1;
0212         *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
0213     } else {
0214         *maskp = (1 << crp->var_field_width[in_pos]) - 1;
0215         *posp = crp->reg_width;
0216         for (k = 0; k <= in_pos; k++)
0217             *posp -= abs(crp->var_field_width[k]);
0218     }
0219 }
0220 
0221 static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
0222                     const struct pinmux_cfg_reg *crp,
0223                     unsigned int field, u32 value)
0224 {
0225     void __iomem *mapped_reg;
0226     unsigned int pos;
0227     u32 mask, data;
0228 
0229     sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
0230 
0231     dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
0232         "r_width = %u, f_width = %u\n",
0233         crp->reg, value, field, crp->reg_width, hweight32(mask));
0234 
0235     mask = ~(mask << pos);
0236     value = value << pos;
0237 
0238     data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
0239     data &= mask;
0240     data |= value;
0241 
0242     sh_pfc_unlock_reg(pfc, crp->reg, data);
0243     sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
0244 }
0245 
0246 static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
0247                  const struct pinmux_cfg_reg **crp,
0248                  unsigned int *fieldp, u32 *valuep)
0249 {
0250     unsigned int k = 0;
0251 
0252     while (1) {
0253         const struct pinmux_cfg_reg *config_reg =
0254             pfc->info->cfg_regs + k;
0255         unsigned int r_width = config_reg->reg_width;
0256         unsigned int f_width = config_reg->field_width;
0257         unsigned int curr_width;
0258         unsigned int bit_pos;
0259         unsigned int pos = 0;
0260         unsigned int m = 0;
0261 
0262         if (!r_width)
0263             break;
0264 
0265         for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width, m++) {
0266             u32 ncomb;
0267             u32 n;
0268 
0269             if (f_width) {
0270                 curr_width = f_width;
0271             } else {
0272                 curr_width = abs(config_reg->var_field_width[m]);
0273                 if (config_reg->var_field_width[m] < 0)
0274                     continue;
0275             }
0276 
0277             ncomb = 1 << curr_width;
0278             for (n = 0; n < ncomb; n++) {
0279                 if (config_reg->enum_ids[pos + n] == enum_id) {
0280                     *crp = config_reg;
0281                     *fieldp = m;
0282                     *valuep = n;
0283                     return 0;
0284                 }
0285             }
0286             pos += ncomb;
0287         }
0288         k++;
0289     }
0290 
0291     return -EINVAL;
0292 }
0293 
0294 static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
0295                   u16 *enum_idp)
0296 {
0297     const u16 *data = pfc->info->pinmux_data;
0298     unsigned int k;
0299 
0300     if (pos) {
0301         *enum_idp = data[pos + 1];
0302         return pos + 1;
0303     }
0304 
0305     for (k = 0; k < pfc->info->pinmux_data_size; k++) {
0306         if (data[k] == mark) {
0307             *enum_idp = data[k + 1];
0308             return k + 1;
0309         }
0310     }
0311 
0312     dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
0313         mark);
0314     return -EINVAL;
0315 }
0316 
0317 int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
0318 {
0319     const struct pinmux_range *range;
0320     int pos = 0;
0321 
0322     switch (pinmux_type) {
0323     case PINMUX_TYPE_GPIO:
0324     case PINMUX_TYPE_FUNCTION:
0325         range = NULL;
0326         break;
0327 
0328 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
0329     case PINMUX_TYPE_OUTPUT:
0330         range = &pfc->info->output;
0331         break;
0332 
0333     case PINMUX_TYPE_INPUT:
0334         range = &pfc->info->input;
0335         break;
0336 #endif /* CONFIG_PINCTRL_SH_PFC_GPIO */
0337 
0338     default:
0339         return -EINVAL;
0340     }
0341 
0342     /* Iterate over all the configuration fields we need to update. */
0343     while (1) {
0344         const struct pinmux_cfg_reg *cr;
0345         unsigned int field;
0346         u16 enum_id;
0347         u32 value;
0348         int in_range;
0349         int ret;
0350 
0351         pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
0352         if (pos < 0)
0353             return pos;
0354 
0355         if (!enum_id)
0356             break;
0357 
0358         /* Check if the configuration field selects a function. If it
0359          * doesn't, skip the field if it's not applicable to the
0360          * requested pinmux type.
0361          */
0362         in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
0363         if (!in_range) {
0364             if (pinmux_type == PINMUX_TYPE_FUNCTION) {
0365                 /* Functions are allowed to modify all
0366                  * fields.
0367                  */
0368                 in_range = 1;
0369             } else if (pinmux_type != PINMUX_TYPE_GPIO) {
0370                 /* Input/output types can only modify fields
0371                  * that correspond to their respective ranges.
0372                  */
0373                 in_range = sh_pfc_enum_in_range(enum_id, range);
0374 
0375                 /*
0376                  * special case pass through for fixed
0377                  * input-only or output-only pins without
0378                  * function enum register association.
0379                  */
0380                 if (in_range && enum_id == range->force)
0381                     continue;
0382             }
0383             /* GPIOs are only allowed to modify function fields. */
0384         }
0385 
0386         if (!in_range)
0387             continue;
0388 
0389         ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
0390         if (ret < 0)
0391             return ret;
0392 
0393         sh_pfc_write_config_reg(pfc, cr, field, value);
0394     }
0395 
0396     return 0;
0397 }
0398 
0399 static int sh_pfc_init_ranges(struct sh_pfc *pfc)
0400 {
0401     struct sh_pfc_pin_range *range;
0402     unsigned int nr_ranges;
0403     unsigned int i;
0404 
0405     if (pfc->info->pins[0].pin == (u16)-1) {
0406         /* Pin number -1 denotes that the SoC doesn't report pin numbers
0407          * in its pin arrays yet. Consider the pin numbers range as
0408          * continuous and allocate a single range.
0409          */
0410         pfc->nr_ranges = 1;
0411         pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges),
0412                        GFP_KERNEL);
0413         if (pfc->ranges == NULL)
0414             return -ENOMEM;
0415 
0416         pfc->ranges->start = 0;
0417         pfc->ranges->end = pfc->info->nr_pins - 1;
0418         pfc->nr_gpio_pins = pfc->info->nr_pins;
0419 
0420         return 0;
0421     }
0422 
0423     /* Count, allocate and fill the ranges. The PFC SoC data pins array must
0424      * be sorted by pin numbers, and pins without a GPIO port must come
0425      * last.
0426      */
0427     for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
0428         if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
0429             nr_ranges++;
0430     }
0431 
0432     pfc->nr_ranges = nr_ranges;
0433     pfc->ranges = devm_kcalloc(pfc->dev, nr_ranges, sizeof(*pfc->ranges),
0434                    GFP_KERNEL);
0435     if (pfc->ranges == NULL)
0436         return -ENOMEM;
0437 
0438     range = pfc->ranges;
0439     range->start = pfc->info->pins[0].pin;
0440 
0441     for (i = 1; i < pfc->info->nr_pins; ++i) {
0442         if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
0443             continue;
0444 
0445         range->end = pfc->info->pins[i-1].pin;
0446         if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
0447             pfc->nr_gpio_pins = range->end + 1;
0448 
0449         range++;
0450         range->start = pfc->info->pins[i].pin;
0451     }
0452 
0453     range->end = pfc->info->pins[i-1].pin;
0454     if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
0455         pfc->nr_gpio_pins = range->end + 1;
0456 
0457     return 0;
0458 }
0459 
0460 #ifdef CONFIG_OF
0461 static const struct of_device_id sh_pfc_of_table[] = {
0462 #ifdef CONFIG_PINCTRL_PFC_EMEV2
0463     {
0464         .compatible = "renesas,pfc-emev2",
0465         .data = &emev2_pinmux_info,
0466     },
0467 #endif
0468 #ifdef CONFIG_PINCTRL_PFC_R8A73A4
0469     {
0470         .compatible = "renesas,pfc-r8a73a4",
0471         .data = &r8a73a4_pinmux_info,
0472     },
0473 #endif
0474 #ifdef CONFIG_PINCTRL_PFC_R8A7740
0475     {
0476         .compatible = "renesas,pfc-r8a7740",
0477         .data = &r8a7740_pinmux_info,
0478     },
0479 #endif
0480 #ifdef CONFIG_PINCTRL_PFC_R8A7742
0481     {
0482         .compatible = "renesas,pfc-r8a7742",
0483         .data = &r8a7742_pinmux_info,
0484     },
0485 #endif
0486 #ifdef CONFIG_PINCTRL_PFC_R8A7743
0487     {
0488         .compatible = "renesas,pfc-r8a7743",
0489         .data = &r8a7743_pinmux_info,
0490     },
0491 #endif
0492 #ifdef CONFIG_PINCTRL_PFC_R8A7744
0493     {
0494         .compatible = "renesas,pfc-r8a7744",
0495         .data = &r8a7744_pinmux_info,
0496     },
0497 #endif
0498 #ifdef CONFIG_PINCTRL_PFC_R8A7745
0499     {
0500         .compatible = "renesas,pfc-r8a7745",
0501         .data = &r8a7745_pinmux_info,
0502     },
0503 #endif
0504 #ifdef CONFIG_PINCTRL_PFC_R8A77470
0505     {
0506         .compatible = "renesas,pfc-r8a77470",
0507         .data = &r8a77470_pinmux_info,
0508     },
0509 #endif
0510 #ifdef CONFIG_PINCTRL_PFC_R8A774A1
0511     {
0512         .compatible = "renesas,pfc-r8a774a1",
0513         .data = &r8a774a1_pinmux_info,
0514     },
0515 #endif
0516 #ifdef CONFIG_PINCTRL_PFC_R8A774B1
0517     {
0518         .compatible = "renesas,pfc-r8a774b1",
0519         .data = &r8a774b1_pinmux_info,
0520     },
0521 #endif
0522 #ifdef CONFIG_PINCTRL_PFC_R8A774C0
0523     {
0524         .compatible = "renesas,pfc-r8a774c0",
0525         .data = &r8a774c0_pinmux_info,
0526     },
0527 #endif
0528 #ifdef CONFIG_PINCTRL_PFC_R8A774E1
0529     {
0530         .compatible = "renesas,pfc-r8a774e1",
0531         .data = &r8a774e1_pinmux_info,
0532     },
0533 #endif
0534 #ifdef CONFIG_PINCTRL_PFC_R8A7778
0535     {
0536         .compatible = "renesas,pfc-r8a7778",
0537         .data = &r8a7778_pinmux_info,
0538     },
0539 #endif
0540 #ifdef CONFIG_PINCTRL_PFC_R8A7779
0541     {
0542         .compatible = "renesas,pfc-r8a7779",
0543         .data = &r8a7779_pinmux_info,
0544     },
0545 #endif
0546 #ifdef CONFIG_PINCTRL_PFC_R8A7790
0547     {
0548         .compatible = "renesas,pfc-r8a7790",
0549         .data = &r8a7790_pinmux_info,
0550     },
0551 #endif
0552 #ifdef CONFIG_PINCTRL_PFC_R8A7791
0553     {
0554         .compatible = "renesas,pfc-r8a7791",
0555         .data = &r8a7791_pinmux_info,
0556     },
0557 #endif
0558 #ifdef CONFIG_PINCTRL_PFC_R8A7792
0559     {
0560         .compatible = "renesas,pfc-r8a7792",
0561         .data = &r8a7792_pinmux_info,
0562     },
0563 #endif
0564 #ifdef CONFIG_PINCTRL_PFC_R8A7793
0565     {
0566         .compatible = "renesas,pfc-r8a7793",
0567         .data = &r8a7793_pinmux_info,
0568     },
0569 #endif
0570 #ifdef CONFIG_PINCTRL_PFC_R8A7794
0571     {
0572         .compatible = "renesas,pfc-r8a7794",
0573         .data = &r8a7794_pinmux_info,
0574     },
0575 #endif
0576 /*
0577  * Both r8a7795 entries must be present to make sanity checks work, but only
0578  * the first entry is actually used.
0579  * R-Car H3 ES1.x is matched using soc_device_match() instead.
0580  */
0581 #ifdef CONFIG_PINCTRL_PFC_R8A77951
0582     {
0583         .compatible = "renesas,pfc-r8a7795",
0584         .data = &r8a77951_pinmux_info,
0585     },
0586 #endif
0587 #ifdef CONFIG_PINCTRL_PFC_R8A77950
0588     {
0589         .compatible = "renesas,pfc-r8a7795",
0590         .data = &r8a77950_pinmux_info,
0591     },
0592 #endif
0593 #ifdef CONFIG_PINCTRL_PFC_R8A77960
0594     {
0595         .compatible = "renesas,pfc-r8a7796",
0596         .data = &r8a77960_pinmux_info,
0597     },
0598 #endif
0599 #ifdef CONFIG_PINCTRL_PFC_R8A77961
0600     {
0601         .compatible = "renesas,pfc-r8a77961",
0602         .data = &r8a77961_pinmux_info,
0603     },
0604 #endif
0605 #ifdef CONFIG_PINCTRL_PFC_R8A77965
0606     {
0607         .compatible = "renesas,pfc-r8a77965",
0608         .data = &r8a77965_pinmux_info,
0609     },
0610 #endif
0611 #ifdef CONFIG_PINCTRL_PFC_R8A77970
0612     {
0613         .compatible = "renesas,pfc-r8a77970",
0614         .data = &r8a77970_pinmux_info,
0615     },
0616 #endif
0617 #ifdef CONFIG_PINCTRL_PFC_R8A77980
0618     {
0619         .compatible = "renesas,pfc-r8a77980",
0620         .data = &r8a77980_pinmux_info,
0621     },
0622 #endif
0623 #ifdef CONFIG_PINCTRL_PFC_R8A77990
0624     {
0625         .compatible = "renesas,pfc-r8a77990",
0626         .data = &r8a77990_pinmux_info,
0627     },
0628 #endif
0629 #ifdef CONFIG_PINCTRL_PFC_R8A77995
0630     {
0631         .compatible = "renesas,pfc-r8a77995",
0632         .data = &r8a77995_pinmux_info,
0633     },
0634 #endif
0635 #ifdef CONFIG_PINCTRL_PFC_R8A779A0
0636     {
0637         .compatible = "renesas,pfc-r8a779a0",
0638         .data = &r8a779a0_pinmux_info,
0639     },
0640 #endif
0641 #ifdef CONFIG_PINCTRL_PFC_R8A779F0
0642     {
0643         .compatible = "renesas,pfc-r8a779f0",
0644         .data = &r8a779f0_pinmux_info,
0645     },
0646 #endif
0647 #ifdef CONFIG_PINCTRL_PFC_R8A779G0
0648     {
0649         .compatible = "renesas,pfc-r8a779g0",
0650         .data = &r8a779g0_pinmux_info,
0651     },
0652 #endif
0653 #ifdef CONFIG_PINCTRL_PFC_SH73A0
0654     {
0655         .compatible = "renesas,pfc-sh73a0",
0656         .data = &sh73a0_pinmux_info,
0657     },
0658 #endif
0659     { },
0660 };
0661 #endif
0662 
0663 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM_PSCI_FW)
0664 static void sh_pfc_nop_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
0665 {
0666 }
0667 
0668 static void sh_pfc_save_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
0669 {
0670     pfc->saved_regs[idx] = sh_pfc_read(pfc, reg);
0671 }
0672 
0673 static void sh_pfc_restore_reg(struct sh_pfc *pfc, u32 reg, unsigned int idx)
0674 {
0675     sh_pfc_write(pfc, reg, pfc->saved_regs[idx]);
0676 }
0677 
0678 static unsigned int sh_pfc_walk_regs(struct sh_pfc *pfc,
0679     void (*do_reg)(struct sh_pfc *pfc, u32 reg, unsigned int idx))
0680 {
0681     unsigned int i, n = 0;
0682 
0683     if (pfc->info->cfg_regs)
0684         for (i = 0; pfc->info->cfg_regs[i].reg; i++)
0685             do_reg(pfc, pfc->info->cfg_regs[i].reg, n++);
0686 
0687     if (pfc->info->drive_regs)
0688         for (i = 0; pfc->info->drive_regs[i].reg; i++)
0689             do_reg(pfc, pfc->info->drive_regs[i].reg, n++);
0690 
0691     if (pfc->info->bias_regs)
0692         for (i = 0; pfc->info->bias_regs[i].puen ||
0693                 pfc->info->bias_regs[i].pud; i++) {
0694             if (pfc->info->bias_regs[i].puen)
0695                 do_reg(pfc, pfc->info->bias_regs[i].puen, n++);
0696             if (pfc->info->bias_regs[i].pud)
0697                 do_reg(pfc, pfc->info->bias_regs[i].pud, n++);
0698         }
0699 
0700     if (pfc->info->ioctrl_regs)
0701         for (i = 0; pfc->info->ioctrl_regs[i].reg; i++)
0702             do_reg(pfc, pfc->info->ioctrl_regs[i].reg, n++);
0703 
0704     return n;
0705 }
0706 
0707 static int sh_pfc_suspend_init(struct sh_pfc *pfc)
0708 {
0709     unsigned int n;
0710 
0711     /* This is the best we can do to check for the presence of PSCI */
0712     if (!psci_ops.cpu_suspend)
0713         return 0;
0714 
0715     n = sh_pfc_walk_regs(pfc, sh_pfc_nop_reg);
0716     if (!n)
0717         return 0;
0718 
0719     pfc->saved_regs = devm_kmalloc_array(pfc->dev, n,
0720                          sizeof(*pfc->saved_regs),
0721                          GFP_KERNEL);
0722     if (!pfc->saved_regs)
0723         return -ENOMEM;
0724 
0725     dev_dbg(pfc->dev, "Allocated space to save %u regs\n", n);
0726     return 0;
0727 }
0728 
0729 static int sh_pfc_suspend_noirq(struct device *dev)
0730 {
0731     struct sh_pfc *pfc = dev_get_drvdata(dev);
0732 
0733     if (pfc->saved_regs)
0734         sh_pfc_walk_regs(pfc, sh_pfc_save_reg);
0735     return 0;
0736 }
0737 
0738 static int sh_pfc_resume_noirq(struct device *dev)
0739 {
0740     struct sh_pfc *pfc = dev_get_drvdata(dev);
0741 
0742     if (pfc->saved_regs)
0743         sh_pfc_walk_regs(pfc, sh_pfc_restore_reg);
0744     return 0;
0745 }
0746 
0747 static const struct dev_pm_ops sh_pfc_pm  = {
0748     SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sh_pfc_suspend_noirq, sh_pfc_resume_noirq)
0749 };
0750 #define DEV_PM_OPS  &sh_pfc_pm
0751 #else
0752 static int sh_pfc_suspend_init(struct sh_pfc *pfc) { return 0; }
0753 #define DEV_PM_OPS  NULL
0754 #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
0755 
0756 #ifdef DEBUG
0757 #define SH_PFC_MAX_REGS     300
0758 #define SH_PFC_MAX_ENUMS    5000
0759 
0760 static unsigned int sh_pfc_errors __initdata;
0761 static unsigned int sh_pfc_warnings __initdata;
0762 static bool sh_pfc_bias_done __initdata;
0763 static bool sh_pfc_drive_done __initdata;
0764 static bool sh_pfc_power_done __initdata;
0765 static struct {
0766     u32 reg;
0767     u32 bits;
0768 } *sh_pfc_regs __initdata;
0769 static u32 sh_pfc_num_regs __initdata;
0770 static u16 *sh_pfc_enums __initdata;
0771 static u32 sh_pfc_num_enums __initdata;
0772 
0773 #define sh_pfc_err(fmt, ...)                    \
0774     do {                            \
0775         pr_err("%s: " fmt, drvname, ##__VA_ARGS__); \
0776         sh_pfc_errors++;                \
0777     } while (0)
0778 
0779 #define sh_pfc_err_once(type, fmt, ...)             \
0780     do {                            \
0781         if (!sh_pfc_ ## type ## _done) {        \
0782             sh_pfc_ ## type ## _done = true;    \
0783             sh_pfc_err(fmt, ##__VA_ARGS__);     \
0784         }                       \
0785     } while (0)
0786 
0787 #define sh_pfc_warn(fmt, ...)                   \
0788     do {                            \
0789         pr_warn("%s: " fmt, drvname, ##__VA_ARGS__);    \
0790         sh_pfc_warnings++;              \
0791     } while (0)
0792 
0793 static bool __init is0s(const u16 *enum_ids, unsigned int n)
0794 {
0795     unsigned int i;
0796 
0797     for (i = 0; i < n; i++)
0798         if (enum_ids[i])
0799             return false;
0800 
0801     return true;
0802 }
0803 
0804 static bool __init same_name(const char *a, const char *b)
0805 {
0806     return a && b && !strcmp(a, b);
0807 }
0808 
0809 static void __init sh_pfc_check_reg(const char *drvname, u32 reg, u32 bits)
0810 {
0811     unsigned int i;
0812 
0813     for (i = 0; i < sh_pfc_num_regs; i++) {
0814         if (reg != sh_pfc_regs[i].reg)
0815             continue;
0816 
0817         if (bits & sh_pfc_regs[i].bits)
0818             sh_pfc_err("reg 0x%x: bits 0x%x conflict\n", reg,
0819                    bits & sh_pfc_regs[i].bits);
0820 
0821         sh_pfc_regs[i].bits |= bits;
0822         return;
0823     }
0824 
0825     if (sh_pfc_num_regs == SH_PFC_MAX_REGS) {
0826         pr_warn_once("%s: Please increase SH_PFC_MAX_REGS\n", drvname);
0827         return;
0828     }
0829 
0830     sh_pfc_regs[sh_pfc_num_regs].reg = reg;
0831     sh_pfc_regs[sh_pfc_num_regs].bits = bits;
0832     sh_pfc_num_regs++;
0833 }
0834 
0835 static int __init sh_pfc_check_enum(const char *drvname, u16 enum_id)
0836 {
0837     unsigned int i;
0838 
0839     for (i = 0; i < sh_pfc_num_enums; i++) {
0840         if (enum_id == sh_pfc_enums[i])
0841             return -EINVAL;
0842     }
0843 
0844     if (sh_pfc_num_enums == SH_PFC_MAX_ENUMS) {
0845         pr_warn_once("%s: Please increase SH_PFC_MAX_ENUMS\n", drvname);
0846         return 0;
0847     }
0848 
0849     sh_pfc_enums[sh_pfc_num_enums++] = enum_id;
0850     return 0;
0851 }
0852 
0853 static void __init sh_pfc_check_reg_enums(const char *drvname, u32 reg,
0854                       const u16 *enums, unsigned int n)
0855 {
0856     unsigned int i;
0857 
0858     for (i = 0; i < n; i++) {
0859         if (enums[i] && sh_pfc_check_enum(drvname, enums[i]))
0860             sh_pfc_err("reg 0x%x enum_id %u conflict\n", reg,
0861                    enums[i]);
0862     }
0863 }
0864 
0865 static const struct sh_pfc_pin __init *sh_pfc_find_pin(
0866     const struct sh_pfc_soc_info *info, u32 reg, unsigned int pin)
0867 {
0868     const char *drvname = info->name;
0869     unsigned int i;
0870 
0871     if (pin == SH_PFC_PIN_NONE)
0872         return NULL;
0873 
0874     for (i = 0; i < info->nr_pins; i++) {
0875         if (pin == info->pins[i].pin)
0876             return &info->pins[i];
0877     }
0878 
0879     sh_pfc_err("reg 0x%x: pin %u not found\n", reg, pin);
0880     return NULL;
0881 }
0882 
0883 static void __init sh_pfc_check_cfg_reg(const char *drvname,
0884                     const struct pinmux_cfg_reg *cfg_reg)
0885 {
0886     unsigned int i, n, rw, r;
0887     int fw;
0888 
0889     sh_pfc_check_reg(drvname, cfg_reg->reg,
0890              GENMASK(cfg_reg->reg_width - 1, 0));
0891 
0892     if (cfg_reg->field_width) {
0893         fw = cfg_reg->field_width;
0894         n = (cfg_reg->reg_width / fw) << fw;
0895         for (i = 0, r = 0; i < n; i += 1 << fw) {
0896             if (is0s(&cfg_reg->enum_ids[i], 1 << fw))
0897                 r++;
0898         }
0899 
0900         if ((r << fw) * sizeof(u16) > cfg_reg->reg_width / fw)
0901             sh_pfc_warn("reg 0x%x can be described with variable-width reserved fields\n",
0902                     cfg_reg->reg);
0903 
0904         /* Skip field checks (done at build time) */
0905         goto check_enum_ids;
0906     }
0907 
0908     for (i = 0, n = 0, rw = 0; (fw = cfg_reg->var_field_width[i]); i++) {
0909         if (fw < 0) {
0910             rw += -fw;
0911         } else {
0912             if (is0s(&cfg_reg->enum_ids[n], 1 << fw))
0913                 sh_pfc_warn("reg 0x%x: field [%u:%u] can be described as reserved\n",
0914                         cfg_reg->reg, rw, rw + fw - 1);
0915             n += 1 << fw;
0916             rw += fw;
0917         }
0918     }
0919 
0920     if (rw != cfg_reg->reg_width)
0921         sh_pfc_err("reg 0x%x: var_field_width declares %u instead of %u bits\n",
0922                cfg_reg->reg, rw, cfg_reg->reg_width);
0923 
0924     if (n != cfg_reg->nr_enum_ids)
0925         sh_pfc_err("reg 0x%x: enum_ids[] has %u instead of %u values\n",
0926                cfg_reg->reg, cfg_reg->nr_enum_ids, n);
0927 
0928 check_enum_ids:
0929     sh_pfc_check_reg_enums(drvname, cfg_reg->reg, cfg_reg->enum_ids, n);
0930 }
0931 
0932 static void __init sh_pfc_check_drive_reg(const struct sh_pfc_soc_info *info,
0933                       const struct pinmux_drive_reg *drive)
0934 {
0935     const char *drvname = info->name;
0936     const struct sh_pfc_pin *pin;
0937     unsigned int i;
0938 
0939     for (i = 0; i < ARRAY_SIZE(drive->fields); i++) {
0940         const struct pinmux_drive_reg_field *field = &drive->fields[i];
0941 
0942         if (!field->pin && !field->offset && !field->size)
0943             continue;
0944 
0945         sh_pfc_check_reg(info->name, drive->reg,
0946                  GENMASK(field->offset + field->size - 1,
0947                      field->offset));
0948 
0949         pin = sh_pfc_find_pin(info, drive->reg, field->pin);
0950         if (pin && !(pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH))
0951             sh_pfc_err("drive_reg 0x%x: field %u: pin %s lacks SH_PFC_PIN_CFG_DRIVE_STRENGTH flag\n",
0952                    drive->reg, i, pin->name);
0953     }
0954 }
0955 
0956 static void __init sh_pfc_check_bias_reg(const struct sh_pfc_soc_info *info,
0957                      const struct pinmux_bias_reg *bias)
0958 {
0959     const char *drvname = info->name;
0960     const struct sh_pfc_pin *pin;
0961     unsigned int i;
0962     u32 bits;
0963 
0964     for (i = 0, bits = 0; i < ARRAY_SIZE(bias->pins); i++)
0965         if (bias->pins[i] != SH_PFC_PIN_NONE)
0966             bits |= BIT(i);
0967 
0968     if (bias->puen)
0969         sh_pfc_check_reg(info->name, bias->puen, bits);
0970     if (bias->pud)
0971         sh_pfc_check_reg(info->name, bias->pud, bits);
0972     for (i = 0; i < ARRAY_SIZE(bias->pins); i++) {
0973         pin = sh_pfc_find_pin(info, bias->puen, bias->pins[i]);
0974         if (!pin)
0975             continue;
0976 
0977         if (bias->puen && bias->pud) {
0978             /*
0979              * Pull-enable and pull-up/down control registers
0980              * As some SoCs have pins that support only pull-up
0981              * or pull-down, we just check for one of them
0982              */
0983             if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN))
0984                 sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks one or more SH_PFC_PIN_CFG_PULL_* flags\n",
0985                        bias->puen, i, pin->name);
0986         } else if (bias->puen) {
0987             /* Pull-up control register only */
0988             if (!(pin->configs & SH_PFC_PIN_CFG_PULL_UP))
0989                 sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_UP flag\n",
0990                        bias->puen, i, pin->name);
0991         } else if (bias->pud) {
0992             /* Pull-down control register only */
0993             if (!(pin->configs & SH_PFC_PIN_CFG_PULL_DOWN))
0994                 sh_pfc_err("bias_reg 0x%x:%u: pin %s lacks SH_PFC_PIN_CFG_PULL_DOWN flag\n",
0995                        bias->pud, i, pin->name);
0996         }
0997     }
0998 }
0999 
1000 static void __init sh_pfc_compare_groups(const char *drvname,
1001                      const struct sh_pfc_pin_group *a,
1002                      const struct sh_pfc_pin_group *b)
1003 {
1004     unsigned int i;
1005     size_t len;
1006 
1007     if (same_name(a->name, b->name))
1008         sh_pfc_err("group %s: name conflict\n", a->name);
1009 
1010     if (a->nr_pins > b->nr_pins)
1011         swap(a, b);
1012 
1013     len = a->nr_pins * sizeof(a->pins[0]);
1014     for (i = 0; i <= b->nr_pins - a->nr_pins; i++) {
1015         if (a->pins == b->pins + i || a->mux == b->mux + i ||
1016             memcmp(a->pins, b->pins + i, len) ||
1017             memcmp(a->mux, b->mux + i, len))
1018             continue;
1019 
1020         if (a->nr_pins == b->nr_pins)
1021             sh_pfc_warn("group %s can be an alias for %s\n",
1022                     a->name, b->name);
1023         else
1024             sh_pfc_warn("group %s is a subset of %s\n", a->name,
1025                     b->name);
1026     }
1027 }
1028 
1029 static void __init sh_pfc_check_info(const struct sh_pfc_soc_info *info)
1030 {
1031     const struct pinmux_drive_reg *drive_regs = info->drive_regs;
1032 #define drive_nfields   ARRAY_SIZE(drive_regs->fields)
1033 #define drive_ofs(i)    drive_regs[(i) / drive_nfields]
1034 #define drive_reg(i)    drive_ofs(i).reg
1035 #define drive_bit(i)    ((i) % drive_nfields)
1036 #define drive_field(i)  drive_ofs(i).fields[drive_bit(i)]
1037     const struct pinmux_bias_reg *bias_regs = info->bias_regs;
1038 #define bias_npins  ARRAY_SIZE(bias_regs->pins)
1039 #define bias_ofs(i) bias_regs[(i) / bias_npins]
1040 #define bias_puen(i)    bias_ofs(i).puen
1041 #define bias_pud(i) bias_ofs(i).pud
1042 #define bias_bit(i) ((i) % bias_npins)
1043 #define bias_pin(i) bias_ofs(i).pins[bias_bit(i)]
1044     const char *drvname = info->name;
1045     unsigned int *refcnts;
1046     unsigned int i, j, k;
1047 
1048     pr_info("sh_pfc: Checking %s\n", drvname);
1049     sh_pfc_num_regs = 0;
1050     sh_pfc_num_enums = 0;
1051     sh_pfc_bias_done = false;
1052     sh_pfc_drive_done = false;
1053     sh_pfc_power_done = false;
1054 
1055     /* Check pins */
1056     for (i = 0; i < info->nr_pins; i++) {
1057         const struct sh_pfc_pin *pin = &info->pins[i];
1058         unsigned int x;
1059 
1060         if (!pin->name) {
1061             sh_pfc_err("empty pin %u\n", i);
1062             continue;
1063         }
1064         for (j = 0; j < i; j++) {
1065             const struct sh_pfc_pin *pin2 = &info->pins[j];
1066 
1067             if (same_name(pin->name, pin2->name))
1068                 sh_pfc_err("pin %s: name conflict\n",
1069                        pin->name);
1070 
1071             if (pin->pin != (u16)-1 && pin->pin == pin2->pin)
1072                 sh_pfc_err("pin %s/%s: pin %u conflict\n",
1073                        pin->name, pin2->name, pin->pin);
1074 
1075             if (pin->enum_id && pin->enum_id == pin2->enum_id)
1076                 sh_pfc_err("pin %s/%s: enum_id %u conflict\n",
1077                        pin->name, pin2->name,
1078                        pin->enum_id);
1079         }
1080 
1081         if (pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) {
1082             if (!info->ops || !info->ops->get_bias ||
1083                 !info->ops->set_bias)
1084                 sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_* flag set but .[gs]et_bias() not implemented\n");
1085 
1086             if (!bias_regs &&
1087                  (!info->ops || !info->ops->pin_to_portcr))
1088                 sh_pfc_err_once(bias, "SH_PFC_PIN_CFG_PULL_UP flag set but no bias_regs defined and .pin_to_portcr() not implemented\n");
1089         }
1090 
1091         if ((pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN) && bias_regs) {
1092             const struct pinmux_bias_reg *bias_reg =
1093                 rcar_pin_to_bias_reg(info, pin->pin, &x);
1094 
1095             if (!bias_reg ||
1096                 ((pin->configs & SH_PFC_PIN_CFG_PULL_UP) &&
1097                  !bias_reg->puen))
1098                 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_UP flag set but pin not in bias_regs\n",
1099                        pin->name);
1100 
1101             if (!bias_reg ||
1102                 ((pin->configs & SH_PFC_PIN_CFG_PULL_DOWN) &&
1103                  !bias_reg->pud))
1104                 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_PULL_DOWN flag set but pin not in bias_regs\n",
1105                        pin->name);
1106         }
1107 
1108         if (pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH) {
1109             if (!drive_regs) {
1110                 sh_pfc_err_once(drive, "SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but drive_regs missing\n");
1111             } else {
1112                 for (j = 0; drive_reg(j); j++) {
1113                     if (!drive_field(j).pin &&
1114                         !drive_field(j).offset &&
1115                         !drive_field(j).size)
1116                         continue;
1117 
1118                     if (drive_field(j).pin == pin->pin)
1119                         break;
1120                 }
1121 
1122                 if (!drive_reg(j))
1123                     sh_pfc_err("pin %s: SH_PFC_PIN_CFG_DRIVE_STRENGTH flag set but not in drive_regs\n",
1124                            pin->name);
1125             }
1126         }
1127 
1128         if (pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE) {
1129             if (!info->ops || !info->ops->pin_to_pocctrl)
1130                 sh_pfc_err_once(power, "SH_PFC_PIN_CFG_IO_VOLTAGE flag set but .pin_to_pocctrl() not implemented\n");
1131             else if (info->ops->pin_to_pocctrl(pin->pin, &x) < 0)
1132                 sh_pfc_err("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE set but invalid pin_to_pocctrl()\n",
1133                        pin->name);
1134         } else if (info->ops && info->ops->pin_to_pocctrl &&
1135                info->ops->pin_to_pocctrl(pin->pin, &x) >= 0) {
1136             sh_pfc_warn("pin %s: SH_PFC_PIN_CFG_IO_VOLTAGE not set but valid pin_to_pocctrl()\n",
1137                     pin->name);
1138         }
1139     }
1140 
1141     /* Check groups and functions */
1142     refcnts = kcalloc(info->nr_groups, sizeof(*refcnts), GFP_KERNEL);
1143     if (!refcnts)
1144         return;
1145 
1146     for (i = 0; i < info->nr_functions; i++) {
1147         const struct sh_pfc_function *func = &info->functions[i];
1148 
1149         if (!func->name) {
1150             sh_pfc_err("empty function %u\n", i);
1151             continue;
1152         }
1153         for (j = 0; j < i; j++) {
1154             if (same_name(func->name, info->functions[j].name))
1155                 sh_pfc_err("function %s: name conflict\n",
1156                        func->name);
1157         }
1158         for (j = 0; j < func->nr_groups; j++) {
1159             for (k = 0; k < info->nr_groups; k++) {
1160                 if (same_name(func->groups[j],
1161                           info->groups[k].name)) {
1162                     refcnts[k]++;
1163                     break;
1164                 }
1165             }
1166 
1167             if (k == info->nr_groups)
1168                 sh_pfc_err("function %s: group %s not found\n",
1169                        func->name, func->groups[j]);
1170         }
1171     }
1172 
1173     for (i = 0; i < info->nr_groups; i++) {
1174         const struct sh_pfc_pin_group *group = &info->groups[i];
1175 
1176         if (!group->name) {
1177             sh_pfc_err("empty group %u\n", i);
1178             continue;
1179         }
1180         for (j = 0; j < i; j++)
1181             sh_pfc_compare_groups(drvname, group, &info->groups[j]);
1182 
1183         if (!refcnts[i])
1184             sh_pfc_err("orphan group %s\n", group->name);
1185         else if (refcnts[i] > 1)
1186             sh_pfc_warn("group %s referenced by %u functions\n",
1187                     group->name, refcnts[i]);
1188     }
1189 
1190     kfree(refcnts);
1191 
1192     /* Check config register descriptions */
1193     for (i = 0; info->cfg_regs && info->cfg_regs[i].reg; i++)
1194         sh_pfc_check_cfg_reg(drvname, &info->cfg_regs[i]);
1195 
1196     /* Check drive strength registers */
1197     for (i = 0; drive_regs && drive_regs[i].reg; i++)
1198         sh_pfc_check_drive_reg(info, &drive_regs[i]);
1199 
1200     for (i = 0; drive_regs && drive_reg(i); i++) {
1201         if (!drive_field(i).pin && !drive_field(i).offset &&
1202             !drive_field(i).size)
1203             continue;
1204 
1205         for (j = 0; j < i; j++) {
1206             if (drive_field(i).pin == drive_field(j).pin &&
1207                 drive_field(j).offset && drive_field(j).size) {
1208                 sh_pfc_err("drive_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",
1209                        drive_reg(i), drive_bit(i),
1210                        drive_reg(j), drive_bit(j));
1211             }
1212         }
1213     }
1214 
1215     /* Check bias registers */
1216     for (i = 0; bias_regs && (bias_regs[i].puen || bias_regs[i].pud); i++)
1217         sh_pfc_check_bias_reg(info, &bias_regs[i]);
1218 
1219     for (i = 0; bias_regs && (bias_puen(i) || bias_pud(i)); i++) {
1220         if (bias_pin(i) == SH_PFC_PIN_NONE)
1221             continue;
1222 
1223         for (j = 0; j < i; j++) {
1224             if (bias_pin(i) != bias_pin(j))
1225                 continue;
1226 
1227             if (bias_puen(i) && bias_puen(j))
1228                 sh_pfc_err("bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",
1229                        bias_puen(i), bias_bit(i),
1230                        bias_puen(j), bias_bit(j));
1231             if (bias_pud(i) && bias_pud(j))
1232                 sh_pfc_err("bias_reg 0x%x:%zu/0x%x:%zu: pin conflict\n",
1233                        bias_pud(i), bias_bit(i),
1234                        bias_pud(j), bias_bit(j));
1235         }
1236     }
1237 
1238     /* Check ioctrl registers */
1239     for (i = 0; info->ioctrl_regs && info->ioctrl_regs[i].reg; i++)
1240         sh_pfc_check_reg(drvname, info->ioctrl_regs[i].reg, U32_MAX);
1241 
1242     /* Check data registers */
1243     for (i = 0; info->data_regs && info->data_regs[i].reg; i++) {
1244         sh_pfc_check_reg(drvname, info->data_regs[i].reg,
1245                  GENMASK(info->data_regs[i].reg_width - 1, 0));
1246         sh_pfc_check_reg_enums(drvname, info->data_regs[i].reg,
1247                        info->data_regs[i].enum_ids,
1248                        info->data_regs[i].reg_width);
1249     }
1250 
1251 #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
1252     /* Check function GPIOs */
1253     for (i = 0; i < info->nr_func_gpios; i++) {
1254         const struct pinmux_func *func = &info->func_gpios[i];
1255 
1256         if (!func->name) {
1257             sh_pfc_err("empty function gpio %u\n", i);
1258             continue;
1259         }
1260         for (j = 0; j < i; j++) {
1261             if (same_name(func->name, info->func_gpios[j].name))
1262                 sh_pfc_err("func_gpio %s: name conflict\n",
1263                        func->name);
1264         }
1265         if (sh_pfc_check_enum(drvname, func->enum_id))
1266             sh_pfc_err("%s enum_id %u conflict\n", func->name,
1267                    func->enum_id);
1268     }
1269 #endif
1270 }
1271 
1272 static void __init sh_pfc_check_driver(const struct platform_driver *pdrv)
1273 {
1274     unsigned int i;
1275 
1276     if (!IS_ENABLED(CONFIG_SUPERH) &&
1277         !of_find_matching_node(NULL, pdrv->driver.of_match_table))
1278         return;
1279 
1280     sh_pfc_regs = kcalloc(SH_PFC_MAX_REGS, sizeof(*sh_pfc_regs),
1281                   GFP_KERNEL);
1282     if (!sh_pfc_regs)
1283         return;
1284 
1285     sh_pfc_enums = kcalloc(SH_PFC_MAX_ENUMS, sizeof(*sh_pfc_enums),
1286                   GFP_KERNEL);
1287     if (!sh_pfc_enums)
1288         goto free_regs;
1289 
1290     pr_warn("sh_pfc: Checking builtin pinmux tables\n");
1291 
1292     for (i = 0; pdrv->id_table[i].name[0]; i++)
1293         sh_pfc_check_info((void *)pdrv->id_table[i].driver_data);
1294 
1295 #ifdef CONFIG_OF
1296     for (i = 0; pdrv->driver.of_match_table[i].compatible[0]; i++)
1297         sh_pfc_check_info(pdrv->driver.of_match_table[i].data);
1298 #endif
1299 
1300     pr_warn("sh_pfc: Detected %u errors and %u warnings\n", sh_pfc_errors,
1301         sh_pfc_warnings);
1302 
1303     kfree(sh_pfc_enums);
1304 free_regs:
1305     kfree(sh_pfc_regs);
1306 }
1307 
1308 #else /* !DEBUG */
1309 static inline void sh_pfc_check_driver(struct platform_driver *pdrv) {}
1310 #endif /* !DEBUG */
1311 
1312 #ifdef CONFIG_OF
1313 static const void *sh_pfc_quirk_match(void)
1314 {
1315 #ifdef CONFIG_PINCTRL_PFC_R8A77950
1316     const struct soc_device_attribute *match;
1317     static const struct soc_device_attribute quirks[] = {
1318         {
1319             .soc_id = "r8a7795", .revision = "ES1.*",
1320             .data = &r8a77950_pinmux_info,
1321         },
1322         { /* sentinel */ }
1323     };
1324 
1325     match = soc_device_match(quirks);
1326     if (match)
1327         return match->data;
1328 #endif /* CONFIG_PINCTRL_PFC_R8A77950 */
1329 
1330     return NULL;
1331 }
1332 #endif /* CONFIG_OF */
1333 
1334 static int sh_pfc_probe(struct platform_device *pdev)
1335 {
1336     const struct sh_pfc_soc_info *info;
1337     struct sh_pfc *pfc;
1338     int ret;
1339 
1340 #ifdef CONFIG_OF
1341     if (pdev->dev.of_node) {
1342         info = sh_pfc_quirk_match();
1343         if (!info)
1344             info = of_device_get_match_data(&pdev->dev);
1345     } else
1346 #endif
1347         info = (const void *)platform_get_device_id(pdev)->driver_data;
1348 
1349     pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL);
1350     if (pfc == NULL)
1351         return -ENOMEM;
1352 
1353     pfc->info = info;
1354     pfc->dev = &pdev->dev;
1355 
1356     ret = sh_pfc_map_resources(pfc, pdev);
1357     if (unlikely(ret < 0))
1358         return ret;
1359 
1360     spin_lock_init(&pfc->lock);
1361 
1362     if (info->ops && info->ops->init) {
1363         ret = info->ops->init(pfc);
1364         if (ret < 0)
1365             return ret;
1366 
1367         /* .init() may have overridden pfc->info */
1368         info = pfc->info;
1369     }
1370 
1371     ret = sh_pfc_suspend_init(pfc);
1372     if (ret)
1373         return ret;
1374 
1375     /* Enable dummy states for those platforms without pinctrl support */
1376     if (!of_have_populated_dt())
1377         pinctrl_provide_dummies();
1378 
1379     ret = sh_pfc_init_ranges(pfc);
1380     if (ret < 0)
1381         return ret;
1382 
1383     /*
1384      * Initialize pinctrl bindings first
1385      */
1386     ret = sh_pfc_register_pinctrl(pfc);
1387     if (unlikely(ret != 0))
1388         return ret;
1389 
1390 #ifdef CONFIG_PINCTRL_SH_PFC_GPIO
1391     /*
1392      * Then the GPIO chip
1393      */
1394     ret = sh_pfc_register_gpiochip(pfc);
1395     if (unlikely(ret != 0)) {
1396         /*
1397          * If the GPIO chip fails to come up we still leave the
1398          * PFC state as it is, given that there are already
1399          * extant users of it that have succeeded by this point.
1400          */
1401         dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
1402     }
1403 #endif
1404 
1405     platform_set_drvdata(pdev, pfc);
1406 
1407     dev_info(pfc->dev, "%s support registered\n", info->name);
1408 
1409     return 0;
1410 }
1411 
1412 static const struct platform_device_id sh_pfc_id_table[] = {
1413 #ifdef CONFIG_PINCTRL_PFC_SH7203
1414     { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
1415 #endif
1416 #ifdef CONFIG_PINCTRL_PFC_SH7264
1417     { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info },
1418 #endif
1419 #ifdef CONFIG_PINCTRL_PFC_SH7269
1420     { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info },
1421 #endif
1422 #ifdef CONFIG_PINCTRL_PFC_SH7720
1423     { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info },
1424 #endif
1425 #ifdef CONFIG_PINCTRL_PFC_SH7722
1426     { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info },
1427 #endif
1428 #ifdef CONFIG_PINCTRL_PFC_SH7723
1429     { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info },
1430 #endif
1431 #ifdef CONFIG_PINCTRL_PFC_SH7724
1432     { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info },
1433 #endif
1434 #ifdef CONFIG_PINCTRL_PFC_SH7734
1435     { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info },
1436 #endif
1437 #ifdef CONFIG_PINCTRL_PFC_SH7757
1438     { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info },
1439 #endif
1440 #ifdef CONFIG_PINCTRL_PFC_SH7785
1441     { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info },
1442 #endif
1443 #ifdef CONFIG_PINCTRL_PFC_SH7786
1444     { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info },
1445 #endif
1446 #ifdef CONFIG_PINCTRL_PFC_SHX3
1447     { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info },
1448 #endif
1449     { },
1450 };
1451 
1452 static struct platform_driver sh_pfc_driver = {
1453     .probe      = sh_pfc_probe,
1454     .id_table   = sh_pfc_id_table,
1455     .driver     = {
1456         .name   = DRV_NAME,
1457         .of_match_table = of_match_ptr(sh_pfc_of_table),
1458         .pm     = DEV_PM_OPS,
1459     },
1460 };
1461 
1462 static int __init sh_pfc_init(void)
1463 {
1464     sh_pfc_check_driver(&sh_pfc_driver);
1465     return platform_driver_register(&sh_pfc_driver);
1466 }
1467 postcore_initcall(sh_pfc_init);
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