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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2015, Sony Mobile Communications AB.
0004  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
0005  */
0006 
0007 #include <linux/module.h>
0008 #include <linux/platform_device.h>
0009 #include <linux/pinctrl/pinctrl.h>
0010 #include <linux/pinctrl/pinmux.h>
0011 #include <linux/pinctrl/pinconf.h>
0012 #include <linux/pinctrl/pinconf-generic.h>
0013 #include <linux/slab.h>
0014 #include <linux/regmap.h>
0015 #include <linux/gpio/driver.h>
0016 #include <linux/interrupt.h>
0017 #include <linux/of_device.h>
0018 #include <linux/of_irq.h>
0019 
0020 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
0021 
0022 #include "../core.h"
0023 #include "../pinctrl-utils.h"
0024 
0025 /* mode */
0026 #define PM8XXX_GPIO_MODE_ENABLED    BIT(0)
0027 #define PM8XXX_GPIO_MODE_INPUT      0
0028 #define PM8XXX_GPIO_MODE_OUTPUT     2
0029 
0030 /* output buffer */
0031 #define PM8XXX_GPIO_PUSH_PULL       0
0032 #define PM8XXX_GPIO_OPEN_DRAIN      1
0033 
0034 /* bias */
0035 #define PM8XXX_GPIO_BIAS_PU_30      0
0036 #define PM8XXX_GPIO_BIAS_PU_1P5     1
0037 #define PM8XXX_GPIO_BIAS_PU_31P5    2
0038 #define PM8XXX_GPIO_BIAS_PU_1P5_30  3
0039 #define PM8XXX_GPIO_BIAS_PD     4
0040 #define PM8XXX_GPIO_BIAS_NP     5
0041 
0042 /* GPIO registers */
0043 #define SSBI_REG_ADDR_GPIO_BASE     0x150
0044 #define SSBI_REG_ADDR_GPIO(n)       (SSBI_REG_ADDR_GPIO_BASE + n)
0045 
0046 #define PM8XXX_BANK_WRITE       BIT(7)
0047 
0048 #define PM8XXX_MAX_GPIOS               44
0049 
0050 #define PM8XXX_GPIO_PHYSICAL_OFFSET 1
0051 
0052 /* custom pinconf parameters */
0053 #define PM8XXX_QCOM_DRIVE_STRENGH      (PIN_CONFIG_END + 1)
0054 #define PM8XXX_QCOM_PULL_UP_STRENGTH   (PIN_CONFIG_END + 2)
0055 
0056 /**
0057  * struct pm8xxx_pin_data - dynamic configuration for a pin
0058  * @reg:               address of the control register
0059  * @power_source:      logical selected voltage source, mapping in static data
0060  *                     is used translate to register values
0061  * @mode:              operating mode for the pin (input/output)
0062  * @open_drain:        output buffer configured as open-drain (vs push-pull)
0063  * @output_value:      configured output value
0064  * @bias:              register view of configured bias
0065  * @pull_up_strength:  placeholder for selected pull up strength
0066  *                     only used to configure bias when pull up is selected
0067  * @output_strength:   selector of output-strength
0068  * @disable:           pin disabled / configured as tristate
0069  * @function:          pinmux selector
0070  * @inverted:          pin logic is inverted
0071  */
0072 struct pm8xxx_pin_data {
0073     unsigned reg;
0074     u8 power_source;
0075     u8 mode;
0076     bool open_drain;
0077     bool output_value;
0078     u8 bias;
0079     u8 pull_up_strength;
0080     u8 output_strength;
0081     bool disable;
0082     u8 function;
0083     bool inverted;
0084 };
0085 
0086 struct pm8xxx_gpio {
0087     struct device *dev;
0088     struct regmap *regmap;
0089     struct pinctrl_dev *pctrl;
0090     struct gpio_chip chip;
0091 
0092     struct pinctrl_desc desc;
0093     unsigned npins;
0094 };
0095 
0096 static const struct pinconf_generic_params pm8xxx_gpio_bindings[] = {
0097     {"qcom,drive-strength",     PM8XXX_QCOM_DRIVE_STRENGH,  0},
0098     {"qcom,pull-up-strength",   PM8XXX_QCOM_PULL_UP_STRENGTH,   0},
0099 };
0100 
0101 #ifdef CONFIG_DEBUG_FS
0102 static const struct pin_config_item pm8xxx_conf_items[ARRAY_SIZE(pm8xxx_gpio_bindings)] = {
0103     PCONFDUMP(PM8XXX_QCOM_DRIVE_STRENGH, "drive-strength", NULL, true),
0104     PCONFDUMP(PM8XXX_QCOM_PULL_UP_STRENGTH,  "pull up strength", NULL, true),
0105 };
0106 #endif
0107 
0108 static const char * const pm8xxx_groups[PM8XXX_MAX_GPIOS] = {
0109     "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
0110     "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
0111     "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
0112     "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
0113     "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
0114     "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
0115     "gpio44",
0116 };
0117 
0118 static const char * const pm8xxx_gpio_functions[] = {
0119     PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED,
0120     PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2,
0121     PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2,
0122     PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4,
0123 };
0124 
0125 static int pm8xxx_read_bank(struct pm8xxx_gpio *pctrl,
0126                 struct pm8xxx_pin_data *pin, int bank)
0127 {
0128     unsigned int val = bank << 4;
0129     int ret;
0130 
0131     ret = regmap_write(pctrl->regmap, pin->reg, val);
0132     if (ret) {
0133         dev_err(pctrl->dev, "failed to select bank %d\n", bank);
0134         return ret;
0135     }
0136 
0137     ret = regmap_read(pctrl->regmap, pin->reg, &val);
0138     if (ret) {
0139         dev_err(pctrl->dev, "failed to read register %d\n", bank);
0140         return ret;
0141     }
0142 
0143     return val;
0144 }
0145 
0146 static int pm8xxx_write_bank(struct pm8xxx_gpio *pctrl,
0147                  struct pm8xxx_pin_data *pin,
0148                  int bank,
0149                  u8 val)
0150 {
0151     int ret;
0152 
0153     val |= PM8XXX_BANK_WRITE;
0154     val |= bank << 4;
0155 
0156     ret = regmap_write(pctrl->regmap, pin->reg, val);
0157     if (ret)
0158         dev_err(pctrl->dev, "failed to write register\n");
0159 
0160     return ret;
0161 }
0162 
0163 static int pm8xxx_get_groups_count(struct pinctrl_dev *pctldev)
0164 {
0165     struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
0166 
0167     return pctrl->npins;
0168 }
0169 
0170 static const char *pm8xxx_get_group_name(struct pinctrl_dev *pctldev,
0171                      unsigned group)
0172 {
0173     return pm8xxx_groups[group];
0174 }
0175 
0176 
0177 static int pm8xxx_get_group_pins(struct pinctrl_dev *pctldev,
0178                  unsigned group,
0179                  const unsigned **pins,
0180                  unsigned *num_pins)
0181 {
0182     struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
0183 
0184     *pins = &pctrl->desc.pins[group].number;
0185     *num_pins = 1;
0186 
0187     return 0;
0188 }
0189 
0190 static const struct pinctrl_ops pm8xxx_pinctrl_ops = {
0191     .get_groups_count   = pm8xxx_get_groups_count,
0192     .get_group_name     = pm8xxx_get_group_name,
0193     .get_group_pins         = pm8xxx_get_group_pins,
0194     .dt_node_to_map     = pinconf_generic_dt_node_to_map_group,
0195     .dt_free_map        = pinctrl_utils_free_map,
0196 };
0197 
0198 static int pm8xxx_get_functions_count(struct pinctrl_dev *pctldev)
0199 {
0200     return ARRAY_SIZE(pm8xxx_gpio_functions);
0201 }
0202 
0203 static const char *pm8xxx_get_function_name(struct pinctrl_dev *pctldev,
0204                         unsigned function)
0205 {
0206     return pm8xxx_gpio_functions[function];
0207 }
0208 
0209 static int pm8xxx_get_function_groups(struct pinctrl_dev *pctldev,
0210                       unsigned function,
0211                       const char * const **groups,
0212                       unsigned * const num_groups)
0213 {
0214     struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
0215 
0216     *groups = pm8xxx_groups;
0217     *num_groups = pctrl->npins;
0218     return 0;
0219 }
0220 
0221 static int pm8xxx_pinmux_set_mux(struct pinctrl_dev *pctldev,
0222                  unsigned function,
0223                  unsigned group)
0224 {
0225     struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
0226     struct pm8xxx_pin_data *pin = pctrl->desc.pins[group].drv_data;
0227     u8 val;
0228 
0229     pin->function = function;
0230     val = pin->function << 1;
0231 
0232     pm8xxx_write_bank(pctrl, pin, 4, val);
0233 
0234     return 0;
0235 }
0236 
0237 static const struct pinmux_ops pm8xxx_pinmux_ops = {
0238     .get_functions_count    = pm8xxx_get_functions_count,
0239     .get_function_name  = pm8xxx_get_function_name,
0240     .get_function_groups    = pm8xxx_get_function_groups,
0241     .set_mux        = pm8xxx_pinmux_set_mux,
0242 };
0243 
0244 static int pm8xxx_pin_config_get(struct pinctrl_dev *pctldev,
0245                  unsigned int offset,
0246                  unsigned long *config)
0247 {
0248     struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
0249     struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
0250     unsigned param = pinconf_to_config_param(*config);
0251     unsigned arg;
0252 
0253     switch (param) {
0254     case PIN_CONFIG_BIAS_DISABLE:
0255         if (pin->bias != PM8XXX_GPIO_BIAS_NP)
0256             return -EINVAL;
0257         arg = 1;
0258         break;
0259     case PIN_CONFIG_BIAS_PULL_DOWN:
0260         if (pin->bias != PM8XXX_GPIO_BIAS_PD)
0261             return -EINVAL;
0262         arg = 1;
0263         break;
0264     case PIN_CONFIG_BIAS_PULL_UP:
0265         if (pin->bias > PM8XXX_GPIO_BIAS_PU_1P5_30)
0266             return -EINVAL;
0267         arg = 1;
0268         break;
0269     case PM8XXX_QCOM_PULL_UP_STRENGTH:
0270         arg = pin->pull_up_strength;
0271         break;
0272     case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
0273         if (!pin->disable)
0274             return -EINVAL;
0275         arg = 1;
0276         break;
0277     case PIN_CONFIG_INPUT_ENABLE:
0278         if (pin->mode != PM8XXX_GPIO_MODE_INPUT)
0279             return -EINVAL;
0280         arg = 1;
0281         break;
0282     case PIN_CONFIG_OUTPUT:
0283         if (pin->mode & PM8XXX_GPIO_MODE_OUTPUT)
0284             arg = pin->output_value;
0285         else
0286             arg = 0;
0287         break;
0288     case PIN_CONFIG_POWER_SOURCE:
0289         arg = pin->power_source;
0290         break;
0291     case PM8XXX_QCOM_DRIVE_STRENGH:
0292         arg = pin->output_strength;
0293         break;
0294     case PIN_CONFIG_DRIVE_PUSH_PULL:
0295         if (pin->open_drain)
0296             return -EINVAL;
0297         arg = 1;
0298         break;
0299     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0300         if (!pin->open_drain)
0301             return -EINVAL;
0302         arg = 1;
0303         break;
0304     default:
0305         return -EINVAL;
0306     }
0307 
0308     *config = pinconf_to_config_packed(param, arg);
0309 
0310     return 0;
0311 }
0312 
0313 static int pm8xxx_pin_config_set(struct pinctrl_dev *pctldev,
0314                  unsigned int offset,
0315                  unsigned long *configs,
0316                  unsigned num_configs)
0317 {
0318     struct pm8xxx_gpio *pctrl = pinctrl_dev_get_drvdata(pctldev);
0319     struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
0320     unsigned param;
0321     unsigned arg;
0322     unsigned i;
0323     u8 banks = 0;
0324     u8 val;
0325 
0326     for (i = 0; i < num_configs; i++) {
0327         param = pinconf_to_config_param(configs[i]);
0328         arg = pinconf_to_config_argument(configs[i]);
0329 
0330         switch (param) {
0331         case PIN_CONFIG_BIAS_DISABLE:
0332             pin->bias = PM8XXX_GPIO_BIAS_NP;
0333             banks |= BIT(2);
0334             pin->disable = 0;
0335             banks |= BIT(3);
0336             break;
0337         case PIN_CONFIG_BIAS_PULL_DOWN:
0338             pin->bias = PM8XXX_GPIO_BIAS_PD;
0339             banks |= BIT(2);
0340             pin->disable = 0;
0341             banks |= BIT(3);
0342             break;
0343         case PM8XXX_QCOM_PULL_UP_STRENGTH:
0344             if (arg > PM8XXX_GPIO_BIAS_PU_1P5_30) {
0345                 dev_err(pctrl->dev, "invalid pull-up strength\n");
0346                 return -EINVAL;
0347             }
0348             pin->pull_up_strength = arg;
0349             fallthrough;
0350         case PIN_CONFIG_BIAS_PULL_UP:
0351             pin->bias = pin->pull_up_strength;
0352             banks |= BIT(2);
0353             pin->disable = 0;
0354             banks |= BIT(3);
0355             break;
0356         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
0357             pin->disable = 1;
0358             banks |= BIT(3);
0359             break;
0360         case PIN_CONFIG_INPUT_ENABLE:
0361             pin->mode = PM8XXX_GPIO_MODE_INPUT;
0362             banks |= BIT(0) | BIT(1);
0363             break;
0364         case PIN_CONFIG_OUTPUT:
0365             pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
0366             pin->output_value = !!arg;
0367             banks |= BIT(0) | BIT(1);
0368             break;
0369         case PIN_CONFIG_POWER_SOURCE:
0370             pin->power_source = arg;
0371             banks |= BIT(0);
0372             break;
0373         case PM8XXX_QCOM_DRIVE_STRENGH:
0374             if (arg > PMIC_GPIO_STRENGTH_LOW) {
0375                 dev_err(pctrl->dev, "invalid drive strength\n");
0376                 return -EINVAL;
0377             }
0378             pin->output_strength = arg;
0379             banks |= BIT(3);
0380             break;
0381         case PIN_CONFIG_DRIVE_PUSH_PULL:
0382             pin->open_drain = 0;
0383             banks |= BIT(1);
0384             break;
0385         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0386             pin->open_drain = 1;
0387             banks |= BIT(1);
0388             break;
0389         default:
0390             dev_err(pctrl->dev,
0391                 "unsupported config parameter: %x\n",
0392                 param);
0393             return -EINVAL;
0394         }
0395     }
0396 
0397     if (banks & BIT(0)) {
0398         val = pin->power_source << 1;
0399         val |= PM8XXX_GPIO_MODE_ENABLED;
0400         pm8xxx_write_bank(pctrl, pin, 0, val);
0401     }
0402 
0403     if (banks & BIT(1)) {
0404         val = pin->mode << 2;
0405         val |= pin->open_drain << 1;
0406         val |= pin->output_value;
0407         pm8xxx_write_bank(pctrl, pin, 1, val);
0408     }
0409 
0410     if (banks & BIT(2)) {
0411         val = pin->bias << 1;
0412         pm8xxx_write_bank(pctrl, pin, 2, val);
0413     }
0414 
0415     if (banks & BIT(3)) {
0416         val = pin->output_strength << 2;
0417         val |= pin->disable;
0418         pm8xxx_write_bank(pctrl, pin, 3, val);
0419     }
0420 
0421     if (banks & BIT(4)) {
0422         val = pin->function << 1;
0423         pm8xxx_write_bank(pctrl, pin, 4, val);
0424     }
0425 
0426     if (banks & BIT(5)) {
0427         val = 0;
0428         if (!pin->inverted)
0429             val |= BIT(3);
0430         pm8xxx_write_bank(pctrl, pin, 5, val);
0431     }
0432 
0433     return 0;
0434 }
0435 
0436 static const struct pinconf_ops pm8xxx_pinconf_ops = {
0437     .is_generic = true,
0438     .pin_config_group_get = pm8xxx_pin_config_get,
0439     .pin_config_group_set = pm8xxx_pin_config_set,
0440 };
0441 
0442 static const struct pinctrl_desc pm8xxx_pinctrl_desc = {
0443     .name = "pm8xxx_gpio",
0444     .pctlops = &pm8xxx_pinctrl_ops,
0445     .pmxops = &pm8xxx_pinmux_ops,
0446     .confops = &pm8xxx_pinconf_ops,
0447     .owner = THIS_MODULE,
0448 };
0449 
0450 static int pm8xxx_gpio_direction_input(struct gpio_chip *chip,
0451                        unsigned offset)
0452 {
0453     struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
0454     struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
0455     u8 val;
0456 
0457     pin->mode = PM8XXX_GPIO_MODE_INPUT;
0458     val = pin->mode << 2;
0459 
0460     pm8xxx_write_bank(pctrl, pin, 1, val);
0461 
0462     return 0;
0463 }
0464 
0465 static int pm8xxx_gpio_direction_output(struct gpio_chip *chip,
0466                     unsigned offset,
0467                     int value)
0468 {
0469     struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
0470     struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
0471     u8 val;
0472 
0473     pin->mode = PM8XXX_GPIO_MODE_OUTPUT;
0474     pin->output_value = !!value;
0475 
0476     val = pin->mode << 2;
0477     val |= pin->open_drain << 1;
0478     val |= pin->output_value;
0479 
0480     pm8xxx_write_bank(pctrl, pin, 1, val);
0481 
0482     return 0;
0483 }
0484 
0485 static int pm8xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
0486 {
0487     struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
0488     struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
0489     int ret, irq;
0490     bool state;
0491 
0492     if (pin->mode == PM8XXX_GPIO_MODE_OUTPUT)
0493         return pin->output_value;
0494 
0495     irq = chip->to_irq(chip, offset);
0496     if (irq >= 0) {
0497         ret = irq_get_irqchip_state(irq, IRQCHIP_STATE_LINE_LEVEL,
0498                         &state);
0499         if (!ret)
0500             ret = !!state;
0501     } else
0502         ret = -EINVAL;
0503 
0504     return ret;
0505 }
0506 
0507 static void pm8xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
0508 {
0509     struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
0510     struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
0511     u8 val;
0512 
0513     pin->output_value = !!value;
0514 
0515     val = pin->mode << 2;
0516     val |= pin->open_drain << 1;
0517     val |= pin->output_value;
0518 
0519     pm8xxx_write_bank(pctrl, pin, 1, val);
0520 }
0521 
0522 static int pm8xxx_gpio_of_xlate(struct gpio_chip *chip,
0523                 const struct of_phandle_args *gpio_desc,
0524                 u32 *flags)
0525 {
0526     if (chip->of_gpio_n_cells < 2)
0527         return -EINVAL;
0528 
0529     if (flags)
0530         *flags = gpio_desc->args[1];
0531 
0532     return gpio_desc->args[0] - PM8XXX_GPIO_PHYSICAL_OFFSET;
0533 }
0534 
0535 
0536 #ifdef CONFIG_DEBUG_FS
0537 #include <linux/seq_file.h>
0538 
0539 static void pm8xxx_gpio_dbg_show_one(struct seq_file *s,
0540                   struct pinctrl_dev *pctldev,
0541                   struct gpio_chip *chip,
0542                   unsigned offset,
0543                   unsigned gpio)
0544 {
0545     struct pm8xxx_gpio *pctrl = gpiochip_get_data(chip);
0546     struct pm8xxx_pin_data *pin = pctrl->desc.pins[offset].drv_data;
0547 
0548     static const char * const modes[] = {
0549         "in", "both", "out", "off"
0550     };
0551     static const char * const biases[] = {
0552         "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
0553         "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
0554     };
0555     static const char * const buffer_types[] = {
0556         "push-pull", "open-drain"
0557     };
0558     static const char * const strengths[] = {
0559         "no", "high", "medium", "low"
0560     };
0561 
0562     seq_printf(s, " gpio%-2d:", offset + PM8XXX_GPIO_PHYSICAL_OFFSET);
0563     if (pin->disable) {
0564         seq_puts(s, " ---");
0565     } else {
0566         seq_printf(s, " %-4s", modes[pin->mode]);
0567         seq_printf(s, " %-7s", pm8xxx_gpio_functions[pin->function]);
0568         seq_printf(s, " VIN%d", pin->power_source);
0569         seq_printf(s, " %-27s", biases[pin->bias]);
0570         seq_printf(s, " %-10s", buffer_types[pin->open_drain]);
0571         seq_printf(s, " %-4s", pin->output_value ? "high" : "low");
0572         seq_printf(s, " %-7s", strengths[pin->output_strength]);
0573         if (pin->inverted)
0574             seq_puts(s, " inverted");
0575     }
0576 }
0577 
0578 static void pm8xxx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
0579 {
0580     unsigned gpio = chip->base;
0581     unsigned i;
0582 
0583     for (i = 0; i < chip->ngpio; i++, gpio++) {
0584         pm8xxx_gpio_dbg_show_one(s, NULL, chip, i, gpio);
0585         seq_puts(s, "\n");
0586     }
0587 }
0588 
0589 #else
0590 #define pm8xxx_gpio_dbg_show NULL
0591 #endif
0592 
0593 static const struct gpio_chip pm8xxx_gpio_template = {
0594     .direction_input = pm8xxx_gpio_direction_input,
0595     .direction_output = pm8xxx_gpio_direction_output,
0596     .get = pm8xxx_gpio_get,
0597     .set = pm8xxx_gpio_set,
0598     .of_xlate = pm8xxx_gpio_of_xlate,
0599     .dbg_show = pm8xxx_gpio_dbg_show,
0600     .owner = THIS_MODULE,
0601 };
0602 
0603 static int pm8xxx_pin_populate(struct pm8xxx_gpio *pctrl,
0604                    struct pm8xxx_pin_data *pin)
0605 {
0606     int val;
0607 
0608     val = pm8xxx_read_bank(pctrl, pin, 0);
0609     if (val < 0)
0610         return val;
0611 
0612     pin->power_source = (val >> 1) & 0x7;
0613 
0614     val = pm8xxx_read_bank(pctrl, pin, 1);
0615     if (val < 0)
0616         return val;
0617 
0618     pin->mode = (val >> 2) & 0x3;
0619     pin->open_drain = !!(val & BIT(1));
0620     pin->output_value = val & BIT(0);
0621 
0622     val = pm8xxx_read_bank(pctrl, pin, 2);
0623     if (val < 0)
0624         return val;
0625 
0626     pin->bias = (val >> 1) & 0x7;
0627     if (pin->bias <= PM8XXX_GPIO_BIAS_PU_1P5_30)
0628         pin->pull_up_strength = pin->bias;
0629     else
0630         pin->pull_up_strength = PM8XXX_GPIO_BIAS_PU_30;
0631 
0632     val = pm8xxx_read_bank(pctrl, pin, 3);
0633     if (val < 0)
0634         return val;
0635 
0636     pin->output_strength = (val >> 2) & 0x3;
0637     pin->disable = val & BIT(0);
0638 
0639     val = pm8xxx_read_bank(pctrl, pin, 4);
0640     if (val < 0)
0641         return val;
0642 
0643     pin->function = (val >> 1) & 0x7;
0644 
0645     val = pm8xxx_read_bank(pctrl, pin, 5);
0646     if (val < 0)
0647         return val;
0648 
0649     pin->inverted = !(val & BIT(3));
0650 
0651     return 0;
0652 }
0653 
0654 static struct irq_chip pm8xxx_irq_chip = {
0655     .name = "ssbi-gpio",
0656     .irq_mask_ack = irq_chip_mask_ack_parent,
0657     .irq_unmask = irq_chip_unmask_parent,
0658     .irq_set_type = irq_chip_set_type_parent,
0659     .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
0660 };
0661 
0662 static int pm8xxx_domain_translate(struct irq_domain *domain,
0663                    struct irq_fwspec *fwspec,
0664                    unsigned long *hwirq,
0665                    unsigned int *type)
0666 {
0667     struct pm8xxx_gpio *pctrl = container_of(domain->host_data,
0668                          struct pm8xxx_gpio, chip);
0669 
0670     if (fwspec->param_count != 2 || fwspec->param[0] < 1 ||
0671         fwspec->param[0] > pctrl->chip.ngpio)
0672         return -EINVAL;
0673 
0674     *hwirq = fwspec->param[0] - PM8XXX_GPIO_PHYSICAL_OFFSET;
0675     *type = fwspec->param[1];
0676 
0677     return 0;
0678 }
0679 
0680 static unsigned int pm8xxx_child_offset_to_irq(struct gpio_chip *chip,
0681                            unsigned int offset)
0682 {
0683     return offset + PM8XXX_GPIO_PHYSICAL_OFFSET;
0684 }
0685 
0686 static int pm8xxx_child_to_parent_hwirq(struct gpio_chip *chip,
0687                     unsigned int child_hwirq,
0688                     unsigned int child_type,
0689                     unsigned int *parent_hwirq,
0690                     unsigned int *parent_type)
0691 {
0692     *parent_hwirq = child_hwirq + 0xc0;
0693     *parent_type = child_type;
0694 
0695     return 0;
0696 }
0697 
0698 static const struct of_device_id pm8xxx_gpio_of_match[] = {
0699     { .compatible = "qcom,pm8018-gpio", .data = (void *) 6 },
0700     { .compatible = "qcom,pm8038-gpio", .data = (void *) 12 },
0701     { .compatible = "qcom,pm8058-gpio", .data = (void *) 44 },
0702     { .compatible = "qcom,pm8917-gpio", .data = (void *) 38 },
0703     { .compatible = "qcom,pm8921-gpio", .data = (void *) 44 },
0704     { },
0705 };
0706 MODULE_DEVICE_TABLE(of, pm8xxx_gpio_of_match);
0707 
0708 static int pm8xxx_gpio_probe(struct platform_device *pdev)
0709 {
0710     struct pm8xxx_pin_data *pin_data;
0711     struct irq_domain *parent_domain;
0712     struct device_node *parent_node;
0713     struct pinctrl_pin_desc *pins;
0714     struct gpio_irq_chip *girq;
0715     struct pm8xxx_gpio *pctrl;
0716     int ret, i;
0717 
0718     pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
0719     if (!pctrl)
0720         return -ENOMEM;
0721 
0722     pctrl->dev = &pdev->dev;
0723     pctrl->npins = (uintptr_t) device_get_match_data(&pdev->dev);
0724 
0725     pctrl->regmap = dev_get_regmap(pdev->dev.parent, NULL);
0726     if (!pctrl->regmap) {
0727         dev_err(&pdev->dev, "parent regmap unavailable\n");
0728         return -ENXIO;
0729     }
0730 
0731     pctrl->desc = pm8xxx_pinctrl_desc;
0732     pctrl->desc.npins = pctrl->npins;
0733 
0734     pins = devm_kcalloc(&pdev->dev,
0735                 pctrl->desc.npins,
0736                 sizeof(struct pinctrl_pin_desc),
0737                 GFP_KERNEL);
0738     if (!pins)
0739         return -ENOMEM;
0740 
0741     pin_data = devm_kcalloc(&pdev->dev,
0742                 pctrl->desc.npins,
0743                 sizeof(struct pm8xxx_pin_data),
0744                 GFP_KERNEL);
0745     if (!pin_data)
0746         return -ENOMEM;
0747 
0748     for (i = 0; i < pctrl->desc.npins; i++) {
0749         pin_data[i].reg = SSBI_REG_ADDR_GPIO(i);
0750 
0751         ret = pm8xxx_pin_populate(pctrl, &pin_data[i]);
0752         if (ret)
0753             return ret;
0754 
0755         pins[i].number = i;
0756         pins[i].name = pm8xxx_groups[i];
0757         pins[i].drv_data = &pin_data[i];
0758     }
0759     pctrl->desc.pins = pins;
0760 
0761     pctrl->desc.num_custom_params = ARRAY_SIZE(pm8xxx_gpio_bindings);
0762     pctrl->desc.custom_params = pm8xxx_gpio_bindings;
0763 #ifdef CONFIG_DEBUG_FS
0764     pctrl->desc.custom_conf_items = pm8xxx_conf_items;
0765 #endif
0766 
0767     pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
0768     if (IS_ERR(pctrl->pctrl)) {
0769         dev_err(&pdev->dev, "couldn't register pm8xxx gpio driver\n");
0770         return PTR_ERR(pctrl->pctrl);
0771     }
0772 
0773     pctrl->chip = pm8xxx_gpio_template;
0774     pctrl->chip.base = -1;
0775     pctrl->chip.parent = &pdev->dev;
0776     pctrl->chip.of_gpio_n_cells = 2;
0777     pctrl->chip.label = dev_name(pctrl->dev);
0778     pctrl->chip.ngpio = pctrl->npins;
0779 
0780     parent_node = of_irq_find_parent(pctrl->dev->of_node);
0781     if (!parent_node)
0782         return -ENXIO;
0783 
0784     parent_domain = irq_find_host(parent_node);
0785     of_node_put(parent_node);
0786     if (!parent_domain)
0787         return -ENXIO;
0788 
0789     girq = &pctrl->chip.irq;
0790     girq->chip = &pm8xxx_irq_chip;
0791     girq->default_type = IRQ_TYPE_NONE;
0792     girq->handler = handle_level_irq;
0793     girq->fwnode = of_node_to_fwnode(pctrl->dev->of_node);
0794     girq->parent_domain = parent_domain;
0795     girq->child_to_parent_hwirq = pm8xxx_child_to_parent_hwirq;
0796     girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_twocell;
0797     girq->child_offset_to_irq = pm8xxx_child_offset_to_irq;
0798     girq->child_irq_domain_ops.translate = pm8xxx_domain_translate;
0799 
0800     ret = gpiochip_add_data(&pctrl->chip, pctrl);
0801     if (ret) {
0802         dev_err(&pdev->dev, "failed register gpiochip\n");
0803         return ret;
0804     }
0805 
0806     /*
0807      * For DeviceTree-supported systems, the gpio core checks the
0808      * pinctrl's device node for the "gpio-ranges" property.
0809      * If it is present, it takes care of adding the pin ranges
0810      * for the driver. In this case the driver can skip ahead.
0811      *
0812      * In order to remain compatible with older, existing DeviceTree
0813      * files which don't set the "gpio-ranges" property or systems that
0814      * utilize ACPI the driver has to call gpiochip_add_pin_range().
0815      */
0816     if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
0817         ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
0818                          0, 0, pctrl->chip.ngpio);
0819         if (ret) {
0820             dev_err(pctrl->dev, "failed to add pin range\n");
0821             goto unregister_gpiochip;
0822         }
0823     }
0824 
0825     platform_set_drvdata(pdev, pctrl);
0826 
0827     dev_dbg(&pdev->dev, "Qualcomm pm8xxx gpio driver probed\n");
0828 
0829     return 0;
0830 
0831 unregister_gpiochip:
0832     gpiochip_remove(&pctrl->chip);
0833 
0834     return ret;
0835 }
0836 
0837 static int pm8xxx_gpio_remove(struct platform_device *pdev)
0838 {
0839     struct pm8xxx_gpio *pctrl = platform_get_drvdata(pdev);
0840 
0841     gpiochip_remove(&pctrl->chip);
0842 
0843     return 0;
0844 }
0845 
0846 static struct platform_driver pm8xxx_gpio_driver = {
0847     .driver = {
0848         .name = "qcom-ssbi-gpio",
0849         .of_match_table = pm8xxx_gpio_of_match,
0850     },
0851     .probe = pm8xxx_gpio_probe,
0852     .remove = pm8xxx_gpio_remove,
0853 };
0854 
0855 module_platform_driver(pm8xxx_gpio_driver);
0856 
0857 MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
0858 MODULE_DESCRIPTION("Qualcomm PM8xxx GPIO driver");
0859 MODULE_LICENSE("GPL v2");
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