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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2012-2014, 2016-2021 The Linux Foundation. All rights reserved.
0004  */
0005 
0006 #include <linux/gpio/driver.h>
0007 #include <linux/interrupt.h>
0008 #include <linux/module.h>
0009 #include <linux/of.h>
0010 #include <linux/of_irq.h>
0011 #include <linux/pinctrl/pinconf-generic.h>
0012 #include <linux/pinctrl/pinconf.h>
0013 #include <linux/pinctrl/pinmux.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/regmap.h>
0016 #include <linux/slab.h>
0017 #include <linux/spmi.h>
0018 #include <linux/types.h>
0019 
0020 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
0021 
0022 #include "../core.h"
0023 #include "../pinctrl-utils.h"
0024 
0025 #define PMIC_GPIO_ADDRESS_RANGE         0x100
0026 
0027 /* type and subtype registers base address offsets */
0028 #define PMIC_GPIO_REG_TYPE          0x4
0029 #define PMIC_GPIO_REG_SUBTYPE           0x5
0030 
0031 /* GPIO peripheral type and subtype out_values */
0032 #define PMIC_GPIO_TYPE              0x10
0033 #define PMIC_GPIO_SUBTYPE_GPIO_4CH      0x1
0034 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH     0x5
0035 #define PMIC_GPIO_SUBTYPE_GPIO_8CH      0x9
0036 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH     0xd
0037 #define PMIC_GPIO_SUBTYPE_GPIO_LV       0x10
0038 #define PMIC_GPIO_SUBTYPE_GPIO_MV       0x11
0039 
0040 #define PMIC_MPP_REG_RT_STS         0x10
0041 #define PMIC_MPP_REG_RT_STS_VAL_MASK        0x1
0042 
0043 /* control register base address offsets */
0044 #define PMIC_GPIO_REG_MODE_CTL          0x40
0045 #define PMIC_GPIO_REG_DIG_VIN_CTL       0x41
0046 #define PMIC_GPIO_REG_DIG_PULL_CTL      0x42
0047 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL  0x44
0048 #define PMIC_GPIO_REG_DIG_IN_CTL        0x43
0049 #define PMIC_GPIO_REG_DIG_OUT_CTL       0x45
0050 #define PMIC_GPIO_REG_EN_CTL            0x46
0051 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL   0x4A
0052 
0053 /* PMIC_GPIO_REG_MODE_CTL */
0054 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT      0x1
0055 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT   1
0056 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK    0x7
0057 #define PMIC_GPIO_REG_MODE_DIR_SHIFT        4
0058 #define PMIC_GPIO_REG_MODE_DIR_MASK     0x7
0059 
0060 #define PMIC_GPIO_MODE_DIGITAL_INPUT        0
0061 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT       1
0062 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2
0063 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU     3
0064 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK   0x3
0065 
0066 /* PMIC_GPIO_REG_DIG_VIN_CTL */
0067 #define PMIC_GPIO_REG_VIN_SHIFT         0
0068 #define PMIC_GPIO_REG_VIN_MASK          0x7
0069 
0070 /* PMIC_GPIO_REG_DIG_PULL_CTL */
0071 #define PMIC_GPIO_REG_PULL_SHIFT        0
0072 #define PMIC_GPIO_REG_PULL_MASK         0x7
0073 
0074 #define PMIC_GPIO_PULL_DOWN         4
0075 #define PMIC_GPIO_PULL_DISABLE          5
0076 
0077 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
0078 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT       0x80
0079 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7
0080 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK  0xF
0081 
0082 /* PMIC_GPIO_REG_DIG_IN_CTL */
0083 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN     0x80
0084 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK   0x7
0085 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK     0xf
0086 
0087 /* PMIC_GPIO_REG_DIG_OUT_CTL */
0088 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT    0
0089 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK     0x3
0090 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT        4
0091 #define PMIC_GPIO_REG_OUT_TYPE_MASK     0x3
0092 
0093 /*
0094  * Output type - indicates pin should be configured as push-pull,
0095  * open drain or open source.
0096  */
0097 #define PMIC_GPIO_OUT_BUF_CMOS          0
0098 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS   1
0099 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS   2
0100 
0101 /* PMIC_GPIO_REG_EN_CTL */
0102 #define PMIC_GPIO_REG_MASTER_EN_SHIFT       7
0103 
0104 #define PMIC_GPIO_PHYSICAL_OFFSET       1
0105 
0106 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
0107 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK        0x3
0108 
0109 /* Qualcomm specific pin configurations */
0110 #define PMIC_GPIO_CONF_PULL_UP          (PIN_CONFIG_END + 1)
0111 #define PMIC_GPIO_CONF_STRENGTH         (PIN_CONFIG_END + 2)
0112 #define PMIC_GPIO_CONF_ATEST            (PIN_CONFIG_END + 3)
0113 #define PMIC_GPIO_CONF_ANALOG_PASS      (PIN_CONFIG_END + 4)
0114 #define PMIC_GPIO_CONF_DTEST_BUFFER     (PIN_CONFIG_END + 5)
0115 
0116 /* The index of each function in pmic_gpio_functions[] array */
0117 enum pmic_gpio_func_index {
0118     PMIC_GPIO_FUNC_INDEX_NORMAL,
0119     PMIC_GPIO_FUNC_INDEX_PAIRED,
0120     PMIC_GPIO_FUNC_INDEX_FUNC1,
0121     PMIC_GPIO_FUNC_INDEX_FUNC2,
0122     PMIC_GPIO_FUNC_INDEX_FUNC3,
0123     PMIC_GPIO_FUNC_INDEX_FUNC4,
0124     PMIC_GPIO_FUNC_INDEX_DTEST1,
0125     PMIC_GPIO_FUNC_INDEX_DTEST2,
0126     PMIC_GPIO_FUNC_INDEX_DTEST3,
0127     PMIC_GPIO_FUNC_INDEX_DTEST4,
0128 };
0129 
0130 /**
0131  * struct pmic_gpio_pad - keep current GPIO settings
0132  * @base: Address base in SPMI device.
0133  * @is_enabled: Set to false when GPIO should be put in high Z state.
0134  * @out_value: Cached pin output value
0135  * @have_buffer: Set to true if GPIO output could be configured in push-pull,
0136  *  open-drain or open-source mode.
0137  * @output_enabled: Set to true if GPIO output logic is enabled.
0138  * @input_enabled: Set to true if GPIO input buffer logic is enabled.
0139  * @analog_pass: Set to true if GPIO is in analog-pass-through mode.
0140  * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
0141  * @num_sources: Number of power-sources supported by this GPIO.
0142  * @power_source: Current power-source used.
0143  * @buffer_type: Push-pull, open-drain or open-source.
0144  * @pullup: Constant current which flow trough GPIO output buffer.
0145  * @strength: No, Low, Medium, High
0146  * @function: See pmic_gpio_functions[]
0147  * @atest: the ATEST selection for GPIO analog-pass-through mode
0148  * @dtest_buffer: the DTEST buffer selection for digital input mode.
0149  */
0150 struct pmic_gpio_pad {
0151     u16     base;
0152     bool        is_enabled;
0153     bool        out_value;
0154     bool        have_buffer;
0155     bool        output_enabled;
0156     bool        input_enabled;
0157     bool        analog_pass;
0158     bool        lv_mv_type;
0159     unsigned int    num_sources;
0160     unsigned int    power_source;
0161     unsigned int    buffer_type;
0162     unsigned int    pullup;
0163     unsigned int    strength;
0164     unsigned int    function;
0165     unsigned int    atest;
0166     unsigned int    dtest_buffer;
0167 };
0168 
0169 struct pmic_gpio_state {
0170     struct device   *dev;
0171     struct regmap   *map;
0172     struct pinctrl_dev *ctrl;
0173     struct gpio_chip chip;
0174     struct irq_chip irq;
0175     u8 usid;
0176     u8 pid_base;
0177 };
0178 
0179 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
0180     {"qcom,pull-up-strength",   PMIC_GPIO_CONF_PULL_UP,     0},
0181     {"qcom,drive-strength",     PMIC_GPIO_CONF_STRENGTH,    0},
0182     {"qcom,atest",          PMIC_GPIO_CONF_ATEST,       0},
0183     {"qcom,analog-pass",        PMIC_GPIO_CONF_ANALOG_PASS, 0},
0184     {"qcom,dtest-buffer",           PMIC_GPIO_CONF_DTEST_BUFFER,    0},
0185 };
0186 
0187 #ifdef CONFIG_DEBUG_FS
0188 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
0189     PCONFDUMP(PMIC_GPIO_CONF_PULL_UP,  "pull up strength", NULL, true),
0190     PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
0191     PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
0192     PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
0193     PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
0194 };
0195 #endif
0196 
0197 static const char *const pmic_gpio_groups[] = {
0198     "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
0199     "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
0200     "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
0201     "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
0202     "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
0203 };
0204 
0205 static const char *const pmic_gpio_functions[] = {
0206     [PMIC_GPIO_FUNC_INDEX_NORMAL]   = PMIC_GPIO_FUNC_NORMAL,
0207     [PMIC_GPIO_FUNC_INDEX_PAIRED]   = PMIC_GPIO_FUNC_PAIRED,
0208     [PMIC_GPIO_FUNC_INDEX_FUNC1]    = PMIC_GPIO_FUNC_FUNC1,
0209     [PMIC_GPIO_FUNC_INDEX_FUNC2]    = PMIC_GPIO_FUNC_FUNC2,
0210     [PMIC_GPIO_FUNC_INDEX_FUNC3]    = PMIC_GPIO_FUNC_FUNC3,
0211     [PMIC_GPIO_FUNC_INDEX_FUNC4]    = PMIC_GPIO_FUNC_FUNC4,
0212     [PMIC_GPIO_FUNC_INDEX_DTEST1]   = PMIC_GPIO_FUNC_DTEST1,
0213     [PMIC_GPIO_FUNC_INDEX_DTEST2]   = PMIC_GPIO_FUNC_DTEST2,
0214     [PMIC_GPIO_FUNC_INDEX_DTEST3]   = PMIC_GPIO_FUNC_DTEST3,
0215     [PMIC_GPIO_FUNC_INDEX_DTEST4]   = PMIC_GPIO_FUNC_DTEST4,
0216 };
0217 
0218 static int pmic_gpio_read(struct pmic_gpio_state *state,
0219               struct pmic_gpio_pad *pad, unsigned int addr)
0220 {
0221     unsigned int val;
0222     int ret;
0223 
0224     ret = regmap_read(state->map, pad->base + addr, &val);
0225     if (ret < 0)
0226         dev_err(state->dev, "read 0x%x failed\n", addr);
0227     else
0228         ret = val;
0229 
0230     return ret;
0231 }
0232 
0233 static int pmic_gpio_write(struct pmic_gpio_state *state,
0234                struct pmic_gpio_pad *pad, unsigned int addr,
0235                unsigned int val)
0236 {
0237     int ret;
0238 
0239     ret = regmap_write(state->map, pad->base + addr, val);
0240     if (ret < 0)
0241         dev_err(state->dev, "write 0x%x failed\n", addr);
0242 
0243     return ret;
0244 }
0245 
0246 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
0247 {
0248     /* Every PIN is a group */
0249     return pctldev->desc->npins;
0250 }
0251 
0252 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
0253                         unsigned pin)
0254 {
0255     return pctldev->desc->pins[pin].name;
0256 }
0257 
0258 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
0259                     const unsigned **pins, unsigned *num_pins)
0260 {
0261     *pins = &pctldev->desc->pins[pin].number;
0262     *num_pins = 1;
0263     return 0;
0264 }
0265 
0266 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
0267     .get_groups_count   = pmic_gpio_get_groups_count,
0268     .get_group_name     = pmic_gpio_get_group_name,
0269     .get_group_pins     = pmic_gpio_get_group_pins,
0270     .dt_node_to_map     = pinconf_generic_dt_node_to_map_group,
0271     .dt_free_map        = pinctrl_utils_free_map,
0272 };
0273 
0274 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
0275 {
0276     return ARRAY_SIZE(pmic_gpio_functions);
0277 }
0278 
0279 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
0280                            unsigned function)
0281 {
0282     return pmic_gpio_functions[function];
0283 }
0284 
0285 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
0286                      unsigned function,
0287                      const char *const **groups,
0288                      unsigned *const num_qgroups)
0289 {
0290     *groups = pmic_gpio_groups;
0291     *num_qgroups = pctldev->desc->npins;
0292     return 0;
0293 }
0294 
0295 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
0296                 unsigned pin)
0297 {
0298     struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
0299     struct pmic_gpio_pad *pad;
0300     unsigned int val;
0301     int ret;
0302 
0303     if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
0304         pr_err("function: %d is not defined\n", function);
0305         return -EINVAL;
0306     }
0307 
0308     pad = pctldev->desc->pins[pin].drv_data;
0309     /*
0310      * Non-LV/MV subtypes only support 2 special functions,
0311      * offsetting the dtestx function values by 2
0312      */
0313     if (!pad->lv_mv_type) {
0314         if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
0315                 function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
0316             pr_err("LV/MV subtype doesn't have func3/func4\n");
0317             return -EINVAL;
0318         }
0319         if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
0320             function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
0321                     PMIC_GPIO_FUNC_INDEX_FUNC3);
0322     }
0323 
0324     pad->function = function;
0325 
0326     if (pad->analog_pass)
0327         val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
0328     else if (pad->output_enabled && pad->input_enabled)
0329         val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
0330     else if (pad->output_enabled)
0331         val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
0332     else
0333         val = PMIC_GPIO_MODE_DIGITAL_INPUT;
0334 
0335     if (pad->lv_mv_type) {
0336         ret = pmic_gpio_write(state, pad,
0337                 PMIC_GPIO_REG_MODE_CTL, val);
0338         if (ret < 0)
0339             return ret;
0340 
0341         val = pad->atest - 1;
0342         ret = pmic_gpio_write(state, pad,
0343                 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
0344         if (ret < 0)
0345             return ret;
0346 
0347         val = pad->out_value
0348             << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
0349         val |= pad->function
0350             & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
0351         ret = pmic_gpio_write(state, pad,
0352             PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
0353         if (ret < 0)
0354             return ret;
0355     } else {
0356         val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
0357         val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
0358         val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
0359 
0360         ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
0361         if (ret < 0)
0362             return ret;
0363     }
0364 
0365     val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
0366 
0367     return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
0368 }
0369 
0370 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
0371     .get_functions_count    = pmic_gpio_get_functions_count,
0372     .get_function_name  = pmic_gpio_get_function_name,
0373     .get_function_groups    = pmic_gpio_get_function_groups,
0374     .set_mux        = pmic_gpio_set_mux,
0375 };
0376 
0377 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
0378                 unsigned int pin, unsigned long *config)
0379 {
0380     unsigned param = pinconf_to_config_param(*config);
0381     struct pmic_gpio_pad *pad;
0382     unsigned arg;
0383 
0384     pad = pctldev->desc->pins[pin].drv_data;
0385 
0386     switch (param) {
0387     case PIN_CONFIG_DRIVE_PUSH_PULL:
0388         if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
0389             return -EINVAL;
0390         arg = 1;
0391         break;
0392     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0393         if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
0394             return -EINVAL;
0395         arg = 1;
0396         break;
0397     case PIN_CONFIG_DRIVE_OPEN_SOURCE:
0398         if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
0399             return -EINVAL;
0400         arg = 1;
0401         break;
0402     case PIN_CONFIG_BIAS_PULL_DOWN:
0403         if (pad->pullup != PMIC_GPIO_PULL_DOWN)
0404             return -EINVAL;
0405         arg = 1;
0406         break;
0407     case PIN_CONFIG_BIAS_DISABLE:
0408         if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
0409             return -EINVAL;
0410         arg = 1;
0411         break;
0412     case PIN_CONFIG_BIAS_PULL_UP:
0413         if (pad->pullup != PMIC_GPIO_PULL_UP_30)
0414             return -EINVAL;
0415         arg = 1;
0416         break;
0417     case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
0418         if (pad->is_enabled)
0419             return -EINVAL;
0420         arg = 1;
0421         break;
0422     case PIN_CONFIG_POWER_SOURCE:
0423         arg = pad->power_source;
0424         break;
0425     case PIN_CONFIG_INPUT_ENABLE:
0426         if (!pad->input_enabled)
0427             return -EINVAL;
0428         arg = 1;
0429         break;
0430     case PIN_CONFIG_OUTPUT_ENABLE:
0431         arg = pad->output_enabled;
0432         break;
0433     case PIN_CONFIG_OUTPUT:
0434         arg = pad->out_value;
0435         break;
0436     case PMIC_GPIO_CONF_PULL_UP:
0437         arg = pad->pullup;
0438         break;
0439     case PMIC_GPIO_CONF_STRENGTH:
0440         arg = pad->strength;
0441         break;
0442     case PMIC_GPIO_CONF_ATEST:
0443         arg = pad->atest;
0444         break;
0445     case PMIC_GPIO_CONF_ANALOG_PASS:
0446         arg = pad->analog_pass;
0447         break;
0448     case PMIC_GPIO_CONF_DTEST_BUFFER:
0449         arg = pad->dtest_buffer;
0450         break;
0451     default:
0452         return -EINVAL;
0453     }
0454 
0455     *config = pinconf_to_config_packed(param, arg);
0456     return 0;
0457 }
0458 
0459 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
0460                 unsigned long *configs, unsigned nconfs)
0461 {
0462     struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
0463     struct pmic_gpio_pad *pad;
0464     unsigned param, arg;
0465     unsigned int val;
0466     int i, ret;
0467 
0468     pad = pctldev->desc->pins[pin].drv_data;
0469 
0470     pad->is_enabled = true;
0471     for (i = 0; i < nconfs; i++) {
0472         param = pinconf_to_config_param(configs[i]);
0473         arg = pinconf_to_config_argument(configs[i]);
0474 
0475         switch (param) {
0476         case PIN_CONFIG_DRIVE_PUSH_PULL:
0477             pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
0478             break;
0479         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0480             if (!pad->have_buffer)
0481                 return -EINVAL;
0482             pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
0483             break;
0484         case PIN_CONFIG_DRIVE_OPEN_SOURCE:
0485             if (!pad->have_buffer)
0486                 return -EINVAL;
0487             pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
0488             break;
0489         case PIN_CONFIG_BIAS_DISABLE:
0490             pad->pullup = PMIC_GPIO_PULL_DISABLE;
0491             break;
0492         case PIN_CONFIG_BIAS_PULL_UP:
0493             pad->pullup = PMIC_GPIO_PULL_UP_30;
0494             break;
0495         case PIN_CONFIG_BIAS_PULL_DOWN:
0496             if (arg)
0497                 pad->pullup = PMIC_GPIO_PULL_DOWN;
0498             else
0499                 pad->pullup = PMIC_GPIO_PULL_DISABLE;
0500             break;
0501         case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
0502             pad->is_enabled = false;
0503             break;
0504         case PIN_CONFIG_POWER_SOURCE:
0505             if (arg >= pad->num_sources)
0506                 return -EINVAL;
0507             pad->power_source = arg;
0508             break;
0509         case PIN_CONFIG_INPUT_ENABLE:
0510             pad->input_enabled = arg ? true : false;
0511             break;
0512         case PIN_CONFIG_OUTPUT_ENABLE:
0513             pad->output_enabled = arg ? true : false;
0514             break;
0515         case PIN_CONFIG_OUTPUT:
0516             pad->output_enabled = true;
0517             pad->out_value = arg;
0518             break;
0519         case PMIC_GPIO_CONF_PULL_UP:
0520             if (arg > PMIC_GPIO_PULL_UP_1P5_30)
0521                 return -EINVAL;
0522             pad->pullup = arg;
0523             break;
0524         case PMIC_GPIO_CONF_STRENGTH:
0525             if (arg > PMIC_GPIO_STRENGTH_LOW)
0526                 return -EINVAL;
0527             pad->strength = arg;
0528             break;
0529         case PMIC_GPIO_CONF_ATEST:
0530             if (!pad->lv_mv_type || arg > 4)
0531                 return -EINVAL;
0532             pad->atest = arg;
0533             break;
0534         case PMIC_GPIO_CONF_ANALOG_PASS:
0535             if (!pad->lv_mv_type)
0536                 return -EINVAL;
0537             pad->analog_pass = true;
0538             break;
0539         case PMIC_GPIO_CONF_DTEST_BUFFER:
0540             if (arg > 4)
0541                 return -EINVAL;
0542             pad->dtest_buffer = arg;
0543             break;
0544         default:
0545             return -EINVAL;
0546         }
0547     }
0548 
0549     val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
0550 
0551     ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
0552     if (ret < 0)
0553         return ret;
0554 
0555     val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
0556 
0557     ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
0558     if (ret < 0)
0559         return ret;
0560 
0561     val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
0562     val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
0563 
0564     ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
0565     if (ret < 0)
0566         return ret;
0567 
0568     if (pad->dtest_buffer == 0) {
0569         val = 0;
0570     } else {
0571         if (pad->lv_mv_type) {
0572             val = pad->dtest_buffer - 1;
0573             val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
0574         } else {
0575             val = BIT(pad->dtest_buffer - 1);
0576         }
0577     }
0578     ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
0579     if (ret < 0)
0580         return ret;
0581 
0582     if (pad->analog_pass)
0583         val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
0584     else if (pad->output_enabled && pad->input_enabled)
0585         val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
0586     else if (pad->output_enabled)
0587         val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
0588     else
0589         val = PMIC_GPIO_MODE_DIGITAL_INPUT;
0590 
0591     if (pad->lv_mv_type) {
0592         ret = pmic_gpio_write(state, pad,
0593                 PMIC_GPIO_REG_MODE_CTL, val);
0594         if (ret < 0)
0595             return ret;
0596 
0597         val = pad->atest - 1;
0598         ret = pmic_gpio_write(state, pad,
0599                 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
0600         if (ret < 0)
0601             return ret;
0602 
0603         val = pad->out_value
0604             << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
0605         val |= pad->function
0606             & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
0607         ret = pmic_gpio_write(state, pad,
0608             PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
0609         if (ret < 0)
0610             return ret;
0611     } else {
0612         val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
0613         val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
0614         val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
0615 
0616         ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
0617         if (ret < 0)
0618             return ret;
0619     }
0620 
0621     val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
0622 
0623     ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
0624 
0625     return ret;
0626 }
0627 
0628 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
0629                       struct seq_file *s, unsigned pin)
0630 {
0631     struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
0632     struct pmic_gpio_pad *pad;
0633     int ret, val, function;
0634 
0635     static const char *const biases[] = {
0636         "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
0637         "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
0638     };
0639     static const char *const buffer_types[] = {
0640         "push-pull", "open-drain", "open-source"
0641     };
0642     static const char *const strengths[] = {
0643         "no", "high", "medium", "low"
0644     };
0645 
0646     pad = pctldev->desc->pins[pin].drv_data;
0647 
0648     seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
0649 
0650     val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
0651 
0652     if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
0653         seq_puts(s, " ---");
0654     } else {
0655         if (pad->input_enabled) {
0656             ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
0657             if (ret < 0)
0658                 return;
0659 
0660             ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
0661             pad->out_value = ret;
0662         }
0663         /*
0664          * For the non-LV/MV subtypes only 2 special functions are
0665          * available, offsetting the dtest function values by 2.
0666          */
0667         function = pad->function;
0668         if (!pad->lv_mv_type &&
0669                 pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
0670             function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
0671                 PMIC_GPIO_FUNC_INDEX_FUNC3;
0672 
0673         if (pad->analog_pass)
0674             seq_puts(s, " analog-pass");
0675         else
0676             seq_printf(s, " %-4s",
0677                     pad->output_enabled ? "out" : "in");
0678         seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
0679         seq_printf(s, " %-7s", pmic_gpio_functions[function]);
0680         seq_printf(s, " vin-%d", pad->power_source);
0681         seq_printf(s, " %-27s", biases[pad->pullup]);
0682         seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
0683         seq_printf(s, " %-7s", strengths[pad->strength]);
0684         seq_printf(s, " atest-%d", pad->atest);
0685         seq_printf(s, " dtest-%d", pad->dtest_buffer);
0686     }
0687 }
0688 
0689 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
0690     .is_generic         = true,
0691     .pin_config_group_get       = pmic_gpio_config_get,
0692     .pin_config_group_set       = pmic_gpio_config_set,
0693     .pin_config_group_dbg_show  = pmic_gpio_config_dbg_show,
0694 };
0695 
0696 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
0697 {
0698     struct pmic_gpio_state *state = gpiochip_get_data(chip);
0699     unsigned long config;
0700 
0701     config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
0702 
0703     return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
0704 }
0705 
0706 static int pmic_gpio_direction_output(struct gpio_chip *chip,
0707                       unsigned pin, int val)
0708 {
0709     struct pmic_gpio_state *state = gpiochip_get_data(chip);
0710     unsigned long config;
0711 
0712     config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
0713 
0714     return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
0715 }
0716 
0717 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
0718 {
0719     struct pmic_gpio_state *state = gpiochip_get_data(chip);
0720     struct pmic_gpio_pad *pad;
0721     int ret;
0722 
0723     pad = state->ctrl->desc->pins[pin].drv_data;
0724 
0725     if (!pad->is_enabled)
0726         return -EINVAL;
0727 
0728     if (pad->input_enabled) {
0729         ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
0730         if (ret < 0)
0731             return ret;
0732 
0733         pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
0734     }
0735 
0736     return !!pad->out_value;
0737 }
0738 
0739 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
0740 {
0741     struct pmic_gpio_state *state = gpiochip_get_data(chip);
0742     unsigned long config;
0743 
0744     config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
0745 
0746     pmic_gpio_config_set(state->ctrl, pin, &config, 1);
0747 }
0748 
0749 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
0750                   const struct of_phandle_args *gpio_desc,
0751                   u32 *flags)
0752 {
0753     if (chip->of_gpio_n_cells < 2)
0754         return -EINVAL;
0755 
0756     if (flags)
0757         *flags = gpio_desc->args[1];
0758 
0759     return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
0760 }
0761 
0762 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
0763 {
0764     struct pmic_gpio_state *state = gpiochip_get_data(chip);
0765     unsigned i;
0766 
0767     for (i = 0; i < chip->ngpio; i++) {
0768         pmic_gpio_config_dbg_show(state->ctrl, s, i);
0769         seq_puts(s, "\n");
0770     }
0771 }
0772 
0773 static const struct gpio_chip pmic_gpio_gpio_template = {
0774     .direction_input    = pmic_gpio_direction_input,
0775     .direction_output   = pmic_gpio_direction_output,
0776     .get            = pmic_gpio_get,
0777     .set            = pmic_gpio_set,
0778     .request        = gpiochip_generic_request,
0779     .free           = gpiochip_generic_free,
0780     .of_xlate       = pmic_gpio_of_xlate,
0781     .dbg_show       = pmic_gpio_dbg_show,
0782 };
0783 
0784 static int pmic_gpio_populate(struct pmic_gpio_state *state,
0785                   struct pmic_gpio_pad *pad)
0786 {
0787     int type, subtype, val, dir;
0788 
0789     type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
0790     if (type < 0)
0791         return type;
0792 
0793     if (type != PMIC_GPIO_TYPE) {
0794         dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
0795             type, pad->base);
0796         return -ENODEV;
0797     }
0798 
0799     subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
0800     if (subtype < 0)
0801         return subtype;
0802 
0803     switch (subtype) {
0804     case PMIC_GPIO_SUBTYPE_GPIO_4CH:
0805         pad->have_buffer = true;
0806         fallthrough;
0807     case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
0808         pad->num_sources = 4;
0809         break;
0810     case PMIC_GPIO_SUBTYPE_GPIO_8CH:
0811         pad->have_buffer = true;
0812         fallthrough;
0813     case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
0814         pad->num_sources = 8;
0815         break;
0816     case PMIC_GPIO_SUBTYPE_GPIO_LV:
0817         pad->num_sources = 1;
0818         pad->have_buffer = true;
0819         pad->lv_mv_type = true;
0820         break;
0821     case PMIC_GPIO_SUBTYPE_GPIO_MV:
0822         pad->num_sources = 2;
0823         pad->have_buffer = true;
0824         pad->lv_mv_type = true;
0825         break;
0826     default:
0827         dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
0828         return -ENODEV;
0829     }
0830 
0831     if (pad->lv_mv_type) {
0832         val = pmic_gpio_read(state, pad,
0833                 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
0834         if (val < 0)
0835             return val;
0836 
0837         pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
0838         pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
0839 
0840         val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
0841         if (val < 0)
0842             return val;
0843 
0844         dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
0845     } else {
0846         val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
0847         if (val < 0)
0848             return val;
0849 
0850         pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
0851 
0852         dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
0853         dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
0854         pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
0855         pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
0856     }
0857 
0858     switch (dir) {
0859     case PMIC_GPIO_MODE_DIGITAL_INPUT:
0860         pad->input_enabled = true;
0861         pad->output_enabled = false;
0862         break;
0863     case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
0864         pad->input_enabled = false;
0865         pad->output_enabled = true;
0866         break;
0867     case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
0868         pad->input_enabled = true;
0869         pad->output_enabled = true;
0870         break;
0871     case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
0872         if (!pad->lv_mv_type)
0873             return -ENODEV;
0874         pad->analog_pass = true;
0875         break;
0876     default:
0877         dev_err(state->dev, "unknown GPIO direction\n");
0878         return -ENODEV;
0879     }
0880 
0881     val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
0882     if (val < 0)
0883         return val;
0884 
0885     pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
0886     pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
0887 
0888     val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
0889     if (val < 0)
0890         return val;
0891 
0892     pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
0893     pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
0894 
0895     val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
0896     if (val < 0)
0897         return val;
0898 
0899     if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
0900         pad->dtest_buffer =
0901             (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
0902     else if (!pad->lv_mv_type)
0903         pad->dtest_buffer = ffs(val);
0904     else
0905         pad->dtest_buffer = 0;
0906 
0907     val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
0908     if (val < 0)
0909         return val;
0910 
0911     pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
0912     pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
0913 
0914     pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
0915     pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
0916 
0917     if (pad->lv_mv_type) {
0918         val = pmic_gpio_read(state, pad,
0919                 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
0920         if (val < 0)
0921             return val;
0922         pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
0923     }
0924 
0925     /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
0926     pad->is_enabled = true;
0927     return 0;
0928 }
0929 
0930 static int pmic_gpio_domain_translate(struct irq_domain *domain,
0931                       struct irq_fwspec *fwspec,
0932                       unsigned long *hwirq,
0933                       unsigned int *type)
0934 {
0935     struct pmic_gpio_state *state = container_of(domain->host_data,
0936                              struct pmic_gpio_state,
0937                              chip);
0938 
0939     if (fwspec->param_count != 2 ||
0940         fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio)
0941         return -EINVAL;
0942 
0943     *hwirq = fwspec->param[0] - PMIC_GPIO_PHYSICAL_OFFSET;
0944     *type = fwspec->param[1];
0945 
0946     return 0;
0947 }
0948 
0949 static unsigned int pmic_gpio_child_offset_to_irq(struct gpio_chip *chip,
0950                           unsigned int offset)
0951 {
0952     return offset + PMIC_GPIO_PHYSICAL_OFFSET;
0953 }
0954 
0955 static int pmic_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
0956                        unsigned int child_hwirq,
0957                        unsigned int child_type,
0958                        unsigned int *parent_hwirq,
0959                        unsigned int *parent_type)
0960 {
0961     struct pmic_gpio_state *state = gpiochip_get_data(chip);
0962 
0963     *parent_hwirq = child_hwirq + state->pid_base;
0964     *parent_type = child_type;
0965 
0966     return 0;
0967 }
0968 
0969 static int pmic_gpio_populate_parent_fwspec(struct gpio_chip *chip,
0970                         union gpio_irq_fwspec *gfwspec,
0971                         unsigned int parent_hwirq,
0972                         unsigned int parent_type)
0973 {
0974     struct pmic_gpio_state *state = gpiochip_get_data(chip);
0975     struct irq_fwspec *fwspec = &gfwspec->fwspec;
0976 
0977     fwspec->fwnode = chip->irq.parent_domain->fwnode;
0978 
0979     fwspec->param_count = 4;
0980     fwspec->param[0] = state->usid;
0981     fwspec->param[1] = parent_hwirq;
0982     /* param[2] must be left as 0 */
0983     fwspec->param[3] = parent_type;
0984 
0985     return 0;
0986 }
0987 
0988 static int pmic_gpio_probe(struct platform_device *pdev)
0989 {
0990     struct irq_domain *parent_domain;
0991     struct device_node *parent_node;
0992     struct device *dev = &pdev->dev;
0993     struct pinctrl_pin_desc *pindesc;
0994     struct pinctrl_desc *pctrldesc;
0995     struct pmic_gpio_pad *pad, *pads;
0996     struct pmic_gpio_state *state;
0997     struct gpio_irq_chip *girq;
0998     const struct spmi_device *parent_spmi_dev;
0999     int ret, npins, i;
1000     u32 reg;
1001 
1002     ret = of_property_read_u32(dev->of_node, "reg", &reg);
1003     if (ret < 0) {
1004         dev_err(dev, "missing base address");
1005         return ret;
1006     }
1007 
1008     npins = (uintptr_t) device_get_match_data(&pdev->dev);
1009 
1010     state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
1011     if (!state)
1012         return -ENOMEM;
1013 
1014     platform_set_drvdata(pdev, state);
1015 
1016     state->dev = &pdev->dev;
1017     state->map = dev_get_regmap(dev->parent, NULL);
1018     parent_spmi_dev = to_spmi_device(dev->parent);
1019     state->usid = parent_spmi_dev->usid;
1020     state->pid_base = reg >> 8;
1021 
1022     pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
1023     if (!pindesc)
1024         return -ENOMEM;
1025 
1026     pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
1027     if (!pads)
1028         return -ENOMEM;
1029 
1030     pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
1031     if (!pctrldesc)
1032         return -ENOMEM;
1033 
1034     pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
1035     pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
1036     pctrldesc->confops = &pmic_gpio_pinconf_ops;
1037     pctrldesc->owner = THIS_MODULE;
1038     pctrldesc->name = dev_name(dev);
1039     pctrldesc->pins = pindesc;
1040     pctrldesc->npins = npins;
1041     pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
1042     pctrldesc->custom_params = pmic_gpio_bindings;
1043 #ifdef CONFIG_DEBUG_FS
1044     pctrldesc->custom_conf_items = pmic_conf_items;
1045 #endif
1046 
1047     for (i = 0; i < npins; i++, pindesc++) {
1048         pad = &pads[i];
1049         pindesc->drv_data = pad;
1050         pindesc->number = i;
1051         pindesc->name = pmic_gpio_groups[i];
1052 
1053         pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
1054 
1055         ret = pmic_gpio_populate(state, pad);
1056         if (ret < 0)
1057             return ret;
1058     }
1059 
1060     state->chip = pmic_gpio_gpio_template;
1061     state->chip.parent = dev;
1062     state->chip.base = -1;
1063     state->chip.ngpio = npins;
1064     state->chip.label = dev_name(dev);
1065     state->chip.of_gpio_n_cells = 2;
1066     state->chip.can_sleep = false;
1067 
1068     state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
1069     if (IS_ERR(state->ctrl))
1070         return PTR_ERR(state->ctrl);
1071 
1072     parent_node = of_irq_find_parent(state->dev->of_node);
1073     if (!parent_node)
1074         return -ENXIO;
1075 
1076     parent_domain = irq_find_host(parent_node);
1077     of_node_put(parent_node);
1078     if (!parent_domain)
1079         return -ENXIO;
1080 
1081     state->irq.name = "spmi-gpio",
1082     state->irq.irq_ack = irq_chip_ack_parent,
1083     state->irq.irq_mask = irq_chip_mask_parent,
1084     state->irq.irq_unmask = irq_chip_unmask_parent,
1085     state->irq.irq_set_type = irq_chip_set_type_parent,
1086     state->irq.irq_set_wake = irq_chip_set_wake_parent,
1087     state->irq.flags = IRQCHIP_MASK_ON_SUSPEND,
1088 
1089     girq = &state->chip.irq;
1090     girq->chip = &state->irq;
1091     girq->default_type = IRQ_TYPE_NONE;
1092     girq->handler = handle_level_irq;
1093     girq->fwnode = of_node_to_fwnode(state->dev->of_node);
1094     girq->parent_domain = parent_domain;
1095     girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq;
1096     girq->populate_parent_alloc_arg = pmic_gpio_populate_parent_fwspec;
1097     girq->child_offset_to_irq = pmic_gpio_child_offset_to_irq;
1098     girq->child_irq_domain_ops.translate = pmic_gpio_domain_translate;
1099 
1100     ret = gpiochip_add_data(&state->chip, state);
1101     if (ret) {
1102         dev_err(state->dev, "can't add gpio chip\n");
1103         return ret;
1104     }
1105 
1106     /*
1107      * For DeviceTree-supported systems, the gpio core checks the
1108      * pinctrl's device node for the "gpio-ranges" property.
1109      * If it is present, it takes care of adding the pin ranges
1110      * for the driver. In this case the driver can skip ahead.
1111      *
1112      * In order to remain compatible with older, existing DeviceTree
1113      * files which don't set the "gpio-ranges" property or systems that
1114      * utilize ACPI the driver has to call gpiochip_add_pin_range().
1115      */
1116     if (!of_property_read_bool(dev->of_node, "gpio-ranges")) {
1117         ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0,
1118                          npins);
1119         if (ret) {
1120             dev_err(dev, "failed to add pin range\n");
1121             goto err_range;
1122         }
1123     }
1124 
1125     return 0;
1126 
1127 err_range:
1128     gpiochip_remove(&state->chip);
1129     return ret;
1130 }
1131 
1132 static int pmic_gpio_remove(struct platform_device *pdev)
1133 {
1134     struct pmic_gpio_state *state = platform_get_drvdata(pdev);
1135 
1136     gpiochip_remove(&state->chip);
1137     return 0;
1138 }
1139 
1140 static const struct of_device_id pmic_gpio_of_match[] = {
1141     { .compatible = "qcom,pm2250-gpio", .data = (void *) 10 },
1142     /* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */
1143     { .compatible = "qcom,pm660-gpio", .data = (void *) 13 },
1144     /* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */
1145     { .compatible = "qcom,pm660l-gpio", .data = (void *) 12 },
1146     { .compatible = "qcom,pm6125-gpio", .data = (void *) 9 },
1147     { .compatible = "qcom,pm6150-gpio", .data = (void *) 10 },
1148     { .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 },
1149     { .compatible = "qcom,pm6350-gpio", .data = (void *) 9 },
1150     { .compatible = "qcom,pm7325-gpio", .data = (void *) 10 },
1151     { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
1152     { .compatible = "qcom,pm8008-gpio", .data = (void *) 2 },
1153     { .compatible = "qcom,pm8019-gpio", .data = (void *) 6 },
1154     /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */
1155     { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 },
1156     { .compatible = "qcom,pmc8180-gpio", .data = (void *) 10 },
1157     /* pm8150b has 12 GPIOs with holes on 3, r and 7 */
1158     { .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 },
1159     /* pm8150l has 12 GPIOs with holes on 7 */
1160     { .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
1161     { .compatible = "qcom,pmc8180c-gpio", .data = (void *) 12 },
1162     { .compatible = "qcom,pm8226-gpio", .data = (void *) 8 },
1163     { .compatible = "qcom,pm8350-gpio", .data = (void *) 10 },
1164     { .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 },
1165     { .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 },
1166     { .compatible = "qcom,pm8450-gpio", .data = (void *) 4 },
1167     { .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
1168     { .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
1169     /* pm8950 has 8 GPIOs with holes on 3 */
1170     { .compatible = "qcom,pm8950-gpio", .data = (void *) 8 },
1171     { .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
1172     { .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
1173     { .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
1174     { .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 },
1175     { .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
1176     { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
1177     { .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
1178     { .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 },
1179     /* pmp8074 has 12 GPIOs with holes on 1 and 12 */
1180     { .compatible = "qcom,pmp8074-gpio", .data = (void *) 12 },
1181     { .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 },
1182     { .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 },
1183     /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
1184     { .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
1185     /* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */
1186     { .compatible = "qcom,pmx55-gpio", .data = (void *) 11 },
1187     { .compatible = "qcom,pmx65-gpio", .data = (void *) 16 },
1188     { },
1189 };
1190 
1191 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
1192 
1193 static struct platform_driver pmic_gpio_driver = {
1194     .driver = {
1195            .name = "qcom-spmi-gpio",
1196            .of_match_table = pmic_gpio_of_match,
1197     },
1198     .probe  = pmic_gpio_probe,
1199     .remove = pmic_gpio_remove,
1200 };
1201 
1202 module_platform_driver(pmic_gpio_driver);
1203 
1204 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
1205 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
1206 MODULE_ALIAS("platform:qcom-spmi-gpio");
1207 MODULE_LICENSE("GPL v2");
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