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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
0004  */
0005 
0006 #include <linux/module.h>
0007 #include <linux/of.h>
0008 #include <linux/platform_device.h>
0009 #include <linux/pinctrl/pinctrl.h>
0010 
0011 #include "pinctrl-msm.h"
0012 
0013 static const char * const sm8250_tiles[] = {
0014     "west",
0015     "south",
0016     "north",
0017 };
0018 
0019 enum {
0020     WEST,
0021     SOUTH,
0022     NORTH,
0023 };
0024 
0025 #define FUNCTION(fname)                 \
0026     [msm_mux_##fname] = {               \
0027         .name = #fname,             \
0028         .groups = fname##_groups,       \
0029         .ngroups = ARRAY_SIZE(fname##_groups),  \
0030     }
0031 
0032 #define REG_SIZE 0x1000
0033 #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
0034     {                       \
0035         .name = "gpio" #id,         \
0036         .pins = gpio##id##_pins,        \
0037         .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
0038         .funcs = (int[]){           \
0039             msm_mux_gpio, /* gpio mode */   \
0040             msm_mux_##f1,           \
0041             msm_mux_##f2,           \
0042             msm_mux_##f3,           \
0043             msm_mux_##f4,           \
0044             msm_mux_##f5,           \
0045             msm_mux_##f6,           \
0046             msm_mux_##f7,           \
0047             msm_mux_##f8,           \
0048             msm_mux_##f9            \
0049         },                  \
0050         .nfuncs = 10,               \
0051         .ctl_reg = REG_SIZE * id,       \
0052         .io_reg = REG_SIZE * id + 0x4,      \
0053         .intr_cfg_reg = REG_SIZE * id + 0x8,    \
0054         .intr_status_reg = REG_SIZE * id + 0xc, \
0055         .intr_target_reg = REG_SIZE * id + 0x8, \
0056         .tile = _tile,              \
0057         .mux_bit = 2,               \
0058         .pull_bit = 0,              \
0059         .drv_bit = 6,               \
0060         .oe_bit = 9,                \
0061         .in_bit = 0,                \
0062         .out_bit = 1,               \
0063         .intr_enable_bit = 0,           \
0064         .intr_status_bit = 0,           \
0065         .intr_target_bit = 5,           \
0066         .intr_target_kpss_val = 3,      \
0067         .intr_raw_status_bit = 4,       \
0068         .intr_polarity_bit = 1,         \
0069         .intr_detection_bit = 2,        \
0070         .intr_detection_width = 2,      \
0071     }
0072 
0073 #define SDC_PINGROUP(pg_name, ctl, pull, drv)   \
0074     {                       \
0075         .name = #pg_name,           \
0076         .pins = pg_name##_pins,         \
0077         .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins),  \
0078         .ctl_reg = ctl,             \
0079         .io_reg = 0,                \
0080         .intr_cfg_reg = 0,          \
0081         .intr_status_reg = 0,           \
0082         .intr_target_reg = 0,           \
0083         .tile = NORTH,              \
0084         .mux_bit = -1,              \
0085         .pull_bit = pull,           \
0086         .drv_bit = drv,             \
0087         .oe_bit = -1,               \
0088         .in_bit = -1,               \
0089         .out_bit = -1,              \
0090         .intr_enable_bit = -1,          \
0091         .intr_status_bit = -1,          \
0092         .intr_target_bit = -1,          \
0093         .intr_raw_status_bit = -1,      \
0094         .intr_polarity_bit = -1,        \
0095         .intr_detection_bit = -1,       \
0096         .intr_detection_width = -1,     \
0097     }
0098 
0099 #define UFS_RESET(pg_name, offset)              \
0100     {                       \
0101         .name = #pg_name,           \
0102         .pins = pg_name##_pins,         \
0103         .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins),  \
0104         .ctl_reg = offset,          \
0105         .io_reg = offset + 0x4,         \
0106         .intr_cfg_reg = 0,          \
0107         .intr_status_reg = 0,           \
0108         .intr_target_reg = 0,           \
0109         .tile = SOUTH,              \
0110         .mux_bit = -1,              \
0111         .pull_bit = 3,              \
0112         .drv_bit = 0,               \
0113         .oe_bit = -1,               \
0114         .in_bit = -1,               \
0115         .out_bit = 0,               \
0116         .intr_enable_bit = -1,          \
0117         .intr_status_bit = -1,          \
0118         .intr_target_bit = -1,          \
0119         .intr_raw_status_bit = -1,      \
0120         .intr_polarity_bit = -1,        \
0121         .intr_detection_bit = -1,       \
0122         .intr_detection_width = -1,     \
0123     }
0124 
0125 static const struct pinctrl_pin_desc sm8250_pins[] = {
0126     PINCTRL_PIN(0, "GPIO_0"),
0127     PINCTRL_PIN(1, "GPIO_1"),
0128     PINCTRL_PIN(2, "GPIO_2"),
0129     PINCTRL_PIN(3, "GPIO_3"),
0130     PINCTRL_PIN(4, "GPIO_4"),
0131     PINCTRL_PIN(5, "GPIO_5"),
0132     PINCTRL_PIN(6, "GPIO_6"),
0133     PINCTRL_PIN(7, "GPIO_7"),
0134     PINCTRL_PIN(8, "GPIO_8"),
0135     PINCTRL_PIN(9, "GPIO_9"),
0136     PINCTRL_PIN(10, "GPIO_10"),
0137     PINCTRL_PIN(11, "GPIO_11"),
0138     PINCTRL_PIN(12, "GPIO_12"),
0139     PINCTRL_PIN(13, "GPIO_13"),
0140     PINCTRL_PIN(14, "GPIO_14"),
0141     PINCTRL_PIN(15, "GPIO_15"),
0142     PINCTRL_PIN(16, "GPIO_16"),
0143     PINCTRL_PIN(17, "GPIO_17"),
0144     PINCTRL_PIN(18, "GPIO_18"),
0145     PINCTRL_PIN(19, "GPIO_19"),
0146     PINCTRL_PIN(20, "GPIO_20"),
0147     PINCTRL_PIN(21, "GPIO_21"),
0148     PINCTRL_PIN(22, "GPIO_22"),
0149     PINCTRL_PIN(23, "GPIO_23"),
0150     PINCTRL_PIN(24, "GPIO_24"),
0151     PINCTRL_PIN(25, "GPIO_25"),
0152     PINCTRL_PIN(26, "GPIO_26"),
0153     PINCTRL_PIN(27, "GPIO_27"),
0154     PINCTRL_PIN(28, "GPIO_28"),
0155     PINCTRL_PIN(29, "GPIO_29"),
0156     PINCTRL_PIN(30, "GPIO_30"),
0157     PINCTRL_PIN(31, "GPIO_31"),
0158     PINCTRL_PIN(32, "GPIO_32"),
0159     PINCTRL_PIN(33, "GPIO_33"),
0160     PINCTRL_PIN(34, "GPIO_34"),
0161     PINCTRL_PIN(35, "GPIO_35"),
0162     PINCTRL_PIN(36, "GPIO_36"),
0163     PINCTRL_PIN(37, "GPIO_37"),
0164     PINCTRL_PIN(38, "GPIO_38"),
0165     PINCTRL_PIN(39, "GPIO_39"),
0166     PINCTRL_PIN(40, "GPIO_40"),
0167     PINCTRL_PIN(41, "GPIO_41"),
0168     PINCTRL_PIN(42, "GPIO_42"),
0169     PINCTRL_PIN(43, "GPIO_43"),
0170     PINCTRL_PIN(44, "GPIO_44"),
0171     PINCTRL_PIN(45, "GPIO_45"),
0172     PINCTRL_PIN(46, "GPIO_46"),
0173     PINCTRL_PIN(47, "GPIO_47"),
0174     PINCTRL_PIN(48, "GPIO_48"),
0175     PINCTRL_PIN(49, "GPIO_49"),
0176     PINCTRL_PIN(50, "GPIO_50"),
0177     PINCTRL_PIN(51, "GPIO_51"),
0178     PINCTRL_PIN(52, "GPIO_52"),
0179     PINCTRL_PIN(53, "GPIO_53"),
0180     PINCTRL_PIN(54, "GPIO_54"),
0181     PINCTRL_PIN(55, "GPIO_55"),
0182     PINCTRL_PIN(56, "GPIO_56"),
0183     PINCTRL_PIN(57, "GPIO_57"),
0184     PINCTRL_PIN(58, "GPIO_58"),
0185     PINCTRL_PIN(59, "GPIO_59"),
0186     PINCTRL_PIN(60, "GPIO_60"),
0187     PINCTRL_PIN(61, "GPIO_61"),
0188     PINCTRL_PIN(62, "GPIO_62"),
0189     PINCTRL_PIN(63, "GPIO_63"),
0190     PINCTRL_PIN(64, "GPIO_64"),
0191     PINCTRL_PIN(65, "GPIO_65"),
0192     PINCTRL_PIN(66, "GPIO_66"),
0193     PINCTRL_PIN(67, "GPIO_67"),
0194     PINCTRL_PIN(68, "GPIO_68"),
0195     PINCTRL_PIN(69, "GPIO_69"),
0196     PINCTRL_PIN(70, "GPIO_70"),
0197     PINCTRL_PIN(71, "GPIO_71"),
0198     PINCTRL_PIN(72, "GPIO_72"),
0199     PINCTRL_PIN(73, "GPIO_73"),
0200     PINCTRL_PIN(74, "GPIO_74"),
0201     PINCTRL_PIN(75, "GPIO_75"),
0202     PINCTRL_PIN(76, "GPIO_76"),
0203     PINCTRL_PIN(77, "GPIO_77"),
0204     PINCTRL_PIN(78, "GPIO_78"),
0205     PINCTRL_PIN(79, "GPIO_79"),
0206     PINCTRL_PIN(80, "GPIO_80"),
0207     PINCTRL_PIN(81, "GPIO_81"),
0208     PINCTRL_PIN(82, "GPIO_82"),
0209     PINCTRL_PIN(83, "GPIO_83"),
0210     PINCTRL_PIN(84, "GPIO_84"),
0211     PINCTRL_PIN(85, "GPIO_85"),
0212     PINCTRL_PIN(86, "GPIO_86"),
0213     PINCTRL_PIN(87, "GPIO_87"),
0214     PINCTRL_PIN(88, "GPIO_88"),
0215     PINCTRL_PIN(89, "GPIO_89"),
0216     PINCTRL_PIN(90, "GPIO_90"),
0217     PINCTRL_PIN(91, "GPIO_91"),
0218     PINCTRL_PIN(92, "GPIO_92"),
0219     PINCTRL_PIN(93, "GPIO_93"),
0220     PINCTRL_PIN(94, "GPIO_94"),
0221     PINCTRL_PIN(95, "GPIO_95"),
0222     PINCTRL_PIN(96, "GPIO_96"),
0223     PINCTRL_PIN(97, "GPIO_97"),
0224     PINCTRL_PIN(98, "GPIO_98"),
0225     PINCTRL_PIN(99, "GPIO_99"),
0226     PINCTRL_PIN(100, "GPIO_100"),
0227     PINCTRL_PIN(101, "GPIO_101"),
0228     PINCTRL_PIN(102, "GPIO_102"),
0229     PINCTRL_PIN(103, "GPIO_103"),
0230     PINCTRL_PIN(104, "GPIO_104"),
0231     PINCTRL_PIN(105, "GPIO_105"),
0232     PINCTRL_PIN(106, "GPIO_106"),
0233     PINCTRL_PIN(107, "GPIO_107"),
0234     PINCTRL_PIN(108, "GPIO_108"),
0235     PINCTRL_PIN(109, "GPIO_109"),
0236     PINCTRL_PIN(110, "GPIO_110"),
0237     PINCTRL_PIN(111, "GPIO_111"),
0238     PINCTRL_PIN(112, "GPIO_112"),
0239     PINCTRL_PIN(113, "GPIO_113"),
0240     PINCTRL_PIN(114, "GPIO_114"),
0241     PINCTRL_PIN(115, "GPIO_115"),
0242     PINCTRL_PIN(116, "GPIO_116"),
0243     PINCTRL_PIN(117, "GPIO_117"),
0244     PINCTRL_PIN(118, "GPIO_118"),
0245     PINCTRL_PIN(119, "GPIO_119"),
0246     PINCTRL_PIN(120, "GPIO_120"),
0247     PINCTRL_PIN(121, "GPIO_121"),
0248     PINCTRL_PIN(122, "GPIO_122"),
0249     PINCTRL_PIN(123, "GPIO_123"),
0250     PINCTRL_PIN(124, "GPIO_124"),
0251     PINCTRL_PIN(125, "GPIO_125"),
0252     PINCTRL_PIN(126, "GPIO_126"),
0253     PINCTRL_PIN(127, "GPIO_127"),
0254     PINCTRL_PIN(128, "GPIO_128"),
0255     PINCTRL_PIN(129, "GPIO_129"),
0256     PINCTRL_PIN(130, "GPIO_130"),
0257     PINCTRL_PIN(131, "GPIO_131"),
0258     PINCTRL_PIN(132, "GPIO_132"),
0259     PINCTRL_PIN(133, "GPIO_133"),
0260     PINCTRL_PIN(134, "GPIO_134"),
0261     PINCTRL_PIN(135, "GPIO_135"),
0262     PINCTRL_PIN(136, "GPIO_136"),
0263     PINCTRL_PIN(137, "GPIO_137"),
0264     PINCTRL_PIN(138, "GPIO_138"),
0265     PINCTRL_PIN(139, "GPIO_139"),
0266     PINCTRL_PIN(140, "GPIO_140"),
0267     PINCTRL_PIN(141, "GPIO_141"),
0268     PINCTRL_PIN(142, "GPIO_142"),
0269     PINCTRL_PIN(143, "GPIO_143"),
0270     PINCTRL_PIN(144, "GPIO_144"),
0271     PINCTRL_PIN(145, "GPIO_145"),
0272     PINCTRL_PIN(146, "GPIO_146"),
0273     PINCTRL_PIN(147, "GPIO_147"),
0274     PINCTRL_PIN(148, "GPIO_148"),
0275     PINCTRL_PIN(149, "GPIO_149"),
0276     PINCTRL_PIN(150, "GPIO_150"),
0277     PINCTRL_PIN(151, "GPIO_151"),
0278     PINCTRL_PIN(152, "GPIO_152"),
0279     PINCTRL_PIN(153, "GPIO_153"),
0280     PINCTRL_PIN(154, "GPIO_154"),
0281     PINCTRL_PIN(155, "GPIO_155"),
0282     PINCTRL_PIN(156, "GPIO_156"),
0283     PINCTRL_PIN(157, "GPIO_157"),
0284     PINCTRL_PIN(158, "GPIO_158"),
0285     PINCTRL_PIN(159, "GPIO_159"),
0286     PINCTRL_PIN(160, "GPIO_160"),
0287     PINCTRL_PIN(161, "GPIO_161"),
0288     PINCTRL_PIN(162, "GPIO_162"),
0289     PINCTRL_PIN(163, "GPIO_163"),
0290     PINCTRL_PIN(164, "GPIO_164"),
0291     PINCTRL_PIN(165, "GPIO_165"),
0292     PINCTRL_PIN(166, "GPIO_166"),
0293     PINCTRL_PIN(167, "GPIO_167"),
0294     PINCTRL_PIN(168, "GPIO_168"),
0295     PINCTRL_PIN(169, "GPIO_169"),
0296     PINCTRL_PIN(170, "GPIO_170"),
0297     PINCTRL_PIN(171, "GPIO_171"),
0298     PINCTRL_PIN(172, "GPIO_172"),
0299     PINCTRL_PIN(173, "GPIO_173"),
0300     PINCTRL_PIN(174, "GPIO_174"),
0301     PINCTRL_PIN(175, "GPIO_175"),
0302     PINCTRL_PIN(176, "GPIO_176"),
0303     PINCTRL_PIN(177, "GPIO_177"),
0304     PINCTRL_PIN(178, "GPIO_178"),
0305     PINCTRL_PIN(179, "GPIO_179"),
0306     PINCTRL_PIN(180, "SDC2_CLK"),
0307     PINCTRL_PIN(181, "SDC2_CMD"),
0308     PINCTRL_PIN(182, "SDC2_DATA"),
0309     PINCTRL_PIN(183, "UFS_RESET"),
0310 };
0311 
0312 #define DECLARE_MSM_GPIO_PINS(pin) \
0313     static const unsigned int gpio##pin##_pins[] = { pin }
0314 DECLARE_MSM_GPIO_PINS(0);
0315 DECLARE_MSM_GPIO_PINS(1);
0316 DECLARE_MSM_GPIO_PINS(2);
0317 DECLARE_MSM_GPIO_PINS(3);
0318 DECLARE_MSM_GPIO_PINS(4);
0319 DECLARE_MSM_GPIO_PINS(5);
0320 DECLARE_MSM_GPIO_PINS(6);
0321 DECLARE_MSM_GPIO_PINS(7);
0322 DECLARE_MSM_GPIO_PINS(8);
0323 DECLARE_MSM_GPIO_PINS(9);
0324 DECLARE_MSM_GPIO_PINS(10);
0325 DECLARE_MSM_GPIO_PINS(11);
0326 DECLARE_MSM_GPIO_PINS(12);
0327 DECLARE_MSM_GPIO_PINS(13);
0328 DECLARE_MSM_GPIO_PINS(14);
0329 DECLARE_MSM_GPIO_PINS(15);
0330 DECLARE_MSM_GPIO_PINS(16);
0331 DECLARE_MSM_GPIO_PINS(17);
0332 DECLARE_MSM_GPIO_PINS(18);
0333 DECLARE_MSM_GPIO_PINS(19);
0334 DECLARE_MSM_GPIO_PINS(20);
0335 DECLARE_MSM_GPIO_PINS(21);
0336 DECLARE_MSM_GPIO_PINS(22);
0337 DECLARE_MSM_GPIO_PINS(23);
0338 DECLARE_MSM_GPIO_PINS(24);
0339 DECLARE_MSM_GPIO_PINS(25);
0340 DECLARE_MSM_GPIO_PINS(26);
0341 DECLARE_MSM_GPIO_PINS(27);
0342 DECLARE_MSM_GPIO_PINS(28);
0343 DECLARE_MSM_GPIO_PINS(29);
0344 DECLARE_MSM_GPIO_PINS(30);
0345 DECLARE_MSM_GPIO_PINS(31);
0346 DECLARE_MSM_GPIO_PINS(32);
0347 DECLARE_MSM_GPIO_PINS(33);
0348 DECLARE_MSM_GPIO_PINS(34);
0349 DECLARE_MSM_GPIO_PINS(35);
0350 DECLARE_MSM_GPIO_PINS(36);
0351 DECLARE_MSM_GPIO_PINS(37);
0352 DECLARE_MSM_GPIO_PINS(38);
0353 DECLARE_MSM_GPIO_PINS(39);
0354 DECLARE_MSM_GPIO_PINS(40);
0355 DECLARE_MSM_GPIO_PINS(41);
0356 DECLARE_MSM_GPIO_PINS(42);
0357 DECLARE_MSM_GPIO_PINS(43);
0358 DECLARE_MSM_GPIO_PINS(44);
0359 DECLARE_MSM_GPIO_PINS(45);
0360 DECLARE_MSM_GPIO_PINS(46);
0361 DECLARE_MSM_GPIO_PINS(47);
0362 DECLARE_MSM_GPIO_PINS(48);
0363 DECLARE_MSM_GPIO_PINS(49);
0364 DECLARE_MSM_GPIO_PINS(50);
0365 DECLARE_MSM_GPIO_PINS(51);
0366 DECLARE_MSM_GPIO_PINS(52);
0367 DECLARE_MSM_GPIO_PINS(53);
0368 DECLARE_MSM_GPIO_PINS(54);
0369 DECLARE_MSM_GPIO_PINS(55);
0370 DECLARE_MSM_GPIO_PINS(56);
0371 DECLARE_MSM_GPIO_PINS(57);
0372 DECLARE_MSM_GPIO_PINS(58);
0373 DECLARE_MSM_GPIO_PINS(59);
0374 DECLARE_MSM_GPIO_PINS(60);
0375 DECLARE_MSM_GPIO_PINS(61);
0376 DECLARE_MSM_GPIO_PINS(62);
0377 DECLARE_MSM_GPIO_PINS(63);
0378 DECLARE_MSM_GPIO_PINS(64);
0379 DECLARE_MSM_GPIO_PINS(65);
0380 DECLARE_MSM_GPIO_PINS(66);
0381 DECLARE_MSM_GPIO_PINS(67);
0382 DECLARE_MSM_GPIO_PINS(68);
0383 DECLARE_MSM_GPIO_PINS(69);
0384 DECLARE_MSM_GPIO_PINS(70);
0385 DECLARE_MSM_GPIO_PINS(71);
0386 DECLARE_MSM_GPIO_PINS(72);
0387 DECLARE_MSM_GPIO_PINS(73);
0388 DECLARE_MSM_GPIO_PINS(74);
0389 DECLARE_MSM_GPIO_PINS(75);
0390 DECLARE_MSM_GPIO_PINS(76);
0391 DECLARE_MSM_GPIO_PINS(77);
0392 DECLARE_MSM_GPIO_PINS(78);
0393 DECLARE_MSM_GPIO_PINS(79);
0394 DECLARE_MSM_GPIO_PINS(80);
0395 DECLARE_MSM_GPIO_PINS(81);
0396 DECLARE_MSM_GPIO_PINS(82);
0397 DECLARE_MSM_GPIO_PINS(83);
0398 DECLARE_MSM_GPIO_PINS(84);
0399 DECLARE_MSM_GPIO_PINS(85);
0400 DECLARE_MSM_GPIO_PINS(86);
0401 DECLARE_MSM_GPIO_PINS(87);
0402 DECLARE_MSM_GPIO_PINS(88);
0403 DECLARE_MSM_GPIO_PINS(89);
0404 DECLARE_MSM_GPIO_PINS(90);
0405 DECLARE_MSM_GPIO_PINS(91);
0406 DECLARE_MSM_GPIO_PINS(92);
0407 DECLARE_MSM_GPIO_PINS(93);
0408 DECLARE_MSM_GPIO_PINS(94);
0409 DECLARE_MSM_GPIO_PINS(95);
0410 DECLARE_MSM_GPIO_PINS(96);
0411 DECLARE_MSM_GPIO_PINS(97);
0412 DECLARE_MSM_GPIO_PINS(98);
0413 DECLARE_MSM_GPIO_PINS(99);
0414 DECLARE_MSM_GPIO_PINS(100);
0415 DECLARE_MSM_GPIO_PINS(101);
0416 DECLARE_MSM_GPIO_PINS(102);
0417 DECLARE_MSM_GPIO_PINS(103);
0418 DECLARE_MSM_GPIO_PINS(104);
0419 DECLARE_MSM_GPIO_PINS(105);
0420 DECLARE_MSM_GPIO_PINS(106);
0421 DECLARE_MSM_GPIO_PINS(107);
0422 DECLARE_MSM_GPIO_PINS(108);
0423 DECLARE_MSM_GPIO_PINS(109);
0424 DECLARE_MSM_GPIO_PINS(110);
0425 DECLARE_MSM_GPIO_PINS(111);
0426 DECLARE_MSM_GPIO_PINS(112);
0427 DECLARE_MSM_GPIO_PINS(113);
0428 DECLARE_MSM_GPIO_PINS(114);
0429 DECLARE_MSM_GPIO_PINS(115);
0430 DECLARE_MSM_GPIO_PINS(116);
0431 DECLARE_MSM_GPIO_PINS(117);
0432 DECLARE_MSM_GPIO_PINS(118);
0433 DECLARE_MSM_GPIO_PINS(119);
0434 DECLARE_MSM_GPIO_PINS(120);
0435 DECLARE_MSM_GPIO_PINS(121);
0436 DECLARE_MSM_GPIO_PINS(122);
0437 DECLARE_MSM_GPIO_PINS(123);
0438 DECLARE_MSM_GPIO_PINS(124);
0439 DECLARE_MSM_GPIO_PINS(125);
0440 DECLARE_MSM_GPIO_PINS(126);
0441 DECLARE_MSM_GPIO_PINS(127);
0442 DECLARE_MSM_GPIO_PINS(128);
0443 DECLARE_MSM_GPIO_PINS(129);
0444 DECLARE_MSM_GPIO_PINS(130);
0445 DECLARE_MSM_GPIO_PINS(131);
0446 DECLARE_MSM_GPIO_PINS(132);
0447 DECLARE_MSM_GPIO_PINS(133);
0448 DECLARE_MSM_GPIO_PINS(134);
0449 DECLARE_MSM_GPIO_PINS(135);
0450 DECLARE_MSM_GPIO_PINS(136);
0451 DECLARE_MSM_GPIO_PINS(137);
0452 DECLARE_MSM_GPIO_PINS(138);
0453 DECLARE_MSM_GPIO_PINS(139);
0454 DECLARE_MSM_GPIO_PINS(140);
0455 DECLARE_MSM_GPIO_PINS(141);
0456 DECLARE_MSM_GPIO_PINS(142);
0457 DECLARE_MSM_GPIO_PINS(143);
0458 DECLARE_MSM_GPIO_PINS(144);
0459 DECLARE_MSM_GPIO_PINS(145);
0460 DECLARE_MSM_GPIO_PINS(146);
0461 DECLARE_MSM_GPIO_PINS(147);
0462 DECLARE_MSM_GPIO_PINS(148);
0463 DECLARE_MSM_GPIO_PINS(149);
0464 DECLARE_MSM_GPIO_PINS(150);
0465 DECLARE_MSM_GPIO_PINS(151);
0466 DECLARE_MSM_GPIO_PINS(152);
0467 DECLARE_MSM_GPIO_PINS(153);
0468 DECLARE_MSM_GPIO_PINS(154);
0469 DECLARE_MSM_GPIO_PINS(155);
0470 DECLARE_MSM_GPIO_PINS(156);
0471 DECLARE_MSM_GPIO_PINS(157);
0472 DECLARE_MSM_GPIO_PINS(158);
0473 DECLARE_MSM_GPIO_PINS(159);
0474 DECLARE_MSM_GPIO_PINS(160);
0475 DECLARE_MSM_GPIO_PINS(161);
0476 DECLARE_MSM_GPIO_PINS(162);
0477 DECLARE_MSM_GPIO_PINS(163);
0478 DECLARE_MSM_GPIO_PINS(164);
0479 DECLARE_MSM_GPIO_PINS(165);
0480 DECLARE_MSM_GPIO_PINS(166);
0481 DECLARE_MSM_GPIO_PINS(167);
0482 DECLARE_MSM_GPIO_PINS(168);
0483 DECLARE_MSM_GPIO_PINS(169);
0484 DECLARE_MSM_GPIO_PINS(170);
0485 DECLARE_MSM_GPIO_PINS(171);
0486 DECLARE_MSM_GPIO_PINS(172);
0487 DECLARE_MSM_GPIO_PINS(173);
0488 DECLARE_MSM_GPIO_PINS(174);
0489 DECLARE_MSM_GPIO_PINS(175);
0490 DECLARE_MSM_GPIO_PINS(176);
0491 DECLARE_MSM_GPIO_PINS(177);
0492 DECLARE_MSM_GPIO_PINS(178);
0493 DECLARE_MSM_GPIO_PINS(179);
0494 
0495 static const unsigned int ufs_reset_pins[] = { 180 };
0496 static const unsigned int sdc2_clk_pins[] = { 181 };
0497 static const unsigned int sdc2_cmd_pins[] = { 182 };
0498 static const unsigned int sdc2_data_pins[] = { 183 };
0499 
0500 enum sm8250_functions {
0501     msm_mux_aoss_cti,
0502     msm_mux_atest,
0503     msm_mux_audio_ref,
0504     msm_mux_cam_mclk,
0505     msm_mux_cci_async,
0506     msm_mux_cci_i2c,
0507     msm_mux_cci_timer0,
0508     msm_mux_cci_timer1,
0509     msm_mux_cci_timer2,
0510     msm_mux_cci_timer3,
0511     msm_mux_cci_timer4,
0512     msm_mux_cri_trng,
0513     msm_mux_cri_trng0,
0514     msm_mux_cri_trng1,
0515     msm_mux_dbg_out,
0516     msm_mux_ddr_bist,
0517     msm_mux_ddr_pxi0,
0518     msm_mux_ddr_pxi1,
0519     msm_mux_ddr_pxi2,
0520     msm_mux_ddr_pxi3,
0521     msm_mux_dp_hot,
0522     msm_mux_dp_lcd,
0523     msm_mux_gcc_gp1,
0524     msm_mux_gcc_gp2,
0525     msm_mux_gcc_gp3,
0526     msm_mux_gpio,
0527     msm_mux_ibi_i3c,
0528     msm_mux_jitter_bist,
0529     msm_mux_lpass_slimbus,
0530     msm_mux_mdp_vsync,
0531     msm_mux_mdp_vsync0,
0532     msm_mux_mdp_vsync1,
0533     msm_mux_mdp_vsync2,
0534     msm_mux_mdp_vsync3,
0535     msm_mux_mi2s0_data0,
0536     msm_mux_mi2s0_data1,
0537     msm_mux_mi2s0_sck,
0538     msm_mux_mi2s0_ws,
0539     msm_mux_mi2s1_data0,
0540     msm_mux_mi2s1_data1,
0541     msm_mux_mi2s1_sck,
0542     msm_mux_mi2s1_ws,
0543     msm_mux_mi2s2_data0,
0544     msm_mux_mi2s2_data1,
0545     msm_mux_mi2s2_sck,
0546     msm_mux_mi2s2_ws,
0547     msm_mux_pci_e0,
0548     msm_mux_pci_e1,
0549     msm_mux_pci_e2,
0550     msm_mux_phase_flag,
0551     msm_mux_pll_bist,
0552     msm_mux_pll_bypassnl,
0553     msm_mux_pll_clk,
0554     msm_mux_pll_reset,
0555     msm_mux_pri_mi2s,
0556     msm_mux_prng_rosc,
0557     msm_mux_qdss_cti,
0558     msm_mux_qdss_gpio,
0559     msm_mux_qspi0,
0560     msm_mux_qspi1,
0561     msm_mux_qspi2,
0562     msm_mux_qspi3,
0563     msm_mux_qspi_clk,
0564     msm_mux_qspi_cs,
0565     msm_mux_qup0,
0566     msm_mux_qup1,
0567     msm_mux_qup10,
0568     msm_mux_qup11,
0569     msm_mux_qup12,
0570     msm_mux_qup13,
0571     msm_mux_qup14,
0572     msm_mux_qup15,
0573     msm_mux_qup16,
0574     msm_mux_qup17,
0575     msm_mux_qup18,
0576     msm_mux_qup19,
0577     msm_mux_qup2,
0578     msm_mux_qup3,
0579     msm_mux_qup4,
0580     msm_mux_qup5,
0581     msm_mux_qup6,
0582     msm_mux_qup7,
0583     msm_mux_qup8,
0584     msm_mux_qup9,
0585     msm_mux_qup_l4,
0586     msm_mux_qup_l5,
0587     msm_mux_qup_l6,
0588     msm_mux_sd_write,
0589     msm_mux_sdc40,
0590     msm_mux_sdc41,
0591     msm_mux_sdc42,
0592     msm_mux_sdc43,
0593     msm_mux_sdc4_clk,
0594     msm_mux_sdc4_cmd,
0595     msm_mux_sec_mi2s,
0596     msm_mux_sp_cmu,
0597     msm_mux_tgu_ch0,
0598     msm_mux_tgu_ch1,
0599     msm_mux_tgu_ch2,
0600     msm_mux_tgu_ch3,
0601     msm_mux_tsense_pwm1,
0602     msm_mux_tsense_pwm2,
0603     msm_mux_tsif0_clk,
0604     msm_mux_tsif0_data,
0605     msm_mux_tsif0_en,
0606     msm_mux_tsif0_error,
0607     msm_mux_tsif0_sync,
0608     msm_mux_tsif1_clk,
0609     msm_mux_tsif1_data,
0610     msm_mux_tsif1_en,
0611     msm_mux_tsif1_error,
0612     msm_mux_tsif1_sync,
0613     msm_mux_usb2phy_ac,
0614     msm_mux_usb_phy,
0615     msm_mux_vsense_trigger,
0616     msm_mux__,
0617 };
0618 
0619 static const char * const tsif1_data_groups[] = {
0620     "gpio75",
0621 };
0622 static const char * const sdc41_groups[] = {
0623     "gpio75",
0624 };
0625 static const char * const tsif1_sync_groups[] = {
0626     "gpio76",
0627 };
0628 static const char * const sdc40_groups[] = {
0629     "gpio76",
0630 };
0631 static const char * const aoss_cti_groups[] = {
0632     "gpio77",
0633 };
0634 static const char * const phase_flag_groups[] = {
0635     "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51",
0636     "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio77",
0637     "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
0638     "gpio103", "gpio104", "gpio115", "gpio116", "gpio117", "gpio118",
0639     "gpio119", "gpio120", "gpio122", "gpio124", "gpio125",
0640 };
0641 static const char * const sd_write_groups[] = {
0642     "gpio78",
0643 };
0644 static const char * const pci_e0_groups[] = {
0645     "gpio79", "gpio80",
0646 };
0647 static const char * const pci_e1_groups[] = {
0648     "gpio82", "gpio83",
0649 };
0650 static const char * const pci_e2_groups[] = {
0651     "gpio85", "gpio86",
0652 };
0653 static const char * const tgu_ch0_groups[] = {
0654     "gpio85",
0655 };
0656 static const char * const atest_groups[] = {
0657     "gpio24", "gpio25", "gpio26", "gpio27", "gpio32", "gpio33", "gpio34",
0658     "gpio35", "gpio36", "gpio37", "gpio85", "gpio86", "gpio87", "gpio88",
0659     "gpio89",
0660 };
0661 static const char * const tgu_ch3_groups[] = {
0662     "gpio86",
0663 };
0664 static const char * const tsif1_error_groups[] = {
0665     "gpio90",
0666 };
0667 static const char * const tgu_ch1_groups[] = {
0668     "gpio90",
0669 };
0670 static const char * const tsif0_error_groups[] = {
0671     "gpio91",
0672 };
0673 static const char * const tgu_ch2_groups[] = {
0674     "gpio91",
0675 };
0676 static const char * const cam_mclk_groups[] = {
0677     "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100",
0678 };
0679 static const char * const ddr_bist_groups[] = {
0680     "gpio94", "gpio95", "gpio143", "gpio144",
0681 };
0682 static const char * const pll_bypassnl_groups[] = {
0683     "gpio96",
0684 };
0685 static const char * const pll_reset_groups[] = {
0686     "gpio97",
0687 };
0688 static const char * const cci_i2c_groups[] = {
0689     "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106",
0690     "gpio107", "gpio108",
0691 };
0692 static const char * const qdss_gpio_groups[] = {
0693     "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100",
0694     "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106",
0695     "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", "gpio160",
0696     "gpio161", "gpio162", "gpio163", "gpio164", "gpio165", "gpio166",
0697     "gpio167", "gpio168", "gpio169", "gpio170", "gpio171", "gpio172",
0698     "gpio173", "gpio174", "gpio175", "gpio176", "gpio177",
0699 };
0700 static const char * const gcc_gp1_groups[] = {
0701     "gpio106", "gpio136",
0702 };
0703 static const char * const gcc_gp2_groups[] = {
0704     "gpio107", "gpio137",
0705 };
0706 static const char * const gcc_gp3_groups[] = {
0707     "gpio108", "gpio138",
0708 };
0709 static const char * const cci_timer0_groups[] = {
0710     "gpio109",
0711 };
0712 static const char * const cci_timer1_groups[] = {
0713     "gpio110",
0714 };
0715 static const char * const cci_timer2_groups[] = {
0716     "gpio111",
0717 };
0718 static const char * const cci_timer3_groups[] = {
0719     "gpio112",
0720 };
0721 static const char * const cci_async_groups[] = {
0722     "gpio112", "gpio113", "gpio114",
0723 };
0724 static const char * const cci_timer4_groups[] = {
0725     "gpio113",
0726 };
0727 static const char * const qup2_groups[] = {
0728     "gpio115", "gpio116", "gpio117", "gpio118",
0729 };
0730 static const char * const qup3_groups[] = {
0731     "gpio119", "gpio120", "gpio121", "gpio122",
0732 };
0733 static const char * const tsense_pwm1_groups[] = {
0734     "gpio123",
0735 };
0736 static const char * const tsense_pwm2_groups[] = {
0737     "gpio123",
0738 };
0739 static const char * const qup9_groups[] = {
0740     "gpio125", "gpio126", "gpio127", "gpio128",
0741 };
0742 static const char * const qup10_groups[] = {
0743     "gpio129", "gpio130", "gpio131", "gpio132",
0744 };
0745 static const char * const mi2s2_sck_groups[] = {
0746     "gpio133",
0747 };
0748 static const char * const mi2s2_data0_groups[] = {
0749     "gpio134",
0750 };
0751 static const char * const mi2s2_ws_groups[] = {
0752     "gpio135",
0753 };
0754 static const char * const pri_mi2s_groups[] = {
0755     "gpio136",
0756 };
0757 static const char * const sec_mi2s_groups[] = {
0758     "gpio137",
0759 };
0760 static const char * const audio_ref_groups[] = {
0761     "gpio137",
0762 };
0763 static const char * const mi2s2_data1_groups[] = {
0764     "gpio137",
0765 };
0766 static const char * const mi2s0_sck_groups[] = {
0767     "gpio138",
0768 };
0769 static const char * const mi2s0_data0_groups[] = {
0770     "gpio139",
0771 };
0772 static const char * const mi2s0_data1_groups[] = {
0773     "gpio140",
0774 };
0775 static const char * const mi2s0_ws_groups[] = {
0776     "gpio141",
0777 };
0778 static const char * const lpass_slimbus_groups[] = {
0779     "gpio142", "gpio143", "gpio144", "gpio145",
0780 };
0781 static const char * const mi2s1_sck_groups[] = {
0782     "gpio142",
0783 };
0784 static const char * const mi2s1_data0_groups[] = {
0785     "gpio143",
0786 };
0787 static const char * const mi2s1_data1_groups[] = {
0788     "gpio144",
0789 };
0790 static const char * const mi2s1_ws_groups[] = {
0791     "gpio145",
0792 };
0793 static const char * const cri_trng0_groups[] = {
0794     "gpio159",
0795 };
0796 static const char * const cri_trng1_groups[] = {
0797     "gpio160",
0798 };
0799 static const char * const cri_trng_groups[] = {
0800     "gpio161",
0801 };
0802 static const char * const sp_cmu_groups[] = {
0803     "gpio162",
0804 };
0805 static const char * const prng_rosc_groups[] = {
0806     "gpio163",
0807 };
0808 static const char * const qup19_groups[] = {
0809     "gpio0", "gpio1", "gpio2", "gpio3",
0810 };
0811 static const char * const gpio_groups[] = {
0812     "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
0813     "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
0814     "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
0815     "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
0816     "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
0817     "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
0818     "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
0819     "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
0820     "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
0821     "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
0822     "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
0823     "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
0824     "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
0825     "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
0826     "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
0827     "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
0828     "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
0829     "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
0830     "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
0831     "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
0832     "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
0833     "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
0834     "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
0835     "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158",
0836     "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
0837     "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
0838     "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176",
0839     "gpio177", "gpio178", "gpio179",
0840 };
0841 static const char * const qdss_cti_groups[] = {
0842     "gpio0", "gpio2", "gpio2", "gpio44", "gpio45", "gpio46", "gpio92",
0843     "gpio93",
0844 };
0845 static const char * const qup1_groups[] = {
0846     "gpio4", "gpio5", "gpio6", "gpio7",
0847 };
0848 static const char * const ibi_i3c_groups[] = {
0849     "gpio4", "gpio5", "gpio24", "gpio25", "gpio28", "gpio29", "gpio40",
0850     "gpio41",
0851 };
0852 static const char * const qup_l4_groups[] = {
0853     "gpio6", "gpio14", "gpio46", "gpio123",
0854 };
0855 static const char * const qup_l5_groups[] = {
0856     "gpio7", "gpio15", "gpio47", "gpio124",
0857 };
0858 static const char * const qup4_groups[] = {
0859     "gpio8", "gpio9", "gpio10", "gpio11",
0860 };
0861 static const char * const qup5_groups[] = {
0862     "gpio12", "gpio13", "gpio14", "gpio15",
0863 };
0864 static const char * const qup6_groups[] = {
0865     "gpio16", "gpio17", "gpio18", "gpio19",
0866 };
0867 static const char * const qup7_groups[] = {
0868     "gpio20", "gpio21", "gpio22", "gpio23",
0869 };
0870 static const char * const qup8_groups[] = {
0871     "gpio24", "gpio25", "gpio26", "gpio27",
0872 };
0873 static const char * const qup0_groups[] = {
0874     "gpio28", "gpio29", "gpio30", "gpio31",
0875 };
0876 static const char * const qup12_groups[] = {
0877     "gpio32", "gpio33", "gpio34", "gpio35",
0878 };
0879 static const char * const qup13_groups[] = {
0880     "gpio36", "gpio37", "gpio38", "gpio39",
0881 };
0882 static const char * const qup14_groups[] = {
0883     "gpio40", "gpio41", "gpio42", "gpio43",
0884 };
0885 static const char * const ddr_pxi3_groups[] = {
0886     "gpio40", "gpio43",
0887 };
0888 static const char * const ddr_pxi1_groups[] = {
0889     "gpio41", "gpio42",
0890 };
0891 static const char * const vsense_trigger_groups[] = {
0892     "gpio42",
0893 };
0894 static const char * const qup15_groups[] = {
0895     "gpio44", "gpio45", "gpio46", "gpio47",
0896 };
0897 static const char * const dbg_out_groups[] = {
0898     "gpio44",
0899 };
0900 static const char * const qup16_groups[] = {
0901     "gpio48", "gpio49", "gpio50", "gpio51",
0902 };
0903 static const char * const qup17_groups[] = {
0904     "gpio52", "gpio53", "gpio54", "gpio55",
0905 };
0906 static const char * const ddr_pxi0_groups[] = {
0907     "gpio52", "gpio53",
0908 };
0909 static const char * const jitter_bist_groups[] = {
0910     "gpio54",
0911 };
0912 static const char * const pll_bist_groups[] = {
0913     "gpio55",
0914 };
0915 static const char * const ddr_pxi2_groups[] = {
0916     "gpio55", "gpio56",
0917 };
0918 static const char * const qup18_groups[] = {
0919     "gpio56", "gpio57", "gpio58", "gpio59",
0920 };
0921 static const char * const qup11_groups[] = {
0922     "gpio60", "gpio61", "gpio62", "gpio63",
0923 };
0924 static const char * const usb2phy_ac_groups[] = {
0925     "gpio64", "gpio90",
0926 };
0927 static const char * const qup_l6_groups[] = {
0928     "gpio64", "gpio77", "gpio92", "gpio93",
0929 };
0930 static const char * const usb_phy_groups[] = {
0931     "gpio65",
0932 };
0933 static const char * const pll_clk_groups[] = {
0934     "gpio65",
0935 };
0936 static const char * const mdp_vsync_groups[] = {
0937     "gpio66", "gpio67", "gpio68", "gpio122", "gpio124",
0938 };
0939 static const char * const dp_lcd_groups[] = {
0940     "gpio67",
0941 };
0942 static const char * const dp_hot_groups[] = {
0943     "gpio68",
0944 };
0945 static const char * const qspi_cs_groups[] = {
0946     "gpio69", "gpio75",
0947 };
0948 static const char * const tsif0_clk_groups[] = {
0949     "gpio69",
0950 };
0951 static const char * const qspi0_groups[] = {
0952     "gpio70",
0953 };
0954 static const char * const tsif0_en_groups[] = {
0955     "gpio70",
0956 };
0957 static const char * const mdp_vsync0_groups[] = {
0958     "gpio70",
0959 };
0960 static const char * const mdp_vsync1_groups[] = {
0961     "gpio70",
0962 };
0963 static const char * const mdp_vsync2_groups[] = {
0964     "gpio70",
0965 };
0966 static const char * const mdp_vsync3_groups[] = {
0967     "gpio70",
0968 };
0969 static const char * const qspi1_groups[] = {
0970     "gpio71",
0971 };
0972 static const char * const tsif0_data_groups[] = {
0973     "gpio71",
0974 };
0975 static const char * const sdc4_cmd_groups[] = {
0976     "gpio71",
0977 };
0978 static const char * const qspi2_groups[] = {
0979     "gpio72",
0980 };
0981 static const char * const tsif0_sync_groups[] = {
0982     "gpio72",
0983 };
0984 static const char * const sdc43_groups[] = {
0985     "gpio72",
0986 };
0987 static const char * const qspi_clk_groups[] = {
0988     "gpio73",
0989 };
0990 static const char * const tsif1_clk_groups[] = {
0991     "gpio73",
0992 };
0993 static const char * const sdc4_clk_groups[] = {
0994     "gpio73",
0995 };
0996 static const char * const qspi3_groups[] = {
0997     "gpio74",
0998 };
0999 static const char * const tsif1_en_groups[] = {
1000     "gpio74",
1001 };
1002 static const char * const sdc42_groups[] = {
1003     "gpio74",
1004 };
1005 
1006 static const struct msm_function sm8250_functions[] = {
1007     FUNCTION(aoss_cti),
1008     FUNCTION(atest),
1009     FUNCTION(audio_ref),
1010     FUNCTION(cam_mclk),
1011     FUNCTION(cci_async),
1012     FUNCTION(cci_i2c),
1013     FUNCTION(cci_timer0),
1014     FUNCTION(cci_timer1),
1015     FUNCTION(cci_timer2),
1016     FUNCTION(cci_timer3),
1017     FUNCTION(cci_timer4),
1018     FUNCTION(cri_trng),
1019     FUNCTION(cri_trng0),
1020     FUNCTION(cri_trng1),
1021     FUNCTION(dbg_out),
1022     FUNCTION(ddr_bist),
1023     FUNCTION(ddr_pxi0),
1024     FUNCTION(ddr_pxi1),
1025     FUNCTION(ddr_pxi2),
1026     FUNCTION(ddr_pxi3),
1027     FUNCTION(dp_hot),
1028     FUNCTION(dp_lcd),
1029     FUNCTION(gcc_gp1),
1030     FUNCTION(gcc_gp2),
1031     FUNCTION(gcc_gp3),
1032     FUNCTION(gpio),
1033     FUNCTION(ibi_i3c),
1034     FUNCTION(jitter_bist),
1035     FUNCTION(lpass_slimbus),
1036     FUNCTION(mdp_vsync),
1037     FUNCTION(mdp_vsync0),
1038     FUNCTION(mdp_vsync1),
1039     FUNCTION(mdp_vsync2),
1040     FUNCTION(mdp_vsync3),
1041     FUNCTION(mi2s0_data0),
1042     FUNCTION(mi2s0_data1),
1043     FUNCTION(mi2s0_sck),
1044     FUNCTION(mi2s0_ws),
1045     FUNCTION(mi2s1_data0),
1046     FUNCTION(mi2s1_data1),
1047     FUNCTION(mi2s1_sck),
1048     FUNCTION(mi2s1_ws),
1049     FUNCTION(mi2s2_data0),
1050     FUNCTION(mi2s2_data1),
1051     FUNCTION(mi2s2_sck),
1052     FUNCTION(mi2s2_ws),
1053     FUNCTION(pci_e0),
1054     FUNCTION(pci_e1),
1055     FUNCTION(pci_e2),
1056     FUNCTION(phase_flag),
1057     FUNCTION(pll_bist),
1058     FUNCTION(pll_bypassnl),
1059     FUNCTION(pll_clk),
1060     FUNCTION(pll_reset),
1061     FUNCTION(pri_mi2s),
1062     FUNCTION(prng_rosc),
1063     FUNCTION(qdss_cti),
1064     FUNCTION(qdss_gpio),
1065     FUNCTION(qspi0),
1066     FUNCTION(qspi1),
1067     FUNCTION(qspi2),
1068     FUNCTION(qspi3),
1069     FUNCTION(qspi_clk),
1070     FUNCTION(qspi_cs),
1071     FUNCTION(qup0),
1072     FUNCTION(qup1),
1073     FUNCTION(qup10),
1074     FUNCTION(qup11),
1075     FUNCTION(qup12),
1076     FUNCTION(qup13),
1077     FUNCTION(qup14),
1078     FUNCTION(qup15),
1079     FUNCTION(qup16),
1080     FUNCTION(qup17),
1081     FUNCTION(qup18),
1082     FUNCTION(qup19),
1083     FUNCTION(qup2),
1084     FUNCTION(qup3),
1085     FUNCTION(qup4),
1086     FUNCTION(qup5),
1087     FUNCTION(qup6),
1088     FUNCTION(qup7),
1089     FUNCTION(qup8),
1090     FUNCTION(qup9),
1091     FUNCTION(qup_l4),
1092     FUNCTION(qup_l5),
1093     FUNCTION(qup_l6),
1094     FUNCTION(sd_write),
1095     FUNCTION(sdc40),
1096     FUNCTION(sdc41),
1097     FUNCTION(sdc42),
1098     FUNCTION(sdc43),
1099     FUNCTION(sdc4_clk),
1100     FUNCTION(sdc4_cmd),
1101     FUNCTION(sec_mi2s),
1102     FUNCTION(sp_cmu),
1103     FUNCTION(tgu_ch0),
1104     FUNCTION(tgu_ch1),
1105     FUNCTION(tgu_ch2),
1106     FUNCTION(tgu_ch3),
1107     FUNCTION(tsense_pwm1),
1108     FUNCTION(tsense_pwm2),
1109     FUNCTION(tsif0_clk),
1110     FUNCTION(tsif0_data),
1111     FUNCTION(tsif0_en),
1112     FUNCTION(tsif0_error),
1113     FUNCTION(tsif0_sync),
1114     FUNCTION(tsif1_clk),
1115     FUNCTION(tsif1_data),
1116     FUNCTION(tsif1_en),
1117     FUNCTION(tsif1_error),
1118     FUNCTION(tsif1_sync),
1119     FUNCTION(usb2phy_ac),
1120     FUNCTION(usb_phy),
1121     FUNCTION(vsense_trigger),
1122 };
1123 
1124 /* Every pin is maintained as a single group, and missing or non-existing pin
1125  * would be maintained as dummy group to synchronize pin group index with
1126  * pin descriptor registered with pinctrl core.
1127  * Clients would not be able to request these dummy pin groups.
1128  */
1129 static const struct msm_pingroup sm8250_groups[] = {
1130     [0] = PINGROUP(0, SOUTH, qup19, qdss_cti, _, _, _, _, _, _, _),
1131     [1] = PINGROUP(1, SOUTH, qup19, _, _, _, _, _, _, _, _),
1132     [2] = PINGROUP(2, SOUTH, qup19, qdss_cti, qdss_cti, _, _, _, _, _, _),
1133     [3] = PINGROUP(3, SOUTH, qup19, _, _, _, _, _, _, _, _),
1134     [4] = PINGROUP(4, NORTH, qup1, ibi_i3c, _, _, _, _, _, _, _),
1135     [5] = PINGROUP(5, NORTH, qup1, ibi_i3c, _, _, _, _, _, _, _),
1136     [6] = PINGROUP(6, NORTH, qup1, qup_l4, _, _, _, _, _, _, _),
1137     [7] = PINGROUP(7, NORTH, qup1, qup_l5, _, _, _, _, _, _, _),
1138     [8] = PINGROUP(8, NORTH, qup4, _, _, _, _, _, _, _, _),
1139     [9] = PINGROUP(9, NORTH, qup4, _, _, _, _, _, _, _, _),
1140     [10] = PINGROUP(10, NORTH, qup4, _, _, _, _, _, _, _, _),
1141     [11] = PINGROUP(11, NORTH, qup4, _, _, _, _, _, _, _, _),
1142     [12] = PINGROUP(12, NORTH, qup5, _, _, _, _, _, _, _, _),
1143     [13] = PINGROUP(13, NORTH, qup5, _, _, _, _, _, _, _, _),
1144     [14] = PINGROUP(14, NORTH, qup5, qup_l4, _, _, _, _, _, _, _),
1145     [15] = PINGROUP(15, NORTH, qup5, qup_l5, _, _, _, _, _, _, _),
1146     [16] = PINGROUP(16, NORTH, qup6, _, _, _, _, _, _, _, _),
1147     [17] = PINGROUP(17, NORTH, qup6, _, _, _, _, _, _, _, _),
1148     [18] = PINGROUP(18, NORTH, qup6, _, _, _, _, _, _, _, _),
1149     [19] = PINGROUP(19, NORTH, qup6, _, _, _, _, _, _, _, _),
1150     [20] = PINGROUP(20, NORTH, qup7, _, _, _, _, _, _, _, _),
1151     [21] = PINGROUP(21, NORTH, qup7, _, _, _, _, _, _, _, _),
1152     [22] = PINGROUP(22, NORTH, qup7, _, _, _, _, _, _, _, _),
1153     [23] = PINGROUP(23, NORTH, qup7, _, _, _, _, _, _, _, _),
1154     [24] = PINGROUP(24, SOUTH, qup8, ibi_i3c, atest, _, _, _, _, _, _),
1155     [25] = PINGROUP(25, SOUTH, qup8, ibi_i3c, atest, _, _, _, _, _, _),
1156     [26] = PINGROUP(26, SOUTH, qup8, atest, _, _, _, _, _, _, _),
1157     [27] = PINGROUP(27, SOUTH, qup8, atest, _, _, _, _, _, _, _),
1158     [28] = PINGROUP(28, NORTH, qup0, ibi_i3c, _, _, _, _, _, _, _),
1159     [29] = PINGROUP(29, NORTH, qup0, ibi_i3c, _, _, _, _, _, _, _),
1160     [30] = PINGROUP(30, NORTH, qup0, _, _, _, _, _, _, _, _),
1161     [31] = PINGROUP(31, NORTH, qup0, _, _, _, _, _, _, _, _),
1162     [32] = PINGROUP(32, SOUTH, qup12, _, atest, _, _, _, _, _, _),
1163     [33] = PINGROUP(33, SOUTH, qup12, atest, _, _, _, _, _, _, _),
1164     [34] = PINGROUP(34, SOUTH, qup12, atest, _, _, _, _, _, _, _),
1165     [35] = PINGROUP(35, SOUTH, qup12, atest, _, _, _, _, _, _, _),
1166     [36] = PINGROUP(36, SOUTH, qup13, atest, _, _, _, _, _, _, _),
1167     [37] = PINGROUP(37, SOUTH, qup13, atest, _, _, _, _, _, _, _),
1168     [38] = PINGROUP(38, SOUTH, qup13, _, _, _, _, _, _, _, _),
1169     [39] = PINGROUP(39, SOUTH, qup13, _, _, _, _, _, _, _, _),
1170     [40] = PINGROUP(40, SOUTH, qup14, ibi_i3c, _, ddr_pxi3, _, _, _, _, _),
1171     [41] = PINGROUP(41, SOUTH, qup14, ibi_i3c, _, ddr_pxi1, _, _, _, _, _),
1172     [42] = PINGROUP(42, SOUTH, qup14, vsense_trigger, ddr_pxi1, _, _, _, _, _, _),
1173     [43] = PINGROUP(43, SOUTH, qup14, ddr_pxi3, _, _, _, _, _, _, _),
1174     [44] = PINGROUP(44, SOUTH, qup15, qdss_cti, dbg_out, _, _, _, _, _, _),
1175     [45] = PINGROUP(45, SOUTH, qup15, qdss_cti, phase_flag, _, _, _, _, _, _),
1176     [46] = PINGROUP(46, SOUTH, qup15, qup_l4, qdss_cti, phase_flag, _, _, _, _, _),
1177     [47] = PINGROUP(47, SOUTH, qup15, qup_l5, phase_flag, _, _, _, _, _, _),
1178     [48] = PINGROUP(48, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _),
1179     [49] = PINGROUP(49, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _),
1180     [50] = PINGROUP(50, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _),
1181     [51] = PINGROUP(51, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _),
1182     [52] = PINGROUP(52, SOUTH, qup17, ddr_pxi0, _, _, _, _, _, _, _),
1183     [53] = PINGROUP(53, SOUTH, qup17, ddr_pxi0, _, _, _, _, _, _, _),
1184     [54] = PINGROUP(54, SOUTH, qup17, jitter_bist, _, _, _, _, _, _, _),
1185     [55] = PINGROUP(55, SOUTH, qup17, pll_bist, ddr_pxi2, _, _, _, _, _, _),
1186     [56] = PINGROUP(56, SOUTH, qup18, ddr_pxi2, _, _, _, _, _, _, _),
1187     [57] = PINGROUP(57, SOUTH, qup18, _, _, _, _, _, _, _, _),
1188     [58] = PINGROUP(58, SOUTH, qup18, _, _, _, _, _, _, _, _),
1189     [59] = PINGROUP(59, SOUTH, qup18, _, _, _, _, _, _, _, _),
1190     [60] = PINGROUP(60, SOUTH, qup11, _, _, _, _, _, _, _, _),
1191     [61] = PINGROUP(61, SOUTH, qup11, _, _, _, _, _, _, _, _),
1192     [62] = PINGROUP(62, SOUTH, qup11, _, _, _, _, _, _, _, _),
1193     [63] = PINGROUP(63, SOUTH, qup11, _, _, _, _, _, _, _, _),
1194     [64] = PINGROUP(64, SOUTH, usb2phy_ac, qup_l6, _, _, _, _, _, _, _),
1195     [65] = PINGROUP(65, SOUTH, usb_phy, pll_clk, _, _, _, _, _, _, _),
1196     [66] = PINGROUP(66, NORTH, mdp_vsync, _, _, _, _, _, _, _, _),
1197     [67] = PINGROUP(67, NORTH, mdp_vsync, dp_lcd, _, _, _, _, _, _, _),
1198     [68] = PINGROUP(68, NORTH, mdp_vsync, dp_hot, _, _, _, _, _, _, _),
1199     [69] = PINGROUP(69, SOUTH, qspi_cs, tsif0_clk, phase_flag, _, _, _, _, _, _),
1200     [70] = PINGROUP(70, SOUTH, qspi0, tsif0_en, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, phase_flag, _, _),
1201     [71] = PINGROUP(71, SOUTH, qspi1, tsif0_data, sdc4_cmd, phase_flag, _, _, _, _, _),
1202     [72] = PINGROUP(72, SOUTH, qspi2, tsif0_sync, sdc43, phase_flag, _, _, _, _, _),
1203     [73] = PINGROUP(73, SOUTH, qspi_clk, tsif1_clk, sdc4_clk, phase_flag, _, _, _, _, _),
1204     [74] = PINGROUP(74, SOUTH, qspi3, tsif1_en, sdc42, phase_flag, _, _, _, _, _),
1205     [75] = PINGROUP(75, SOUTH, qspi_cs, tsif1_data, sdc41, _, _, _, _, _, _),
1206     [76] = PINGROUP(76, SOUTH, tsif1_sync, sdc40, _, _, _, _, _, _, _),
1207     [77] = PINGROUP(77, NORTH, qup_l6, aoss_cti, phase_flag, _, _, _, _, _, _),
1208     [78] = PINGROUP(78, NORTH, sd_write, phase_flag, _, _, _, _, _, _, _),
1209     [79] = PINGROUP(79, NORTH, pci_e0, phase_flag, _, _, _, _, _, _, _),
1210     [80] = PINGROUP(80, NORTH, pci_e0, phase_flag, _, _, _, _, _, _, _),
1211     [81] = PINGROUP(81, NORTH, phase_flag, _, _, _, _, _, _, _, _),
1212     [82] = PINGROUP(82, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _),
1213     [83] = PINGROUP(83, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _),
1214     [84] = PINGROUP(84, NORTH, phase_flag, _, _, _, _, _, _, _, _),
1215     [85] = PINGROUP(85, SOUTH, pci_e2, tgu_ch0, atest, _, _, _, _, _, _),
1216     [86] = PINGROUP(86, SOUTH, pci_e2, tgu_ch3, atest, _, _, _, _, _, _),
1217     [87] = PINGROUP(87, SOUTH, atest, _, _, _, _, _, _, _, _),
1218     [88] = PINGROUP(88, SOUTH, _, atest, _, _, _, _, _, _, _),
1219     [89] = PINGROUP(89, SOUTH, _, atest, _, _, _, _, _, _, _),
1220     [90] = PINGROUP(90, SOUTH, tsif1_error, usb2phy_ac, tgu_ch1, _, _, _, _, _, _),
1221     [91] = PINGROUP(91, SOUTH, tsif0_error, tgu_ch2, _, _, _, _, _, _, _),
1222     [92] = PINGROUP(92, NORTH, qup_l6, qdss_cti, _, _, _, _, _, _, _),
1223     [93] = PINGROUP(93, NORTH, qup_l6, qdss_cti, _, _, _, _, _, _, _),
1224     [94] = PINGROUP(94, NORTH, cam_mclk, ddr_bist, qdss_gpio, _, _, _, _, _, _),
1225     [95] = PINGROUP(95, NORTH, cam_mclk, ddr_bist, qdss_gpio, _, _, _, _, _, _),
1226     [96] = PINGROUP(96, NORTH, cam_mclk, pll_bypassnl, qdss_gpio, _, _, _, _, _, _),
1227     [97] = PINGROUP(97, NORTH, cam_mclk, pll_reset, qdss_gpio, _, _, _, _, _, _),
1228     [98] = PINGROUP(98, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1229     [99] = PINGROUP(99, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1230     [100] = PINGROUP(100, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
1231     [101] = PINGROUP(101, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1232     [102] = PINGROUP(102, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1233     [103] = PINGROUP(103, NORTH, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
1234     [104] = PINGROUP(104, NORTH, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
1235     [105] = PINGROUP(105, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
1236     [106] = PINGROUP(106, NORTH, cci_i2c, gcc_gp1, qdss_gpio, _, _, _, _, _, _),
1237     [107] = PINGROUP(107, NORTH, cci_i2c, gcc_gp2, qdss_gpio, _, _, _, _, _, _),
1238     [108] = PINGROUP(108, NORTH, cci_i2c, gcc_gp3, qdss_gpio, _, _, _, _, _, _),
1239     [109] = PINGROUP(109, NORTH, cci_timer0, qdss_gpio, _, _, _, _, _, _, _),
1240     [110] = PINGROUP(110, NORTH, cci_timer1, qdss_gpio, _, _, _, _, _, _, _),
1241     [111] = PINGROUP(111, NORTH, cci_timer2, qdss_gpio, _, _, _, _, _, _, _),
1242     [112] = PINGROUP(112, NORTH, cci_timer3, cci_async, _, _, _, _, _, _, _),
1243     [113] = PINGROUP(113, NORTH, cci_timer4, cci_async, _, _, _, _, _, _, _),
1244     [114] = PINGROUP(114, NORTH, cci_async, _, _, _, _, _, _, _, _),
1245     [115] = PINGROUP(115, NORTH, qup2, phase_flag, _, _, _, _, _, _, _),
1246     [116] = PINGROUP(116, NORTH, qup2, phase_flag, _, _, _, _, _, _, _),
1247     [117] = PINGROUP(117, NORTH, qup2, phase_flag, _, _, _, _, _, _, _),
1248     [118] = PINGROUP(118, NORTH, qup2, phase_flag, _, _, _, _, _, _, _),
1249     [119] = PINGROUP(119, NORTH, qup3, phase_flag, _, _, _, _, _, _, _),
1250     [120] = PINGROUP(120, NORTH, qup3, phase_flag, _, _, _, _, _, _, _),
1251     [121] = PINGROUP(121, NORTH, qup3, _, _, _, _, _, _, _, _),
1252     [122] = PINGROUP(122, NORTH, qup3, mdp_vsync, phase_flag, _, _, _, _, _, _),
1253     [123] = PINGROUP(123, NORTH, qup_l4, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _),
1254     [124] = PINGROUP(124, NORTH, qup_l5, mdp_vsync, phase_flag, _, _, _, _, _, _),
1255     [125] = PINGROUP(125, SOUTH, qup9, phase_flag, _, _, _, _, _, _, _),
1256     [126] = PINGROUP(126, SOUTH, qup9, _, _, _, _, _, _, _, _),
1257     [127] = PINGROUP(127, SOUTH, qup9, _, _, _, _, _, _, _, _),
1258     [128] = PINGROUP(128, SOUTH, qup9, _, _, _, _, _, _, _, _),
1259     [129] = PINGROUP(129, SOUTH, qup10, _, _, _, _, _, _, _, _),
1260     [130] = PINGROUP(130, SOUTH, qup10, _, _, _, _, _, _, _, _),
1261     [131] = PINGROUP(131, SOUTH, qup10, _, _, _, _, _, _, _, _),
1262     [132] = PINGROUP(132, SOUTH, qup10, _, _, _, _, _, _, _, _),
1263     [133] = PINGROUP(133, WEST, mi2s2_sck, _, _, _, _, _, _, _, _),
1264     [134] = PINGROUP(134, WEST, mi2s2_data0, _, _, _, _, _, _, _, _),
1265     [135] = PINGROUP(135, WEST, mi2s2_ws, _, _, _, _, _, _, _, _),
1266     [136] = PINGROUP(136, WEST, pri_mi2s, gcc_gp1, _, _, _, _, _, _, _),
1267     [137] = PINGROUP(137, WEST, sec_mi2s, audio_ref, mi2s2_data1, gcc_gp2, _, _, _, _, _),
1268     [138] = PINGROUP(138, WEST, mi2s0_sck, gcc_gp3, _, _, _, _, _, _, _),
1269     [139] = PINGROUP(139, WEST, mi2s0_data0, _, _, _, _, _, _, _, _),
1270     [140] = PINGROUP(140, WEST, mi2s0_data1, _, _, _, _, _, _, _, _),
1271     [141] = PINGROUP(141, WEST, mi2s0_ws, _, _, _, _, _, _, _, _),
1272     [142] = PINGROUP(142, WEST, lpass_slimbus, mi2s1_sck, _, _, _, _, _, _, _),
1273     [143] = PINGROUP(143, WEST, lpass_slimbus, mi2s1_data0, ddr_bist, _, _, _, _, _, _),
1274     [144] = PINGROUP(144, WEST, lpass_slimbus, mi2s1_data1, ddr_bist, _, _, _, _, _, _),
1275     [145] = PINGROUP(145, WEST, lpass_slimbus, mi2s1_ws, _, _, _, _, _, _, _),
1276     [146] = PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _),
1277     [147] = PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _),
1278     [148] = PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _),
1279     [149] = PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _),
1280     [150] = PINGROUP(150, WEST, _, _, _, _, _, _, _, _, _),
1281     [151] = PINGROUP(151, WEST, _, _, _, _, _, _, _, _, _),
1282     [152] = PINGROUP(152, WEST, _, _, _, _, _, _, _, _, _),
1283     [153] = PINGROUP(153, WEST, _, _, _, _, _, _, _, _, _),
1284     [154] = PINGROUP(154, WEST, _, _, _, _, _, _, _, _, _),
1285     [155] = PINGROUP(155, WEST, _, _, _, _, _, _, _, _, _),
1286     [156] = PINGROUP(156, WEST, _, _, _, _, _, _, _, _, _),
1287     [157] = PINGROUP(157, WEST, _, _, _, _, _, _, _, _, _),
1288     [158] = PINGROUP(158, WEST, _, _, _, _, _, _, _, _, _),
1289     [159] = PINGROUP(159, WEST, cri_trng0, _, _, _, _, _, _, _, _),
1290     [160] = PINGROUP(160, WEST, cri_trng1, qdss_gpio, _, _, _, _, _, _, _),
1291     [161] = PINGROUP(161, WEST, cri_trng, qdss_gpio, _, _, _, _, _, _, _),
1292     [162] = PINGROUP(162, WEST, sp_cmu, qdss_gpio, _, _, _, _, _, _, _),
1293     [163] = PINGROUP(163, WEST, prng_rosc, qdss_gpio, _, _, _, _, _, _, _),
1294     [164] = PINGROUP(164, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1295     [165] = PINGROUP(165, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1296     [166] = PINGROUP(166, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1297     [167] = PINGROUP(167, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1298     [168] = PINGROUP(168, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1299     [169] = PINGROUP(169, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1300     [170] = PINGROUP(170, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1301     [171] = PINGROUP(171, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1302     [172] = PINGROUP(172, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1303     [173] = PINGROUP(173, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1304     [174] = PINGROUP(174, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1305     [175] = PINGROUP(175, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1306     [176] = PINGROUP(176, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1307     [177] = PINGROUP(177, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
1308     [178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, _),
1309     [179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, _),
1310     [180] = UFS_RESET(ufs_reset, 0xb8000),
1311     [181] = SDC_PINGROUP(sdc2_clk, 0xb7000, 14, 6),
1312     [182] = SDC_PINGROUP(sdc2_cmd, 0xb7000, 11, 3),
1313     [183] = SDC_PINGROUP(sdc2_data, 0xb7000, 9, 0),
1314 };
1315 
1316 static const struct msm_gpio_wakeirq_map sm8250_pdc_map[] = {
1317     { 0, 79 }, { 1, 84 }, { 2, 80 }, { 3, 82 }, { 4, 107 }, { 7, 43 },
1318     { 11, 42 }, { 14, 44 }, { 15, 52 }, { 19, 67 }, { 23, 68 }, { 24, 105 },
1319     { 27, 92 }, { 28, 106 }, { 31, 69 }, { 35, 70 }, { 39, 73 },
1320     { 40, 108 }, { 43, 71 }, { 45, 72 }, { 47, 83 }, { 51, 74 }, { 55, 77 },
1321     { 59, 78 }, { 63, 75 }, { 64, 81 }, { 65, 87 }, { 66, 88 }, { 67, 89 },
1322     { 68, 54 }, { 70, 85 }, { 77, 46 }, { 80, 90 }, { 81, 91 }, { 83, 97 },
1323     { 84, 98 }, { 86, 99 }, { 87, 100 }, { 88, 101 }, { 89, 102 },
1324     { 92, 103 }, { 93, 104 }, { 100, 53 }, { 103, 47 }, { 104, 48 },
1325     { 108, 49 }, { 109, 94 }, { 110, 95 }, { 111, 96 }, { 112, 55 },
1326     { 113, 56 }, { 118, 50 }, { 121, 51 }, { 122, 57 }, { 123, 58 },
1327     { 124, 45 }, { 126, 59 }, { 128, 76 }, { 129, 86 }, { 132, 93 },
1328     { 133, 65 }, { 134, 66 }, { 136, 62 }, { 137, 63 }, { 138, 64 },
1329     { 142, 60 }, { 143, 61 }
1330 };
1331 
1332 static const struct msm_pinctrl_soc_data sm8250_pinctrl = {
1333     .pins = sm8250_pins,
1334     .npins = ARRAY_SIZE(sm8250_pins),
1335     .functions = sm8250_functions,
1336     .nfunctions = ARRAY_SIZE(sm8250_functions),
1337     .groups = sm8250_groups,
1338     .ngroups = ARRAY_SIZE(sm8250_groups),
1339     .ngpios = 181,
1340     .tiles = sm8250_tiles,
1341     .ntiles = ARRAY_SIZE(sm8250_tiles),
1342     .wakeirq_map = sm8250_pdc_map,
1343     .nwakeirq_map = ARRAY_SIZE(sm8250_pdc_map),
1344 };
1345 
1346 static int sm8250_pinctrl_probe(struct platform_device *pdev)
1347 {
1348     return msm_pinctrl_probe(pdev, &sm8250_pinctrl);
1349 }
1350 
1351 static const struct of_device_id sm8250_pinctrl_of_match[] = {
1352     { .compatible = "qcom,sm8250-pinctrl", },
1353     { },
1354 };
1355 
1356 static struct platform_driver sm8250_pinctrl_driver = {
1357     .driver = {
1358         .name = "sm8250-pinctrl",
1359         .of_match_table = sm8250_pinctrl_of_match,
1360     },
1361     .probe = sm8250_pinctrl_probe,
1362     .remove = msm_pinctrl_remove,
1363 };
1364 
1365 static int __init sm8250_pinctrl_init(void)
1366 {
1367     return platform_driver_register(&sm8250_pinctrl_driver);
1368 }
1369 arch_initcall(sm8250_pinctrl_init);
1370 
1371 static void __exit sm8250_pinctrl_exit(void)
1372 {
1373     platform_driver_unregister(&sm8250_pinctrl_driver);
1374 }
1375 module_exit(sm8250_pinctrl_exit);
1376 
1377 MODULE_DESCRIPTION("QTI sm8250 pinctrl driver");
1378 MODULE_LICENSE("GPL v2");
1379 MODULE_DEVICE_TABLE(of, sm8250_pinctrl_of_match);
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