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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
0004  */
0005 
0006 #include <linux/module.h>
0007 #include <linux/of.h>
0008 #include <linux/platform_device.h>
0009 #include <linux/pinctrl/pinctrl.h>
0010 
0011 #include "pinctrl-msm.h"
0012 
0013 static const char * const sm6115_tiles[] = {
0014     "south",
0015     "east",
0016     "west"
0017 };
0018 
0019 enum {
0020     SOUTH,
0021     EAST,
0022     WEST
0023 };
0024 
0025 #define FUNCTION(fname)                 \
0026     [msm_mux_##fname] = {               \
0027         .name = #fname,             \
0028         .groups = fname##_groups,       \
0029         .ngroups = ARRAY_SIZE(fname##_groups),  \
0030     }
0031 
0032 #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
0033     {                       \
0034         .name = "gpio" #id,         \
0035         .pins = gpio##id##_pins,        \
0036         .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
0037         .funcs = (int[]){           \
0038             msm_mux_gpio, /* gpio mode */   \
0039             msm_mux_##f1,           \
0040             msm_mux_##f2,           \
0041             msm_mux_##f3,           \
0042             msm_mux_##f4,           \
0043             msm_mux_##f5,           \
0044             msm_mux_##f6,           \
0045             msm_mux_##f7,           \
0046             msm_mux_##f8,           \
0047             msm_mux_##f9            \
0048         },                  \
0049         .nfuncs = 10,               \
0050         .ctl_reg = 0x1000 * id,     \
0051         .io_reg = 0x4 + 0x1000 * id,        \
0052         .intr_cfg_reg = 0x8 + 0x1000 * id,  \
0053         .intr_status_reg = 0xc + 0x1000 * id,   \
0054         .intr_target_reg = 0x8 + 0x1000 * id,   \
0055         .tile = _tile,          \
0056         .mux_bit = 2,           \
0057         .pull_bit = 0,          \
0058         .drv_bit = 6,           \
0059         .oe_bit = 9,            \
0060         .in_bit = 0,            \
0061         .out_bit = 1,           \
0062         .intr_enable_bit = 0,       \
0063         .intr_status_bit = 0,       \
0064         .intr_target_bit = 5,       \
0065         .intr_target_kpss_val = 3,  \
0066         .intr_raw_status_bit = 4,   \
0067         .intr_polarity_bit = 1,     \
0068         .intr_detection_bit = 2,    \
0069         .intr_detection_width = 2,  \
0070     }
0071 
0072 #define SDC_QDSD_PINGROUP(pg_name, _tile, ctl, pull, drv)   \
0073     {                       \
0074         .name = #pg_name,           \
0075         .pins = pg_name##_pins,         \
0076         .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins),  \
0077         .ctl_reg = ctl,             \
0078         .io_reg = 0,                \
0079         .intr_cfg_reg = 0,          \
0080         .intr_status_reg = 0,           \
0081         .intr_target_reg = 0,           \
0082         .tile = _tile,              \
0083         .mux_bit = -1,              \
0084         .pull_bit = pull,           \
0085         .drv_bit = drv,             \
0086         .oe_bit = -1,               \
0087         .in_bit = -1,               \
0088         .out_bit = -1,              \
0089         .intr_enable_bit = -1,          \
0090         .intr_status_bit = -1,          \
0091         .intr_target_bit = -1,          \
0092         .intr_raw_status_bit = -1,      \
0093         .intr_polarity_bit = -1,        \
0094         .intr_detection_bit = -1,       \
0095         .intr_detection_width = -1,     \
0096     }
0097 
0098 #define UFS_RESET(pg_name, offset)          \
0099     {                       \
0100         .name = #pg_name,           \
0101         .pins = pg_name##_pins,         \
0102         .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins),  \
0103         .ctl_reg = offset,          \
0104         .io_reg = offset + 0x4,         \
0105         .intr_cfg_reg = 0,          \
0106         .intr_status_reg = 0,           \
0107         .intr_target_reg = 0,           \
0108         .tile = WEST,               \
0109         .mux_bit = -1,              \
0110         .pull_bit = 3,              \
0111         .drv_bit = 0,               \
0112         .oe_bit = -1,               \
0113         .in_bit = -1,               \
0114         .out_bit = 0,               \
0115         .intr_enable_bit = -1,          \
0116         .intr_status_bit = -1,          \
0117         .intr_target_bit = -1,          \
0118         .intr_raw_status_bit = -1,      \
0119         .intr_polarity_bit = -1,        \
0120         .intr_detection_bit = -1,       \
0121         .intr_detection_width = -1,     \
0122     }
0123 static const struct pinctrl_pin_desc sm6115_pins[] = {
0124     PINCTRL_PIN(0, "GPIO_0"),
0125     PINCTRL_PIN(1, "GPIO_1"),
0126     PINCTRL_PIN(2, "GPIO_2"),
0127     PINCTRL_PIN(3, "GPIO_3"),
0128     PINCTRL_PIN(4, "GPIO_4"),
0129     PINCTRL_PIN(5, "GPIO_5"),
0130     PINCTRL_PIN(6, "GPIO_6"),
0131     PINCTRL_PIN(7, "GPIO_7"),
0132     PINCTRL_PIN(8, "GPIO_8"),
0133     PINCTRL_PIN(9, "GPIO_9"),
0134     PINCTRL_PIN(10, "GPIO_10"),
0135     PINCTRL_PIN(11, "GPIO_11"),
0136     PINCTRL_PIN(12, "GPIO_12"),
0137     PINCTRL_PIN(13, "GPIO_13"),
0138     PINCTRL_PIN(14, "GPIO_14"),
0139     PINCTRL_PIN(15, "GPIO_15"),
0140     PINCTRL_PIN(16, "GPIO_16"),
0141     PINCTRL_PIN(17, "GPIO_17"),
0142     PINCTRL_PIN(18, "GPIO_18"),
0143     PINCTRL_PIN(19, "GPIO_19"),
0144     PINCTRL_PIN(20, "GPIO_20"),
0145     PINCTRL_PIN(21, "GPIO_21"),
0146     PINCTRL_PIN(22, "GPIO_22"),
0147     PINCTRL_PIN(23, "GPIO_23"),
0148     PINCTRL_PIN(24, "GPIO_24"),
0149     PINCTRL_PIN(25, "GPIO_25"),
0150     PINCTRL_PIN(26, "GPIO_26"),
0151     PINCTRL_PIN(27, "GPIO_27"),
0152     PINCTRL_PIN(28, "GPIO_28"),
0153     PINCTRL_PIN(29, "GPIO_29"),
0154     PINCTRL_PIN(30, "GPIO_30"),
0155     PINCTRL_PIN(31, "GPIO_31"),
0156     PINCTRL_PIN(32, "GPIO_32"),
0157     PINCTRL_PIN(33, "GPIO_33"),
0158     PINCTRL_PIN(34, "GPIO_34"),
0159     PINCTRL_PIN(35, "GPIO_35"),
0160     PINCTRL_PIN(36, "GPIO_36"),
0161     PINCTRL_PIN(37, "GPIO_37"),
0162     PINCTRL_PIN(38, "GPIO_38"),
0163     PINCTRL_PIN(39, "GPIO_39"),
0164     PINCTRL_PIN(40, "GPIO_40"),
0165     PINCTRL_PIN(41, "GPIO_41"),
0166     PINCTRL_PIN(42, "GPIO_42"),
0167     PINCTRL_PIN(43, "GPIO_43"),
0168     PINCTRL_PIN(44, "GPIO_44"),
0169     PINCTRL_PIN(45, "GPIO_45"),
0170     PINCTRL_PIN(46, "GPIO_46"),
0171     PINCTRL_PIN(47, "GPIO_47"),
0172     PINCTRL_PIN(48, "GPIO_48"),
0173     PINCTRL_PIN(49, "GPIO_49"),
0174     PINCTRL_PIN(50, "GPIO_50"),
0175     PINCTRL_PIN(51, "GPIO_51"),
0176     PINCTRL_PIN(52, "GPIO_52"),
0177     PINCTRL_PIN(53, "GPIO_53"),
0178     PINCTRL_PIN(54, "GPIO_54"),
0179     PINCTRL_PIN(55, "GPIO_55"),
0180     PINCTRL_PIN(56, "GPIO_56"),
0181     PINCTRL_PIN(57, "GPIO_57"),
0182     PINCTRL_PIN(58, "GPIO_58"),
0183     PINCTRL_PIN(59, "GPIO_59"),
0184     PINCTRL_PIN(60, "GPIO_60"),
0185     PINCTRL_PIN(61, "GPIO_61"),
0186     PINCTRL_PIN(62, "GPIO_62"),
0187     PINCTRL_PIN(63, "GPIO_63"),
0188     PINCTRL_PIN(64, "GPIO_64"),
0189     PINCTRL_PIN(65, "GPIO_65"),
0190     PINCTRL_PIN(66, "GPIO_66"),
0191     PINCTRL_PIN(67, "GPIO_67"),
0192     PINCTRL_PIN(68, "GPIO_68"),
0193     PINCTRL_PIN(69, "GPIO_69"),
0194     PINCTRL_PIN(70, "GPIO_70"),
0195     PINCTRL_PIN(71, "GPIO_71"),
0196     PINCTRL_PIN(72, "GPIO_72"),
0197     PINCTRL_PIN(73, "GPIO_73"),
0198     PINCTRL_PIN(74, "GPIO_74"),
0199     PINCTRL_PIN(75, "GPIO_75"),
0200     PINCTRL_PIN(76, "GPIO_76"),
0201     PINCTRL_PIN(77, "GPIO_77"),
0202     PINCTRL_PIN(78, "GPIO_78"),
0203     PINCTRL_PIN(79, "GPIO_79"),
0204     PINCTRL_PIN(80, "GPIO_80"),
0205     PINCTRL_PIN(81, "GPIO_81"),
0206     PINCTRL_PIN(82, "GPIO_82"),
0207     PINCTRL_PIN(83, "GPIO_83"),
0208     PINCTRL_PIN(84, "GPIO_84"),
0209     PINCTRL_PIN(85, "GPIO_85"),
0210     PINCTRL_PIN(86, "GPIO_86"),
0211     PINCTRL_PIN(87, "GPIO_87"),
0212     PINCTRL_PIN(88, "GPIO_88"),
0213     PINCTRL_PIN(89, "GPIO_89"),
0214     PINCTRL_PIN(90, "GPIO_90"),
0215     PINCTRL_PIN(91, "GPIO_91"),
0216     PINCTRL_PIN(92, "GPIO_92"),
0217     PINCTRL_PIN(93, "GPIO_93"),
0218     PINCTRL_PIN(94, "GPIO_94"),
0219     PINCTRL_PIN(95, "GPIO_95"),
0220     PINCTRL_PIN(96, "GPIO_96"),
0221     PINCTRL_PIN(97, "GPIO_97"),
0222     PINCTRL_PIN(98, "GPIO_98"),
0223     PINCTRL_PIN(99, "GPIO_99"),
0224     PINCTRL_PIN(100, "GPIO_100"),
0225     PINCTRL_PIN(101, "GPIO_101"),
0226     PINCTRL_PIN(102, "GPIO_102"),
0227     PINCTRL_PIN(103, "GPIO_103"),
0228     PINCTRL_PIN(104, "GPIO_104"),
0229     PINCTRL_PIN(105, "GPIO_105"),
0230     PINCTRL_PIN(106, "GPIO_106"),
0231     PINCTRL_PIN(107, "GPIO_107"),
0232     PINCTRL_PIN(108, "GPIO_108"),
0233     PINCTRL_PIN(109, "GPIO_109"),
0234     PINCTRL_PIN(110, "GPIO_110"),
0235     PINCTRL_PIN(111, "GPIO_111"),
0236     PINCTRL_PIN(112, "GPIO_112"),
0237     PINCTRL_PIN(113, "UFS_RESET"),
0238     PINCTRL_PIN(114, "SDC1_RCLK"),
0239     PINCTRL_PIN(115, "SDC1_CLK"),
0240     PINCTRL_PIN(116, "SDC1_CMD"),
0241     PINCTRL_PIN(117, "SDC1_DATA"),
0242     PINCTRL_PIN(118, "SDC2_CLK"),
0243     PINCTRL_PIN(119, "SDC2_CMD"),
0244     PINCTRL_PIN(120, "SDC2_DATA"),
0245 };
0246 
0247 #define DECLARE_MSM_GPIO_PINS(pin) \
0248     static const unsigned int gpio##pin##_pins[] = { pin }
0249 DECLARE_MSM_GPIO_PINS(0);
0250 DECLARE_MSM_GPIO_PINS(1);
0251 DECLARE_MSM_GPIO_PINS(2);
0252 DECLARE_MSM_GPIO_PINS(3);
0253 DECLARE_MSM_GPIO_PINS(4);
0254 DECLARE_MSM_GPIO_PINS(5);
0255 DECLARE_MSM_GPIO_PINS(6);
0256 DECLARE_MSM_GPIO_PINS(7);
0257 DECLARE_MSM_GPIO_PINS(8);
0258 DECLARE_MSM_GPIO_PINS(9);
0259 DECLARE_MSM_GPIO_PINS(10);
0260 DECLARE_MSM_GPIO_PINS(11);
0261 DECLARE_MSM_GPIO_PINS(12);
0262 DECLARE_MSM_GPIO_PINS(13);
0263 DECLARE_MSM_GPIO_PINS(14);
0264 DECLARE_MSM_GPIO_PINS(15);
0265 DECLARE_MSM_GPIO_PINS(16);
0266 DECLARE_MSM_GPIO_PINS(17);
0267 DECLARE_MSM_GPIO_PINS(18);
0268 DECLARE_MSM_GPIO_PINS(19);
0269 DECLARE_MSM_GPIO_PINS(20);
0270 DECLARE_MSM_GPIO_PINS(21);
0271 DECLARE_MSM_GPIO_PINS(22);
0272 DECLARE_MSM_GPIO_PINS(23);
0273 DECLARE_MSM_GPIO_PINS(24);
0274 DECLARE_MSM_GPIO_PINS(25);
0275 DECLARE_MSM_GPIO_PINS(26);
0276 DECLARE_MSM_GPIO_PINS(27);
0277 DECLARE_MSM_GPIO_PINS(28);
0278 DECLARE_MSM_GPIO_PINS(29);
0279 DECLARE_MSM_GPIO_PINS(30);
0280 DECLARE_MSM_GPIO_PINS(31);
0281 DECLARE_MSM_GPIO_PINS(32);
0282 DECLARE_MSM_GPIO_PINS(33);
0283 DECLARE_MSM_GPIO_PINS(34);
0284 DECLARE_MSM_GPIO_PINS(35);
0285 DECLARE_MSM_GPIO_PINS(36);
0286 DECLARE_MSM_GPIO_PINS(37);
0287 DECLARE_MSM_GPIO_PINS(38);
0288 DECLARE_MSM_GPIO_PINS(39);
0289 DECLARE_MSM_GPIO_PINS(40);
0290 DECLARE_MSM_GPIO_PINS(41);
0291 DECLARE_MSM_GPIO_PINS(42);
0292 DECLARE_MSM_GPIO_PINS(43);
0293 DECLARE_MSM_GPIO_PINS(44);
0294 DECLARE_MSM_GPIO_PINS(45);
0295 DECLARE_MSM_GPIO_PINS(46);
0296 DECLARE_MSM_GPIO_PINS(47);
0297 DECLARE_MSM_GPIO_PINS(48);
0298 DECLARE_MSM_GPIO_PINS(49);
0299 DECLARE_MSM_GPIO_PINS(50);
0300 DECLARE_MSM_GPIO_PINS(51);
0301 DECLARE_MSM_GPIO_PINS(52);
0302 DECLARE_MSM_GPIO_PINS(53);
0303 DECLARE_MSM_GPIO_PINS(54);
0304 DECLARE_MSM_GPIO_PINS(55);
0305 DECLARE_MSM_GPIO_PINS(56);
0306 DECLARE_MSM_GPIO_PINS(57);
0307 DECLARE_MSM_GPIO_PINS(58);
0308 DECLARE_MSM_GPIO_PINS(59);
0309 DECLARE_MSM_GPIO_PINS(60);
0310 DECLARE_MSM_GPIO_PINS(61);
0311 DECLARE_MSM_GPIO_PINS(62);
0312 DECLARE_MSM_GPIO_PINS(63);
0313 DECLARE_MSM_GPIO_PINS(64);
0314 DECLARE_MSM_GPIO_PINS(65);
0315 DECLARE_MSM_GPIO_PINS(66);
0316 DECLARE_MSM_GPIO_PINS(67);
0317 DECLARE_MSM_GPIO_PINS(68);
0318 DECLARE_MSM_GPIO_PINS(69);
0319 DECLARE_MSM_GPIO_PINS(70);
0320 DECLARE_MSM_GPIO_PINS(71);
0321 DECLARE_MSM_GPIO_PINS(72);
0322 DECLARE_MSM_GPIO_PINS(73);
0323 DECLARE_MSM_GPIO_PINS(74);
0324 DECLARE_MSM_GPIO_PINS(75);
0325 DECLARE_MSM_GPIO_PINS(76);
0326 DECLARE_MSM_GPIO_PINS(77);
0327 DECLARE_MSM_GPIO_PINS(78);
0328 DECLARE_MSM_GPIO_PINS(79);
0329 DECLARE_MSM_GPIO_PINS(80);
0330 DECLARE_MSM_GPIO_PINS(81);
0331 DECLARE_MSM_GPIO_PINS(82);
0332 DECLARE_MSM_GPIO_PINS(83);
0333 DECLARE_MSM_GPIO_PINS(84);
0334 DECLARE_MSM_GPIO_PINS(85);
0335 DECLARE_MSM_GPIO_PINS(86);
0336 DECLARE_MSM_GPIO_PINS(87);
0337 DECLARE_MSM_GPIO_PINS(88);
0338 DECLARE_MSM_GPIO_PINS(89);
0339 DECLARE_MSM_GPIO_PINS(90);
0340 DECLARE_MSM_GPIO_PINS(91);
0341 DECLARE_MSM_GPIO_PINS(92);
0342 DECLARE_MSM_GPIO_PINS(93);
0343 DECLARE_MSM_GPIO_PINS(94);
0344 DECLARE_MSM_GPIO_PINS(95);
0345 DECLARE_MSM_GPIO_PINS(96);
0346 DECLARE_MSM_GPIO_PINS(97);
0347 DECLARE_MSM_GPIO_PINS(98);
0348 DECLARE_MSM_GPIO_PINS(99);
0349 DECLARE_MSM_GPIO_PINS(100);
0350 DECLARE_MSM_GPIO_PINS(101);
0351 DECLARE_MSM_GPIO_PINS(102);
0352 DECLARE_MSM_GPIO_PINS(103);
0353 DECLARE_MSM_GPIO_PINS(104);
0354 DECLARE_MSM_GPIO_PINS(105);
0355 DECLARE_MSM_GPIO_PINS(106);
0356 DECLARE_MSM_GPIO_PINS(107);
0357 DECLARE_MSM_GPIO_PINS(108);
0358 DECLARE_MSM_GPIO_PINS(109);
0359 DECLARE_MSM_GPIO_PINS(110);
0360 DECLARE_MSM_GPIO_PINS(111);
0361 DECLARE_MSM_GPIO_PINS(112);
0362 
0363 static const unsigned int ufs_reset_pins[] = { 113 };
0364 static const unsigned int sdc1_rclk_pins[] = { 114 };
0365 static const unsigned int sdc1_clk_pins[] = { 115 };
0366 static const unsigned int sdc1_cmd_pins[] = { 116 };
0367 static const unsigned int sdc1_data_pins[] = { 117 };
0368 static const unsigned int sdc2_clk_pins[] = { 118 };
0369 static const unsigned int sdc2_cmd_pins[] = { 119 };
0370 static const unsigned int sdc2_data_pins[] = { 120 };
0371 
0372 enum sm6115_functions {
0373     msm_mux_adsp_ext,
0374     msm_mux_agera_pll,
0375     msm_mux_atest,
0376     msm_mux_cam_mclk,
0377     msm_mux_cci_async,
0378     msm_mux_cci_i2c,
0379     msm_mux_cci_timer,
0380     msm_mux_cri_trng,
0381     msm_mux_dac_calib,
0382     msm_mux_dbg_out,
0383     msm_mux_ddr_bist,
0384     msm_mux_ddr_pxi0,
0385     msm_mux_ddr_pxi1,
0386     msm_mux_ddr_pxi2,
0387     msm_mux_ddr_pxi3,
0388     msm_mux_gcc_gp1,
0389     msm_mux_gcc_gp2,
0390     msm_mux_gcc_gp3,
0391     msm_mux_gpio,
0392     msm_mux_gp_pdm0,
0393     msm_mux_gp_pdm1,
0394     msm_mux_gp_pdm2,
0395     msm_mux_gsm0_tx,
0396     msm_mux_gsm1_tx,
0397     msm_mux_jitter_bist,
0398     msm_mux_mdp_vsync,
0399     msm_mux_mdp_vsync_out_0,
0400     msm_mux_mdp_vsync_out_1,
0401     msm_mux_mpm_pwr,
0402     msm_mux_mss_lte,
0403     msm_mux_m_voc,
0404     msm_mux_nav_gpio,
0405     msm_mux_pa_indicator,
0406     msm_mux_pbs,
0407     msm_mux_pbs_out,
0408     msm_mux_phase_flag,
0409     msm_mux_pll_bist,
0410     msm_mux_pll_bypassnl,
0411     msm_mux_pll_reset,
0412     msm_mux_prng_rosc,
0413     msm_mux_qdss_cti,
0414     msm_mux_qdss_gpio,
0415     msm_mux_qup0,
0416     msm_mux_qup1,
0417     msm_mux_qup2,
0418     msm_mux_qup3,
0419     msm_mux_qup4,
0420     msm_mux_qup5,
0421     msm_mux_sdc1_tb,
0422     msm_mux_sdc2_tb,
0423     msm_mux_sd_write,
0424     msm_mux_ssbi_wtr1,
0425     msm_mux_tgu,
0426     msm_mux_tsense_pwm,
0427     msm_mux_uim1_clk,
0428     msm_mux_uim1_data,
0429     msm_mux_uim1_present,
0430     msm_mux_uim1_reset,
0431     msm_mux_uim2_clk,
0432     msm_mux_uim2_data,
0433     msm_mux_uim2_present,
0434     msm_mux_uim2_reset,
0435     msm_mux_usb_phy,
0436     msm_mux_vfr_1,
0437     msm_mux_vsense_trigger,
0438     msm_mux_wlan1_adc0,
0439     msm_mux_wlan1_adc1,
0440     msm_mux__,
0441 };
0442 
0443 static const char * const qup0_groups[] = {
0444     "gpio0", "gpio1", "gpio2", "gpio3", "gpio82", "gpio86",
0445 };
0446 static const char * const gpio_groups[] = {
0447     "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
0448     "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
0449     "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
0450     "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
0451     "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
0452     "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
0453     "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
0454     "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
0455     "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
0456     "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
0457     "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
0458     "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
0459     "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
0460     "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
0461     "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
0462     "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
0463     "gpio111", "gpio112",
0464 };
0465 static const char * const ddr_bist_groups[] = {
0466     "gpio0", "gpio1", "gpio2", "gpio3",
0467 };
0468 static const char * const phase_flag_groups[] = {
0469     "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6",
0470     "gpio14", "gpio15", "gpio16", "gpio17", "gpio22", "gpio23", "gpio24",
0471     "gpio25", "gpio26", "gpio29", "gpio30", "gpio31", "gpio32", "gpio33",
0472     "gpio35", "gpio36", "gpio43", "gpio44", "gpio45", "gpio63", "gpio64",
0473     "gpio102", "gpio103", "gpio104", "gpio105",
0474 };
0475 static const char * const qdss_gpio_groups[] = {
0476     "gpio0", "gpio1", "gpio2", "gpio3", "gpio8", "gpio9", "gpio10",
0477     "gpio11", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
0478     "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
0479     "gpio47", "gpio48", "gpio69", "gpio70", "gpio87", "gpio90", "gpio91",
0480     "gpio94", "gpio95", "gpio104", "gpio105", "gpio106", "gpio107",
0481     "gpio109", "gpio110",
0482 };
0483 static const char * const atest_groups[] = {
0484     "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6",
0485     "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio29", "gpio30",
0486     "gpio31", "gpio32", "gpio33", "gpio86", "gpio87", "gpio88", "gpio89",
0487     "gpio100", "gpio101",
0488 };
0489 static const char * const mpm_pwr_groups[] = {
0490     "gpio1",
0491 };
0492 static const char * const m_voc_groups[] = {
0493     "gpio0",
0494 };
0495 static const char * const dac_calib_groups[] = {
0496     "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio14", "gpio15",
0497     "gpio16", "gpio17", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
0498     "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio80", "gpio81",
0499     "gpio82", "gpio102", "gpio103", "gpio104", "gpio105"
0500 };
0501 static const char * const qup1_groups[] = {
0502     "gpio4", "gpio5", "gpio69", "gpio70",
0503 };
0504 static const char * const cri_trng_groups[] = {
0505     "gpio4", "gpio5", "gpio18",
0506 };
0507 static const char * const qup2_groups[] = {
0508     "gpio6", "gpio7", "gpio71", "gpio80",
0509 };
0510 static const char * const qup3_groups[] = {
0511     "gpio8", "gpio9", "gpio10", "gpio11",
0512 };
0513 static const char * const pbs_out_groups[] = {
0514     "gpio8", "gpio9", "gpio52",
0515 };
0516 static const char * const pll_bist_groups[] = {
0517     "gpio8", "gpio9",
0518 };
0519 static const char * const tsense_pwm_groups[] = {
0520     "gpio8",
0521 };
0522 static const char * const agera_pll_groups[] = {
0523     "gpio10", "gpio11",
0524 };
0525 static const char * const pbs_groups[] = {
0526     "gpio10", "gpio11", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
0527     "gpio23", "gpio24", "gpio25", "gpio26", "gpio47", "gpio48", "gpio87",
0528     "gpio90", "gpio91",
0529 };
0530 static const char * const qup4_groups[] = {
0531     "gpio12", "gpio13", "gpio96", "gpio97",
0532 };
0533 static const char * const tgu_groups[] = {
0534     "gpio12", "gpio13", "gpio14", "gpio15",
0535 };
0536 static const char * const qup5_groups[] = {
0537     "gpio14", "gpio15", "gpio16", "gpio17",
0538 };
0539 static const char * const sdc2_tb_groups[] = {
0540     "gpio18",
0541 };
0542 static const char * const sdc1_tb_groups[] = {
0543     "gpio19",
0544 };
0545 static const char * const cam_mclk_groups[] = {
0546     "gpio20", "gpio21", "gpio27", "gpio28",
0547 };
0548 static const char * const adsp_ext_groups[] = {
0549     "gpio21",
0550 };
0551 static const char * const cci_i2c_groups[] = {
0552     "gpio22", "gpio23", "gpio29", "gpio30",
0553 };
0554 static const char * const prng_rosc_groups[] = {
0555     "gpio22", "gpio23",
0556 };
0557 static const char * const cci_timer_groups[] = {
0558     "gpio24", "gpio25", "gpio28", "gpio32",
0559 };
0560 static const char * const gcc_gp1_groups[] = {
0561     "gpio24", "gpio86",
0562 };
0563 static const char * const cci_async_groups[] = {
0564     "gpio25",
0565 };
0566 static const char * const vsense_trigger_groups[] = {
0567     "gpio26",
0568 };
0569 static const char * const qdss_cti_groups[] = {
0570     "gpio27", "gpio28", "gpio72", "gpio73", "gpio96", "gpio97",
0571 };
0572 static const char * const gp_pdm0_groups[] = {
0573     "gpio31", "gpio95",
0574 };
0575 static const char * const gp_pdm1_groups[] = {
0576     "gpio32", "gpio96",
0577 };
0578 static const char * const gp_pdm2_groups[] = {
0579     "gpio33", "gpio97",
0580 };
0581 static const char * const nav_gpio_groups[] = {
0582     "gpio42", "gpio47", "gpio52", "gpio95", "gpio96", "gpio97", "gpio106",
0583     "gpio107", "gpio108",
0584 };
0585 static const char * const vfr_1_groups[] = {
0586     "gpio48",
0587 };
0588 static const char * const pa_indicator_groups[] = {
0589     "gpio49",
0590 };
0591 static const char * const gsm1_tx_groups[] = {
0592     "gpio53",
0593 };
0594 static const char * const ssbi_wtr1_groups[] = {
0595     "gpio59", "gpio60",
0596 };
0597 static const char * const pll_bypassnl_groups[] = {
0598     "gpio62",
0599 };
0600 static const char * const pll_reset_groups[] = {
0601     "gpio63",
0602 };
0603 static const char * const ddr_pxi0_groups[] = {
0604     "gpio63", "gpio64",
0605 };
0606 static const char * const gsm0_tx_groups[] = {
0607     "gpio64",
0608 };
0609 static const char * const gcc_gp2_groups[] = {
0610     "gpio69", "gpio107",
0611 };
0612 static const char * const ddr_pxi1_groups[] = {
0613     "gpio69", "gpio70",
0614 };
0615 static const char * const gcc_gp3_groups[] = {
0616     "gpio70", "gpio106",
0617 };
0618 static const char * const dbg_out_groups[] = {
0619     "gpio71",
0620 };
0621 static const char * const uim2_data_groups[] = {
0622     "gpio72",
0623 };
0624 static const char * const uim2_clk_groups[] = {
0625     "gpio73",
0626 };
0627 static const char * const uim2_reset_groups[] = {
0628     "gpio74",
0629 };
0630 static const char * const uim2_present_groups[] = {
0631     "gpio75",
0632 };
0633 static const char * const uim1_data_groups[] = {
0634     "gpio76",
0635 };
0636 static const char * const uim1_clk_groups[] = {
0637     "gpio77",
0638 };
0639 static const char * const uim1_reset_groups[] = {
0640     "gpio78",
0641 };
0642 static const char * const uim1_present_groups[] = {
0643     "gpio79",
0644 };
0645 static const char * const mdp_vsync_groups[] = {
0646     "gpio81", "gpio96", "gpio97",
0647 };
0648 static const char * const mdp_vsync_out_0_groups[] = {
0649     "gpio81",
0650 };
0651 static const char * const mdp_vsync_out_1_groups[] = {
0652     "gpio81",
0653 };
0654 static const char * const usb_phy_groups[] = {
0655     "gpio89",
0656 };
0657 static const char * const mss_lte_groups[] = {
0658     "gpio90", "gpio91",
0659 };
0660 static const char * const wlan1_adc0_groups[] = {
0661     "gpio94",
0662 };
0663 static const char * const wlan1_adc1_groups[] = {
0664     "gpio95",
0665 };
0666 static const char * const sd_write_groups[] = {
0667     "gpio96",
0668 };
0669 static const char * const jitter_bist_groups[] = {
0670     "gpio96", "gpio97",
0671 };
0672 static const char * const ddr_pxi2_groups[] = {
0673     "gpio102", "gpio103",
0674 };
0675 static const char * const ddr_pxi3_groups[] = {
0676     "gpio104", "gpio105",
0677 };
0678 
0679 static const struct msm_function sm6115_functions[] = {
0680     FUNCTION(adsp_ext),
0681     FUNCTION(agera_pll),
0682     FUNCTION(atest),
0683     FUNCTION(cam_mclk),
0684     FUNCTION(cci_async),
0685     FUNCTION(cci_i2c),
0686     FUNCTION(cci_timer),
0687     FUNCTION(cri_trng),
0688     FUNCTION(dac_calib),
0689     FUNCTION(dbg_out),
0690     FUNCTION(ddr_bist),
0691     FUNCTION(ddr_pxi0),
0692     FUNCTION(ddr_pxi1),
0693     FUNCTION(ddr_pxi2),
0694     FUNCTION(ddr_pxi3),
0695     FUNCTION(gcc_gp1),
0696     FUNCTION(gcc_gp2),
0697     FUNCTION(gcc_gp3),
0698     FUNCTION(gpio),
0699     FUNCTION(gp_pdm0),
0700     FUNCTION(gp_pdm1),
0701     FUNCTION(gp_pdm2),
0702     FUNCTION(gsm0_tx),
0703     FUNCTION(gsm1_tx),
0704     FUNCTION(jitter_bist),
0705     FUNCTION(mdp_vsync),
0706     FUNCTION(mdp_vsync_out_0),
0707     FUNCTION(mdp_vsync_out_1),
0708     FUNCTION(mpm_pwr),
0709     FUNCTION(mss_lte),
0710     FUNCTION(m_voc),
0711     FUNCTION(nav_gpio),
0712     FUNCTION(pa_indicator),
0713     FUNCTION(pbs),
0714     FUNCTION(pbs_out),
0715     FUNCTION(phase_flag),
0716     FUNCTION(pll_bist),
0717     FUNCTION(pll_bypassnl),
0718     FUNCTION(pll_reset),
0719     FUNCTION(prng_rosc),
0720     FUNCTION(qdss_cti),
0721     FUNCTION(qdss_gpio),
0722     FUNCTION(qup0),
0723     FUNCTION(qup1),
0724     FUNCTION(qup2),
0725     FUNCTION(qup3),
0726     FUNCTION(qup4),
0727     FUNCTION(qup5),
0728     FUNCTION(sdc1_tb),
0729     FUNCTION(sdc2_tb),
0730     FUNCTION(sd_write),
0731     FUNCTION(ssbi_wtr1),
0732     FUNCTION(tgu),
0733     FUNCTION(tsense_pwm),
0734     FUNCTION(uim1_clk),
0735     FUNCTION(uim1_data),
0736     FUNCTION(uim1_present),
0737     FUNCTION(uim1_reset),
0738     FUNCTION(uim2_clk),
0739     FUNCTION(uim2_data),
0740     FUNCTION(uim2_present),
0741     FUNCTION(uim2_reset),
0742     FUNCTION(usb_phy),
0743     FUNCTION(vfr_1),
0744     FUNCTION(vsense_trigger),
0745     FUNCTION(wlan1_adc0),
0746     FUNCTION(wlan1_adc1),
0747 };
0748 
0749 /* Every pin is maintained as a single group, and missing or non-existing pin
0750  * would be maintained as dummy group to synchronize pin group index with
0751  * pin descriptor registered with pinctrl core.
0752  * Clients would not be able to request these dummy pin groups.
0753  */
0754 static const struct msm_pingroup sm6115_groups[] = {
0755     [0] = PINGROUP(0, WEST, qup0, m_voc, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _),
0756     [1] = PINGROUP(1, WEST, qup0, mpm_pwr, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _),
0757     [2] = PINGROUP(2, WEST, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _),
0758     [3] = PINGROUP(3, WEST, qup0, ddr_bist, _, phase_flag, qdss_gpio, dac_calib, atest, _, _),
0759     [4] = PINGROUP(4, WEST, qup1, cri_trng, _, phase_flag, dac_calib, atest, _, _, _),
0760     [5] = PINGROUP(5, WEST, qup1, cri_trng, _, phase_flag, dac_calib, atest, _, _, _),
0761     [6] = PINGROUP(6, WEST, qup2, _, phase_flag, dac_calib, atest, _, _, _, _),
0762     [7] = PINGROUP(7, WEST, qup2, _, _, _, _, _, _, _, _),
0763     [8] = PINGROUP(8, EAST, qup3, pbs_out, pll_bist, _, qdss_gpio, _, tsense_pwm, _, _),
0764     [9] = PINGROUP(9, EAST, qup3, pbs_out, pll_bist, _, qdss_gpio, _, _, _, _),
0765     [10] = PINGROUP(10, EAST, qup3, agera_pll, _, pbs, qdss_gpio, _, _, _, _),
0766     [11] = PINGROUP(11, EAST, qup3, agera_pll, _, pbs, qdss_gpio, _, _, _, _),
0767     [12] = PINGROUP(12, WEST, qup4, tgu, _, _, _, _, _, _, _),
0768     [13] = PINGROUP(13, WEST, qup4, tgu, _, _, _, _, _, _, _),
0769     [14] = PINGROUP(14, WEST, qup5, tgu, _, phase_flag, qdss_gpio, dac_calib, _, _, _),
0770     [15] = PINGROUP(15, WEST, qup5, tgu, _, phase_flag, qdss_gpio, dac_calib, _, _, _),
0771     [16] = PINGROUP(16, WEST, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _),
0772     [17] = PINGROUP(17, WEST, qup5, _, phase_flag, qdss_gpio, dac_calib, _, _, _, _),
0773     [18] = PINGROUP(18, EAST, sdc2_tb, cri_trng, pbs, qdss_gpio, _, _, _, _, _),
0774     [19] = PINGROUP(19, EAST, sdc1_tb, pbs, qdss_gpio, _, _, _, _, _, _),
0775     [20] = PINGROUP(20, EAST, cam_mclk, pbs, qdss_gpio, _, _, _, _, _, _),
0776     [21] = PINGROUP(21, EAST, cam_mclk, adsp_ext, pbs, qdss_gpio, _, _, _, _, _),
0777     [22] = PINGROUP(22, EAST, cci_i2c, prng_rosc, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _),
0778     [23] = PINGROUP(23, EAST, cci_i2c, prng_rosc, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _),
0779     [24] = PINGROUP(24, EAST, cci_timer, gcc_gp1, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _),
0780     [25] = PINGROUP(25, EAST, cci_async, cci_timer, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, _),
0781     [26] = PINGROUP(26, EAST, _, pbs, phase_flag, qdss_gpio, dac_calib, atest, vsense_trigger, _, _),
0782     [27] = PINGROUP(27, EAST, cam_mclk, qdss_cti, _, _, _, _, _, _, _),
0783     [28] = PINGROUP(28, EAST, cam_mclk, cci_timer, qdss_cti, _, _, _, _, _, _),
0784     [29] = PINGROUP(29, EAST, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _),
0785     [30] = PINGROUP(30, EAST, cci_i2c, _, phase_flag, dac_calib, atest, _, _, _, _),
0786     [31] = PINGROUP(31, EAST, gp_pdm0, _, phase_flag, dac_calib, atest, _, _, _, _),
0787     [32] = PINGROUP(32, EAST, cci_timer, gp_pdm1, _, phase_flag, dac_calib, atest, _, _, _),
0788     [33] = PINGROUP(33, EAST, gp_pdm2, _, phase_flag, dac_calib, atest, _, _, _, _),
0789     [34] = PINGROUP(34, EAST, _, _, _, _, _, _, _, _, _),
0790     [35] = PINGROUP(35, EAST, _, phase_flag, _, _, _, _, _, _, _),
0791     [36] = PINGROUP(36, EAST, _, phase_flag, _, _, _, _, _, _, _),
0792     [37] = PINGROUP(37, EAST, _, _, _, _, _, _, _, _, _),
0793     [38] = PINGROUP(38, EAST, _, _, _, _, _, _, _, _, _),
0794     [39] = PINGROUP(39, EAST, _, _, _, _, _, _, _, _, _),
0795     [40] = PINGROUP(40, EAST, _, _, _, _, _, _, _, _, _),
0796     [41] = PINGROUP(41, EAST, _, _, _, _, _, _, _, _, _),
0797     [42] = PINGROUP(42, EAST, _, nav_gpio, _, _, _, _, _, _, _),
0798     [43] = PINGROUP(43, EAST, _, _, phase_flag, _, _, _, _, _, _),
0799     [44] = PINGROUP(44, EAST, _, _, phase_flag, _, _, _, _, _, _),
0800     [45] = PINGROUP(45, EAST, _, _, phase_flag, _, _, _, _, _, _),
0801     [46] = PINGROUP(46, EAST, _, _, _, _, _, _, _, _, _),
0802     [47] = PINGROUP(47, EAST, _, nav_gpio, pbs, qdss_gpio, _, _, _, _, _),
0803     [48] = PINGROUP(48, EAST, _, vfr_1, _, pbs, qdss_gpio, _, _, _, _),
0804     [49] = PINGROUP(49, EAST, _, pa_indicator, _, _, _, _, _, _, _),
0805     [50] = PINGROUP(50, EAST, _, _, _, _, _, _, _, _, _),
0806     [51] = PINGROUP(51, EAST, _, _, _, _, _, _, _, _, _),
0807     [52] = PINGROUP(52, EAST, _, nav_gpio, pbs_out, _, _, _, _, _, _),
0808     [53] = PINGROUP(53, EAST, _, gsm1_tx, _, _, _, _, _, _, _),
0809     [54] = PINGROUP(54, EAST, _, _, _, _, _, _, _, _, _),
0810     [55] = PINGROUP(55, EAST, _, _, _, _, _, _, _, _, _),
0811     [56] = PINGROUP(56, EAST, _, _, _, _, _, _, _, _, _),
0812     [57] = PINGROUP(57, EAST, _, _, _, _, _, _, _, _, _),
0813     [58] = PINGROUP(58, EAST, _, _, _, _, _, _, _, _, _),
0814     [59] = PINGROUP(59, EAST, _, ssbi_wtr1, _, _, _, _, _, _, _),
0815     [60] = PINGROUP(60, EAST, _, ssbi_wtr1, _, _, _, _, _, _, _),
0816     [61] = PINGROUP(61, EAST, _, _, _, _, _, _, _, _, _),
0817     [62] = PINGROUP(62, EAST, _, pll_bypassnl, _, _, _, _, _, _, _),
0818     [63] = PINGROUP(63, EAST, pll_reset, _, phase_flag, ddr_pxi0, _, _, _, _, _),
0819     [64] = PINGROUP(64, EAST, gsm0_tx, _, phase_flag, ddr_pxi0, _, _, _, _, _),
0820     [65] = PINGROUP(65, WEST, _, _, _, _, _, _, _, _, _),
0821     [66] = PINGROUP(66, WEST, _, _, _, _, _, _, _, _, _),
0822     [67] = PINGROUP(67, WEST, _, _, _, _, _, _, _, _, _),
0823     [68] = PINGROUP(68, WEST, _, _, _, _, _, _, _, _, _),
0824     [69] = PINGROUP(69, WEST, qup1, gcc_gp2, qdss_gpio, ddr_pxi1, _, _, _, _, _),
0825     [70] = PINGROUP(70, WEST, qup1, gcc_gp3, qdss_gpio, ddr_pxi1, _, _, _, _, _),
0826     [71] = PINGROUP(71, WEST, qup2, dbg_out, _, _, _, _, _, _, _),
0827     [72] = PINGROUP(72, SOUTH, uim2_data, qdss_cti, _, _, _, _, _, _, _),
0828     [73] = PINGROUP(73, SOUTH, uim2_clk, _, qdss_cti, _, _, _, _, _, _),
0829     [74] = PINGROUP(74, SOUTH, uim2_reset, _, _, _, _, _, _, _, _),
0830     [75] = PINGROUP(75, SOUTH, uim2_present, _, _, _, _, _, _, _, _),
0831     [76] = PINGROUP(76, SOUTH, uim1_data, _, _, _, _, _, _, _, _),
0832     [77] = PINGROUP(77, SOUTH, uim1_clk, _, _, _, _, _, _, _, _),
0833     [78] = PINGROUP(78, SOUTH, uim1_reset, _, _, _, _, _, _, _, _),
0834     [79] = PINGROUP(79, SOUTH, uim1_present, _, _, _, _, _, _, _, _),
0835     [80] = PINGROUP(80, WEST, qup2, dac_calib, _, _, _, _, _, _, _),
0836     [81] = PINGROUP(81, WEST, mdp_vsync_out_0, mdp_vsync_out_1, mdp_vsync, dac_calib, _, _, _, _, _),
0837     [82] = PINGROUP(82, WEST, qup0, dac_calib, _, _, _, _, _, _, _),
0838     [83] = PINGROUP(83, WEST, _, _, _, _, _, _, _, _, _),
0839     [84] = PINGROUP(84, WEST, _, _, _, _, _, _, _, _, _),
0840     [85] = PINGROUP(85, WEST, _, _, _, _, _, _, _, _, _),
0841     [86] = PINGROUP(86, WEST, qup0, gcc_gp1, atest, _, _, _, _, _, _),
0842     [87] = PINGROUP(87, EAST, pbs, qdss_gpio, _, _, _, _, _, _, _),
0843     [88] = PINGROUP(88, EAST, _, _, _, _, _, _, _, _, _),
0844     [89] = PINGROUP(89, WEST, usb_phy, atest, _, _, _, _, _, _, _),
0845     [90] = PINGROUP(90, EAST, mss_lte, pbs, qdss_gpio, _, _, _, _, _, _),
0846     [91] = PINGROUP(91, EAST, mss_lte, pbs, qdss_gpio, _, _, _, _, _, _),
0847     [92] = PINGROUP(92, WEST, _, _, _, _, _, _, _, _, _),
0848     [93] = PINGROUP(93, WEST, _, _, _, _, _, _, _, _, _),
0849     [94] = PINGROUP(94, WEST, _, qdss_gpio, wlan1_adc0, _, _, _, _, _, _),
0850     [95] = PINGROUP(95, WEST, nav_gpio, gp_pdm0, qdss_gpio, wlan1_adc1, _, _, _, _, _),
0851     [96] = PINGROUP(96, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm1, sd_write, jitter_bist, qdss_cti, qdss_cti, _),
0852     [97] = PINGROUP(97, WEST, qup4, nav_gpio, mdp_vsync, gp_pdm2, jitter_bist, qdss_cti, qdss_cti, _, _),
0853     [98] = PINGROUP(98, SOUTH, _, _, _, _, _, _, _, _, _),
0854     [99] = PINGROUP(99, SOUTH, _, _, _, _, _, _, _, _, _),
0855     [100] = PINGROUP(100, SOUTH, atest, _, _, _, _, _, _, _, _),
0856     [101] = PINGROUP(101, SOUTH, atest, _, _, _, _, _, _, _, _),
0857     [102] = PINGROUP(102, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _),
0858     [103] = PINGROUP(103, SOUTH, _, phase_flag, dac_calib, ddr_pxi2, _, _, _, _, _),
0859     [104] = PINGROUP(104, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _),
0860     [105] = PINGROUP(105, SOUTH, _, phase_flag, qdss_gpio, dac_calib, ddr_pxi3, _, _, _, _),
0861     [106] = PINGROUP(106, SOUTH, nav_gpio, gcc_gp3, qdss_gpio, _, _, _, _, _, _),
0862     [107] = PINGROUP(107, SOUTH, nav_gpio, gcc_gp2, qdss_gpio, _, _, _, _, _, _),
0863     [108] = PINGROUP(108, SOUTH, nav_gpio, _, _, _, _, _, _, _, _),
0864     [109] = PINGROUP(109, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _),
0865     [110] = PINGROUP(110, SOUTH, _, qdss_gpio, _, _, _, _, _, _, _),
0866     [111] = PINGROUP(111, SOUTH, _, _, _, _, _, _, _, _, _),
0867     [112] = PINGROUP(112, SOUTH, _, _, _, _, _, _, _, _, _),
0868     [113] = UFS_RESET(ufs_reset, 0x78000),
0869     [114] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x75000, 15, 0),
0870     [115] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x75000, 13, 6),
0871     [116] = SDC_QDSD_PINGROUP(sdc1_cmd, WEST, 0x75000, 11, 3),
0872     [117] = SDC_QDSD_PINGROUP(sdc1_data, WEST, 0x75000, 9, 0),
0873     [118] = SDC_QDSD_PINGROUP(sdc2_clk, SOUTH, 0x73000, 14, 6),
0874     [119] = SDC_QDSD_PINGROUP(sdc2_cmd, SOUTH, 0x73000, 11, 3),
0875     [120] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x73000, 9, 0),
0876 };
0877 
0878 static const struct msm_pinctrl_soc_data sm6115_tlmm = {
0879     .pins = sm6115_pins,
0880     .npins = ARRAY_SIZE(sm6115_pins),
0881     .functions = sm6115_functions,
0882     .nfunctions = ARRAY_SIZE(sm6115_functions),
0883     .groups = sm6115_groups,
0884     .ngroups = ARRAY_SIZE(sm6115_groups),
0885     .ngpios = 114,
0886     .tiles = sm6115_tiles,
0887     .ntiles = ARRAY_SIZE(sm6115_tiles),
0888 };
0889 
0890 static int sm6115_tlmm_probe(struct platform_device *pdev)
0891 {
0892     return msm_pinctrl_probe(pdev, &sm6115_tlmm);
0893 }
0894 
0895 static const struct of_device_id sm6115_tlmm_of_match[] = {
0896     { .compatible = "qcom,sm6115-tlmm", },
0897     { }
0898 };
0899 
0900 static struct platform_driver sm6115_tlmm_driver = {
0901     .driver = {
0902         .name = "sm6115-tlmm",
0903         .of_match_table = sm6115_tlmm_of_match,
0904     },
0905     .probe = sm6115_tlmm_probe,
0906     .remove = msm_pinctrl_remove,
0907 };
0908 
0909 static int __init sm6115_tlmm_init(void)
0910 {
0911     return platform_driver_register(&sm6115_tlmm_driver);
0912 }
0913 arch_initcall(sm6115_tlmm_init);
0914 
0915 static void __exit sm6115_tlmm_exit(void)
0916 {
0917     platform_driver_unregister(&sm6115_tlmm_driver);
0918 }
0919 module_exit(sm6115_tlmm_exit);
0920 
0921 MODULE_DESCRIPTION("QTI sm6115 tlmm driver");
0922 MODULE_LICENSE("GPL v2");
0923 MODULE_DEVICE_TABLE(of, sm6115_tlmm_of_match);
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