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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
0004  */
0005 
0006 #include <linux/module.h>
0007 #include <linux/of.h>
0008 #include <linux/platform_device.h>
0009 #include <linux/pinctrl/pinctrl.h>
0010 
0011 #include "pinctrl-msm.h"
0012 
0013 #define FUNCTION(fname)                         \
0014     [msm_mux_##fname] = {                       \
0015         .name = #fname,             \
0016         .groups = fname##_groups,               \
0017         .ngroups = ARRAY_SIZE(fname##_groups),  \
0018     }
0019 
0020 #define REG_BASE 0x0
0021 #define REG_SIZE 0x1000
0022 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)    \
0023     {                           \
0024         .name = "gpio" #id,         \
0025         .pins = gpio##id##_pins,        \
0026         .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
0027         .funcs = (int[]){           \
0028             msm_mux_gpio, /* gpio mode */   \
0029             msm_mux_##f1,           \
0030             msm_mux_##f2,           \
0031             msm_mux_##f3,           \
0032             msm_mux_##f4,           \
0033             msm_mux_##f5,           \
0034             msm_mux_##f6,           \
0035             msm_mux_##f7,           \
0036             msm_mux_##f8,           \
0037             msm_mux_##f9            \
0038         },                      \
0039         .nfuncs = 10,               \
0040         .ctl_reg = REG_BASE + REG_SIZE * id,            \
0041         .io_reg = REG_BASE + 0x4 + REG_SIZE * id,       \
0042         .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id,     \
0043         .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id,  \
0044         .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id,  \
0045         .mux_bit = 2,           \
0046         .pull_bit = 0,          \
0047         .drv_bit = 6,           \
0048         .oe_bit = 9,            \
0049         .in_bit = 0,            \
0050         .out_bit = 1,           \
0051         .intr_enable_bit = 0,       \
0052         .intr_status_bit = 0,       \
0053         .intr_target_bit = 5,       \
0054         .intr_target_kpss_val = 3,  \
0055         .intr_raw_status_bit = 4,   \
0056         .intr_polarity_bit = 1,     \
0057         .intr_detection_bit = 2,    \
0058         .intr_detection_width = 2,  \
0059     }
0060 
0061 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv)  \
0062     {                           \
0063         .name = #pg_name,           \
0064         .pins = pg_name##_pins,         \
0065         .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins),  \
0066         .ctl_reg = ctl,             \
0067         .io_reg = 0,                \
0068         .intr_cfg_reg = 0,          \
0069         .intr_status_reg = 0,           \
0070         .intr_target_reg = 0,           \
0071         .mux_bit = -1,              \
0072         .pull_bit = pull,           \
0073         .drv_bit = drv,             \
0074         .oe_bit = -1,               \
0075         .in_bit = -1,               \
0076         .out_bit = -1,              \
0077         .intr_enable_bit = -1,          \
0078         .intr_status_bit = -1,          \
0079         .intr_target_bit = -1,          \
0080         .intr_raw_status_bit = -1,      \
0081         .intr_polarity_bit = -1,        \
0082         .intr_detection_bit = -1,       \
0083         .intr_detection_width = -1,     \
0084     }
0085 
0086 #define UFS_RESET(pg_name, offset)              \
0087     {                           \
0088         .name = #pg_name,           \
0089         .pins = pg_name##_pins,         \
0090         .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins),  \
0091         .ctl_reg = offset,          \
0092         .io_reg = offset + 0x4,         \
0093         .intr_cfg_reg = 0,          \
0094         .intr_status_reg = 0,           \
0095         .intr_target_reg = 0,           \
0096         .mux_bit = -1,              \
0097         .pull_bit = 3,              \
0098         .drv_bit = 0,               \
0099         .oe_bit = -1,               \
0100         .in_bit = -1,               \
0101         .out_bit = 0,               \
0102         .intr_enable_bit = -1,          \
0103         .intr_status_bit = -1,          \
0104         .intr_target_bit = -1,          \
0105         .intr_raw_status_bit = -1,      \
0106         .intr_polarity_bit = -1,        \
0107         .intr_detection_bit = -1,       \
0108         .intr_detection_width = -1,     \
0109     }
0110 
0111 static const struct pinctrl_pin_desc sdx65_pins[] = {
0112     PINCTRL_PIN(0, "GPIO_0"),
0113     PINCTRL_PIN(1, "GPIO_1"),
0114     PINCTRL_PIN(2, "GPIO_2"),
0115     PINCTRL_PIN(3, "GPIO_3"),
0116     PINCTRL_PIN(4, "GPIO_4"),
0117     PINCTRL_PIN(5, "GPIO_5"),
0118     PINCTRL_PIN(6, "GPIO_6"),
0119     PINCTRL_PIN(7, "GPIO_7"),
0120     PINCTRL_PIN(8, "GPIO_8"),
0121     PINCTRL_PIN(9, "GPIO_9"),
0122     PINCTRL_PIN(10, "GPIO_10"),
0123     PINCTRL_PIN(11, "GPIO_11"),
0124     PINCTRL_PIN(12, "GPIO_12"),
0125     PINCTRL_PIN(13, "GPIO_13"),
0126     PINCTRL_PIN(14, "GPIO_14"),
0127     PINCTRL_PIN(15, "GPIO_15"),
0128     PINCTRL_PIN(16, "GPIO_16"),
0129     PINCTRL_PIN(17, "GPIO_17"),
0130     PINCTRL_PIN(18, "GPIO_18"),
0131     PINCTRL_PIN(19, "GPIO_19"),
0132     PINCTRL_PIN(20, "GPIO_20"),
0133     PINCTRL_PIN(21, "GPIO_21"),
0134     PINCTRL_PIN(22, "GPIO_22"),
0135     PINCTRL_PIN(23, "GPIO_23"),
0136     PINCTRL_PIN(24, "GPIO_24"),
0137     PINCTRL_PIN(25, "GPIO_25"),
0138     PINCTRL_PIN(26, "GPIO_26"),
0139     PINCTRL_PIN(27, "GPIO_27"),
0140     PINCTRL_PIN(28, "GPIO_28"),
0141     PINCTRL_PIN(29, "GPIO_29"),
0142     PINCTRL_PIN(30, "GPIO_30"),
0143     PINCTRL_PIN(31, "GPIO_31"),
0144     PINCTRL_PIN(32, "GPIO_32"),
0145     PINCTRL_PIN(33, "GPIO_33"),
0146     PINCTRL_PIN(34, "GPIO_34"),
0147     PINCTRL_PIN(35, "GPIO_35"),
0148     PINCTRL_PIN(36, "GPIO_36"),
0149     PINCTRL_PIN(37, "GPIO_37"),
0150     PINCTRL_PIN(38, "GPIO_38"),
0151     PINCTRL_PIN(39, "GPIO_39"),
0152     PINCTRL_PIN(40, "GPIO_40"),
0153     PINCTRL_PIN(41, "GPIO_41"),
0154     PINCTRL_PIN(42, "GPIO_42"),
0155     PINCTRL_PIN(43, "GPIO_43"),
0156     PINCTRL_PIN(44, "GPIO_44"),
0157     PINCTRL_PIN(45, "GPIO_45"),
0158     PINCTRL_PIN(46, "GPIO_46"),
0159     PINCTRL_PIN(47, "GPIO_47"),
0160     PINCTRL_PIN(48, "GPIO_48"),
0161     PINCTRL_PIN(49, "GPIO_49"),
0162     PINCTRL_PIN(50, "GPIO_50"),
0163     PINCTRL_PIN(51, "GPIO_51"),
0164     PINCTRL_PIN(52, "GPIO_52"),
0165     PINCTRL_PIN(53, "GPIO_53"),
0166     PINCTRL_PIN(54, "GPIO_54"),
0167     PINCTRL_PIN(55, "GPIO_55"),
0168     PINCTRL_PIN(56, "GPIO_56"),
0169     PINCTRL_PIN(57, "GPIO_57"),
0170     PINCTRL_PIN(58, "GPIO_58"),
0171     PINCTRL_PIN(59, "GPIO_59"),
0172     PINCTRL_PIN(60, "GPIO_60"),
0173     PINCTRL_PIN(61, "GPIO_61"),
0174     PINCTRL_PIN(62, "GPIO_62"),
0175     PINCTRL_PIN(63, "GPIO_63"),
0176     PINCTRL_PIN(64, "GPIO_64"),
0177     PINCTRL_PIN(65, "GPIO_65"),
0178     PINCTRL_PIN(66, "GPIO_66"),
0179     PINCTRL_PIN(67, "GPIO_67"),
0180     PINCTRL_PIN(68, "GPIO_68"),
0181     PINCTRL_PIN(69, "GPIO_69"),
0182     PINCTRL_PIN(70, "GPIO_70"),
0183     PINCTRL_PIN(71, "GPIO_71"),
0184     PINCTRL_PIN(72, "GPIO_72"),
0185     PINCTRL_PIN(73, "GPIO_73"),
0186     PINCTRL_PIN(74, "GPIO_74"),
0187     PINCTRL_PIN(75, "GPIO_75"),
0188     PINCTRL_PIN(76, "GPIO_76"),
0189     PINCTRL_PIN(77, "GPIO_77"),
0190     PINCTRL_PIN(78, "GPIO_78"),
0191     PINCTRL_PIN(79, "GPIO_79"),
0192     PINCTRL_PIN(80, "GPIO_80"),
0193     PINCTRL_PIN(81, "GPIO_81"),
0194     PINCTRL_PIN(82, "GPIO_82"),
0195     PINCTRL_PIN(83, "GPIO_83"),
0196     PINCTRL_PIN(84, "GPIO_84"),
0197     PINCTRL_PIN(85, "GPIO_85"),
0198     PINCTRL_PIN(86, "GPIO_86"),
0199     PINCTRL_PIN(87, "GPIO_87"),
0200     PINCTRL_PIN(88, "GPIO_88"),
0201     PINCTRL_PIN(89, "GPIO_89"),
0202     PINCTRL_PIN(90, "GPIO_90"),
0203     PINCTRL_PIN(91, "GPIO_91"),
0204     PINCTRL_PIN(92, "GPIO_92"),
0205     PINCTRL_PIN(93, "GPIO_93"),
0206     PINCTRL_PIN(94, "GPIO_94"),
0207     PINCTRL_PIN(95, "GPIO_95"),
0208     PINCTRL_PIN(96, "GPIO_96"),
0209     PINCTRL_PIN(97, "GPIO_97"),
0210     PINCTRL_PIN(98, "GPIO_98"),
0211     PINCTRL_PIN(99, "GPIO_99"),
0212     PINCTRL_PIN(100, "GPIO_100"),
0213     PINCTRL_PIN(101, "GPIO_101"),
0214     PINCTRL_PIN(102, "GPIO_102"),
0215     PINCTRL_PIN(103, "GPIO_103"),
0216     PINCTRL_PIN(104, "GPIO_104"),
0217     PINCTRL_PIN(105, "GPIO_105"),
0218     PINCTRL_PIN(106, "GPIO_106"),
0219     PINCTRL_PIN(107, "GPIO_107"),
0220     PINCTRL_PIN(108, "UFS_RESET"),
0221     PINCTRL_PIN(109, "SDC1_RCLK"),
0222     PINCTRL_PIN(110, "SDC1_CLK"),
0223     PINCTRL_PIN(111, "SDC1_CMD"),
0224     PINCTRL_PIN(112, "SDC1_DATA"),
0225 };
0226 
0227 #define DECLARE_MSM_GPIO_PINS(pin) \
0228     static const unsigned int gpio##pin##_pins[] = { pin }
0229 DECLARE_MSM_GPIO_PINS(0);
0230 DECLARE_MSM_GPIO_PINS(1);
0231 DECLARE_MSM_GPIO_PINS(2);
0232 DECLARE_MSM_GPIO_PINS(3);
0233 DECLARE_MSM_GPIO_PINS(4);
0234 DECLARE_MSM_GPIO_PINS(5);
0235 DECLARE_MSM_GPIO_PINS(6);
0236 DECLARE_MSM_GPIO_PINS(7);
0237 DECLARE_MSM_GPIO_PINS(8);
0238 DECLARE_MSM_GPIO_PINS(9);
0239 DECLARE_MSM_GPIO_PINS(10);
0240 DECLARE_MSM_GPIO_PINS(11);
0241 DECLARE_MSM_GPIO_PINS(12);
0242 DECLARE_MSM_GPIO_PINS(13);
0243 DECLARE_MSM_GPIO_PINS(14);
0244 DECLARE_MSM_GPIO_PINS(15);
0245 DECLARE_MSM_GPIO_PINS(16);
0246 DECLARE_MSM_GPIO_PINS(17);
0247 DECLARE_MSM_GPIO_PINS(18);
0248 DECLARE_MSM_GPIO_PINS(19);
0249 DECLARE_MSM_GPIO_PINS(20);
0250 DECLARE_MSM_GPIO_PINS(21);
0251 DECLARE_MSM_GPIO_PINS(22);
0252 DECLARE_MSM_GPIO_PINS(23);
0253 DECLARE_MSM_GPIO_PINS(24);
0254 DECLARE_MSM_GPIO_PINS(25);
0255 DECLARE_MSM_GPIO_PINS(26);
0256 DECLARE_MSM_GPIO_PINS(27);
0257 DECLARE_MSM_GPIO_PINS(28);
0258 DECLARE_MSM_GPIO_PINS(29);
0259 DECLARE_MSM_GPIO_PINS(30);
0260 DECLARE_MSM_GPIO_PINS(31);
0261 DECLARE_MSM_GPIO_PINS(32);
0262 DECLARE_MSM_GPIO_PINS(33);
0263 DECLARE_MSM_GPIO_PINS(34);
0264 DECLARE_MSM_GPIO_PINS(35);
0265 DECLARE_MSM_GPIO_PINS(36);
0266 DECLARE_MSM_GPIO_PINS(37);
0267 DECLARE_MSM_GPIO_PINS(38);
0268 DECLARE_MSM_GPIO_PINS(39);
0269 DECLARE_MSM_GPIO_PINS(40);
0270 DECLARE_MSM_GPIO_PINS(41);
0271 DECLARE_MSM_GPIO_PINS(42);
0272 DECLARE_MSM_GPIO_PINS(43);
0273 DECLARE_MSM_GPIO_PINS(44);
0274 DECLARE_MSM_GPIO_PINS(45);
0275 DECLARE_MSM_GPIO_PINS(46);
0276 DECLARE_MSM_GPIO_PINS(47);
0277 DECLARE_MSM_GPIO_PINS(48);
0278 DECLARE_MSM_GPIO_PINS(49);
0279 DECLARE_MSM_GPIO_PINS(50);
0280 DECLARE_MSM_GPIO_PINS(51);
0281 DECLARE_MSM_GPIO_PINS(52);
0282 DECLARE_MSM_GPIO_PINS(53);
0283 DECLARE_MSM_GPIO_PINS(54);
0284 DECLARE_MSM_GPIO_PINS(55);
0285 DECLARE_MSM_GPIO_PINS(56);
0286 DECLARE_MSM_GPIO_PINS(57);
0287 DECLARE_MSM_GPIO_PINS(58);
0288 DECLARE_MSM_GPIO_PINS(59);
0289 DECLARE_MSM_GPIO_PINS(60);
0290 DECLARE_MSM_GPIO_PINS(61);
0291 DECLARE_MSM_GPIO_PINS(62);
0292 DECLARE_MSM_GPIO_PINS(63);
0293 DECLARE_MSM_GPIO_PINS(64);
0294 DECLARE_MSM_GPIO_PINS(65);
0295 DECLARE_MSM_GPIO_PINS(66);
0296 DECLARE_MSM_GPIO_PINS(67);
0297 DECLARE_MSM_GPIO_PINS(68);
0298 DECLARE_MSM_GPIO_PINS(69);
0299 DECLARE_MSM_GPIO_PINS(70);
0300 DECLARE_MSM_GPIO_PINS(71);
0301 DECLARE_MSM_GPIO_PINS(72);
0302 DECLARE_MSM_GPIO_PINS(73);
0303 DECLARE_MSM_GPIO_PINS(74);
0304 DECLARE_MSM_GPIO_PINS(75);
0305 DECLARE_MSM_GPIO_PINS(76);
0306 DECLARE_MSM_GPIO_PINS(77);
0307 DECLARE_MSM_GPIO_PINS(78);
0308 DECLARE_MSM_GPIO_PINS(79);
0309 DECLARE_MSM_GPIO_PINS(80);
0310 DECLARE_MSM_GPIO_PINS(81);
0311 DECLARE_MSM_GPIO_PINS(82);
0312 DECLARE_MSM_GPIO_PINS(83);
0313 DECLARE_MSM_GPIO_PINS(84);
0314 DECLARE_MSM_GPIO_PINS(85);
0315 DECLARE_MSM_GPIO_PINS(86);
0316 DECLARE_MSM_GPIO_PINS(87);
0317 DECLARE_MSM_GPIO_PINS(88);
0318 DECLARE_MSM_GPIO_PINS(89);
0319 DECLARE_MSM_GPIO_PINS(90);
0320 DECLARE_MSM_GPIO_PINS(91);
0321 DECLARE_MSM_GPIO_PINS(92);
0322 DECLARE_MSM_GPIO_PINS(93);
0323 DECLARE_MSM_GPIO_PINS(94);
0324 DECLARE_MSM_GPIO_PINS(95);
0325 DECLARE_MSM_GPIO_PINS(96);
0326 DECLARE_MSM_GPIO_PINS(97);
0327 DECLARE_MSM_GPIO_PINS(98);
0328 DECLARE_MSM_GPIO_PINS(99);
0329 DECLARE_MSM_GPIO_PINS(100);
0330 DECLARE_MSM_GPIO_PINS(101);
0331 DECLARE_MSM_GPIO_PINS(102);
0332 DECLARE_MSM_GPIO_PINS(103);
0333 DECLARE_MSM_GPIO_PINS(104);
0334 DECLARE_MSM_GPIO_PINS(105);
0335 DECLARE_MSM_GPIO_PINS(106);
0336 DECLARE_MSM_GPIO_PINS(107);
0337 
0338 static const unsigned int ufs_reset_pins[] = { 108 };
0339 static const unsigned int sdc1_rclk_pins[] = { 109 };
0340 static const unsigned int sdc1_clk_pins[] = { 110 };
0341 static const unsigned int sdc1_cmd_pins[] = { 111 };
0342 static const unsigned int sdc1_data_pins[] = { 112 };
0343 
0344 enum sdx65_functions {
0345     msm_mux_qlink0_wmss,
0346     msm_mux_adsp_ext,
0347     msm_mux_atest_char,
0348     msm_mux_atest_char0,
0349     msm_mux_atest_char1,
0350     msm_mux_atest_char2,
0351     msm_mux_atest_char3,
0352     msm_mux_audio_ref,
0353     msm_mux_bimc_dte0,
0354     msm_mux_bimc_dte1,
0355     msm_mux_blsp_i2c1,
0356     msm_mux_blsp_i2c2,
0357     msm_mux_blsp_i2c3,
0358     msm_mux_blsp_i2c4,
0359     msm_mux_blsp_spi1,
0360     msm_mux_blsp_spi2,
0361     msm_mux_blsp_spi3,
0362     msm_mux_blsp_spi4,
0363     msm_mux_blsp_uart1,
0364     msm_mux_blsp_uart2,
0365     msm_mux_blsp_uart3,
0366     msm_mux_blsp_uart4,
0367     msm_mux_char_exec,
0368     msm_mux_coex_uart,
0369     msm_mux_coex_uart2,
0370     msm_mux_cri_trng,
0371     msm_mux_cri_trng0,
0372     msm_mux_cri_trng1,
0373     msm_mux_dbg_out,
0374     msm_mux_ddr_bist,
0375     msm_mux_ddr_pxi0,
0376     msm_mux_ebi0_wrcdc,
0377     msm_mux_ebi2_a,
0378     msm_mux_ebi2_lcd,
0379     msm_mux_ext_dbg,
0380     msm_mux_gcc_gp1,
0381     msm_mux_gcc_gp2,
0382     msm_mux_gcc_gp3,
0383     msm_mux_gcc_plltest,
0384     msm_mux_gpio,
0385     msm_mux_i2s_mclk,
0386     msm_mux_jitter_bist,
0387     msm_mux_ldo_en,
0388     msm_mux_ldo_update,
0389     msm_mux_m_voc,
0390     msm_mux_mgpi_clk,
0391     msm_mux_native_char,
0392     msm_mux_native_tsens,
0393     msm_mux_native_tsense,
0394     msm_mux_nav_gpio,
0395     msm_mux_pa_indicator,
0396     msm_mux_pci_e,
0397     msm_mux_pcie_clkreq,
0398     msm_mux_pll_bist,
0399     msm_mux_pll_ref,
0400     msm_mux_pri_mi2s,
0401     msm_mux_pri_mi2s_ws,
0402     msm_mux_prng_rosc,
0403     msm_mux_qdss_cti,
0404     msm_mux_qdss_gpio,
0405     msm_mux_qlink0_en,
0406     msm_mux_qlink0_req,
0407     msm_mux_qlink1_en,
0408     msm_mux_qlink1_req,
0409     msm_mux_qlink1_wmss,
0410     msm_mux_qlink2_en,
0411     msm_mux_qlink2_req,
0412     msm_mux_qlink2_wmss,
0413     msm_mux_sdc1_tb,
0414     msm_mux_sec_mi2s,
0415     msm_mux_spmi_coex,
0416     msm_mux_spmi_vgi,
0417     msm_mux_tgu_ch0,
0418     msm_mux_uim1_clk,
0419     msm_mux_uim1_data,
0420     msm_mux_uim1_present,
0421     msm_mux_uim1_reset,
0422     msm_mux_uim2_clk,
0423     msm_mux_uim2_data,
0424     msm_mux_uim2_present,
0425     msm_mux_uim2_reset,
0426     msm_mux_usb2phy_ac,
0427     msm_mux_vsense_trigger,
0428     msm_mux__,
0429 };
0430 
0431 static const char * const gpio_groups[] = {
0432     "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
0433     "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
0434     "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
0435     "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
0436     "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
0437     "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
0438     "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
0439     "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
0440     "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
0441     "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
0442     "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
0443     "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
0444     "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
0445     "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
0446     "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
0447     "gpio105", "gpio106", "gpio107",
0448 };
0449 static const char * const uim2_data_groups[] = {
0450     "gpio0",
0451 };
0452 static const char * const blsp_uart1_groups[] = {
0453     "gpio0", "gpio1", "gpio2", "gpio3", "gpio48", "gpio49", "gpio80",
0454     "gpio81",
0455 };
0456 static const char * const ebi0_wrcdc_groups[] = {
0457     "gpio0", "gpio2",
0458 };
0459 static const char * const uim2_present_groups[] = {
0460     "gpio1",
0461 };
0462 static const char * const uim2_reset_groups[] = {
0463     "gpio2",
0464 };
0465 static const char * const blsp_i2c1_groups[] = {
0466     "gpio2", "gpio3", "gpio82", "gpio83",
0467 };
0468 static const char * const uim2_clk_groups[] = {
0469     "gpio3",
0470 };
0471 static const char * const blsp_spi2_groups[] = {
0472     "gpio4", "gpio5", "gpio6", "gpio7", "gpio23", "gpio47", "gpio62",
0473 };
0474 static const char * const blsp_uart2_groups[] = {
0475     "gpio4", "gpio5", "gpio6", "gpio7", "gpio63", "gpio64", "gpio65",
0476     "gpio66",
0477 };
0478 static const char * const blsp_i2c2_groups[] = {
0479     "gpio6", "gpio7", "gpio65", "gpio66",
0480 };
0481 static const char * const char_exec_groups[] = {
0482     "gpio6", "gpio7",
0483 };
0484 static const char * const qdss_gpio_groups[] = {
0485     "gpio4", "gpio5", "gpio6", "gpio7", "gpio12", "gpio13",
0486     "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
0487     "gpio33", "gpio42", "gpio63", "gpio64", "gpio65", "gpio66",
0488 };
0489 static const char * const blsp_spi3_groups[] = {
0490     "gpio8", "gpio9", "gpio10", "gpio11", "gpio23", "gpio47", "gpio62",
0491 };
0492 static const char * const blsp_uart3_groups[] = {
0493     "gpio8", "gpio9", "gpio10", "gpio11",
0494 };
0495 static const char * const ext_dbg_groups[] = {
0496     "gpio8", "gpio9", "gpio10", "gpio11",
0497 };
0498 static const char * const ldo_en_groups[] = {
0499     "gpio8",
0500 };
0501 static const char * const blsp_i2c3_groups[] = {
0502     "gpio10", "gpio11",
0503 };
0504 static const char * const gcc_gp3_groups[] = {
0505     "gpio11",
0506 };
0507 static const char * const pri_mi2s_ws_groups[] = {
0508     "gpio12",
0509 };
0510 static const char * const pri_mi2s_groups[] = {
0511     "gpio13", "gpio14", "gpio15",
0512 };
0513 static const char * const vsense_trigger_groups[] = {
0514     "gpio13",
0515 };
0516 static const char * const native_tsens_groups[] = {
0517     "gpio14",
0518 };
0519 static const char * const bimc_dte0_groups[] = {
0520     "gpio14", "gpio59",
0521 };
0522 static const char * const bimc_dte1_groups[] = {
0523     "gpio15", "gpio61",
0524 };
0525 static const char * const sec_mi2s_groups[] = {
0526     "gpio16", "gpio17", "gpio18", "gpio19",
0527 };
0528 static const char * const blsp_spi4_groups[] = {
0529     "gpio16", "gpio17", "gpio18", "gpio19", "gpio23", "gpio47", "gpio62",
0530 };
0531 static const char * const blsp_uart4_groups[] = {
0532     "gpio16", "gpio17", "gpio18", "gpio19", "gpio22", "gpio23", "gpio48",
0533     "gpio49",
0534 };
0535 static const char * const qdss_cti_groups[] = {
0536     "gpio16", "gpio16", "gpio17", "gpio17", "gpio54", "gpio54", "gpio55",
0537     "gpio55", "gpio59", "gpio60", "gpio65", "gpio65", "gpio66", "gpio66",
0538     "gpio94", "gpio94", "gpio95", "gpio95",
0539 };
0540 static const char * const blsp_i2c4_groups[] = {
0541     "gpio18", "gpio19", "gpio84", "gpio85",
0542 };
0543 static const char * const gcc_gp1_groups[] = {
0544     "gpio18",
0545 };
0546 static const char * const jitter_bist_groups[] = {
0547     "gpio19",
0548 };
0549 static const char * const gcc_gp2_groups[] = {
0550     "gpio19",
0551 };
0552 static const char * const pll_bist_groups[] = {
0553     "gpio22",
0554 };
0555 static const char * const blsp_spi1_groups[] = {
0556     "gpio23", "gpio47", "gpio62", "gpio80", "gpio81", "gpio82", "gpio83",
0557 };
0558 static const char * const adsp_ext_groups[] = {
0559     "gpio24", "gpio25",
0560 };
0561 static const char * const qlink0_wmss_groups[] = {
0562     "gpio28",
0563 };
0564 static const char * const native_tsense_groups[] = {
0565     "gpio29", "gpio72",
0566 };
0567 static const char * const nav_gpio_groups[] = {
0568     "gpio31", "gpio32",
0569 };
0570 static const char * const pll_ref_groups[] = {
0571     "gpio32",
0572 };
0573 static const char * const pa_indicator_groups[] = {
0574     "gpio33",
0575 };
0576 static const char * const qlink0_en_groups[] = {
0577     "gpio34",
0578 };
0579 static const char * const qlink0_req_groups[] = {
0580     "gpio35",
0581 };
0582 static const char * const dbg_out_groups[] = {
0583     "gpio35",
0584 };
0585 static const char * const cri_trng_groups[] = {
0586     "gpio36",
0587 };
0588 static const char * const prng_rosc_groups[] = {
0589     "gpio38",
0590 };
0591 static const char * const cri_trng0_groups[] = {
0592     "gpio40",
0593 };
0594 static const char * const cri_trng1_groups[] = {
0595     "gpio41",
0596 };
0597 static const char * const coex_uart_groups[] = {
0598     "gpio44", "gpio45",
0599 };
0600 static const char * const ddr_pxi0_groups[] = {
0601     "gpio45", "gpio46",
0602 };
0603 static const char * const m_voc_groups[] = {
0604     "gpio46", "gpio48", "gpio49", "gpio59", "gpio60",
0605 };
0606 static const char * const ddr_bist_groups[] = {
0607     "gpio46", "gpio47", "gpio48", "gpio49",
0608 };
0609 static const char * const pci_e_groups[] = {
0610     "gpio53",
0611 };
0612 static const char * const tgu_ch0_groups[] = {
0613     "gpio55",
0614 };
0615 static const char * const pcie_clkreq_groups[] = {
0616     "gpio56",
0617 };
0618 static const char * const native_char_groups[] = {
0619     "gpio26", "gpio29", "gpio33", "gpio42", "gpio57",
0620 };
0621 static const char * const mgpi_clk_groups[] = {
0622     "gpio61", "gpio71",
0623 };
0624 static const char * const qlink2_wmss_groups[] = {
0625     "gpio61",
0626 };
0627 static const char * const i2s_mclk_groups[] = {
0628     "gpio62",
0629 };
0630 static const char * const audio_ref_groups[] = {
0631     "gpio62",
0632 };
0633 static const char * const ldo_update_groups[] = {
0634     "gpio62",
0635 };
0636 static const char * const atest_char_groups[] = {
0637     "gpio63",
0638 };
0639 static const char * const atest_char3_groups[] = {
0640     "gpio64",
0641 };
0642 static const char * const atest_char2_groups[] = {
0643     "gpio65",
0644 };
0645 static const char * const atest_char1_groups[] = {
0646     "gpio66",
0647 };
0648 static const char * const uim1_data_groups[] = {
0649     "gpio67",
0650 };
0651 static const char * const atest_char0_groups[] = {
0652     "gpio67",
0653 };
0654 static const char * const uim1_present_groups[] = {
0655     "gpio68",
0656 };
0657 static const char * const uim1_reset_groups[] = {
0658     "gpio69",
0659 };
0660 static const char * const uim1_clk_groups[] = {
0661     "gpio70",
0662 };
0663 static const char * const qlink2_en_groups[] = {
0664     "gpio71",
0665 };
0666 static const char * const qlink1_en_groups[] = {
0667     "gpio72",
0668 };
0669 static const char * const qlink1_req_groups[] = {
0670     "gpio73",
0671 };
0672 static const char * const qlink1_wmss_groups[] = {
0673     "gpio74",
0674 };
0675 static const char * const coex_uart2_groups[] = {
0676     "gpio75", "gpio76", "gpio102", "gpio103",
0677 };
0678 static const char * const spmi_coex_groups[] = {
0679     "gpio75", "gpio76",
0680 };
0681 static const char * const qlink2_req_groups[] = {
0682     "gpio77",
0683 };
0684 static const char * const spmi_vgi_groups[] = {
0685     "gpio78", "gpio79",
0686 };
0687 static const char * const gcc_plltest_groups[] = {
0688     "gpio81", "gpio82",
0689 };
0690 static const char * const ebi2_lcd_groups[] = {
0691     "gpio84", "gpio85", "gpio90",
0692 };
0693 static const char * const ebi2_a_groups[] = {
0694     "gpio89",
0695 };
0696 static const char * const usb2phy_ac_groups[] = {
0697     "gpio93",
0698 };
0699 static const char * const sdc1_tb_groups[] = {
0700     "gpio106",
0701 };
0702 
0703 static const struct msm_function sdx65_functions[] = {
0704     FUNCTION(qlink0_wmss),
0705     FUNCTION(adsp_ext),
0706     FUNCTION(atest_char),
0707     FUNCTION(atest_char0),
0708     FUNCTION(atest_char1),
0709     FUNCTION(atest_char2),
0710     FUNCTION(atest_char3),
0711     FUNCTION(audio_ref),
0712     FUNCTION(bimc_dte0),
0713     FUNCTION(bimc_dte1),
0714     FUNCTION(blsp_i2c1),
0715     FUNCTION(blsp_i2c2),
0716     FUNCTION(blsp_i2c3),
0717     FUNCTION(blsp_i2c4),
0718     FUNCTION(blsp_spi1),
0719     FUNCTION(blsp_spi2),
0720     FUNCTION(blsp_spi3),
0721     FUNCTION(blsp_spi4),
0722     FUNCTION(blsp_uart1),
0723     FUNCTION(blsp_uart2),
0724     FUNCTION(blsp_uart3),
0725     FUNCTION(blsp_uart4),
0726     FUNCTION(char_exec),
0727     FUNCTION(coex_uart),
0728     FUNCTION(coex_uart2),
0729     FUNCTION(cri_trng),
0730     FUNCTION(cri_trng0),
0731     FUNCTION(cri_trng1),
0732     FUNCTION(dbg_out),
0733     FUNCTION(ddr_bist),
0734     FUNCTION(ddr_pxi0),
0735     FUNCTION(ebi0_wrcdc),
0736     FUNCTION(ebi2_a),
0737     FUNCTION(ebi2_lcd),
0738     FUNCTION(ext_dbg),
0739     FUNCTION(gcc_gp1),
0740     FUNCTION(gcc_gp2),
0741     FUNCTION(gcc_gp3),
0742     FUNCTION(gcc_plltest),
0743     FUNCTION(gpio),
0744     FUNCTION(i2s_mclk),
0745     FUNCTION(jitter_bist),
0746     FUNCTION(ldo_en),
0747     FUNCTION(ldo_update),
0748     FUNCTION(m_voc),
0749     FUNCTION(mgpi_clk),
0750     FUNCTION(native_char),
0751     FUNCTION(native_tsens),
0752     FUNCTION(native_tsense),
0753     FUNCTION(nav_gpio),
0754     FUNCTION(pa_indicator),
0755     FUNCTION(pci_e),
0756     FUNCTION(pcie_clkreq),
0757     FUNCTION(pll_bist),
0758     FUNCTION(pll_ref),
0759     FUNCTION(pri_mi2s),
0760     FUNCTION(pri_mi2s_ws),
0761     FUNCTION(prng_rosc),
0762     FUNCTION(qdss_cti),
0763     FUNCTION(qdss_gpio),
0764     FUNCTION(qlink0_en),
0765     FUNCTION(qlink0_req),
0766     FUNCTION(qlink1_en),
0767     FUNCTION(qlink1_req),
0768     FUNCTION(qlink1_wmss),
0769     FUNCTION(qlink2_en),
0770     FUNCTION(qlink2_req),
0771     FUNCTION(qlink2_wmss),
0772     FUNCTION(sdc1_tb),
0773     FUNCTION(sec_mi2s),
0774     FUNCTION(spmi_coex),
0775     FUNCTION(spmi_vgi),
0776     FUNCTION(tgu_ch0),
0777     FUNCTION(uim1_clk),
0778     FUNCTION(uim1_data),
0779     FUNCTION(uim1_present),
0780     FUNCTION(uim1_reset),
0781     FUNCTION(uim2_clk),
0782     FUNCTION(uim2_data),
0783     FUNCTION(uim2_present),
0784     FUNCTION(uim2_reset),
0785     FUNCTION(usb2phy_ac),
0786     FUNCTION(vsense_trigger),
0787 };
0788 
0789 /* Every pin is maintained as a single group, and missing or non-existing pin
0790  * would be maintained as dummy group to synchronize pin group index with
0791  * pin descriptor registered with pinctrl core.
0792  * Clients would not be able to request these dummy pin groups.
0793  */
0794 static const struct msm_pingroup sdx65_groups[] = {
0795     [0] = PINGROUP(0, uim2_data, blsp_uart1, ebi0_wrcdc, _, _, _, _, _, _),
0796     [1] = PINGROUP(1, uim2_present, blsp_uart1, _, _, _, _, _, _, _),
0797     [2] = PINGROUP(2, uim2_reset, blsp_uart1, blsp_i2c1, ebi0_wrcdc, _, _, _, _, _),
0798     [3] = PINGROUP(3, uim2_clk, blsp_uart1, blsp_i2c1, _, _, _, _, _, _),
0799     [4] = PINGROUP(4, blsp_spi2, blsp_uart2, _, qdss_gpio, _, _, _, _, _),
0800     [5] = PINGROUP(5, blsp_spi2, blsp_uart2, _, qdss_gpio, _, _, _, _, _),
0801     [6] = PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_gpio, _, _, _),
0802     [7] = PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, char_exec, _, qdss_gpio, _, _, _),
0803     [8] = PINGROUP(8, blsp_spi3, blsp_uart3, ext_dbg, ldo_en, _, _, _, _, _),
0804     [9] = PINGROUP(9, blsp_spi3, blsp_uart3, ext_dbg, _, _, _, _, _, _),
0805     [10] = PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, _, _, _, _, _),
0806     [11] = PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, ext_dbg, gcc_gp3, _, _, _, _),
0807     [12] = PINGROUP(12, pri_mi2s_ws, _, qdss_gpio, _, _, _, _, _, _),
0808     [13] = PINGROUP(13, pri_mi2s, _, qdss_gpio, vsense_trigger, _, _, _, _, _),
0809     [14] = PINGROUP(14, pri_mi2s, _, _, qdss_gpio, native_tsens, bimc_dte0, _, _, _),
0810     [15] = PINGROUP(15, pri_mi2s, _, _, qdss_gpio, bimc_dte1, _, _, _, _),
0811     [16] = PINGROUP(16, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, _, qdss_gpio, _),
0812     [17] = PINGROUP(17, sec_mi2s, blsp_spi4, blsp_uart4, qdss_cti, qdss_cti, _, qdss_gpio, _, _),
0813     [18] = PINGROUP(18, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, gcc_gp1, qdss_gpio, _, _, _),
0814     [19] = PINGROUP(19, sec_mi2s, blsp_spi4, blsp_uart4, blsp_i2c4, jitter_bist, gcc_gp2, _, qdss_gpio, _),
0815     [20] = PINGROUP(20, _, _, _, _, _, _, _, _, _),
0816     [21] = PINGROUP(21, _, _, _, _, _, _, _, _, _),
0817     [22] = PINGROUP(22, blsp_uart4, pll_bist, _, _, _, _, _, _, _),
0818     [23] = PINGROUP(23, blsp_uart4, blsp_spi2, blsp_spi1, blsp_spi3, blsp_spi4, _, _, _, _),
0819     [24] = PINGROUP(24, adsp_ext, _, _, _, _, _, _, _, _),
0820     [25] = PINGROUP(25, adsp_ext, _, _, _, _, _, _, _, _),
0821     [26] = PINGROUP(26, _, _, _, native_char, _, _, _, _, _),
0822     [27] = PINGROUP(27, _, _, _, _, _, _, _, _, _),
0823     [28] = PINGROUP(28, qlink0_wmss, _, _, _, _, _, _, _, _),
0824     [29] = PINGROUP(29, _, _, _, native_tsense, native_char, _, _, _, _),
0825     [30] = PINGROUP(30, _, _, _, _, _, _, _, _, _),
0826     [31] = PINGROUP(31, nav_gpio, _, _, _, _, _, _, _, _),
0827     [32] = PINGROUP(32, nav_gpio, pll_ref, _, _, _, _, _, _, _),
0828     [33] = PINGROUP(33, _, pa_indicator, qdss_gpio, native_char, _, _, _, _, _),
0829     [34] = PINGROUP(34, qlink0_en, _, _, _, _, _, _, _, _),
0830     [35] = PINGROUP(35, qlink0_req, dbg_out, _, _, _, _, _, _, _),
0831     [36] = PINGROUP(36, _, _, cri_trng, _, _, _, _, _, _),
0832     [37] = PINGROUP(37, _, _, _, _, _, _, _, _, _),
0833     [38] = PINGROUP(38, _, _, prng_rosc, _, _, _, _, _, _),
0834     [39] = PINGROUP(39, _, _, _, _, _, _, _, _, _),
0835     [40] = PINGROUP(40, _, _, cri_trng0, _, _, _, _, _, _),
0836     [41] = PINGROUP(41, _, _, cri_trng1, _, _, _, _, _, _),
0837     [42] = PINGROUP(42, _, qdss_gpio, native_char, _, _, _, _, _, _),
0838     [43] = PINGROUP(43, _, _, _, _, _, _, _, _, _),
0839     [44] = PINGROUP(44, coex_uart, _, _, _, _, _, _, _, _),
0840     [45] = PINGROUP(45, coex_uart, ddr_pxi0, _, _, _, _, _, _, _),
0841     [46] = PINGROUP(46, m_voc, ddr_bist, ddr_pxi0, _, _, _, _, _, _),
0842     [47] = PINGROUP(47, ddr_bist, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, _, _, _, _),
0843     [48] = PINGROUP(48, m_voc, blsp_uart1, blsp_uart4, ddr_bist, _, _, _, _, _),
0844     [49] = PINGROUP(49, m_voc, blsp_uart1, blsp_uart4, ddr_bist, _, _, _, _, _),
0845     [50] = PINGROUP(50, _, _, _, _, _, _, _, _, _),
0846     [51] = PINGROUP(51, _, _, _, _, _, _, _, _, _),
0847     [52] = PINGROUP(52, _, _, _, _, _, _, _, _, _),
0848     [53] = PINGROUP(53, pci_e, _, _, _, _, _, _, _, _),
0849     [54] = PINGROUP(54, qdss_cti, qdss_cti, _, _, _, _, _, _, _),
0850     [55] = PINGROUP(55, qdss_cti, qdss_cti, tgu_ch0, _, _, _, _, _, _),
0851     [56] = PINGROUP(56, pcie_clkreq, _, _, _, _, _, _, _, _),
0852     [57] = PINGROUP(57, _, native_char, _, _, _, _, _, _, _),
0853     [58] = PINGROUP(58, _, _, _, _, _, _, _, _, _),
0854     [59] = PINGROUP(59, qdss_cti, m_voc, bimc_dte0, _, _, _, _, _, _),
0855     [60] = PINGROUP(60, qdss_cti, _, m_voc, _, _, _, _, _, _),
0856     [61] = PINGROUP(61, mgpi_clk, qlink2_wmss, bimc_dte1, _, _, _, _, _, _),
0857     [62] = PINGROUP(62, i2s_mclk, audio_ref, blsp_spi1, blsp_spi2, blsp_spi3, blsp_spi4, ldo_update, _, _),
0858     [63] = PINGROUP(63, blsp_uart2, _, qdss_gpio, atest_char, _, _, _, _, _),
0859     [64] = PINGROUP(64, blsp_uart2, qdss_gpio, atest_char3, _, _, _, _, _, _),
0860     [65] = PINGROUP(65, blsp_uart2, blsp_i2c2, qdss_cti, qdss_cti, _, qdss_gpio, atest_char2, _, _),
0861     [66] = PINGROUP(66, blsp_uart2, blsp_i2c2, qdss_cti, qdss_cti, qdss_gpio, atest_char1, _, _, _),
0862     [67] = PINGROUP(67, uim1_data, atest_char0, _, _, _, _, _, _, _),
0863     [68] = PINGROUP(68, uim1_present, _, _, _, _, _, _, _, _),
0864     [69] = PINGROUP(69, uim1_reset, _, _, _, _, _, _, _, _),
0865     [70] = PINGROUP(70, uim1_clk, _, _, _, _, _, _, _, _),
0866     [71] = PINGROUP(71, mgpi_clk, qlink2_en, _, _, _, _, _, _, _),
0867     [72] = PINGROUP(72, qlink1_en, _, native_tsense, _, _, _, _, _, _),
0868     [73] = PINGROUP(73, qlink1_req, _, _, _, _, _, _, _, _),
0869     [74] = PINGROUP(74, qlink1_wmss, _, _, _, _, _, _, _, _),
0870     [75] = PINGROUP(75, coex_uart2, spmi_coex, _, _, _, _, _, _, _),
0871     [76] = PINGROUP(76, coex_uart2, spmi_coex, _, _, _, _, _, _, _),
0872     [77] = PINGROUP(77, _, qlink2_req, _, _, _, _, _, _, _),
0873     [78] = PINGROUP(78, spmi_vgi, _, _, _, _, _, _, _, _),
0874     [79] = PINGROUP(79, spmi_vgi, _, _, _, _, _, _, _, _),
0875     [80] = PINGROUP(80, _, blsp_spi1, _, blsp_uart1, _, _, _, _, _),
0876     [81] = PINGROUP(81, _, blsp_spi1, _, blsp_uart1, gcc_plltest, _, _, _, _),
0877     [82] = PINGROUP(82, _, blsp_spi1, _, blsp_i2c1, gcc_plltest, _, _, _, _),
0878     [83] = PINGROUP(83, _, blsp_spi1, _, blsp_i2c1, _, _, _, _, _),
0879     [84] = PINGROUP(84, _, ebi2_lcd, _, blsp_i2c4, _, _, _, _, _),
0880     [85] = PINGROUP(85, _, ebi2_lcd, _, blsp_i2c4, _, _, _, _, _),
0881     [86] = PINGROUP(86, _, _, _, _, _, _, _, _, _),
0882     [87] = PINGROUP(87, _, _, _, _, _, _, _, _, _),
0883     [88] = PINGROUP(88, _, _, _, _, _, _, _, _, _),
0884     [89] = PINGROUP(89, _, _, _, _, ebi2_a, _, _, _, _),
0885     [90] = PINGROUP(90, _, _, _, _, ebi2_lcd, _, _, _, _),
0886     [91] = PINGROUP(91, _, _, _, _, _, _, _, _, _),
0887     [92] = PINGROUP(92, _, _, _, _, _, _, _, _, _),
0888     [93] = PINGROUP(93, _, _, usb2phy_ac, _, _, _, _, _, _),
0889     [94] = PINGROUP(94, qdss_cti, qdss_cti, _, _, _, _, _, _, _),
0890     [95] = PINGROUP(95, qdss_cti, qdss_cti, _, _, _, _, _, _, _),
0891     [96] = PINGROUP(96, _, _, _, _, _, _, _, _, _),
0892     [97] = PINGROUP(97, _, _, _, _, _, _, _, _, _),
0893     [98] = PINGROUP(98, _, _, _, _, _, _, _, _, _),
0894     [99] = PINGROUP(99, _, _, _, _, _, _, _, _, _),
0895     [100] = PINGROUP(100, _, _, _, _, _, _, _, _, _),
0896     [101] = PINGROUP(101, _, _, _, _, _, _, _, _, _),
0897     [102] = PINGROUP(102, _, _, coex_uart2, _, _, _, _, _, _),
0898     [103] = PINGROUP(103, _, _, coex_uart2, _, _, _, _, _, _),
0899     [104] = PINGROUP(104, _, _, _, _, _, _, _, _, _),
0900     [105] = PINGROUP(105, _, _, _, _, _, _, _, _, _),
0901     [106] = PINGROUP(106, sdc1_tb, _, _, _, _, _, _, _, _),
0902     [107] = PINGROUP(107, _, _, _, _, _, _, _, _, _),
0903     [108] = UFS_RESET(ufs_reset, 0x0),
0904     [109] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x9a000, 15, 0),
0905     [110] = SDC_QDSD_PINGROUP(sdc1_clk, 0x9a000, 13, 6),
0906     [111] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x9a000, 11, 3),
0907     [112] = SDC_QDSD_PINGROUP(sdc1_data, 0x9a000, 9, 0),
0908 };
0909 
0910 static const struct msm_gpio_wakeirq_map sdx65_pdc_map[] = {
0911     {1, 20}, {2, 21}, {5, 22}, {6, 23}, {9, 24}, {10, 25},
0912     {11, 26}, {12, 27}, {13, 28}, {14, 29}, {15, 30}, {16, 31},
0913     {17, 32}, {18, 33}, {19, 34}, {21, 35}, {22, 36}, {23, 70},
0914     {24, 37}, {25, 38}, {35, 40}, {43, 41}, {46, 44}, {48, 45},
0915     {49, 57}, {50, 46}, {52, 47}, {54, 49}, {55, 50}, {60, 53},
0916     {61, 54}, {64, 55}, {65, 81}, {68, 56}, {71, 58}, {73, 59},
0917     {77, 77}, {81, 65}, {83, 63}, {84, 64}, {86, 66}, {88, 67},
0918     {89, 68}, {90, 69}, {93, 71}, {94, 72}, {95, 73}, {96, 74},
0919     {99, 75}, {103, 78}, {104, 79}
0920 };
0921 
0922 static const struct msm_pinctrl_soc_data sdx65_pinctrl = {
0923     .pins = sdx65_pins,
0924     .npins = ARRAY_SIZE(sdx65_pins),
0925     .functions = sdx65_functions,
0926     .nfunctions = ARRAY_SIZE(sdx65_functions),
0927     .groups = sdx65_groups,
0928     .ngroups = ARRAY_SIZE(sdx65_groups),
0929     .ngpios = 109,
0930     .wakeirq_map = sdx65_pdc_map,
0931     .nwakeirq_map = ARRAY_SIZE(sdx65_pdc_map),
0932 };
0933 
0934 static int sdx65_pinctrl_probe(struct platform_device *pdev)
0935 {
0936     return msm_pinctrl_probe(pdev, &sdx65_pinctrl);
0937 }
0938 
0939 static const struct of_device_id sdx65_pinctrl_of_match[] = {
0940     { .compatible = "qcom,sdx65-tlmm", },
0941     { },
0942 };
0943 
0944 static struct platform_driver sdx65_pinctrl_driver = {
0945     .driver = {
0946         .name = "sdx65-tlmm",
0947         .of_match_table = sdx65_pinctrl_of_match,
0948     },
0949     .probe = sdx65_pinctrl_probe,
0950     .remove = msm_pinctrl_remove,
0951 };
0952 
0953 static int __init sdx65_pinctrl_init(void)
0954 {
0955     return platform_driver_register(&sdx65_pinctrl_driver);
0956 }
0957 arch_initcall(sdx65_pinctrl_init);
0958 
0959 static void __exit sdx65_pinctrl_exit(void)
0960 {
0961     platform_driver_unregister(&sdx65_pinctrl_driver);
0962 }
0963 module_exit(sdx65_pinctrl_exit);
0964 
0965 MODULE_DESCRIPTION("QTI sdx65 pinctrl driver");
0966 MODULE_LICENSE("GPL v2");
0967 MODULE_DEVICE_TABLE(of, sdx65_pinctrl_of_match);
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