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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
0004  */
0005 
0006 #include <linux/acpi.h>
0007 #include <linux/module.h>
0008 #include <linux/of.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/pinctrl/pinctrl.h>
0011 
0012 #include "pinctrl-msm.h"
0013 
0014 #define FUNCTION(fname)                 \
0015     [msm_mux_##fname] = {               \
0016         .name = #fname,             \
0017         .groups = fname##_groups,       \
0018         .ngroups = ARRAY_SIZE(fname##_groups),  \
0019     }
0020 
0021 #define NORTH   0x00500000
0022 #define SOUTH   0x00900000
0023 #define EAST    0x00100000
0024 #define REG_SIZE 0x1000
0025 #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
0026     {                       \
0027         .name = "gpio" #id,         \
0028         .pins = gpio##id##_pins,        \
0029         .npins = ARRAY_SIZE(gpio##id##_pins),   \
0030         .funcs = (int[]){           \
0031             msm_mux_gpio, /* gpio mode */   \
0032             msm_mux_##f1,           \
0033             msm_mux_##f2,           \
0034             msm_mux_##f3,           \
0035             msm_mux_##f4,           \
0036             msm_mux_##f5,           \
0037             msm_mux_##f6,           \
0038             msm_mux_##f7,           \
0039             msm_mux_##f8,           \
0040             msm_mux_##f9,           \
0041             msm_mux_##f10           \
0042         },                  \
0043         .nfuncs = 11,               \
0044         .ctl_reg = base + REG_SIZE * id,        \
0045         .io_reg = base + 0x4 + REG_SIZE * id,       \
0046         .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
0047         .intr_status_reg = base + 0xc + REG_SIZE * id,  \
0048         .intr_target_reg = base + 0x8 + REG_SIZE * id,  \
0049         .mux_bit = 2,           \
0050         .pull_bit = 0,          \
0051         .drv_bit = 6,           \
0052         .oe_bit = 9,            \
0053         .in_bit = 0,            \
0054         .out_bit = 1,           \
0055         .intr_enable_bit = 0,       \
0056         .intr_status_bit = 0,       \
0057         .intr_target_bit = 5,       \
0058         .intr_target_kpss_val = 3,  \
0059         .intr_raw_status_bit = 4,   \
0060         .intr_polarity_bit = 1,     \
0061         .intr_detection_bit = 2,    \
0062         .intr_detection_width = 2,  \
0063     }
0064 
0065 #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv)  \
0066     {                       \
0067         .name = #pg_name,           \
0068         .pins = pg_name##_pins,         \
0069         .npins = ARRAY_SIZE(pg_name##_pins),    \
0070         .ctl_reg = ctl,             \
0071         .io_reg = 0,                \
0072         .intr_cfg_reg = 0,          \
0073         .intr_status_reg = 0,           \
0074         .intr_target_reg = 0,           \
0075         .mux_bit = -1,              \
0076         .pull_bit = pull,           \
0077         .drv_bit = drv,             \
0078         .oe_bit = -1,               \
0079         .in_bit = -1,               \
0080         .out_bit = -1,              \
0081         .intr_enable_bit = -1,          \
0082         .intr_status_bit = -1,          \
0083         .intr_target_bit = -1,          \
0084         .intr_raw_status_bit = -1,      \
0085         .intr_polarity_bit = -1,        \
0086         .intr_detection_bit = -1,       \
0087         .intr_detection_width = -1,     \
0088     }
0089 
0090 #define UFS_RESET(pg_name, offset)              \
0091     {                       \
0092         .name = #pg_name,           \
0093         .pins = pg_name##_pins,         \
0094         .npins = ARRAY_SIZE(pg_name##_pins),    \
0095         .ctl_reg = offset,          \
0096         .io_reg = offset + 0x4,         \
0097         .intr_cfg_reg = 0,          \
0098         .intr_status_reg = 0,           \
0099         .intr_target_reg = 0,           \
0100         .mux_bit = -1,              \
0101         .pull_bit = 3,              \
0102         .drv_bit = 0,               \
0103         .oe_bit = -1,               \
0104         .in_bit = -1,               \
0105         .out_bit = 0,               \
0106         .intr_enable_bit = -1,          \
0107         .intr_status_bit = -1,          \
0108         .intr_target_bit = -1,          \
0109         .intr_raw_status_bit = -1,      \
0110         .intr_polarity_bit = -1,        \
0111         .intr_detection_bit = -1,       \
0112         .intr_detection_width = -1,     \
0113     }
0114 static const struct pinctrl_pin_desc sdm845_pins[] = {
0115     PINCTRL_PIN(0, "GPIO_0"),
0116     PINCTRL_PIN(1, "GPIO_1"),
0117     PINCTRL_PIN(2, "GPIO_2"),
0118     PINCTRL_PIN(3, "GPIO_3"),
0119     PINCTRL_PIN(4, "GPIO_4"),
0120     PINCTRL_PIN(5, "GPIO_5"),
0121     PINCTRL_PIN(6, "GPIO_6"),
0122     PINCTRL_PIN(7, "GPIO_7"),
0123     PINCTRL_PIN(8, "GPIO_8"),
0124     PINCTRL_PIN(9, "GPIO_9"),
0125     PINCTRL_PIN(10, "GPIO_10"),
0126     PINCTRL_PIN(11, "GPIO_11"),
0127     PINCTRL_PIN(12, "GPIO_12"),
0128     PINCTRL_PIN(13, "GPIO_13"),
0129     PINCTRL_PIN(14, "GPIO_14"),
0130     PINCTRL_PIN(15, "GPIO_15"),
0131     PINCTRL_PIN(16, "GPIO_16"),
0132     PINCTRL_PIN(17, "GPIO_17"),
0133     PINCTRL_PIN(18, "GPIO_18"),
0134     PINCTRL_PIN(19, "GPIO_19"),
0135     PINCTRL_PIN(20, "GPIO_20"),
0136     PINCTRL_PIN(21, "GPIO_21"),
0137     PINCTRL_PIN(22, "GPIO_22"),
0138     PINCTRL_PIN(23, "GPIO_23"),
0139     PINCTRL_PIN(24, "GPIO_24"),
0140     PINCTRL_PIN(25, "GPIO_25"),
0141     PINCTRL_PIN(26, "GPIO_26"),
0142     PINCTRL_PIN(27, "GPIO_27"),
0143     PINCTRL_PIN(28, "GPIO_28"),
0144     PINCTRL_PIN(29, "GPIO_29"),
0145     PINCTRL_PIN(30, "GPIO_30"),
0146     PINCTRL_PIN(31, "GPIO_31"),
0147     PINCTRL_PIN(32, "GPIO_32"),
0148     PINCTRL_PIN(33, "GPIO_33"),
0149     PINCTRL_PIN(34, "GPIO_34"),
0150     PINCTRL_PIN(35, "GPIO_35"),
0151     PINCTRL_PIN(36, "GPIO_36"),
0152     PINCTRL_PIN(37, "GPIO_37"),
0153     PINCTRL_PIN(38, "GPIO_38"),
0154     PINCTRL_PIN(39, "GPIO_39"),
0155     PINCTRL_PIN(40, "GPIO_40"),
0156     PINCTRL_PIN(41, "GPIO_41"),
0157     PINCTRL_PIN(42, "GPIO_42"),
0158     PINCTRL_PIN(43, "GPIO_43"),
0159     PINCTRL_PIN(44, "GPIO_44"),
0160     PINCTRL_PIN(45, "GPIO_45"),
0161     PINCTRL_PIN(46, "GPIO_46"),
0162     PINCTRL_PIN(47, "GPIO_47"),
0163     PINCTRL_PIN(48, "GPIO_48"),
0164     PINCTRL_PIN(49, "GPIO_49"),
0165     PINCTRL_PIN(50, "GPIO_50"),
0166     PINCTRL_PIN(51, "GPIO_51"),
0167     PINCTRL_PIN(52, "GPIO_52"),
0168     PINCTRL_PIN(53, "GPIO_53"),
0169     PINCTRL_PIN(54, "GPIO_54"),
0170     PINCTRL_PIN(55, "GPIO_55"),
0171     PINCTRL_PIN(56, "GPIO_56"),
0172     PINCTRL_PIN(57, "GPIO_57"),
0173     PINCTRL_PIN(58, "GPIO_58"),
0174     PINCTRL_PIN(59, "GPIO_59"),
0175     PINCTRL_PIN(60, "GPIO_60"),
0176     PINCTRL_PIN(61, "GPIO_61"),
0177     PINCTRL_PIN(62, "GPIO_62"),
0178     PINCTRL_PIN(63, "GPIO_63"),
0179     PINCTRL_PIN(64, "GPIO_64"),
0180     PINCTRL_PIN(65, "GPIO_65"),
0181     PINCTRL_PIN(66, "GPIO_66"),
0182     PINCTRL_PIN(67, "GPIO_67"),
0183     PINCTRL_PIN(68, "GPIO_68"),
0184     PINCTRL_PIN(69, "GPIO_69"),
0185     PINCTRL_PIN(70, "GPIO_70"),
0186     PINCTRL_PIN(71, "GPIO_71"),
0187     PINCTRL_PIN(72, "GPIO_72"),
0188     PINCTRL_PIN(73, "GPIO_73"),
0189     PINCTRL_PIN(74, "GPIO_74"),
0190     PINCTRL_PIN(75, "GPIO_75"),
0191     PINCTRL_PIN(76, "GPIO_76"),
0192     PINCTRL_PIN(77, "GPIO_77"),
0193     PINCTRL_PIN(78, "GPIO_78"),
0194     PINCTRL_PIN(79, "GPIO_79"),
0195     PINCTRL_PIN(80, "GPIO_80"),
0196     PINCTRL_PIN(81, "GPIO_81"),
0197     PINCTRL_PIN(82, "GPIO_82"),
0198     PINCTRL_PIN(83, "GPIO_83"),
0199     PINCTRL_PIN(84, "GPIO_84"),
0200     PINCTRL_PIN(85, "GPIO_85"),
0201     PINCTRL_PIN(86, "GPIO_86"),
0202     PINCTRL_PIN(87, "GPIO_87"),
0203     PINCTRL_PIN(88, "GPIO_88"),
0204     PINCTRL_PIN(89, "GPIO_89"),
0205     PINCTRL_PIN(90, "GPIO_90"),
0206     PINCTRL_PIN(91, "GPIO_91"),
0207     PINCTRL_PIN(92, "GPIO_92"),
0208     PINCTRL_PIN(93, "GPIO_93"),
0209     PINCTRL_PIN(94, "GPIO_94"),
0210     PINCTRL_PIN(95, "GPIO_95"),
0211     PINCTRL_PIN(96, "GPIO_96"),
0212     PINCTRL_PIN(97, "GPIO_97"),
0213     PINCTRL_PIN(98, "GPIO_98"),
0214     PINCTRL_PIN(99, "GPIO_99"),
0215     PINCTRL_PIN(100, "GPIO_100"),
0216     PINCTRL_PIN(101, "GPIO_101"),
0217     PINCTRL_PIN(102, "GPIO_102"),
0218     PINCTRL_PIN(103, "GPIO_103"),
0219     PINCTRL_PIN(104, "GPIO_104"),
0220     PINCTRL_PIN(105, "GPIO_105"),
0221     PINCTRL_PIN(106, "GPIO_106"),
0222     PINCTRL_PIN(107, "GPIO_107"),
0223     PINCTRL_PIN(108, "GPIO_108"),
0224     PINCTRL_PIN(109, "GPIO_109"),
0225     PINCTRL_PIN(110, "GPIO_110"),
0226     PINCTRL_PIN(111, "GPIO_111"),
0227     PINCTRL_PIN(112, "GPIO_112"),
0228     PINCTRL_PIN(113, "GPIO_113"),
0229     PINCTRL_PIN(114, "GPIO_114"),
0230     PINCTRL_PIN(115, "GPIO_115"),
0231     PINCTRL_PIN(116, "GPIO_116"),
0232     PINCTRL_PIN(117, "GPIO_117"),
0233     PINCTRL_PIN(118, "GPIO_118"),
0234     PINCTRL_PIN(119, "GPIO_119"),
0235     PINCTRL_PIN(120, "GPIO_120"),
0236     PINCTRL_PIN(121, "GPIO_121"),
0237     PINCTRL_PIN(122, "GPIO_122"),
0238     PINCTRL_PIN(123, "GPIO_123"),
0239     PINCTRL_PIN(124, "GPIO_124"),
0240     PINCTRL_PIN(125, "GPIO_125"),
0241     PINCTRL_PIN(126, "GPIO_126"),
0242     PINCTRL_PIN(127, "GPIO_127"),
0243     PINCTRL_PIN(128, "GPIO_128"),
0244     PINCTRL_PIN(129, "GPIO_129"),
0245     PINCTRL_PIN(130, "GPIO_130"),
0246     PINCTRL_PIN(131, "GPIO_131"),
0247     PINCTRL_PIN(132, "GPIO_132"),
0248     PINCTRL_PIN(133, "GPIO_133"),
0249     PINCTRL_PIN(134, "GPIO_134"),
0250     PINCTRL_PIN(135, "GPIO_135"),
0251     PINCTRL_PIN(136, "GPIO_136"),
0252     PINCTRL_PIN(137, "GPIO_137"),
0253     PINCTRL_PIN(138, "GPIO_138"),
0254     PINCTRL_PIN(139, "GPIO_139"),
0255     PINCTRL_PIN(140, "GPIO_140"),
0256     PINCTRL_PIN(141, "GPIO_141"),
0257     PINCTRL_PIN(142, "GPIO_142"),
0258     PINCTRL_PIN(143, "GPIO_143"),
0259     PINCTRL_PIN(144, "GPIO_144"),
0260     PINCTRL_PIN(145, "GPIO_145"),
0261     PINCTRL_PIN(146, "GPIO_146"),
0262     PINCTRL_PIN(147, "GPIO_147"),
0263     PINCTRL_PIN(148, "GPIO_148"),
0264     PINCTRL_PIN(149, "GPIO_149"),
0265     PINCTRL_PIN(150, "UFS_RESET"),
0266     PINCTRL_PIN(151, "SDC2_CLK"),
0267     PINCTRL_PIN(152, "SDC2_CMD"),
0268     PINCTRL_PIN(153, "SDC2_DATA"),
0269 };
0270 
0271 #define DECLARE_MSM_GPIO_PINS(pin) \
0272     static const unsigned int gpio##pin##_pins[] = { pin }
0273 DECLARE_MSM_GPIO_PINS(0);
0274 DECLARE_MSM_GPIO_PINS(1);
0275 DECLARE_MSM_GPIO_PINS(2);
0276 DECLARE_MSM_GPIO_PINS(3);
0277 DECLARE_MSM_GPIO_PINS(4);
0278 DECLARE_MSM_GPIO_PINS(5);
0279 DECLARE_MSM_GPIO_PINS(6);
0280 DECLARE_MSM_GPIO_PINS(7);
0281 DECLARE_MSM_GPIO_PINS(8);
0282 DECLARE_MSM_GPIO_PINS(9);
0283 DECLARE_MSM_GPIO_PINS(10);
0284 DECLARE_MSM_GPIO_PINS(11);
0285 DECLARE_MSM_GPIO_PINS(12);
0286 DECLARE_MSM_GPIO_PINS(13);
0287 DECLARE_MSM_GPIO_PINS(14);
0288 DECLARE_MSM_GPIO_PINS(15);
0289 DECLARE_MSM_GPIO_PINS(16);
0290 DECLARE_MSM_GPIO_PINS(17);
0291 DECLARE_MSM_GPIO_PINS(18);
0292 DECLARE_MSM_GPIO_PINS(19);
0293 DECLARE_MSM_GPIO_PINS(20);
0294 DECLARE_MSM_GPIO_PINS(21);
0295 DECLARE_MSM_GPIO_PINS(22);
0296 DECLARE_MSM_GPIO_PINS(23);
0297 DECLARE_MSM_GPIO_PINS(24);
0298 DECLARE_MSM_GPIO_PINS(25);
0299 DECLARE_MSM_GPIO_PINS(26);
0300 DECLARE_MSM_GPIO_PINS(27);
0301 DECLARE_MSM_GPIO_PINS(28);
0302 DECLARE_MSM_GPIO_PINS(29);
0303 DECLARE_MSM_GPIO_PINS(30);
0304 DECLARE_MSM_GPIO_PINS(31);
0305 DECLARE_MSM_GPIO_PINS(32);
0306 DECLARE_MSM_GPIO_PINS(33);
0307 DECLARE_MSM_GPIO_PINS(34);
0308 DECLARE_MSM_GPIO_PINS(35);
0309 DECLARE_MSM_GPIO_PINS(36);
0310 DECLARE_MSM_GPIO_PINS(37);
0311 DECLARE_MSM_GPIO_PINS(38);
0312 DECLARE_MSM_GPIO_PINS(39);
0313 DECLARE_MSM_GPIO_PINS(40);
0314 DECLARE_MSM_GPIO_PINS(41);
0315 DECLARE_MSM_GPIO_PINS(42);
0316 DECLARE_MSM_GPIO_PINS(43);
0317 DECLARE_MSM_GPIO_PINS(44);
0318 DECLARE_MSM_GPIO_PINS(45);
0319 DECLARE_MSM_GPIO_PINS(46);
0320 DECLARE_MSM_GPIO_PINS(47);
0321 DECLARE_MSM_GPIO_PINS(48);
0322 DECLARE_MSM_GPIO_PINS(49);
0323 DECLARE_MSM_GPIO_PINS(50);
0324 DECLARE_MSM_GPIO_PINS(51);
0325 DECLARE_MSM_GPIO_PINS(52);
0326 DECLARE_MSM_GPIO_PINS(53);
0327 DECLARE_MSM_GPIO_PINS(54);
0328 DECLARE_MSM_GPIO_PINS(55);
0329 DECLARE_MSM_GPIO_PINS(56);
0330 DECLARE_MSM_GPIO_PINS(57);
0331 DECLARE_MSM_GPIO_PINS(58);
0332 DECLARE_MSM_GPIO_PINS(59);
0333 DECLARE_MSM_GPIO_PINS(60);
0334 DECLARE_MSM_GPIO_PINS(61);
0335 DECLARE_MSM_GPIO_PINS(62);
0336 DECLARE_MSM_GPIO_PINS(63);
0337 DECLARE_MSM_GPIO_PINS(64);
0338 DECLARE_MSM_GPIO_PINS(65);
0339 DECLARE_MSM_GPIO_PINS(66);
0340 DECLARE_MSM_GPIO_PINS(67);
0341 DECLARE_MSM_GPIO_PINS(68);
0342 DECLARE_MSM_GPIO_PINS(69);
0343 DECLARE_MSM_GPIO_PINS(70);
0344 DECLARE_MSM_GPIO_PINS(71);
0345 DECLARE_MSM_GPIO_PINS(72);
0346 DECLARE_MSM_GPIO_PINS(73);
0347 DECLARE_MSM_GPIO_PINS(74);
0348 DECLARE_MSM_GPIO_PINS(75);
0349 DECLARE_MSM_GPIO_PINS(76);
0350 DECLARE_MSM_GPIO_PINS(77);
0351 DECLARE_MSM_GPIO_PINS(78);
0352 DECLARE_MSM_GPIO_PINS(79);
0353 DECLARE_MSM_GPIO_PINS(80);
0354 DECLARE_MSM_GPIO_PINS(81);
0355 DECLARE_MSM_GPIO_PINS(82);
0356 DECLARE_MSM_GPIO_PINS(83);
0357 DECLARE_MSM_GPIO_PINS(84);
0358 DECLARE_MSM_GPIO_PINS(85);
0359 DECLARE_MSM_GPIO_PINS(86);
0360 DECLARE_MSM_GPIO_PINS(87);
0361 DECLARE_MSM_GPIO_PINS(88);
0362 DECLARE_MSM_GPIO_PINS(89);
0363 DECLARE_MSM_GPIO_PINS(90);
0364 DECLARE_MSM_GPIO_PINS(91);
0365 DECLARE_MSM_GPIO_PINS(92);
0366 DECLARE_MSM_GPIO_PINS(93);
0367 DECLARE_MSM_GPIO_PINS(94);
0368 DECLARE_MSM_GPIO_PINS(95);
0369 DECLARE_MSM_GPIO_PINS(96);
0370 DECLARE_MSM_GPIO_PINS(97);
0371 DECLARE_MSM_GPIO_PINS(98);
0372 DECLARE_MSM_GPIO_PINS(99);
0373 DECLARE_MSM_GPIO_PINS(100);
0374 DECLARE_MSM_GPIO_PINS(101);
0375 DECLARE_MSM_GPIO_PINS(102);
0376 DECLARE_MSM_GPIO_PINS(103);
0377 DECLARE_MSM_GPIO_PINS(104);
0378 DECLARE_MSM_GPIO_PINS(105);
0379 DECLARE_MSM_GPIO_PINS(106);
0380 DECLARE_MSM_GPIO_PINS(107);
0381 DECLARE_MSM_GPIO_PINS(108);
0382 DECLARE_MSM_GPIO_PINS(109);
0383 DECLARE_MSM_GPIO_PINS(110);
0384 DECLARE_MSM_GPIO_PINS(111);
0385 DECLARE_MSM_GPIO_PINS(112);
0386 DECLARE_MSM_GPIO_PINS(113);
0387 DECLARE_MSM_GPIO_PINS(114);
0388 DECLARE_MSM_GPIO_PINS(115);
0389 DECLARE_MSM_GPIO_PINS(116);
0390 DECLARE_MSM_GPIO_PINS(117);
0391 DECLARE_MSM_GPIO_PINS(118);
0392 DECLARE_MSM_GPIO_PINS(119);
0393 DECLARE_MSM_GPIO_PINS(120);
0394 DECLARE_MSM_GPIO_PINS(121);
0395 DECLARE_MSM_GPIO_PINS(122);
0396 DECLARE_MSM_GPIO_PINS(123);
0397 DECLARE_MSM_GPIO_PINS(124);
0398 DECLARE_MSM_GPIO_PINS(125);
0399 DECLARE_MSM_GPIO_PINS(126);
0400 DECLARE_MSM_GPIO_PINS(127);
0401 DECLARE_MSM_GPIO_PINS(128);
0402 DECLARE_MSM_GPIO_PINS(129);
0403 DECLARE_MSM_GPIO_PINS(130);
0404 DECLARE_MSM_GPIO_PINS(131);
0405 DECLARE_MSM_GPIO_PINS(132);
0406 DECLARE_MSM_GPIO_PINS(133);
0407 DECLARE_MSM_GPIO_PINS(134);
0408 DECLARE_MSM_GPIO_PINS(135);
0409 DECLARE_MSM_GPIO_PINS(136);
0410 DECLARE_MSM_GPIO_PINS(137);
0411 DECLARE_MSM_GPIO_PINS(138);
0412 DECLARE_MSM_GPIO_PINS(139);
0413 DECLARE_MSM_GPIO_PINS(140);
0414 DECLARE_MSM_GPIO_PINS(141);
0415 DECLARE_MSM_GPIO_PINS(142);
0416 DECLARE_MSM_GPIO_PINS(143);
0417 DECLARE_MSM_GPIO_PINS(144);
0418 DECLARE_MSM_GPIO_PINS(145);
0419 DECLARE_MSM_GPIO_PINS(146);
0420 DECLARE_MSM_GPIO_PINS(147);
0421 DECLARE_MSM_GPIO_PINS(148);
0422 DECLARE_MSM_GPIO_PINS(149);
0423 
0424 static const unsigned int ufs_reset_pins[] = { 150 };
0425 static const unsigned int sdc2_clk_pins[] = { 151 };
0426 static const unsigned int sdc2_cmd_pins[] = { 152 };
0427 static const unsigned int sdc2_data_pins[] = { 153 };
0428 
0429 enum sdm845_functions {
0430     msm_mux_gpio,
0431     msm_mux_adsp_ext,
0432     msm_mux_agera_pll,
0433     msm_mux_atest_char,
0434     msm_mux_atest_tsens,
0435     msm_mux_atest_tsens2,
0436     msm_mux_atest_usb1,
0437     msm_mux_atest_usb10,
0438     msm_mux_atest_usb11,
0439     msm_mux_atest_usb12,
0440     msm_mux_atest_usb13,
0441     msm_mux_atest_usb2,
0442     msm_mux_atest_usb20,
0443     msm_mux_atest_usb21,
0444     msm_mux_atest_usb22,
0445     msm_mux_atest_usb23,
0446     msm_mux_audio_ref,
0447     msm_mux_btfm_slimbus,
0448     msm_mux_cam_mclk,
0449     msm_mux_cci_async,
0450     msm_mux_cci_i2c,
0451     msm_mux_cci_timer0,
0452     msm_mux_cci_timer1,
0453     msm_mux_cci_timer2,
0454     msm_mux_cci_timer3,
0455     msm_mux_cci_timer4,
0456     msm_mux_cri_trng,
0457     msm_mux_cri_trng0,
0458     msm_mux_cri_trng1,
0459     msm_mux_dbg_out,
0460     msm_mux_ddr_bist,
0461     msm_mux_ddr_pxi0,
0462     msm_mux_ddr_pxi1,
0463     msm_mux_ddr_pxi2,
0464     msm_mux_ddr_pxi3,
0465     msm_mux_edp_hot,
0466     msm_mux_edp_lcd,
0467     msm_mux_gcc_gp1,
0468     msm_mux_gcc_gp2,
0469     msm_mux_gcc_gp3,
0470     msm_mux_jitter_bist,
0471     msm_mux_ldo_en,
0472     msm_mux_ldo_update,
0473     msm_mux_lpass_slimbus,
0474     msm_mux_m_voc,
0475     msm_mux_mdp_vsync,
0476     msm_mux_mdp_vsync0,
0477     msm_mux_mdp_vsync1,
0478     msm_mux_mdp_vsync2,
0479     msm_mux_mdp_vsync3,
0480     msm_mux_mss_lte,
0481     msm_mux_nav_pps,
0482     msm_mux_pa_indicator,
0483     msm_mux_pci_e0,
0484     msm_mux_pci_e1,
0485     msm_mux_phase_flag,
0486     msm_mux_pll_bist,
0487     msm_mux_pll_bypassnl,
0488     msm_mux_pll_reset,
0489     msm_mux_pri_mi2s,
0490     msm_mux_pri_mi2s_ws,
0491     msm_mux_prng_rosc,
0492     msm_mux_qdss_cti,
0493     msm_mux_qdss,
0494     msm_mux_qlink_enable,
0495     msm_mux_qlink_request,
0496     msm_mux_qspi_clk,
0497     msm_mux_qspi_cs,
0498     msm_mux_qspi_data,
0499     msm_mux_qua_mi2s,
0500     msm_mux_qup0,
0501     msm_mux_qup1,
0502     msm_mux_qup10,
0503     msm_mux_qup11,
0504     msm_mux_qup12,
0505     msm_mux_qup13,
0506     msm_mux_qup14,
0507     msm_mux_qup15,
0508     msm_mux_qup2,
0509     msm_mux_qup3,
0510     msm_mux_qup4,
0511     msm_mux_qup5,
0512     msm_mux_qup6,
0513     msm_mux_qup7,
0514     msm_mux_qup8,
0515     msm_mux_qup9,
0516     msm_mux_qup_l4,
0517     msm_mux_qup_l5,
0518     msm_mux_qup_l6,
0519     msm_mux_sd_write,
0520     msm_mux_sdc4_clk,
0521     msm_mux_sdc4_cmd,
0522     msm_mux_sdc4_data,
0523     msm_mux_sec_mi2s,
0524     msm_mux_sp_cmu,
0525     msm_mux_spkr_i2s,
0526     msm_mux_ter_mi2s,
0527     msm_mux_tgu_ch0,
0528     msm_mux_tgu_ch1,
0529     msm_mux_tgu_ch2,
0530     msm_mux_tgu_ch3,
0531     msm_mux_tsense_pwm1,
0532     msm_mux_tsense_pwm2,
0533     msm_mux_tsif1_clk,
0534     msm_mux_tsif1_data,
0535     msm_mux_tsif1_en,
0536     msm_mux_tsif1_error,
0537     msm_mux_tsif1_sync,
0538     msm_mux_tsif2_clk,
0539     msm_mux_tsif2_data,
0540     msm_mux_tsif2_en,
0541     msm_mux_tsif2_error,
0542     msm_mux_tsif2_sync,
0543     msm_mux_uim1_clk,
0544     msm_mux_uim1_data,
0545     msm_mux_uim1_present,
0546     msm_mux_uim1_reset,
0547     msm_mux_uim2_clk,
0548     msm_mux_uim2_data,
0549     msm_mux_uim2_present,
0550     msm_mux_uim2_reset,
0551     msm_mux_uim_batt,
0552     msm_mux_usb_phy,
0553     msm_mux_vfr_1,
0554     msm_mux_vsense_trigger,
0555     msm_mux_wlan1_adc0,
0556     msm_mux_wlan1_adc1,
0557     msm_mux_wlan2_adc0,
0558     msm_mux_wlan2_adc1,
0559     msm_mux__,
0560 };
0561 
0562 static const char * const ddr_pxi3_groups[] = {
0563     "gpio12", "gpio13",
0564 };
0565 static const char * const cam_mclk_groups[] = {
0566     "gpio13", "gpio14", "gpio15", "gpio16",
0567 };
0568 static const char * const pll_bypassnl_groups[] = {
0569     "gpio13",
0570 };
0571 static const char * const qdss_groups[] = {
0572     "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
0573     "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
0574     "gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43",
0575     "gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93",
0576     "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
0577     "gpio123", "gpio124",
0578 };
0579 static const char * const pll_reset_groups[] = {
0580     "gpio14",
0581 };
0582 static const char * const cci_i2c_groups[] = {
0583     "gpio17", "gpio18", "gpio19", "gpio20",
0584 };
0585 static const char * const qup1_groups[] = {
0586     "gpio17", "gpio18", "gpio19", "gpio20",
0587 };
0588 static const char * const cci_timer0_groups[] = {
0589     "gpio21",
0590 };
0591 static const char * const gcc_gp2_groups[] = {
0592     "gpio21", "gpio58",
0593 };
0594 static const char * const cci_timer1_groups[] = {
0595     "gpio22",
0596 };
0597 static const char * const gcc_gp3_groups[] = {
0598     "gpio22", "gpio59",
0599 };
0600 static const char * const cci_timer2_groups[] = {
0601     "gpio23",
0602 };
0603 static const char * const cci_timer3_groups[] = {
0604     "gpio24",
0605 };
0606 static const char * const cci_async_groups[] = {
0607     "gpio24", "gpio25", "gpio26",
0608 };
0609 static const char * const cci_timer4_groups[] = {
0610     "gpio25",
0611 };
0612 static const char * const qup2_groups[] = {
0613     "gpio27", "gpio28", "gpio29", "gpio30",
0614 };
0615 static const char * const phase_flag_groups[] = {
0616     "gpio29", "gpio30", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
0617     "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
0618     "gpio64", "gpio74", "gpio75", "gpio76", "gpio77", "gpio89", "gpio90",
0619     "gpio96", "gpio99", "gpio100", "gpio103", "gpio137", "gpio138",
0620     "gpio139", "gpio140", "gpio141", "gpio142", "gpio143",
0621 };
0622 static const char * const qup11_groups[] = {
0623     "gpio31", "gpio32", "gpio33", "gpio34",
0624 };
0625 static const char * const qup14_groups[] = {
0626     "gpio31", "gpio32", "gpio33", "gpio34",
0627 };
0628 static const char * const pci_e0_groups[] = {
0629     "gpio35", "gpio36",
0630 };
0631 static const char * const jitter_bist_groups[] = {
0632     "gpio35",
0633 };
0634 static const char * const pll_bist_groups[] = {
0635     "gpio36",
0636 };
0637 static const char * const atest_tsens_groups[] = {
0638     "gpio36",
0639 };
0640 static const char * const agera_pll_groups[] = {
0641     "gpio37",
0642 };
0643 static const char * const usb_phy_groups[] = {
0644     "gpio38",
0645 };
0646 static const char * const lpass_slimbus_groups[] = {
0647     "gpio39", "gpio70", "gpio71", "gpio72",
0648 };
0649 static const char * const sd_write_groups[] = {
0650     "gpio40",
0651 };
0652 static const char * const tsif1_error_groups[] = {
0653     "gpio40",
0654 };
0655 static const char * const qup3_groups[] = {
0656     "gpio41", "gpio42", "gpio43", "gpio44",
0657 };
0658 static const char * const qup6_groups[] = {
0659     "gpio45", "gpio46", "gpio47", "gpio48",
0660 };
0661 static const char * const qup12_groups[] = {
0662     "gpio49", "gpio50", "gpio51", "gpio52",
0663 };
0664 static const char * const qup10_groups[] = {
0665     "gpio53", "gpio54", "gpio55", "gpio56",
0666 };
0667 static const char * const qua_mi2s_groups[] = {
0668     "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
0669 };
0670 static const char * const gcc_gp1_groups[] = {
0671     "gpio57", "gpio78",
0672 };
0673 static const char * const cri_trng0_groups[] = {
0674     "gpio60",
0675 };
0676 static const char * const cri_trng1_groups[] = {
0677     "gpio61",
0678 };
0679 static const char * const cri_trng_groups[] = {
0680     "gpio62",
0681 };
0682 static const char * const pri_mi2s_groups[] = {
0683     "gpio64", "gpio65", "gpio67", "gpio68",
0684 };
0685 static const char * const sp_cmu_groups[] = {
0686     "gpio64",
0687 };
0688 static const char * const qup8_groups[] = {
0689     "gpio65", "gpio66", "gpio67", "gpio68",
0690 };
0691 static const char * const pri_mi2s_ws_groups[] = {
0692     "gpio66",
0693 };
0694 static const char * const spkr_i2s_groups[] = {
0695     "gpio69", "gpio70", "gpio71", "gpio72",
0696 };
0697 static const char * const audio_ref_groups[] = {
0698     "gpio69",
0699 };
0700 static const char * const tsense_pwm1_groups[] = {
0701     "gpio71",
0702 };
0703 static const char * const tsense_pwm2_groups[] = {
0704     "gpio71",
0705 };
0706 static const char * const btfm_slimbus_groups[] = {
0707     "gpio73", "gpio74",
0708 };
0709 static const char * const atest_usb2_groups[] = {
0710     "gpio73",
0711 };
0712 static const char * const ter_mi2s_groups[] = {
0713     "gpio74", "gpio75", "gpio76", "gpio77", "gpio78",
0714 };
0715 static const char * const atest_usb23_groups[] = {
0716     "gpio74",
0717 };
0718 static const char * const atest_usb22_groups[] = {
0719     "gpio75",
0720 };
0721 static const char * const atest_usb21_groups[] = {
0722     "gpio76",
0723 };
0724 static const char * const atest_usb20_groups[] = {
0725     "gpio77",
0726 };
0727 static const char * const sec_mi2s_groups[] = {
0728     "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
0729 };
0730 static const char * const qup15_groups[] = {
0731     "gpio81", "gpio82", "gpio83", "gpio84",
0732 };
0733 static const char * const qup5_groups[] = {
0734     "gpio85", "gpio86", "gpio87", "gpio88",
0735 };
0736 static const char * const tsif1_clk_groups[] = {
0737     "gpio89",
0738 };
0739 static const char * const qup4_groups[] = {
0740     "gpio89", "gpio90", "gpio91", "gpio92",
0741 };
0742 static const char * const qspi_cs_groups[] = {
0743     "gpio89", "gpio90",
0744 };
0745 static const char * const tgu_ch3_groups[] = {
0746     "gpio89",
0747 };
0748 static const char * const tsif1_en_groups[] = {
0749     "gpio90",
0750 };
0751 static const char * const mdp_vsync0_groups[] = {
0752     "gpio90",
0753 };
0754 static const char * const mdp_vsync1_groups[] = {
0755     "gpio90",
0756 };
0757 static const char * const mdp_vsync2_groups[] = {
0758     "gpio90",
0759 };
0760 static const char * const mdp_vsync3_groups[] = {
0761     "gpio90",
0762 };
0763 static const char * const tgu_ch0_groups[] = {
0764     "gpio90",
0765 };
0766 static const char * const tsif1_data_groups[] = {
0767     "gpio91",
0768 };
0769 static const char * const sdc4_cmd_groups[] = {
0770     "gpio91",
0771 };
0772 static const char * const qspi_data_groups[] = {
0773     "gpio91", "gpio92", "gpio93", "gpio94",
0774 };
0775 static const char * const tgu_ch1_groups[] = {
0776     "gpio91",
0777 };
0778 static const char * const tsif2_error_groups[] = {
0779     "gpio92",
0780 };
0781 static const char * const sdc4_data_groups[] = {
0782     "gpio92",
0783     "gpio94",
0784     "gpio95",
0785     "gpio96",
0786 };
0787 static const char * const vfr_1_groups[] = {
0788     "gpio92",
0789 };
0790 static const char * const tgu_ch2_groups[] = {
0791     "gpio92",
0792 };
0793 static const char * const tsif2_clk_groups[] = {
0794     "gpio93",
0795 };
0796 static const char * const sdc4_clk_groups[] = {
0797     "gpio93",
0798 };
0799 static const char * const qup7_groups[] = {
0800     "gpio93", "gpio94", "gpio95", "gpio96",
0801 };
0802 static const char * const tsif2_en_groups[] = {
0803     "gpio94",
0804 };
0805 static const char * const tsif2_data_groups[] = {
0806     "gpio95",
0807 };
0808 static const char * const qspi_clk_groups[] = {
0809     "gpio95",
0810 };
0811 static const char * const tsif2_sync_groups[] = {
0812     "gpio96",
0813 };
0814 static const char * const ldo_en_groups[] = {
0815     "gpio97",
0816 };
0817 static const char * const ldo_update_groups[] = {
0818     "gpio98",
0819 };
0820 static const char * const pci_e1_groups[] = {
0821     "gpio102", "gpio103",
0822 };
0823 static const char * const prng_rosc_groups[] = {
0824     "gpio102",
0825 };
0826 static const char * const uim2_data_groups[] = {
0827     "gpio105",
0828 };
0829 static const char * const qup13_groups[] = {
0830     "gpio105", "gpio106", "gpio107", "gpio108",
0831 };
0832 static const char * const uim2_clk_groups[] = {
0833     "gpio106",
0834 };
0835 static const char * const uim2_reset_groups[] = {
0836     "gpio107",
0837 };
0838 static const char * const uim2_present_groups[] = {
0839     "gpio108",
0840 };
0841 static const char * const uim1_data_groups[] = {
0842     "gpio109",
0843 };
0844 static const char * const uim1_clk_groups[] = {
0845     "gpio110",
0846 };
0847 static const char * const uim1_reset_groups[] = {
0848     "gpio111",
0849 };
0850 static const char * const uim1_present_groups[] = {
0851     "gpio112",
0852 };
0853 static const char * const uim_batt_groups[] = {
0854     "gpio113",
0855 };
0856 static const char * const edp_hot_groups[] = {
0857     "gpio113",
0858 };
0859 static const char * const nav_pps_groups[] = {
0860     "gpio114", "gpio114", "gpio115", "gpio115", "gpio128", "gpio128",
0861     "gpio129", "gpio129", "gpio143", "gpio143",
0862 };
0863 static const char * const atest_char_groups[] = {
0864     "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
0865 };
0866 static const char * const adsp_ext_groups[] = {
0867     "gpio118",
0868 };
0869 static const char * const qlink_request_groups[] = {
0870     "gpio130",
0871 };
0872 static const char * const qlink_enable_groups[] = {
0873     "gpio131",
0874 };
0875 static const char * const pa_indicator_groups[] = {
0876     "gpio135",
0877 };
0878 static const char * const mss_lte_groups[] = {
0879     "gpio144", "gpio145",
0880 };
0881 static const char * const qup0_groups[] = {
0882     "gpio0", "gpio1", "gpio2", "gpio3",
0883 };
0884 static const char * const gpio_groups[] = {
0885     "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
0886     "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
0887     "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
0888     "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
0889     "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
0890     "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
0891     "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
0892     "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
0893     "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
0894     "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
0895     "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
0896     "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
0897     "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
0898     "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
0899     "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
0900     "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
0901     "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
0902     "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
0903     "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
0904     "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
0905     "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
0906     "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
0907     "gpio147", "gpio148", "gpio149",
0908 };
0909 static const char * const qup9_groups[] = {
0910     "gpio4", "gpio5", "gpio6", "gpio7",
0911 };
0912 static const char * const qdss_cti_groups[] = {
0913     "gpio4", "gpio5", "gpio51", "gpio52", "gpio62", "gpio63", "gpio90",
0914     "gpio91",
0915 };
0916 static const char * const ddr_pxi0_groups[] = {
0917     "gpio6", "gpio7",
0918 };
0919 static const char * const ddr_bist_groups[] = {
0920     "gpio7", "gpio8", "gpio9", "gpio10",
0921 };
0922 static const char * const atest_tsens2_groups[] = {
0923     "gpio7",
0924 };
0925 static const char * const vsense_trigger_groups[] = {
0926     "gpio7",
0927 };
0928 static const char * const atest_usb1_groups[] = {
0929     "gpio7",
0930 };
0931 static const char * const qup_l4_groups[] = {
0932     "gpio8", "gpio35", "gpio105", "gpio123",
0933 };
0934 static const char * const wlan1_adc1_groups[] = {
0935     "gpio8",
0936 };
0937 static const char * const atest_usb13_groups[] = {
0938     "gpio8",
0939 };
0940 static const char * const ddr_pxi1_groups[] = {
0941     "gpio8", "gpio9",
0942 };
0943 static const char * const qup_l5_groups[] = {
0944     "gpio9", "gpio36", "gpio106", "gpio124",
0945 };
0946 static const char * const wlan1_adc0_groups[] = {
0947     "gpio9",
0948 };
0949 static const char * const atest_usb12_groups[] = {
0950     "gpio9",
0951 };
0952 static const char * const mdp_vsync_groups[] = {
0953     "gpio10", "gpio11", "gpio12", "gpio97", "gpio98",
0954 };
0955 static const char * const qup_l6_groups[] = {
0956     "gpio10", "gpio37", "gpio107", "gpio125",
0957 };
0958 static const char * const wlan2_adc1_groups[] = {
0959     "gpio10",
0960 };
0961 static const char * const atest_usb11_groups[] = {
0962     "gpio10",
0963 };
0964 static const char * const ddr_pxi2_groups[] = {
0965     "gpio10", "gpio11",
0966 };
0967 static const char * const edp_lcd_groups[] = {
0968     "gpio11",
0969 };
0970 static const char * const dbg_out_groups[] = {
0971     "gpio11",
0972 };
0973 static const char * const wlan2_adc0_groups[] = {
0974     "gpio11",
0975 };
0976 static const char * const atest_usb10_groups[] = {
0977     "gpio11",
0978 };
0979 static const char * const m_voc_groups[] = {
0980     "gpio12",
0981 };
0982 static const char * const tsif1_sync_groups[] = {
0983     "gpio12",
0984 };
0985 
0986 static const struct msm_function sdm845_functions[] = {
0987     FUNCTION(gpio),
0988     FUNCTION(adsp_ext),
0989     FUNCTION(agera_pll),
0990     FUNCTION(atest_char),
0991     FUNCTION(atest_tsens),
0992     FUNCTION(atest_tsens2),
0993     FUNCTION(atest_usb1),
0994     FUNCTION(atest_usb10),
0995     FUNCTION(atest_usb11),
0996     FUNCTION(atest_usb12),
0997     FUNCTION(atest_usb13),
0998     FUNCTION(atest_usb2),
0999     FUNCTION(atest_usb20),
1000     FUNCTION(atest_usb21),
1001     FUNCTION(atest_usb22),
1002     FUNCTION(atest_usb23),
1003     FUNCTION(audio_ref),
1004     FUNCTION(btfm_slimbus),
1005     FUNCTION(cam_mclk),
1006     FUNCTION(cci_async),
1007     FUNCTION(cci_i2c),
1008     FUNCTION(cci_timer0),
1009     FUNCTION(cci_timer1),
1010     FUNCTION(cci_timer2),
1011     FUNCTION(cci_timer3),
1012     FUNCTION(cci_timer4),
1013     FUNCTION(cri_trng),
1014     FUNCTION(cri_trng0),
1015     FUNCTION(cri_trng1),
1016     FUNCTION(dbg_out),
1017     FUNCTION(ddr_bist),
1018     FUNCTION(ddr_pxi0),
1019     FUNCTION(ddr_pxi1),
1020     FUNCTION(ddr_pxi2),
1021     FUNCTION(ddr_pxi3),
1022     FUNCTION(edp_hot),
1023     FUNCTION(edp_lcd),
1024     FUNCTION(gcc_gp1),
1025     FUNCTION(gcc_gp2),
1026     FUNCTION(gcc_gp3),
1027     FUNCTION(jitter_bist),
1028     FUNCTION(ldo_en),
1029     FUNCTION(ldo_update),
1030     FUNCTION(lpass_slimbus),
1031     FUNCTION(m_voc),
1032     FUNCTION(mdp_vsync),
1033     FUNCTION(mdp_vsync0),
1034     FUNCTION(mdp_vsync1),
1035     FUNCTION(mdp_vsync2),
1036     FUNCTION(mdp_vsync3),
1037     FUNCTION(mss_lte),
1038     FUNCTION(nav_pps),
1039     FUNCTION(pa_indicator),
1040     FUNCTION(pci_e0),
1041     FUNCTION(pci_e1),
1042     FUNCTION(phase_flag),
1043     FUNCTION(pll_bist),
1044     FUNCTION(pll_bypassnl),
1045     FUNCTION(pll_reset),
1046     FUNCTION(pri_mi2s),
1047     FUNCTION(pri_mi2s_ws),
1048     FUNCTION(prng_rosc),
1049     FUNCTION(qdss_cti),
1050     FUNCTION(qdss),
1051     FUNCTION(qlink_enable),
1052     FUNCTION(qlink_request),
1053     FUNCTION(qspi_clk),
1054     FUNCTION(qspi_cs),
1055     FUNCTION(qspi_data),
1056     FUNCTION(qua_mi2s),
1057     FUNCTION(qup0),
1058     FUNCTION(qup1),
1059     FUNCTION(qup10),
1060     FUNCTION(qup11),
1061     FUNCTION(qup12),
1062     FUNCTION(qup13),
1063     FUNCTION(qup14),
1064     FUNCTION(qup15),
1065     FUNCTION(qup2),
1066     FUNCTION(qup3),
1067     FUNCTION(qup4),
1068     FUNCTION(qup5),
1069     FUNCTION(qup6),
1070     FUNCTION(qup7),
1071     FUNCTION(qup8),
1072     FUNCTION(qup9),
1073     FUNCTION(qup_l4),
1074     FUNCTION(qup_l5),
1075     FUNCTION(qup_l6),
1076     FUNCTION(sd_write),
1077     FUNCTION(sdc4_clk),
1078     FUNCTION(sdc4_cmd),
1079     FUNCTION(sdc4_data),
1080     FUNCTION(sec_mi2s),
1081     FUNCTION(sp_cmu),
1082     FUNCTION(spkr_i2s),
1083     FUNCTION(ter_mi2s),
1084     FUNCTION(tgu_ch0),
1085     FUNCTION(tgu_ch1),
1086     FUNCTION(tgu_ch2),
1087     FUNCTION(tgu_ch3),
1088     FUNCTION(tsense_pwm1),
1089     FUNCTION(tsense_pwm2),
1090     FUNCTION(tsif1_clk),
1091     FUNCTION(tsif1_data),
1092     FUNCTION(tsif1_en),
1093     FUNCTION(tsif1_error),
1094     FUNCTION(tsif1_sync),
1095     FUNCTION(tsif2_clk),
1096     FUNCTION(tsif2_data),
1097     FUNCTION(tsif2_en),
1098     FUNCTION(tsif2_error),
1099     FUNCTION(tsif2_sync),
1100     FUNCTION(uim1_clk),
1101     FUNCTION(uim1_data),
1102     FUNCTION(uim1_present),
1103     FUNCTION(uim1_reset),
1104     FUNCTION(uim2_clk),
1105     FUNCTION(uim2_data),
1106     FUNCTION(uim2_present),
1107     FUNCTION(uim2_reset),
1108     FUNCTION(uim_batt),
1109     FUNCTION(usb_phy),
1110     FUNCTION(vfr_1),
1111     FUNCTION(vsense_trigger),
1112     FUNCTION(wlan1_adc0),
1113     FUNCTION(wlan1_adc1),
1114     FUNCTION(wlan2_adc0),
1115     FUNCTION(wlan2_adc1),
1116 };
1117 
1118 /* Every pin is maintained as a single group, and missing or non-existing pin
1119  * would be maintained as dummy group to synchronize pin group index with
1120  * pin descriptor registered with pinctrl core.
1121  * Clients would not be able to request these dummy pin groups.
1122  */
1123 static const struct msm_pingroup sdm845_groups[] = {
1124     PINGROUP(0, EAST, qup0, _, _, _, _, _, _, _, _, _),
1125     PINGROUP(1, EAST, qup0, _, _, _, _, _, _, _, _, _),
1126     PINGROUP(2, EAST, qup0, _, _, _, _, _, _, _, _, _),
1127     PINGROUP(3, EAST, qup0, _, _, _, _, _, _, _, _, _),
1128     PINGROUP(4, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _, _),
1129     PINGROUP(5, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _, _),
1130     PINGROUP(6, NORTH, qup9, _, ddr_pxi0, _, _, _, _, _, _, _),
1131     PINGROUP(7, NORTH, qup9, ddr_bist, _, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _, _),
1132     PINGROUP(8, EAST, qup_l4, _, ddr_bist, _, _, wlan1_adc1, atest_usb13, ddr_pxi1, _, _),
1133     PINGROUP(9, EAST, qup_l5, ddr_bist, _, wlan1_adc0, atest_usb12, ddr_pxi1, _, _, _, _),
1134     PINGROUP(10, EAST, mdp_vsync, qup_l6, ddr_bist, wlan2_adc1, atest_usb11, ddr_pxi2, _, _, _, _),
1135     PINGROUP(11, EAST, mdp_vsync, edp_lcd, dbg_out, wlan2_adc0, atest_usb10, ddr_pxi2, _, _, _, _),
1136     PINGROUP(12, SOUTH, mdp_vsync, m_voc, tsif1_sync, ddr_pxi3, _, _, _, _, _, _),
1137     PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss, ddr_pxi3, _, _, _, _, _, _),
1138     PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss, _, _, _, _, _, _, _),
1139     PINGROUP(15, SOUTH, cam_mclk, qdss, _, _, _, _, _, _, _, _),
1140     PINGROUP(16, SOUTH, cam_mclk, qdss, _, _, _, _, _, _, _, _),
1141     PINGROUP(17, SOUTH, cci_i2c, qup1, qdss, _, _, _, _, _, _, _),
1142     PINGROUP(18, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _),
1143     PINGROUP(19, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _),
1144     PINGROUP(20, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _),
1145     PINGROUP(21, SOUTH, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _, _),
1146     PINGROUP(22, SOUTH, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _, _),
1147     PINGROUP(23, SOUTH, cci_timer2, qdss, _, _, _, _, _, _, _, _),
1148     PINGROUP(24, SOUTH, cci_timer3, cci_async, qdss, _, _, _, _, _, _, _),
1149     PINGROUP(25, SOUTH, cci_timer4, cci_async, qdss, _, _, _, _, _, _, _),
1150     PINGROUP(26, SOUTH, cci_async, qdss, _, _, _, _, _, _, _, _),
1151     PINGROUP(27, EAST, qup2, qdss, _, _, _, _, _, _, _, _),
1152     PINGROUP(28, EAST, qup2, qdss, _, _, _, _, _, _, _, _),
1153     PINGROUP(29, EAST, qup2, _, phase_flag, qdss, _, _, _, _, _, _),
1154     PINGROUP(30, EAST, qup2, phase_flag, qdss, _, _, _, _, _, _, _),
1155     PINGROUP(31, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
1156     PINGROUP(32, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
1157     PINGROUP(33, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
1158     PINGROUP(34, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
1159     PINGROUP(35, SOUTH, pci_e0, qup_l4, jitter_bist, _, _, _, _, _, _, _),
1160     PINGROUP(36, SOUTH, pci_e0, qup_l5, pll_bist, _, atest_tsens, _, _, _, _, _),
1161     PINGROUP(37, SOUTH, qup_l6, agera_pll, _, _, _, _, _, _, _, _),
1162     PINGROUP(38, NORTH, usb_phy, _, _, _, _, _, _, _, _, _),
1163     PINGROUP(39, EAST, lpass_slimbus, _, _, _, _, _, _, _, _, _),
1164     PINGROUP(40, SOUTH, sd_write, tsif1_error, _, _, _, _, _, _, _, _),
1165     PINGROUP(41, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
1166     PINGROUP(42, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
1167     PINGROUP(43, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
1168     PINGROUP(44, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
1169     PINGROUP(45, EAST, qup6, _, _, _, _, _, _, _, _, _),
1170     PINGROUP(46, EAST, qup6, _, _, _, _, _, _, _, _, _),
1171     PINGROUP(47, EAST, qup6, _, _, _, _, _, _, _, _, _),
1172     PINGROUP(48, EAST, qup6, _, _, _, _, _, _, _, _, _),
1173     PINGROUP(49, NORTH, qup12, _, _, _, _, _, _, _, _, _),
1174     PINGROUP(50, NORTH, qup12, _, _, _, _, _, _, _, _, _),
1175     PINGROUP(51, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _, _),
1176     PINGROUP(52, NORTH, qup12, phase_flag, qdss_cti, _, _, _, _, _, _, _),
1177     PINGROUP(53, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _),
1178     PINGROUP(54, NORTH, qup10, _, phase_flag, _, _, _, _, _, _, _),
1179     PINGROUP(55, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _),
1180     PINGROUP(56, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _),
1181     PINGROUP(57, NORTH, qua_mi2s, gcc_gp1, phase_flag, _, _, _, _, _, _, _),
1182     PINGROUP(58, NORTH, qua_mi2s, gcc_gp2, phase_flag, _, _, _, _, _, _, _),
1183     PINGROUP(59, NORTH, qua_mi2s, gcc_gp3, phase_flag, _, _, _, _, _, _, _),
1184     PINGROUP(60, NORTH, qua_mi2s, cri_trng0, phase_flag, _, _, _, _, _, _, _),
1185     PINGROUP(61, NORTH, qua_mi2s, cri_trng1, phase_flag, _, _, _, _, _, _, _),
1186     PINGROUP(62, NORTH, qua_mi2s, cri_trng, phase_flag, qdss_cti, _, _, _, _, _, _),
1187     PINGROUP(63, NORTH, qua_mi2s, _, phase_flag, qdss_cti, _, _, _, _, _, _),
1188     PINGROUP(64, NORTH, pri_mi2s, sp_cmu, phase_flag, _, _, _, _, _, _, _),
1189     PINGROUP(65, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _),
1190     PINGROUP(66, NORTH, pri_mi2s_ws, qup8, _, _, _, _, _, _, _, _),
1191     PINGROUP(67, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _),
1192     PINGROUP(68, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _),
1193     PINGROUP(69, EAST, spkr_i2s, audio_ref, _, _, _, _, _, _, _, _),
1194     PINGROUP(70, EAST, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _, _),
1195     PINGROUP(71, EAST, lpass_slimbus, spkr_i2s, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _),
1196     PINGROUP(72, EAST, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _, _),
1197     PINGROUP(73, EAST, btfm_slimbus, atest_usb2, _, _, _, _, _, _, _, _),
1198     PINGROUP(74, EAST, btfm_slimbus, ter_mi2s, phase_flag, atest_usb23, _, _, _, _, _, _),
1199     PINGROUP(75, EAST, ter_mi2s, phase_flag, qdss, atest_usb22, _, _, _, _, _, _),
1200     PINGROUP(76, EAST, ter_mi2s, phase_flag, qdss, atest_usb21, _, _, _, _, _, _),
1201     PINGROUP(77, EAST, ter_mi2s, phase_flag, qdss, atest_usb20, _, _, _, _, _, _),
1202     PINGROUP(78, EAST, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _, _),
1203     PINGROUP(79, NORTH, sec_mi2s, _, _, qdss, _, _, _, _, _, _),
1204     PINGROUP(80, NORTH, sec_mi2s, _, qdss, _, _, _, _, _, _, _),
1205     PINGROUP(81, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _),
1206     PINGROUP(82, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _),
1207     PINGROUP(83, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _),
1208     PINGROUP(84, NORTH, qup15, _, _, _, _, _, _, _, _, _),
1209     PINGROUP(85, EAST, qup5, _, _, _, _, _, _, _, _, _),
1210     PINGROUP(86, EAST, qup5, _, _, _, _, _, _, _, _, _),
1211     PINGROUP(87, EAST, qup5, _, _, _, _, _, _, _, _, _),
1212     PINGROUP(88, EAST, qup5, _, _, _, _, _, _, _, _, _),
1213     PINGROUP(89, SOUTH, tsif1_clk, qup4, qspi_cs, tgu_ch3, phase_flag, _, _, _, _, _),
1214     PINGROUP(90, SOUTH, tsif1_en, mdp_vsync0, qup4, qspi_cs, mdp_vsync1,
1215                 mdp_vsync2, mdp_vsync3, tgu_ch0, phase_flag, qdss_cti),
1216     PINGROUP(91, SOUTH, tsif1_data, sdc4_cmd, qup4, qspi_data, tgu_ch1, _, qdss_cti, _, _, _),
1217     PINGROUP(92, SOUTH, tsif2_error, sdc4_data, qup4, qspi_data, vfr_1, tgu_ch2, _, _, _, _),
1218     PINGROUP(93, SOUTH, tsif2_clk, sdc4_clk, qup7, qspi_data, _, qdss, _, _, _, _),
1219     PINGROUP(94, SOUTH, tsif2_en, sdc4_data, qup7, qspi_data, _, _, _, _, _, _),
1220     PINGROUP(95, SOUTH, tsif2_data, sdc4_data, qup7, qspi_clk, _, _, _, _, _, _),
1221     PINGROUP(96, SOUTH, tsif2_sync, sdc4_data, qup7, phase_flag, _, _, _, _, _, _),
1222     PINGROUP(97, NORTH, _, _, mdp_vsync, ldo_en, _, _, _, _, _, _),
1223     PINGROUP(98, NORTH, _, mdp_vsync, ldo_update, _, _, _, _, _, _, _),
1224     PINGROUP(99, NORTH, phase_flag, _, _, _, _, _, _, _, _, _),
1225     PINGROUP(100, NORTH, phase_flag, _, _, _, _, _, _, _, _, _),
1226     PINGROUP(101, NORTH, _, _, _, _, _, _, _, _, _, _),
1227     PINGROUP(102, NORTH, pci_e1, prng_rosc, _, _, _, _, _, _, _, _),
1228     PINGROUP(103, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _, _),
1229     PINGROUP(104, NORTH, _, _, _, _, _, _, _, _, _, _),
1230     PINGROUP(105, NORTH, uim2_data, qup13, qup_l4, _, _, _, _, _, _, _),
1231     PINGROUP(106, NORTH, uim2_clk, qup13, qup_l5, _, _, _, _, _, _, _),
1232     PINGROUP(107, NORTH, uim2_reset, qup13, qup_l6, _, _, _, _, _, _, _),
1233     PINGROUP(108, NORTH, uim2_present, qup13, _, _, _, _, _, _, _, _),
1234     PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _, _),
1235     PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _, _),
1236     PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _, _),
1237     PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _, _),
1238     PINGROUP(113, NORTH, uim_batt, edp_hot, _, _, _, _, _, _, _, _),
1239     PINGROUP(114, NORTH, _, nav_pps, nav_pps, _, _, _, _, _, _, _),
1240     PINGROUP(115, NORTH, _, nav_pps, nav_pps, _, _, _, _, _, _, _),
1241     PINGROUP(116, NORTH, _, _, _, _, _, _, _, _, _, _),
1242     PINGROUP(117, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
1243     PINGROUP(118, NORTH, adsp_ext, _, qdss, atest_char, _, _, _, _, _, _),
1244     PINGROUP(119, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
1245     PINGROUP(120, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
1246     PINGROUP(121, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
1247     PINGROUP(122, EAST, _, qdss, _, _, _, _, _, _, _, _),
1248     PINGROUP(123, EAST, qup_l4, _, qdss, _, _, _, _, _, _, _),
1249     PINGROUP(124, EAST, qup_l5, _, qdss, _, _, _, _, _, _, _),
1250     PINGROUP(125, EAST, qup_l6, _, _, _, _, _, _, _, _, _),
1251     PINGROUP(126, EAST, _, _, _, _, _, _, _, _, _, _),
1252     PINGROUP(127, NORTH, _, _, _, _, _, _, _, _, _, _),
1253     PINGROUP(128, NORTH, nav_pps, nav_pps, _, _, _, _, _, _, _, _),
1254     PINGROUP(129, NORTH, nav_pps, nav_pps, _, _, _, _, _, _, _, _),
1255     PINGROUP(130, NORTH, qlink_request, _, _, _, _, _, _, _, _, _),
1256     PINGROUP(131, NORTH, qlink_enable, _, _, _, _, _, _, _, _, _),
1257     PINGROUP(132, NORTH, _, _, _, _, _, _, _, _, _, _),
1258     PINGROUP(133, NORTH, _, _, _, _, _, _, _, _, _, _),
1259     PINGROUP(134, NORTH, _, _, _, _, _, _, _, _, _, _),
1260     PINGROUP(135, NORTH, _, pa_indicator, _, _, _, _, _, _, _, _),
1261     PINGROUP(136, NORTH, _, _, _, _, _, _, _, _, _, _),
1262     PINGROUP(137, NORTH, _, _, phase_flag, _, _, _, _, _, _, _),
1263     PINGROUP(138, NORTH, _, _, phase_flag, _, _, _, _, _, _, _),
1264     PINGROUP(139, NORTH, _, phase_flag, _, _, _, _, _, _, _, _),
1265     PINGROUP(140, NORTH, _, _, phase_flag, _, _, _, _, _, _, _),
1266     PINGROUP(141, NORTH, _, phase_flag, _, _, _, _, _, _, _, _),
1267     PINGROUP(142, NORTH, _, phase_flag, _, _, _, _, _, _, _, _),
1268     PINGROUP(143, NORTH, _, nav_pps, nav_pps, _, phase_flag, _, _, _, _, _),
1269     PINGROUP(144, NORTH, mss_lte, _, _, _, _, _, _, _, _, _),
1270     PINGROUP(145, NORTH, mss_lte, _, _, _, _, _, _, _, _, _),
1271     PINGROUP(146, NORTH, _, _, _, _, _, _, _, _, _, _),
1272     PINGROUP(147, NORTH, _, _, _, _, _, _, _, _, _, _),
1273     PINGROUP(148, NORTH, _, _, _, _, _, _, _, _, _, _),
1274     PINGROUP(149, NORTH, _, _, _, _, _, _, _, _, _, _),
1275     UFS_RESET(ufs_reset, 0x99f000),
1276     SDC_QDSD_PINGROUP(sdc2_clk, 0x99a000, 14, 6),
1277     SDC_QDSD_PINGROUP(sdc2_cmd, 0x99a000, 11, 3),
1278     SDC_QDSD_PINGROUP(sdc2_data, 0x99a000, 9, 0),
1279 };
1280 
1281 static const int sdm845_acpi_reserved_gpios[] = {
1282     0, 1, 2, 3, 81, 82, 83, 84, -1
1283 };
1284 
1285 static const struct msm_gpio_wakeirq_map sdm845_pdc_map[] = {
1286     { 1, 30 }, { 3, 31 }, { 5, 32 }, { 10, 33 }, { 11, 34 },
1287     { 20, 35 }, { 22, 36 }, { 24, 37 }, { 26, 38 }, { 30, 39 },
1288     { 31, 117 }, { 32, 41 }, { 34, 42 }, { 36, 43 }, { 37, 44 },
1289     { 38, 45 }, { 39, 46 }, { 40, 47 }, { 41, 115 }, { 43, 49 },
1290     { 44, 50 }, { 46, 51 }, { 48, 52 }, { 49, 118 }, { 52, 54 },
1291     { 53, 55 }, { 54, 56 }, { 56, 57 }, { 57, 58 }, { 58, 59 },
1292     { 59, 60 }, { 60, 61 }, { 61, 62 }, { 62, 63 }, { 63, 64 },
1293     { 64, 65 }, { 66, 66 }, { 68, 67 }, { 71, 68 }, { 73, 69 },
1294     { 77, 70 }, { 78, 71 }, { 79, 72 }, { 80, 73 }, { 84, 74 },
1295     { 85, 75 }, { 86, 76 }, { 88, 77 }, { 89, 116 }, { 91, 79 },
1296     { 92, 80 }, { 95, 81 }, { 96, 82 }, { 97, 83 }, { 101, 84 },
1297     { 103, 85 }, { 104, 86 }, { 115, 90 }, { 116, 91 }, { 117, 92 },
1298     { 118, 93 }, { 119, 94 }, { 120, 95 }, { 121, 96 }, { 122, 97 },
1299     { 123, 98 }, { 124, 99 }, { 125, 100 }, { 127, 102 }, { 128, 103 },
1300     { 129, 104 }, { 130, 105 }, { 132, 106 }, { 133, 107 }, { 145, 108 },
1301 };
1302 
1303 static const struct msm_pinctrl_soc_data sdm845_pinctrl = {
1304     .pins = sdm845_pins,
1305     .npins = ARRAY_SIZE(sdm845_pins),
1306     .functions = sdm845_functions,
1307     .nfunctions = ARRAY_SIZE(sdm845_functions),
1308     .groups = sdm845_groups,
1309     .ngroups = ARRAY_SIZE(sdm845_groups),
1310     .ngpios = 151,
1311     .wakeirq_map = sdm845_pdc_map,
1312     .nwakeirq_map = ARRAY_SIZE(sdm845_pdc_map),
1313     .wakeirq_dual_edge_errata = true,
1314 };
1315 
1316 static const struct msm_pinctrl_soc_data sdm845_acpi_pinctrl = {
1317     .pins = sdm845_pins,
1318     .npins = ARRAY_SIZE(sdm845_pins),
1319     .groups = sdm845_groups,
1320     .ngroups = ARRAY_SIZE(sdm845_groups),
1321     .reserved_gpios = sdm845_acpi_reserved_gpios,
1322     .ngpios = 150,
1323 };
1324 
1325 static int sdm845_pinctrl_probe(struct platform_device *pdev)
1326 {
1327     int ret;
1328 
1329     if (pdev->dev.of_node) {
1330         ret = msm_pinctrl_probe(pdev, &sdm845_pinctrl);
1331     } else if (has_acpi_companion(&pdev->dev)) {
1332         ret = msm_pinctrl_probe(pdev, &sdm845_acpi_pinctrl);
1333     } else {
1334         dev_err(&pdev->dev, "DT and ACPI disabled\n");
1335         return -EINVAL;
1336     }
1337 
1338     return ret;
1339 }
1340 
1341 #ifdef CONFIG_ACPI
1342 static const struct acpi_device_id sdm845_pinctrl_acpi_match[] = {
1343     { "QCOM0217"},
1344     { },
1345 };
1346 MODULE_DEVICE_TABLE(acpi, sdm845_pinctrl_acpi_match);
1347 #endif
1348 
1349 static const struct of_device_id sdm845_pinctrl_of_match[] = {
1350     { .compatible = "qcom,sdm845-pinctrl", },
1351     { },
1352 };
1353 
1354 static struct platform_driver sdm845_pinctrl_driver = {
1355     .driver = {
1356         .name = "sdm845-pinctrl",
1357         .pm = &msm_pinctrl_dev_pm_ops,
1358         .of_match_table = sdm845_pinctrl_of_match,
1359         .acpi_match_table = ACPI_PTR(sdm845_pinctrl_acpi_match),
1360     },
1361     .probe = sdm845_pinctrl_probe,
1362     .remove = msm_pinctrl_remove,
1363 };
1364 
1365 static int __init sdm845_pinctrl_init(void)
1366 {
1367     return platform_driver_register(&sdm845_pinctrl_driver);
1368 }
1369 arch_initcall(sdm845_pinctrl_init);
1370 
1371 static void __exit sdm845_pinctrl_exit(void)
1372 {
1373     platform_driver_unregister(&sdm845_pinctrl_driver);
1374 }
1375 module_exit(sdm845_pinctrl_exit);
1376 
1377 MODULE_DESCRIPTION("QTI sdm845 pinctrl driver");
1378 MODULE_LICENSE("GPL v2");
1379 MODULE_DEVICE_TABLE(of, sdm845_pinctrl_of_match);
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