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0007 #include <linux/clk.h>
0008 #include <linux/gpio/driver.h>
0009 #include <linux/module.h>
0010 #include <linux/of_device.h>
0011 #include <linux/pinctrl/pinconf-generic.h>
0012 #include <linux/pinctrl/pinconf.h>
0013 #include <linux/pinctrl/pinmux.h>
0014 #include "../pinctrl-utils.h"
0015 #include "pinctrl-lpass-lpi.h"
0016
0017 #define MAX_LPI_NUM_CLKS 2
0018
0019 struct lpi_pinctrl {
0020 struct device *dev;
0021 struct pinctrl_dev *ctrl;
0022 struct gpio_chip chip;
0023 struct pinctrl_desc desc;
0024 char __iomem *tlmm_base;
0025 char __iomem *slew_base;
0026 struct clk_bulk_data clks[MAX_LPI_NUM_CLKS];
0027 struct mutex slew_access_lock;
0028 const struct lpi_pinctrl_variant_data *data;
0029 };
0030
0031 static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin,
0032 unsigned int addr)
0033 {
0034 return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
0035 }
0036
0037 static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin,
0038 unsigned int addr, unsigned int val)
0039 {
0040 iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr);
0041
0042 return 0;
0043 }
0044
0045 static const struct pinctrl_ops lpi_gpio_pinctrl_ops = {
0046 .get_groups_count = pinctrl_generic_get_group_count,
0047 .get_group_name = pinctrl_generic_get_group_name,
0048 .get_group_pins = pinctrl_generic_get_group_pins,
0049 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
0050 .dt_free_map = pinctrl_utils_free_map,
0051 };
0052
0053 static int lpi_gpio_get_functions_count(struct pinctrl_dev *pctldev)
0054 {
0055 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0056
0057 return pctrl->data->nfunctions;
0058 }
0059
0060 static const char *lpi_gpio_get_function_name(struct pinctrl_dev *pctldev,
0061 unsigned int function)
0062 {
0063 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0064
0065 return pctrl->data->functions[function].name;
0066 }
0067
0068 static int lpi_gpio_get_function_groups(struct pinctrl_dev *pctldev,
0069 unsigned int function,
0070 const char *const **groups,
0071 unsigned *const num_qgroups)
0072 {
0073 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0074
0075 *groups = pctrl->data->functions[function].groups;
0076 *num_qgroups = pctrl->data->functions[function].ngroups;
0077
0078 return 0;
0079 }
0080
0081 static int lpi_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
0082 unsigned int group_num)
0083 {
0084 struct lpi_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0085 const struct lpi_pingroup *g = &pctrl->data->groups[group_num];
0086 u32 val;
0087 int i, pin = g->pin;
0088
0089 for (i = 0; i < g->nfuncs; i++) {
0090 if (g->funcs[i] == function)
0091 break;
0092 }
0093
0094 if (WARN_ON(i == g->nfuncs))
0095 return -EINVAL;
0096
0097 val = lpi_gpio_read(pctrl, pin, LPI_GPIO_CFG_REG);
0098 u32p_replace_bits(&val, i, LPI_GPIO_FUNCTION_MASK);
0099 lpi_gpio_write(pctrl, pin, LPI_GPIO_CFG_REG, val);
0100
0101 return 0;
0102 }
0103
0104 static const struct pinmux_ops lpi_gpio_pinmux_ops = {
0105 .get_functions_count = lpi_gpio_get_functions_count,
0106 .get_function_name = lpi_gpio_get_function_name,
0107 .get_function_groups = lpi_gpio_get_function_groups,
0108 .set_mux = lpi_gpio_set_mux,
0109 };
0110
0111 static int lpi_config_get(struct pinctrl_dev *pctldev,
0112 unsigned int pin, unsigned long *config)
0113 {
0114 unsigned int param = pinconf_to_config_param(*config);
0115 struct lpi_pinctrl *state = dev_get_drvdata(pctldev->dev);
0116 unsigned int arg = 0;
0117 int is_out;
0118 int pull;
0119 u32 ctl_reg;
0120
0121 ctl_reg = lpi_gpio_read(state, pin, LPI_GPIO_CFG_REG);
0122 is_out = ctl_reg & LPI_GPIO_OE_MASK;
0123 pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
0124
0125 switch (param) {
0126 case PIN_CONFIG_BIAS_DISABLE:
0127 if (pull == LPI_GPIO_BIAS_DISABLE)
0128 arg = 1;
0129 break;
0130 case PIN_CONFIG_BIAS_PULL_DOWN:
0131 if (pull == LPI_GPIO_PULL_DOWN)
0132 arg = 1;
0133 break;
0134 case PIN_CONFIG_BIAS_BUS_HOLD:
0135 if (pull == LPI_GPIO_KEEPER)
0136 arg = 1;
0137 break;
0138 case PIN_CONFIG_BIAS_PULL_UP:
0139 if (pull == LPI_GPIO_PULL_UP)
0140 arg = 1;
0141 break;
0142 case PIN_CONFIG_INPUT_ENABLE:
0143 case PIN_CONFIG_OUTPUT:
0144 if (is_out)
0145 arg = 1;
0146 break;
0147 default:
0148 return -EINVAL;
0149 }
0150
0151 *config = pinconf_to_config_packed(param, arg);
0152 return 0;
0153 }
0154
0155 static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group,
0156 unsigned long *configs, unsigned int nconfs)
0157 {
0158 struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev);
0159 unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
0160 bool value, output_enabled = false;
0161 const struct lpi_pingroup *g;
0162 unsigned long sval;
0163 int i, slew_offset;
0164 u32 val;
0165
0166 g = &pctrl->data->groups[group];
0167 for (i = 0; i < nconfs; i++) {
0168 param = pinconf_to_config_param(configs[i]);
0169 arg = pinconf_to_config_argument(configs[i]);
0170
0171 switch (param) {
0172 case PIN_CONFIG_BIAS_DISABLE:
0173 pullup = LPI_GPIO_BIAS_DISABLE;
0174 break;
0175 case PIN_CONFIG_BIAS_PULL_DOWN:
0176 pullup = LPI_GPIO_PULL_DOWN;
0177 break;
0178 case PIN_CONFIG_BIAS_BUS_HOLD:
0179 pullup = LPI_GPIO_KEEPER;
0180 break;
0181 case PIN_CONFIG_BIAS_PULL_UP:
0182 pullup = LPI_GPIO_PULL_UP;
0183 break;
0184 case PIN_CONFIG_INPUT_ENABLE:
0185 output_enabled = false;
0186 break;
0187 case PIN_CONFIG_OUTPUT:
0188 output_enabled = true;
0189 value = arg;
0190 break;
0191 case PIN_CONFIG_DRIVE_STRENGTH:
0192 strength = arg;
0193 break;
0194 case PIN_CONFIG_SLEW_RATE:
0195 if (arg > LPI_SLEW_RATE_MAX) {
0196 dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n",
0197 arg, group);
0198 return -EINVAL;
0199 }
0200
0201 slew_offset = g->slew_offset;
0202 if (slew_offset == LPI_NO_SLEW)
0203 break;
0204
0205 mutex_lock(&pctrl->slew_access_lock);
0206
0207 sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
0208 sval &= ~(LPI_SLEW_RATE_MASK << slew_offset);
0209 sval |= arg << slew_offset;
0210 iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG);
0211
0212 mutex_unlock(&pctrl->slew_access_lock);
0213 break;
0214 default:
0215 return -EINVAL;
0216 }
0217 }
0218
0219 val = lpi_gpio_read(pctrl, group, LPI_GPIO_CFG_REG);
0220
0221 u32p_replace_bits(&val, pullup, LPI_GPIO_PULL_MASK);
0222 u32p_replace_bits(&val, LPI_GPIO_DS_TO_VAL(strength),
0223 LPI_GPIO_OUT_STRENGTH_MASK);
0224 u32p_replace_bits(&val, output_enabled, LPI_GPIO_OE_MASK);
0225
0226 lpi_gpio_write(pctrl, group, LPI_GPIO_CFG_REG, val);
0227
0228 if (output_enabled) {
0229 val = u32_encode_bits(value ? 1 : 0, LPI_GPIO_VALUE_OUT_MASK);
0230 lpi_gpio_write(pctrl, group, LPI_GPIO_VALUE_REG, val);
0231 }
0232
0233 return 0;
0234 }
0235
0236 static const struct pinconf_ops lpi_gpio_pinconf_ops = {
0237 .is_generic = true,
0238 .pin_config_group_get = lpi_config_get,
0239 .pin_config_group_set = lpi_config_set,
0240 };
0241
0242 static int lpi_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
0243 {
0244 struct lpi_pinctrl *state = gpiochip_get_data(chip);
0245 unsigned long config;
0246
0247 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
0248
0249 return lpi_config_set(state->ctrl, pin, &config, 1);
0250 }
0251
0252 static int lpi_gpio_direction_output(struct gpio_chip *chip,
0253 unsigned int pin, int val)
0254 {
0255 struct lpi_pinctrl *state = gpiochip_get_data(chip);
0256 unsigned long config;
0257
0258 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
0259
0260 return lpi_config_set(state->ctrl, pin, &config, 1);
0261 }
0262
0263 static int lpi_gpio_get(struct gpio_chip *chip, unsigned int pin)
0264 {
0265 struct lpi_pinctrl *state = gpiochip_get_data(chip);
0266
0267 return lpi_gpio_read(state, pin, LPI_GPIO_VALUE_REG) &
0268 LPI_GPIO_VALUE_IN_MASK;
0269 }
0270
0271 static void lpi_gpio_set(struct gpio_chip *chip, unsigned int pin, int value)
0272 {
0273 struct lpi_pinctrl *state = gpiochip_get_data(chip);
0274 unsigned long config;
0275
0276 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
0277
0278 lpi_config_set(state->ctrl, pin, &config, 1);
0279 }
0280
0281 #ifdef CONFIG_DEBUG_FS
0282 #include <linux/seq_file.h>
0283
0284 static unsigned int lpi_regval_to_drive(u32 val)
0285 {
0286 return (val + 1) * 2;
0287 }
0288
0289 static void lpi_gpio_dbg_show_one(struct seq_file *s,
0290 struct pinctrl_dev *pctldev,
0291 struct gpio_chip *chip,
0292 unsigned int offset,
0293 unsigned int gpio)
0294 {
0295 struct lpi_pinctrl *state = gpiochip_get_data(chip);
0296 struct pinctrl_pin_desc pindesc;
0297 unsigned int func;
0298 int is_out;
0299 int drive;
0300 int pull;
0301 u32 ctl_reg;
0302
0303 static const char * const pulls[] = {
0304 "no pull",
0305 "pull down",
0306 "keeper",
0307 "pull up"
0308 };
0309
0310 pctldev = pctldev ? : state->ctrl;
0311 pindesc = pctldev->desc->pins[offset];
0312 ctl_reg = lpi_gpio_read(state, offset, LPI_GPIO_CFG_REG);
0313 is_out = ctl_reg & LPI_GPIO_OE_MASK;
0314
0315 func = FIELD_GET(LPI_GPIO_FUNCTION_MASK, ctl_reg);
0316 drive = FIELD_GET(LPI_GPIO_OUT_STRENGTH_MASK, ctl_reg);
0317 pull = FIELD_GET(LPI_GPIO_PULL_MASK, ctl_reg);
0318
0319 seq_printf(s, " %-8s: %-3s %d", pindesc.name, is_out ? "out" : "in", func);
0320 seq_printf(s, " %dmA", lpi_regval_to_drive(drive));
0321 seq_printf(s, " %s", pulls[pull]);
0322 }
0323
0324 static void lpi_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
0325 {
0326 unsigned int gpio = chip->base;
0327 unsigned int i;
0328
0329 for (i = 0; i < chip->ngpio; i++, gpio++) {
0330 lpi_gpio_dbg_show_one(s, NULL, chip, i, gpio);
0331 seq_puts(s, "\n");
0332 }
0333 }
0334
0335 #else
0336 #define lpi_gpio_dbg_show NULL
0337 #endif
0338
0339 static const struct gpio_chip lpi_gpio_template = {
0340 .direction_input = lpi_gpio_direction_input,
0341 .direction_output = lpi_gpio_direction_output,
0342 .get = lpi_gpio_get,
0343 .set = lpi_gpio_set,
0344 .request = gpiochip_generic_request,
0345 .free = gpiochip_generic_free,
0346 .dbg_show = lpi_gpio_dbg_show,
0347 };
0348
0349 static int lpi_build_pin_desc_groups(struct lpi_pinctrl *pctrl)
0350 {
0351 int i, ret;
0352
0353 for (i = 0; i < pctrl->data->npins; i++) {
0354 const struct pinctrl_pin_desc *pin_info = pctrl->desc.pins + i;
0355
0356 ret = pinctrl_generic_add_group(pctrl->ctrl, pin_info->name,
0357 (int *)&pin_info->number, 1, NULL);
0358 if (ret < 0)
0359 goto err_pinctrl;
0360 }
0361
0362 return 0;
0363
0364 err_pinctrl:
0365 for (; i > 0; i--)
0366 pinctrl_generic_remove_group(pctrl->ctrl, i - 1);
0367
0368 return ret;
0369 }
0370
0371 int lpi_pinctrl_probe(struct platform_device *pdev)
0372 {
0373 const struct lpi_pinctrl_variant_data *data;
0374 struct device *dev = &pdev->dev;
0375 struct lpi_pinctrl *pctrl;
0376 int ret;
0377
0378 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
0379 if (!pctrl)
0380 return -ENOMEM;
0381
0382 platform_set_drvdata(pdev, pctrl);
0383
0384 data = of_device_get_match_data(dev);
0385 if (!data)
0386 return -EINVAL;
0387
0388 pctrl->data = data;
0389 pctrl->dev = &pdev->dev;
0390
0391 pctrl->clks[0].id = "core";
0392 pctrl->clks[1].id = "audio";
0393
0394 pctrl->tlmm_base = devm_platform_ioremap_resource(pdev, 0);
0395 if (IS_ERR(pctrl->tlmm_base))
0396 return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base),
0397 "TLMM resource not provided\n");
0398
0399 pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1);
0400 if (IS_ERR(pctrl->slew_base))
0401 return dev_err_probe(dev, PTR_ERR(pctrl->slew_base),
0402 "Slew resource not provided\n");
0403
0404 if (of_property_read_bool(dev->of_node, "qcom,adsp-bypass-mode"))
0405 ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
0406 else
0407 ret = devm_clk_bulk_get(dev, MAX_LPI_NUM_CLKS, pctrl->clks);
0408
0409 if (ret)
0410 return ret;
0411
0412 ret = clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks);
0413 if (ret)
0414 return dev_err_probe(dev, ret, "Can't enable clocks\n");
0415
0416 pctrl->desc.pctlops = &lpi_gpio_pinctrl_ops;
0417 pctrl->desc.pmxops = &lpi_gpio_pinmux_ops;
0418 pctrl->desc.confops = &lpi_gpio_pinconf_ops;
0419 pctrl->desc.owner = THIS_MODULE;
0420 pctrl->desc.name = dev_name(dev);
0421 pctrl->desc.pins = data->pins;
0422 pctrl->desc.npins = data->npins;
0423 pctrl->chip = lpi_gpio_template;
0424 pctrl->chip.parent = dev;
0425 pctrl->chip.base = -1;
0426 pctrl->chip.ngpio = data->npins;
0427 pctrl->chip.label = dev_name(dev);
0428 pctrl->chip.of_gpio_n_cells = 2;
0429 pctrl->chip.can_sleep = false;
0430
0431 mutex_init(&pctrl->slew_access_lock);
0432
0433 pctrl->ctrl = devm_pinctrl_register(dev, &pctrl->desc, pctrl);
0434 if (IS_ERR(pctrl->ctrl)) {
0435 ret = PTR_ERR(pctrl->ctrl);
0436 dev_err(dev, "failed to add pin controller\n");
0437 goto err_pinctrl;
0438 }
0439
0440 ret = lpi_build_pin_desc_groups(pctrl);
0441 if (ret)
0442 goto err_pinctrl;
0443
0444 ret = devm_gpiochip_add_data(dev, &pctrl->chip, pctrl);
0445 if (ret) {
0446 dev_err(pctrl->dev, "can't add gpio chip\n");
0447 goto err_pinctrl;
0448 }
0449
0450 return 0;
0451
0452 err_pinctrl:
0453 mutex_destroy(&pctrl->slew_access_lock);
0454 clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
0455
0456 return ret;
0457 }
0458 EXPORT_SYMBOL_GPL(lpi_pinctrl_probe);
0459
0460 int lpi_pinctrl_remove(struct platform_device *pdev)
0461 {
0462 struct lpi_pinctrl *pctrl = platform_get_drvdata(pdev);
0463 int i;
0464
0465 mutex_destroy(&pctrl->slew_access_lock);
0466 clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks);
0467
0468 for (i = 0; i < pctrl->data->npins; i++)
0469 pinctrl_generic_remove_group(pctrl->ctrl, i);
0470
0471 return 0;
0472 }
0473 EXPORT_SYMBOL_GPL(lpi_pinctrl_remove);
0474
0475 MODULE_DESCRIPTION("QTI LPI GPIO pin control driver");
0476 MODULE_LICENSE("GPL");
