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0006 #include <linux/module.h>
0007 #include <linux/of.h>
0008 #include <linux/platform_device.h>
0009 #include <linux/pinctrl/pinctrl.h>
0010
0011 #include "pinctrl-msm.h"
0012
0013 static const struct pinctrl_pin_desc ipq8064_pins[] = {
0014 PINCTRL_PIN(0, "GPIO_0"),
0015 PINCTRL_PIN(1, "GPIO_1"),
0016 PINCTRL_PIN(2, "GPIO_2"),
0017 PINCTRL_PIN(3, "GPIO_3"),
0018 PINCTRL_PIN(4, "GPIO_4"),
0019 PINCTRL_PIN(5, "GPIO_5"),
0020 PINCTRL_PIN(6, "GPIO_6"),
0021 PINCTRL_PIN(7, "GPIO_7"),
0022 PINCTRL_PIN(8, "GPIO_8"),
0023 PINCTRL_PIN(9, "GPIO_9"),
0024 PINCTRL_PIN(10, "GPIO_10"),
0025 PINCTRL_PIN(11, "GPIO_11"),
0026 PINCTRL_PIN(12, "GPIO_12"),
0027 PINCTRL_PIN(13, "GPIO_13"),
0028 PINCTRL_PIN(14, "GPIO_14"),
0029 PINCTRL_PIN(15, "GPIO_15"),
0030 PINCTRL_PIN(16, "GPIO_16"),
0031 PINCTRL_PIN(17, "GPIO_17"),
0032 PINCTRL_PIN(18, "GPIO_18"),
0033 PINCTRL_PIN(19, "GPIO_19"),
0034 PINCTRL_PIN(20, "GPIO_20"),
0035 PINCTRL_PIN(21, "GPIO_21"),
0036 PINCTRL_PIN(22, "GPIO_22"),
0037 PINCTRL_PIN(23, "GPIO_23"),
0038 PINCTRL_PIN(24, "GPIO_24"),
0039 PINCTRL_PIN(25, "GPIO_25"),
0040 PINCTRL_PIN(26, "GPIO_26"),
0041 PINCTRL_PIN(27, "GPIO_27"),
0042 PINCTRL_PIN(28, "GPIO_28"),
0043 PINCTRL_PIN(29, "GPIO_29"),
0044 PINCTRL_PIN(30, "GPIO_30"),
0045 PINCTRL_PIN(31, "GPIO_31"),
0046 PINCTRL_PIN(32, "GPIO_32"),
0047 PINCTRL_PIN(33, "GPIO_33"),
0048 PINCTRL_PIN(34, "GPIO_34"),
0049 PINCTRL_PIN(35, "GPIO_35"),
0050 PINCTRL_PIN(36, "GPIO_36"),
0051 PINCTRL_PIN(37, "GPIO_37"),
0052 PINCTRL_PIN(38, "GPIO_38"),
0053 PINCTRL_PIN(39, "GPIO_39"),
0054 PINCTRL_PIN(40, "GPIO_40"),
0055 PINCTRL_PIN(41, "GPIO_41"),
0056 PINCTRL_PIN(42, "GPIO_42"),
0057 PINCTRL_PIN(43, "GPIO_43"),
0058 PINCTRL_PIN(44, "GPIO_44"),
0059 PINCTRL_PIN(45, "GPIO_45"),
0060 PINCTRL_PIN(46, "GPIO_46"),
0061 PINCTRL_PIN(47, "GPIO_47"),
0062 PINCTRL_PIN(48, "GPIO_48"),
0063 PINCTRL_PIN(49, "GPIO_49"),
0064 PINCTRL_PIN(50, "GPIO_50"),
0065 PINCTRL_PIN(51, "GPIO_51"),
0066 PINCTRL_PIN(52, "GPIO_52"),
0067 PINCTRL_PIN(53, "GPIO_53"),
0068 PINCTRL_PIN(54, "GPIO_54"),
0069 PINCTRL_PIN(55, "GPIO_55"),
0070 PINCTRL_PIN(56, "GPIO_56"),
0071 PINCTRL_PIN(57, "GPIO_57"),
0072 PINCTRL_PIN(58, "GPIO_58"),
0073 PINCTRL_PIN(59, "GPIO_59"),
0074 PINCTRL_PIN(60, "GPIO_60"),
0075 PINCTRL_PIN(61, "GPIO_61"),
0076 PINCTRL_PIN(62, "GPIO_62"),
0077 PINCTRL_PIN(63, "GPIO_63"),
0078 PINCTRL_PIN(64, "GPIO_64"),
0079 PINCTRL_PIN(65, "GPIO_65"),
0080 PINCTRL_PIN(66, "GPIO_66"),
0081 PINCTRL_PIN(67, "GPIO_67"),
0082 PINCTRL_PIN(68, "GPIO_68"),
0083
0084 PINCTRL_PIN(69, "SDC3_CLK"),
0085 PINCTRL_PIN(70, "SDC3_CMD"),
0086 PINCTRL_PIN(71, "SDC3_DATA"),
0087 };
0088
0089 #define DECLARE_IPQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
0090 DECLARE_IPQ_GPIO_PINS(0);
0091 DECLARE_IPQ_GPIO_PINS(1);
0092 DECLARE_IPQ_GPIO_PINS(2);
0093 DECLARE_IPQ_GPIO_PINS(3);
0094 DECLARE_IPQ_GPIO_PINS(4);
0095 DECLARE_IPQ_GPIO_PINS(5);
0096 DECLARE_IPQ_GPIO_PINS(6);
0097 DECLARE_IPQ_GPIO_PINS(7);
0098 DECLARE_IPQ_GPIO_PINS(8);
0099 DECLARE_IPQ_GPIO_PINS(9);
0100 DECLARE_IPQ_GPIO_PINS(10);
0101 DECLARE_IPQ_GPIO_PINS(11);
0102 DECLARE_IPQ_GPIO_PINS(12);
0103 DECLARE_IPQ_GPIO_PINS(13);
0104 DECLARE_IPQ_GPIO_PINS(14);
0105 DECLARE_IPQ_GPIO_PINS(15);
0106 DECLARE_IPQ_GPIO_PINS(16);
0107 DECLARE_IPQ_GPIO_PINS(17);
0108 DECLARE_IPQ_GPIO_PINS(18);
0109 DECLARE_IPQ_GPIO_PINS(19);
0110 DECLARE_IPQ_GPIO_PINS(20);
0111 DECLARE_IPQ_GPIO_PINS(21);
0112 DECLARE_IPQ_GPIO_PINS(22);
0113 DECLARE_IPQ_GPIO_PINS(23);
0114 DECLARE_IPQ_GPIO_PINS(24);
0115 DECLARE_IPQ_GPIO_PINS(25);
0116 DECLARE_IPQ_GPIO_PINS(26);
0117 DECLARE_IPQ_GPIO_PINS(27);
0118 DECLARE_IPQ_GPIO_PINS(28);
0119 DECLARE_IPQ_GPIO_PINS(29);
0120 DECLARE_IPQ_GPIO_PINS(30);
0121 DECLARE_IPQ_GPIO_PINS(31);
0122 DECLARE_IPQ_GPIO_PINS(32);
0123 DECLARE_IPQ_GPIO_PINS(33);
0124 DECLARE_IPQ_GPIO_PINS(34);
0125 DECLARE_IPQ_GPIO_PINS(35);
0126 DECLARE_IPQ_GPIO_PINS(36);
0127 DECLARE_IPQ_GPIO_PINS(37);
0128 DECLARE_IPQ_GPIO_PINS(38);
0129 DECLARE_IPQ_GPIO_PINS(39);
0130 DECLARE_IPQ_GPIO_PINS(40);
0131 DECLARE_IPQ_GPIO_PINS(41);
0132 DECLARE_IPQ_GPIO_PINS(42);
0133 DECLARE_IPQ_GPIO_PINS(43);
0134 DECLARE_IPQ_GPIO_PINS(44);
0135 DECLARE_IPQ_GPIO_PINS(45);
0136 DECLARE_IPQ_GPIO_PINS(46);
0137 DECLARE_IPQ_GPIO_PINS(47);
0138 DECLARE_IPQ_GPIO_PINS(48);
0139 DECLARE_IPQ_GPIO_PINS(49);
0140 DECLARE_IPQ_GPIO_PINS(50);
0141 DECLARE_IPQ_GPIO_PINS(51);
0142 DECLARE_IPQ_GPIO_PINS(52);
0143 DECLARE_IPQ_GPIO_PINS(53);
0144 DECLARE_IPQ_GPIO_PINS(54);
0145 DECLARE_IPQ_GPIO_PINS(55);
0146 DECLARE_IPQ_GPIO_PINS(56);
0147 DECLARE_IPQ_GPIO_PINS(57);
0148 DECLARE_IPQ_GPIO_PINS(58);
0149 DECLARE_IPQ_GPIO_PINS(59);
0150 DECLARE_IPQ_GPIO_PINS(60);
0151 DECLARE_IPQ_GPIO_PINS(61);
0152 DECLARE_IPQ_GPIO_PINS(62);
0153 DECLARE_IPQ_GPIO_PINS(63);
0154 DECLARE_IPQ_GPIO_PINS(64);
0155 DECLARE_IPQ_GPIO_PINS(65);
0156 DECLARE_IPQ_GPIO_PINS(66);
0157 DECLARE_IPQ_GPIO_PINS(67);
0158 DECLARE_IPQ_GPIO_PINS(68);
0159
0160 static const unsigned int sdc3_clk_pins[] = { 69 };
0161 static const unsigned int sdc3_cmd_pins[] = { 70 };
0162 static const unsigned int sdc3_data_pins[] = { 71 };
0163
0164 #define FUNCTION(fname) \
0165 [IPQ_MUX_##fname] = { \
0166 .name = #fname, \
0167 .groups = fname##_groups, \
0168 .ngroups = ARRAY_SIZE(fname##_groups), \
0169 }
0170
0171 #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
0172 { \
0173 .name = "gpio" #id, \
0174 .pins = gpio##id##_pins, \
0175 .npins = ARRAY_SIZE(gpio##id##_pins), \
0176 .funcs = (int[]){ \
0177 IPQ_MUX_gpio, \
0178 IPQ_MUX_##f1, \
0179 IPQ_MUX_##f2, \
0180 IPQ_MUX_##f3, \
0181 IPQ_MUX_##f4, \
0182 IPQ_MUX_##f5, \
0183 IPQ_MUX_##f6, \
0184 IPQ_MUX_##f7, \
0185 IPQ_MUX_##f8, \
0186 IPQ_MUX_##f9, \
0187 IPQ_MUX_##f10, \
0188 }, \
0189 .nfuncs = 11, \
0190 .ctl_reg = 0x1000 + 0x10 * id, \
0191 .io_reg = 0x1004 + 0x10 * id, \
0192 .intr_cfg_reg = 0x1008 + 0x10 * id, \
0193 .intr_status_reg = 0x100c + 0x10 * id, \
0194 .intr_target_reg = 0x400 + 0x4 * id, \
0195 .mux_bit = 2, \
0196 .pull_bit = 0, \
0197 .drv_bit = 6, \
0198 .oe_bit = 9, \
0199 .in_bit = 0, \
0200 .out_bit = 1, \
0201 .intr_enable_bit = 0, \
0202 .intr_status_bit = 0, \
0203 .intr_ack_high = 1, \
0204 .intr_target_bit = 0, \
0205 .intr_target_kpss_val = 4, \
0206 .intr_raw_status_bit = 3, \
0207 .intr_polarity_bit = 1, \
0208 .intr_detection_bit = 2, \
0209 .intr_detection_width = 1, \
0210 }
0211
0212 #define SDC_PINGROUP(pg_name, ctl, pull, drv) \
0213 { \
0214 .name = #pg_name, \
0215 .pins = pg_name##_pins, \
0216 .npins = ARRAY_SIZE(pg_name##_pins), \
0217 .ctl_reg = ctl, \
0218 .io_reg = 0, \
0219 .intr_cfg_reg = 0, \
0220 .intr_status_reg = 0, \
0221 .intr_target_reg = 0, \
0222 .mux_bit = -1, \
0223 .pull_bit = pull, \
0224 .drv_bit = drv, \
0225 .oe_bit = -1, \
0226 .in_bit = -1, \
0227 .out_bit = -1, \
0228 .intr_enable_bit = -1, \
0229 .intr_status_bit = -1, \
0230 .intr_target_bit = -1, \
0231 .intr_target_kpss_val = -1, \
0232 .intr_raw_status_bit = -1, \
0233 .intr_polarity_bit = -1, \
0234 .intr_detection_bit = -1, \
0235 .intr_detection_width = -1, \
0236 }
0237
0238 enum ipq8064_functions {
0239 IPQ_MUX_gpio,
0240 IPQ_MUX_mdio,
0241 IPQ_MUX_mi2s,
0242 IPQ_MUX_pdm,
0243 IPQ_MUX_ssbi,
0244 IPQ_MUX_spmi,
0245 IPQ_MUX_audio_pcm,
0246 IPQ_MUX_gsbi1,
0247 IPQ_MUX_gsbi2,
0248 IPQ_MUX_gsbi4,
0249 IPQ_MUX_gsbi5,
0250 IPQ_MUX_gsbi5_spi_cs1,
0251 IPQ_MUX_gsbi5_spi_cs2,
0252 IPQ_MUX_gsbi5_spi_cs3,
0253 IPQ_MUX_gsbi6,
0254 IPQ_MUX_gsbi7,
0255 IPQ_MUX_nss_spi,
0256 IPQ_MUX_sdc1,
0257 IPQ_MUX_spdif,
0258 IPQ_MUX_nand,
0259 IPQ_MUX_tsif1,
0260 IPQ_MUX_tsif2,
0261 IPQ_MUX_usb_fs_n,
0262 IPQ_MUX_usb_fs,
0263 IPQ_MUX_usb2_hsic,
0264 IPQ_MUX_rgmii2,
0265 IPQ_MUX_sata,
0266 IPQ_MUX_pcie1_rst,
0267 IPQ_MUX_pcie1_prsnt,
0268 IPQ_MUX_pcie1_pwrflt,
0269 IPQ_MUX_pcie1_pwren_n,
0270 IPQ_MUX_pcie1_pwren,
0271 IPQ_MUX_pcie1_clk_req,
0272 IPQ_MUX_pcie2_rst,
0273 IPQ_MUX_pcie2_prsnt,
0274 IPQ_MUX_pcie2_pwrflt,
0275 IPQ_MUX_pcie2_pwren_n,
0276 IPQ_MUX_pcie2_pwren,
0277 IPQ_MUX_pcie2_clk_req,
0278 IPQ_MUX_pcie3_rst,
0279 IPQ_MUX_pcie3_prsnt,
0280 IPQ_MUX_pcie3_pwrflt,
0281 IPQ_MUX_pcie3_pwren_n,
0282 IPQ_MUX_pcie3_pwren,
0283 IPQ_MUX_pcie3_clk_req,
0284 IPQ_MUX_ps_hold,
0285 IPQ_MUX_NA,
0286 };
0287
0288 static const char * const gpio_groups[] = {
0289 "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
0290 "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
0291 "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
0292 "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
0293 "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
0294 "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
0295 "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
0296 "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
0297 "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
0298 "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"
0299 };
0300
0301 static const char * const mdio_groups[] = {
0302 "gpio0", "gpio1", "gpio2", "gpio10", "gpio11", "gpio66",
0303 };
0304
0305 static const char * const mi2s_groups[] = {
0306 "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
0307 "gpio33", "gpio55", "gpio56", "gpio57", "gpio58",
0308 };
0309
0310 static const char * const pdm_groups[] = {
0311 "gpio3", "gpio16", "gpio17", "gpio22", "gpio30", "gpio31",
0312 "gpio34", "gpio35", "gpio52", "gpio55", "gpio56", "gpio58",
0313 "gpio59",
0314 };
0315
0316 static const char * const ssbi_groups[] = {
0317 "gpio10", "gpio11",
0318 };
0319
0320 static const char * const spmi_groups[] = {
0321 "gpio10", "gpio11",
0322 };
0323
0324 static const char * const audio_pcm_groups[] = {
0325 "gpio14", "gpio15", "gpio16", "gpio17",
0326 };
0327
0328 static const char * const gsbi1_groups[] = {
0329 "gpio51", "gpio52", "gpio53", "gpio54",
0330 };
0331
0332 static const char * const gsbi2_groups[] = {
0333 "gpio22", "gpio23", "gpio24", "gpio25",
0334 };
0335
0336 static const char * const gsbi4_groups[] = {
0337 "gpio10", "gpio11", "gpio12", "gpio13",
0338 };
0339
0340 static const char * const gsbi5_groups[] = {
0341 "gpio18", "gpio19", "gpio20", "gpio21",
0342 };
0343
0344 static const char * const gsbi5_spi_cs1_groups[] = {
0345 "gpio6", "gpio61",
0346 };
0347
0348 static const char * const gsbi5_spi_cs2_groups[] = {
0349 "gpio7", "gpio62",
0350 };
0351
0352 static const char * const gsbi5_spi_cs3_groups[] = {
0353 "gpio2",
0354 };
0355
0356 static const char * const gsbi6_groups[] = {
0357 "gpio27", "gpio28", "gpio29", "gpio30", "gpio55", "gpio56",
0358 "gpio57", "gpio58",
0359 };
0360
0361 static const char * const gsbi7_groups[] = {
0362 "gpio6", "gpio7", "gpio8", "gpio9",
0363 };
0364
0365 static const char * const nss_spi_groups[] = {
0366 "gpio14", "gpio15", "gpio16", "gpio17", "gpio55", "gpio56",
0367 "gpio57", "gpio58",
0368 };
0369
0370 static const char * const sdc1_groups[] = {
0371 "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
0372 "gpio44", "gpio45", "gpio46", "gpio47",
0373 };
0374
0375 static const char * const spdif_groups[] = {
0376 "gpio10", "gpio48",
0377 };
0378
0379 static const char * const nand_groups[] = {
0380 "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39",
0381 "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
0382 "gpio46", "gpio47",
0383 };
0384
0385 static const char * const tsif1_groups[] = {
0386 "gpio55", "gpio56", "gpio57", "gpio58",
0387 };
0388
0389 static const char * const tsif2_groups[] = {
0390 "gpio59", "gpio60", "gpio61", "gpio62",
0391 };
0392
0393 static const char * const usb_fs_n_groups[] = {
0394 "gpio6",
0395 };
0396
0397 static const char * const usb_fs_groups[] = {
0398 "gpio6", "gpio7", "gpio8",
0399 };
0400
0401 static const char * const usb2_hsic_groups[] = {
0402 "gpio67", "gpio68",
0403 };
0404
0405 static const char * const rgmii2_groups[] = {
0406 "gpio2", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
0407 "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", "gpio66",
0408 };
0409
0410 static const char * const sata_groups[] = {
0411 "gpio10",
0412 };
0413
0414 static const char * const pcie1_rst_groups[] = {
0415 "gpio3",
0416 };
0417
0418 static const char * const pcie1_prsnt_groups[] = {
0419 "gpio3", "gpio11",
0420 };
0421
0422 static const char * const pcie1_pwren_n_groups[] = {
0423 "gpio4", "gpio12",
0424 };
0425
0426 static const char * const pcie1_pwren_groups[] = {
0427 "gpio4", "gpio12",
0428 };
0429
0430 static const char * const pcie1_pwrflt_groups[] = {
0431 "gpio5", "gpio13",
0432 };
0433
0434 static const char * const pcie1_clk_req_groups[] = {
0435 "gpio5",
0436 };
0437
0438 static const char * const pcie2_rst_groups[] = {
0439 "gpio48",
0440 };
0441
0442 static const char * const pcie2_prsnt_groups[] = {
0443 "gpio11", "gpio48",
0444 };
0445
0446 static const char * const pcie2_pwren_n_groups[] = {
0447 "gpio12", "gpio49",
0448 };
0449
0450 static const char * const pcie2_pwren_groups[] = {
0451 "gpio12", "gpio49",
0452 };
0453
0454 static const char * const pcie2_pwrflt_groups[] = {
0455 "gpio13", "gpio50",
0456 };
0457
0458 static const char * const pcie2_clk_req_groups[] = {
0459 "gpio50",
0460 };
0461
0462 static const char * const pcie3_rst_groups[] = {
0463 "gpio63",
0464 };
0465
0466 static const char * const pcie3_prsnt_groups[] = {
0467 "gpio11",
0468 };
0469
0470 static const char * const pcie3_pwren_n_groups[] = {
0471 "gpio12",
0472 };
0473
0474 static const char * const pcie3_pwren_groups[] = {
0475 "gpio12",
0476 };
0477
0478 static const char * const pcie3_pwrflt_groups[] = {
0479 "gpio13",
0480 };
0481
0482 static const char * const pcie3_clk_req_groups[] = {
0483 "gpio65",
0484 };
0485
0486 static const char * const ps_hold_groups[] = {
0487 "gpio26",
0488 };
0489
0490 static const struct msm_function ipq8064_functions[] = {
0491 FUNCTION(gpio),
0492 FUNCTION(mdio),
0493 FUNCTION(ssbi),
0494 FUNCTION(spmi),
0495 FUNCTION(mi2s),
0496 FUNCTION(pdm),
0497 FUNCTION(audio_pcm),
0498 FUNCTION(gsbi1),
0499 FUNCTION(gsbi2),
0500 FUNCTION(gsbi4),
0501 FUNCTION(gsbi5),
0502 FUNCTION(gsbi5_spi_cs1),
0503 FUNCTION(gsbi5_spi_cs2),
0504 FUNCTION(gsbi5_spi_cs3),
0505 FUNCTION(gsbi6),
0506 FUNCTION(gsbi7),
0507 FUNCTION(nss_spi),
0508 FUNCTION(sdc1),
0509 FUNCTION(spdif),
0510 FUNCTION(nand),
0511 FUNCTION(tsif1),
0512 FUNCTION(tsif2),
0513 FUNCTION(usb_fs_n),
0514 FUNCTION(usb_fs),
0515 FUNCTION(usb2_hsic),
0516 FUNCTION(rgmii2),
0517 FUNCTION(sata),
0518 FUNCTION(pcie1_rst),
0519 FUNCTION(pcie1_prsnt),
0520 FUNCTION(pcie1_pwren_n),
0521 FUNCTION(pcie1_pwren),
0522 FUNCTION(pcie1_pwrflt),
0523 FUNCTION(pcie1_clk_req),
0524 FUNCTION(pcie2_rst),
0525 FUNCTION(pcie2_prsnt),
0526 FUNCTION(pcie2_pwren_n),
0527 FUNCTION(pcie2_pwren),
0528 FUNCTION(pcie2_pwrflt),
0529 FUNCTION(pcie2_clk_req),
0530 FUNCTION(pcie3_rst),
0531 FUNCTION(pcie3_prsnt),
0532 FUNCTION(pcie3_pwren_n),
0533 FUNCTION(pcie3_pwren),
0534 FUNCTION(pcie3_pwrflt),
0535 FUNCTION(pcie3_clk_req),
0536 FUNCTION(ps_hold),
0537 };
0538
0539 static const struct msm_pingroup ipq8064_groups[] = {
0540 PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0541 PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0542 PINGROUP(2, gsbi5_spi_cs3, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA),
0543 PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA),
0544 PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
0545 PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
0546 PINGROUP(6, gsbi7, usb_fs, gsbi5_spi_cs1, usb_fs_n, NA, NA, NA, NA, NA, NA),
0547 PINGROUP(7, gsbi7, usb_fs, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
0548 PINGROUP(8, gsbi7, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA),
0549 PINGROUP(9, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0550 PINGROUP(10, gsbi4, spdif, sata, ssbi, mdio, spmi, NA, NA, NA, NA),
0551 PINGROUP(11, gsbi4, pcie2_prsnt, pcie1_prsnt, pcie3_prsnt, ssbi, mdio, spmi, NA, NA, NA),
0552 PINGROUP(12, gsbi4, pcie2_pwren_n, pcie1_pwren_n, pcie3_pwren_n, pcie2_pwren, pcie1_pwren, pcie3_pwren, NA, NA, NA),
0553 PINGROUP(13, gsbi4, pcie2_pwrflt, pcie1_pwrflt, pcie3_pwrflt, NA, NA, NA, NA, NA, NA),
0554 PINGROUP(14, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
0555 PINGROUP(15, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
0556 PINGROUP(16, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
0557 PINGROUP(17, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
0558 PINGROUP(18, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0559 PINGROUP(19, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0560 PINGROUP(20, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0561 PINGROUP(21, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0562 PINGROUP(22, gsbi2, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
0563 PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0564 PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0565 PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0566 PINGROUP(26, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0567 PINGROUP(27, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
0568 PINGROUP(28, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
0569 PINGROUP(29, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
0570 PINGROUP(30, mi2s, rgmii2, gsbi6, pdm, NA, NA, NA, NA, NA, NA),
0571 PINGROUP(31, mi2s, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
0572 PINGROUP(32, mi2s, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
0573 PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0574 PINGROUP(34, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
0575 PINGROUP(35, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
0576 PINGROUP(36, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0577 PINGROUP(37, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0578 PINGROUP(38, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
0579 PINGROUP(39, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
0580 PINGROUP(40, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
0581 PINGROUP(41, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
0582 PINGROUP(42, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
0583 PINGROUP(43, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
0584 PINGROUP(44, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
0585 PINGROUP(45, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
0586 PINGROUP(46, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
0587 PINGROUP(47, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
0588 PINGROUP(48, pcie2_rst, spdif, NA, NA, NA, NA, NA, NA, NA, NA),
0589 PINGROUP(49, pcie2_pwren_n, pcie2_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
0590 PINGROUP(50, pcie2_clk_req, pcie2_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
0591 PINGROUP(51, gsbi1, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
0592 PINGROUP(52, gsbi1, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
0593 PINGROUP(53, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0594 PINGROUP(54, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0595 PINGROUP(55, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
0596 PINGROUP(56, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
0597 PINGROUP(57, tsif1, mi2s, gsbi6, nss_spi, NA, NA, NA, NA, NA, NA),
0598 PINGROUP(58, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
0599 PINGROUP(59, tsif2, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
0600 PINGROUP(60, tsif2, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
0601 PINGROUP(61, tsif2, rgmii2, gsbi5_spi_cs1, NA, NA, NA, NA, NA, NA, NA),
0602 PINGROUP(62, tsif2, rgmii2, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
0603 PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0604 PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0605 PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0606 PINGROUP(66, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
0607 PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0608 PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
0609 SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6),
0610 SDC_PINGROUP(sdc3_cmd, 0x204a, 11, 3),
0611 SDC_PINGROUP(sdc3_data, 0x204a, 9, 0),
0612 };
0613
0614 #define NUM_GPIO_PINGROUPS 69
0615
0616 static const struct msm_pinctrl_soc_data ipq8064_pinctrl = {
0617 .pins = ipq8064_pins,
0618 .npins = ARRAY_SIZE(ipq8064_pins),
0619 .functions = ipq8064_functions,
0620 .nfunctions = ARRAY_SIZE(ipq8064_functions),
0621 .groups = ipq8064_groups,
0622 .ngroups = ARRAY_SIZE(ipq8064_groups),
0623 .ngpios = NUM_GPIO_PINGROUPS,
0624 };
0625
0626 static int ipq8064_pinctrl_probe(struct platform_device *pdev)
0627 {
0628 return msm_pinctrl_probe(pdev, &ipq8064_pinctrl);
0629 }
0630
0631 static const struct of_device_id ipq8064_pinctrl_of_match[] = {
0632 { .compatible = "qcom,ipq8064-pinctrl", },
0633 { },
0634 };
0635
0636 static struct platform_driver ipq8064_pinctrl_driver = {
0637 .driver = {
0638 .name = "ipq8064-pinctrl",
0639 .of_match_table = ipq8064_pinctrl_of_match,
0640 },
0641 .probe = ipq8064_pinctrl_probe,
0642 .remove = msm_pinctrl_remove,
0643 };
0644
0645 static int __init ipq8064_pinctrl_init(void)
0646 {
0647 return platform_driver_register(&ipq8064_pinctrl_driver);
0648 }
0649 arch_initcall(ipq8064_pinctrl_init);
0650
0651 static void __exit ipq8064_pinctrl_exit(void)
0652 {
0653 platform_driver_unregister(&ipq8064_pinctrl_driver);
0654 }
0655 module_exit(ipq8064_pinctrl_exit);
0656
0657 MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
0658 MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver");
0659 MODULE_LICENSE("GPL v2");
0660 MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match);
