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0009 #include <linux/io.h>
0010 #include <linux/mfd/syscon.h>
0011 #include <linux/module.h>
0012 #include <linux/init.h>
0013 #include <linux/of.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/pinctrl/pinctrl.h>
0016 #include <linux/pinctrl/pinmux.h>
0017 #include <linux/pinctrl/pinconf.h>
0018 #include <linux/pinctrl/pinconf-generic.h>
0019 #include <linux/regmap.h>
0020 #include "pinctrl-utils.h"
0021 #include "core.h"
0022
0023 #define ZYNQ_NUM_MIOS 54
0024
0025 #define ZYNQ_PCTRL_MIO_MST_TRI0 0x10c
0026 #define ZYNQ_PCTRL_MIO_MST_TRI1 0x110
0027
0028 #define ZYNQ_PINMUX_MUX_SHIFT 1
0029 #define ZYNQ_PINMUX_MUX_MASK (0x7f << ZYNQ_PINMUX_MUX_SHIFT)
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0040
0041 struct zynq_pinctrl {
0042 struct pinctrl_dev *pctrl;
0043 struct regmap *syscon;
0044 u32 pctrl_offset;
0045 const struct zynq_pctrl_group *groups;
0046 unsigned int ngroups;
0047 const struct zynq_pinmux_function *funcs;
0048 unsigned int nfuncs;
0049 };
0050
0051 struct zynq_pctrl_group {
0052 const char *name;
0053 const unsigned int *pins;
0054 const unsigned int npins;
0055 };
0056
0057
0058
0059
0060
0061
0062
0063
0064
0065
0066
0067 struct zynq_pinmux_function {
0068 const char *name;
0069 const char * const *groups;
0070 unsigned int ngroups;
0071 unsigned int mux_val;
0072 u32 mux;
0073 u32 mux_mask;
0074 u8 mux_shift;
0075 };
0076
0077 enum zynq_pinmux_functions {
0078 ZYNQ_PMUX_can0,
0079 ZYNQ_PMUX_can1,
0080 ZYNQ_PMUX_ethernet0,
0081 ZYNQ_PMUX_ethernet1,
0082 ZYNQ_PMUX_gpio0,
0083 ZYNQ_PMUX_i2c0,
0084 ZYNQ_PMUX_i2c1,
0085 ZYNQ_PMUX_mdio0,
0086 ZYNQ_PMUX_mdio1,
0087 ZYNQ_PMUX_qspi0,
0088 ZYNQ_PMUX_qspi1,
0089 ZYNQ_PMUX_qspi_fbclk,
0090 ZYNQ_PMUX_qspi_cs1,
0091 ZYNQ_PMUX_spi0,
0092 ZYNQ_PMUX_spi1,
0093 ZYNQ_PMUX_spi0_ss,
0094 ZYNQ_PMUX_spi1_ss,
0095 ZYNQ_PMUX_sdio0,
0096 ZYNQ_PMUX_sdio0_pc,
0097 ZYNQ_PMUX_sdio0_cd,
0098 ZYNQ_PMUX_sdio0_wp,
0099 ZYNQ_PMUX_sdio1,
0100 ZYNQ_PMUX_sdio1_pc,
0101 ZYNQ_PMUX_sdio1_cd,
0102 ZYNQ_PMUX_sdio1_wp,
0103 ZYNQ_PMUX_smc0_nor,
0104 ZYNQ_PMUX_smc0_nor_cs1,
0105 ZYNQ_PMUX_smc0_nor_addr25,
0106 ZYNQ_PMUX_smc0_nand,
0107 ZYNQ_PMUX_ttc0,
0108 ZYNQ_PMUX_ttc1,
0109 ZYNQ_PMUX_uart0,
0110 ZYNQ_PMUX_uart1,
0111 ZYNQ_PMUX_usb0,
0112 ZYNQ_PMUX_usb1,
0113 ZYNQ_PMUX_swdt0,
0114 ZYNQ_PMUX_MAX_FUNC
0115 };
0116
0117 static const struct pinctrl_pin_desc zynq_pins[] = {
0118 PINCTRL_PIN(0, "MIO0"),
0119 PINCTRL_PIN(1, "MIO1"),
0120 PINCTRL_PIN(2, "MIO2"),
0121 PINCTRL_PIN(3, "MIO3"),
0122 PINCTRL_PIN(4, "MIO4"),
0123 PINCTRL_PIN(5, "MIO5"),
0124 PINCTRL_PIN(6, "MIO6"),
0125 PINCTRL_PIN(7, "MIO7"),
0126 PINCTRL_PIN(8, "MIO8"),
0127 PINCTRL_PIN(9, "MIO9"),
0128 PINCTRL_PIN(10, "MIO10"),
0129 PINCTRL_PIN(11, "MIO11"),
0130 PINCTRL_PIN(12, "MIO12"),
0131 PINCTRL_PIN(13, "MIO13"),
0132 PINCTRL_PIN(14, "MIO14"),
0133 PINCTRL_PIN(15, "MIO15"),
0134 PINCTRL_PIN(16, "MIO16"),
0135 PINCTRL_PIN(17, "MIO17"),
0136 PINCTRL_PIN(18, "MIO18"),
0137 PINCTRL_PIN(19, "MIO19"),
0138 PINCTRL_PIN(20, "MIO20"),
0139 PINCTRL_PIN(21, "MIO21"),
0140 PINCTRL_PIN(22, "MIO22"),
0141 PINCTRL_PIN(23, "MIO23"),
0142 PINCTRL_PIN(24, "MIO24"),
0143 PINCTRL_PIN(25, "MIO25"),
0144 PINCTRL_PIN(26, "MIO26"),
0145 PINCTRL_PIN(27, "MIO27"),
0146 PINCTRL_PIN(28, "MIO28"),
0147 PINCTRL_PIN(29, "MIO29"),
0148 PINCTRL_PIN(30, "MIO30"),
0149 PINCTRL_PIN(31, "MIO31"),
0150 PINCTRL_PIN(32, "MIO32"),
0151 PINCTRL_PIN(33, "MIO33"),
0152 PINCTRL_PIN(34, "MIO34"),
0153 PINCTRL_PIN(35, "MIO35"),
0154 PINCTRL_PIN(36, "MIO36"),
0155 PINCTRL_PIN(37, "MIO37"),
0156 PINCTRL_PIN(38, "MIO38"),
0157 PINCTRL_PIN(39, "MIO39"),
0158 PINCTRL_PIN(40, "MIO40"),
0159 PINCTRL_PIN(41, "MIO41"),
0160 PINCTRL_PIN(42, "MIO42"),
0161 PINCTRL_PIN(43, "MIO43"),
0162 PINCTRL_PIN(44, "MIO44"),
0163 PINCTRL_PIN(45, "MIO45"),
0164 PINCTRL_PIN(46, "MIO46"),
0165 PINCTRL_PIN(47, "MIO47"),
0166 PINCTRL_PIN(48, "MIO48"),
0167 PINCTRL_PIN(49, "MIO49"),
0168 PINCTRL_PIN(50, "MIO50"),
0169 PINCTRL_PIN(51, "MIO51"),
0170 PINCTRL_PIN(52, "MIO52"),
0171 PINCTRL_PIN(53, "MIO53"),
0172 PINCTRL_PIN(54, "EMIO_SD0_WP"),
0173 PINCTRL_PIN(55, "EMIO_SD0_CD"),
0174 PINCTRL_PIN(56, "EMIO_SD1_WP"),
0175 PINCTRL_PIN(57, "EMIO_SD1_CD"),
0176 };
0177
0178
0179 static const unsigned int ethernet0_0_pins[] = {16, 17, 18, 19, 20, 21, 22, 23,
0180 24, 25, 26, 27};
0181 static const unsigned int ethernet1_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35,
0182 36, 37, 38, 39};
0183 static const unsigned int mdio0_0_pins[] = {52, 53};
0184 static const unsigned int mdio1_0_pins[] = {52, 53};
0185 static const unsigned int qspi0_0_pins[] = {1, 2, 3, 4, 5, 6};
0186
0187 static const unsigned int qspi1_0_pins[] = {9, 10, 11, 12, 13};
0188 static const unsigned int qspi_cs1_pins[] = {0};
0189 static const unsigned int qspi_fbclk_pins[] = {8};
0190 static const unsigned int spi0_0_pins[] = {16, 17, 21};
0191 static const unsigned int spi0_0_ss0_pins[] = {18};
0192 static const unsigned int spi0_0_ss1_pins[] = {19};
0193 static const unsigned int spi0_0_ss2_pins[] = {20,};
0194 static const unsigned int spi0_1_pins[] = {28, 29, 33};
0195 static const unsigned int spi0_1_ss0_pins[] = {30};
0196 static const unsigned int spi0_1_ss1_pins[] = {31};
0197 static const unsigned int spi0_1_ss2_pins[] = {32};
0198 static const unsigned int spi0_2_pins[] = {40, 41, 45};
0199 static const unsigned int spi0_2_ss0_pins[] = {42};
0200 static const unsigned int spi0_2_ss1_pins[] = {43};
0201 static const unsigned int spi0_2_ss2_pins[] = {44};
0202 static const unsigned int spi1_0_pins[] = {10, 11, 12};
0203 static const unsigned int spi1_0_ss0_pins[] = {13};
0204 static const unsigned int spi1_0_ss1_pins[] = {14};
0205 static const unsigned int spi1_0_ss2_pins[] = {15};
0206 static const unsigned int spi1_1_pins[] = {22, 23, 24};
0207 static const unsigned int spi1_1_ss0_pins[] = {25};
0208 static const unsigned int spi1_1_ss1_pins[] = {26};
0209 static const unsigned int spi1_1_ss2_pins[] = {27};
0210 static const unsigned int spi1_2_pins[] = {34, 35, 36};
0211 static const unsigned int spi1_2_ss0_pins[] = {37};
0212 static const unsigned int spi1_2_ss1_pins[] = {38};
0213 static const unsigned int spi1_2_ss2_pins[] = {39};
0214 static const unsigned int spi1_3_pins[] = {46, 47, 48, 49};
0215 static const unsigned int spi1_3_ss0_pins[] = {49};
0216 static const unsigned int spi1_3_ss1_pins[] = {50};
0217 static const unsigned int spi1_3_ss2_pins[] = {51};
0218
0219 static const unsigned int sdio0_0_pins[] = {16, 17, 18, 19, 20, 21};
0220 static const unsigned int sdio0_1_pins[] = {28, 29, 30, 31, 32, 33};
0221 static const unsigned int sdio0_2_pins[] = {40, 41, 42, 43, 44, 45};
0222 static const unsigned int sdio1_0_pins[] = {10, 11, 12, 13, 14, 15};
0223 static const unsigned int sdio1_1_pins[] = {22, 23, 24, 25, 26, 27};
0224 static const unsigned int sdio1_2_pins[] = {34, 35, 36, 37, 38, 39};
0225 static const unsigned int sdio1_3_pins[] = {46, 47, 48, 49, 50, 51};
0226 static const unsigned int sdio0_emio_wp_pins[] = {54};
0227 static const unsigned int sdio0_emio_cd_pins[] = {55};
0228 static const unsigned int sdio1_emio_wp_pins[] = {56};
0229 static const unsigned int sdio1_emio_cd_pins[] = {57};
0230 static const unsigned int smc0_nor_pins[] = {0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
0231 15, 16, 17, 18, 19, 20, 21, 22, 23,
0232 24, 25, 26, 27, 28, 29, 30, 31, 32,
0233 33, 34, 35, 36, 37, 38, 39};
0234 static const unsigned int smc0_nor_cs1_pins[] = {1};
0235 static const unsigned int smc0_nor_addr25_pins[] = {1};
0236 static const unsigned int smc0_nand_pins[] = {0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
0237 12, 13, 14, 16, 17, 18, 19, 20,
0238 21, 22, 23};
0239 static const unsigned int smc0_nand8_pins[] = {0, 2, 3, 4, 5, 6, 7,
0240 8, 9, 10, 11, 12, 13, 14};
0241
0242 static const unsigned int can0_0_pins[] = {10, 11};
0243 static const unsigned int can0_1_pins[] = {14, 15};
0244 static const unsigned int can0_2_pins[] = {18, 19};
0245 static const unsigned int can0_3_pins[] = {22, 23};
0246 static const unsigned int can0_4_pins[] = {26, 27};
0247 static const unsigned int can0_5_pins[] = {30, 31};
0248 static const unsigned int can0_6_pins[] = {34, 35};
0249 static const unsigned int can0_7_pins[] = {38, 39};
0250 static const unsigned int can0_8_pins[] = {42, 43};
0251 static const unsigned int can0_9_pins[] = {46, 47};
0252 static const unsigned int can0_10_pins[] = {50, 51};
0253 static const unsigned int can1_0_pins[] = {8, 9};
0254 static const unsigned int can1_1_pins[] = {12, 13};
0255 static const unsigned int can1_2_pins[] = {16, 17};
0256 static const unsigned int can1_3_pins[] = {20, 21};
0257 static const unsigned int can1_4_pins[] = {24, 25};
0258 static const unsigned int can1_5_pins[] = {28, 29};
0259 static const unsigned int can1_6_pins[] = {32, 33};
0260 static const unsigned int can1_7_pins[] = {36, 37};
0261 static const unsigned int can1_8_pins[] = {40, 41};
0262 static const unsigned int can1_9_pins[] = {44, 45};
0263 static const unsigned int can1_10_pins[] = {48, 49};
0264 static const unsigned int can1_11_pins[] = {52, 53};
0265 static const unsigned int uart0_0_pins[] = {10, 11};
0266 static const unsigned int uart0_1_pins[] = {14, 15};
0267 static const unsigned int uart0_2_pins[] = {18, 19};
0268 static const unsigned int uart0_3_pins[] = {22, 23};
0269 static const unsigned int uart0_4_pins[] = {26, 27};
0270 static const unsigned int uart0_5_pins[] = {30, 31};
0271 static const unsigned int uart0_6_pins[] = {34, 35};
0272 static const unsigned int uart0_7_pins[] = {38, 39};
0273 static const unsigned int uart0_8_pins[] = {42, 43};
0274 static const unsigned int uart0_9_pins[] = {46, 47};
0275 static const unsigned int uart0_10_pins[] = {50, 51};
0276 static const unsigned int uart1_0_pins[] = {8, 9};
0277 static const unsigned int uart1_1_pins[] = {12, 13};
0278 static const unsigned int uart1_2_pins[] = {16, 17};
0279 static const unsigned int uart1_3_pins[] = {20, 21};
0280 static const unsigned int uart1_4_pins[] = {24, 25};
0281 static const unsigned int uart1_5_pins[] = {28, 29};
0282 static const unsigned int uart1_6_pins[] = {32, 33};
0283 static const unsigned int uart1_7_pins[] = {36, 37};
0284 static const unsigned int uart1_8_pins[] = {40, 41};
0285 static const unsigned int uart1_9_pins[] = {44, 45};
0286 static const unsigned int uart1_10_pins[] = {48, 49};
0287 static const unsigned int uart1_11_pins[] = {52, 53};
0288 static const unsigned int i2c0_0_pins[] = {10, 11};
0289 static const unsigned int i2c0_1_pins[] = {14, 15};
0290 static const unsigned int i2c0_2_pins[] = {18, 19};
0291 static const unsigned int i2c0_3_pins[] = {22, 23};
0292 static const unsigned int i2c0_4_pins[] = {26, 27};
0293 static const unsigned int i2c0_5_pins[] = {30, 31};
0294 static const unsigned int i2c0_6_pins[] = {34, 35};
0295 static const unsigned int i2c0_7_pins[] = {38, 39};
0296 static const unsigned int i2c0_8_pins[] = {42, 43};
0297 static const unsigned int i2c0_9_pins[] = {46, 47};
0298 static const unsigned int i2c0_10_pins[] = {50, 51};
0299 static const unsigned int i2c1_0_pins[] = {12, 13};
0300 static const unsigned int i2c1_1_pins[] = {16, 17};
0301 static const unsigned int i2c1_2_pins[] = {20, 21};
0302 static const unsigned int i2c1_3_pins[] = {24, 25};
0303 static const unsigned int i2c1_4_pins[] = {28, 29};
0304 static const unsigned int i2c1_5_pins[] = {32, 33};
0305 static const unsigned int i2c1_6_pins[] = {36, 37};
0306 static const unsigned int i2c1_7_pins[] = {40, 41};
0307 static const unsigned int i2c1_8_pins[] = {44, 45};
0308 static const unsigned int i2c1_9_pins[] = {48, 49};
0309 static const unsigned int i2c1_10_pins[] = {52, 53};
0310 static const unsigned int ttc0_0_pins[] = {18, 19};
0311 static const unsigned int ttc0_1_pins[] = {30, 31};
0312 static const unsigned int ttc0_2_pins[] = {42, 43};
0313 static const unsigned int ttc1_0_pins[] = {16, 17};
0314 static const unsigned int ttc1_1_pins[] = {28, 29};
0315 static const unsigned int ttc1_2_pins[] = {40, 41};
0316 static const unsigned int swdt0_0_pins[] = {14, 15};
0317 static const unsigned int swdt0_1_pins[] = {26, 27};
0318 static const unsigned int swdt0_2_pins[] = {38, 39};
0319 static const unsigned int swdt0_3_pins[] = {50, 51};
0320 static const unsigned int swdt0_4_pins[] = {52, 53};
0321 static const unsigned int gpio0_0_pins[] = {0};
0322 static const unsigned int gpio0_1_pins[] = {1};
0323 static const unsigned int gpio0_2_pins[] = {2};
0324 static const unsigned int gpio0_3_pins[] = {3};
0325 static const unsigned int gpio0_4_pins[] = {4};
0326 static const unsigned int gpio0_5_pins[] = {5};
0327 static const unsigned int gpio0_6_pins[] = {6};
0328 static const unsigned int gpio0_7_pins[] = {7};
0329 static const unsigned int gpio0_8_pins[] = {8};
0330 static const unsigned int gpio0_9_pins[] = {9};
0331 static const unsigned int gpio0_10_pins[] = {10};
0332 static const unsigned int gpio0_11_pins[] = {11};
0333 static const unsigned int gpio0_12_pins[] = {12};
0334 static const unsigned int gpio0_13_pins[] = {13};
0335 static const unsigned int gpio0_14_pins[] = {14};
0336 static const unsigned int gpio0_15_pins[] = {15};
0337 static const unsigned int gpio0_16_pins[] = {16};
0338 static const unsigned int gpio0_17_pins[] = {17};
0339 static const unsigned int gpio0_18_pins[] = {18};
0340 static const unsigned int gpio0_19_pins[] = {19};
0341 static const unsigned int gpio0_20_pins[] = {20};
0342 static const unsigned int gpio0_21_pins[] = {21};
0343 static const unsigned int gpio0_22_pins[] = {22};
0344 static const unsigned int gpio0_23_pins[] = {23};
0345 static const unsigned int gpio0_24_pins[] = {24};
0346 static const unsigned int gpio0_25_pins[] = {25};
0347 static const unsigned int gpio0_26_pins[] = {26};
0348 static const unsigned int gpio0_27_pins[] = {27};
0349 static const unsigned int gpio0_28_pins[] = {28};
0350 static const unsigned int gpio0_29_pins[] = {29};
0351 static const unsigned int gpio0_30_pins[] = {30};
0352 static const unsigned int gpio0_31_pins[] = {31};
0353 static const unsigned int gpio0_32_pins[] = {32};
0354 static const unsigned int gpio0_33_pins[] = {33};
0355 static const unsigned int gpio0_34_pins[] = {34};
0356 static const unsigned int gpio0_35_pins[] = {35};
0357 static const unsigned int gpio0_36_pins[] = {36};
0358 static const unsigned int gpio0_37_pins[] = {37};
0359 static const unsigned int gpio0_38_pins[] = {38};
0360 static const unsigned int gpio0_39_pins[] = {39};
0361 static const unsigned int gpio0_40_pins[] = {40};
0362 static const unsigned int gpio0_41_pins[] = {41};
0363 static const unsigned int gpio0_42_pins[] = {42};
0364 static const unsigned int gpio0_43_pins[] = {43};
0365 static const unsigned int gpio0_44_pins[] = {44};
0366 static const unsigned int gpio0_45_pins[] = {45};
0367 static const unsigned int gpio0_46_pins[] = {46};
0368 static const unsigned int gpio0_47_pins[] = {47};
0369 static const unsigned int gpio0_48_pins[] = {48};
0370 static const unsigned int gpio0_49_pins[] = {49};
0371 static const unsigned int gpio0_50_pins[] = {50};
0372 static const unsigned int gpio0_51_pins[] = {51};
0373 static const unsigned int gpio0_52_pins[] = {52};
0374 static const unsigned int gpio0_53_pins[] = {53};
0375 static const unsigned int usb0_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35, 36,
0376 37, 38, 39};
0377 static const unsigned int usb1_0_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48,
0378 49, 50, 51};
0379
0380 #define DEFINE_ZYNQ_PINCTRL_GRP(nm) \
0381 { \
0382 .name = #nm "_grp", \
0383 .pins = nm ## _pins, \
0384 .npins = ARRAY_SIZE(nm ## _pins), \
0385 }
0386
0387 static const struct zynq_pctrl_group zynq_pctrl_groups[] = {
0388 DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
0389 DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
0390 DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
0391 DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
0392 DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
0393 DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
0394 DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
0395 DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
0396 DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
0397 DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss0),
0398 DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss1),
0399 DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss2),
0400 DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
0401 DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss0),
0402 DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss1),
0403 DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss2),
0404 DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
0405 DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss0),
0406 DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss1),
0407 DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss2),
0408 DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
0409 DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss0),
0410 DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss1),
0411 DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss2),
0412 DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
0413 DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss0),
0414 DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss1),
0415 DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss2),
0416 DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
0417 DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss0),
0418 DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss1),
0419 DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss2),
0420 DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
0421 DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss0),
0422 DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss1),
0423 DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss2),
0424 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
0425 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
0426 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
0427 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
0428 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
0429 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
0430 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
0431 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
0432 DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
0433 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
0434 DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
0435 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
0436 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
0437 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
0438 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
0439 DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand8),
0440 DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
0441 DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
0442 DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
0443 DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
0444 DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
0445 DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
0446 DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
0447 DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
0448 DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
0449 DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
0450 DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
0451 DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
0452 DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
0453 DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
0454 DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
0455 DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
0456 DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
0457 DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
0458 DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
0459 DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
0460 DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
0461 DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
0462 DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
0463 DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
0464 DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
0465 DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
0466 DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
0467 DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
0468 DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
0469 DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
0470 DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
0471 DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
0472 DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
0473 DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
0474 DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
0475 DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
0476 DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
0477 DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
0478 DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
0479 DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
0480 DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
0481 DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
0482 DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
0483 DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
0484 DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
0485 DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
0486 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
0487 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
0488 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
0489 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
0490 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4),
0491 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5),
0492 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6),
0493 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7),
0494 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8),
0495 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9),
0496 DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10),
0497 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0),
0498 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1),
0499 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2),
0500 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3),
0501 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4),
0502 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5),
0503 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_6),
0504 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_7),
0505 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_8),
0506 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_9),
0507 DEFINE_ZYNQ_PINCTRL_GRP(i2c1_10),
0508 DEFINE_ZYNQ_PINCTRL_GRP(ttc0_0),
0509 DEFINE_ZYNQ_PINCTRL_GRP(ttc0_1),
0510 DEFINE_ZYNQ_PINCTRL_GRP(ttc0_2),
0511 DEFINE_ZYNQ_PINCTRL_GRP(ttc1_0),
0512 DEFINE_ZYNQ_PINCTRL_GRP(ttc1_1),
0513 DEFINE_ZYNQ_PINCTRL_GRP(ttc1_2),
0514 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_0),
0515 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_1),
0516 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_2),
0517 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_3),
0518 DEFINE_ZYNQ_PINCTRL_GRP(swdt0_4),
0519 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_0),
0520 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_1),
0521 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_2),
0522 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_3),
0523 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_4),
0524 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_5),
0525 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_6),
0526 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_7),
0527 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_8),
0528 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_9),
0529 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_10),
0530 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_11),
0531 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_12),
0532 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_13),
0533 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_14),
0534 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_15),
0535 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_16),
0536 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_17),
0537 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_18),
0538 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_19),
0539 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_20),
0540 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_21),
0541 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_22),
0542 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_23),
0543 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_24),
0544 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_25),
0545 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_26),
0546 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_27),
0547 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_28),
0548 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_29),
0549 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_30),
0550 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_31),
0551 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_32),
0552 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_33),
0553 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_34),
0554 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_35),
0555 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_36),
0556 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_37),
0557 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_38),
0558 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_39),
0559 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_40),
0560 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_41),
0561 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_42),
0562 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_43),
0563 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_44),
0564 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_45),
0565 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_46),
0566 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_47),
0567 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_48),
0568 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_49),
0569 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_50),
0570 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_51),
0571 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_52),
0572 DEFINE_ZYNQ_PINCTRL_GRP(gpio0_53),
0573 DEFINE_ZYNQ_PINCTRL_GRP(usb0_0),
0574 DEFINE_ZYNQ_PINCTRL_GRP(usb1_0),
0575 };
0576
0577
0578 static const char * const ethernet0_groups[] = {"ethernet0_0_grp"};
0579 static const char * const ethernet1_groups[] = {"ethernet1_0_grp"};
0580 static const char * const usb0_groups[] = {"usb0_0_grp"};
0581 static const char * const usb1_groups[] = {"usb1_0_grp"};
0582 static const char * const mdio0_groups[] = {"mdio0_0_grp"};
0583 static const char * const mdio1_groups[] = {"mdio1_0_grp"};
0584 static const char * const qspi0_groups[] = {"qspi0_0_grp"};
0585 static const char * const qspi1_groups[] = {"qspi1_0_grp"};
0586 static const char * const qspi_fbclk_groups[] = {"qspi_fbclk_grp"};
0587 static const char * const qspi_cs1_groups[] = {"qspi_cs1_grp"};
0588 static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp",
0589 "spi0_2_grp"};
0590 static const char * const spi1_groups[] = {"spi1_0_grp", "spi1_1_grp",
0591 "spi1_2_grp", "spi1_3_grp"};
0592 static const char * const spi0_ss_groups[] = {"spi0_0_ss0_grp",
0593 "spi0_0_ss1_grp", "spi0_0_ss2_grp", "spi0_1_ss0_grp",
0594 "spi0_1_ss1_grp", "spi0_1_ss2_grp", "spi0_2_ss0_grp",
0595 "spi0_2_ss1_grp", "spi0_2_ss2_grp"};
0596 static const char * const spi1_ss_groups[] = {"spi1_0_ss0_grp",
0597 "spi1_0_ss1_grp", "spi1_0_ss2_grp", "spi1_1_ss0_grp",
0598 "spi1_1_ss1_grp", "spi1_1_ss2_grp", "spi1_2_ss0_grp",
0599 "spi1_2_ss1_grp", "spi1_2_ss2_grp", "spi1_3_ss0_grp",
0600 "spi1_3_ss1_grp", "spi1_3_ss2_grp"};
0601 static const char * const sdio0_groups[] = {"sdio0_0_grp", "sdio0_1_grp",
0602 "sdio0_2_grp"};
0603 static const char * const sdio1_groups[] = {"sdio1_0_grp", "sdio1_1_grp",
0604 "sdio1_2_grp", "sdio1_3_grp"};
0605 static const char * const sdio0_pc_groups[] = {"gpio0_0_grp",
0606 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
0607 "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp",
0608 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
0609 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
0610 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
0611 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
0612 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
0613 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
0614 "gpio0_50_grp", "gpio0_52_grp"};
0615 static const char * const sdio1_pc_groups[] = {"gpio0_1_grp",
0616 "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp",
0617 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
0618 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
0619 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
0620 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
0621 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
0622 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
0623 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
0624 "gpio0_51_grp", "gpio0_53_grp"};
0625 static const char * const sdio0_cd_groups[] = {"gpio0_0_grp",
0626 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
0627 "gpio0_10_grp", "gpio0_12_grp",
0628 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
0629 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
0630 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
0631 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
0632 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
0633 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
0634 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
0635 "gpio0_3_grp", "gpio0_5_grp",
0636 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
0637 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
0638 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
0639 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
0640 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
0641 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
0642 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
0643 "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_cd_grp"};
0644 static const char * const sdio0_wp_groups[] = {"gpio0_0_grp",
0645 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
0646 "gpio0_10_grp", "gpio0_12_grp",
0647 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
0648 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
0649 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
0650 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
0651 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
0652 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
0653 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
0654 "gpio0_3_grp", "gpio0_5_grp",
0655 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
0656 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
0657 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
0658 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
0659 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
0660 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
0661 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
0662 "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_wp_grp"};
0663 static const char * const sdio1_cd_groups[] = {"gpio0_0_grp",
0664 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
0665 "gpio0_10_grp", "gpio0_12_grp",
0666 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
0667 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
0668 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
0669 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
0670 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
0671 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
0672 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
0673 "gpio0_3_grp", "gpio0_5_grp",
0674 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
0675 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
0676 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
0677 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
0678 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
0679 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
0680 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
0681 "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_cd_grp"};
0682 static const char * const sdio1_wp_groups[] = {"gpio0_0_grp",
0683 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
0684 "gpio0_10_grp", "gpio0_12_grp",
0685 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
0686 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
0687 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
0688 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
0689 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
0690 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
0691 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
0692 "gpio0_3_grp", "gpio0_5_grp",
0693 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
0694 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
0695 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
0696 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
0697 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
0698 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
0699 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
0700 "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_wp_grp"};
0701 static const char * const smc0_nor_groups[] = {"smc0_nor_grp"};
0702 static const char * const smc0_nor_cs1_groups[] = {"smc0_nor_cs1_grp"};
0703 static const char * const smc0_nor_addr25_groups[] = {"smc0_nor_addr25_grp"};
0704 static const char * const smc0_nand_groups[] = {"smc0_nand_grp",
0705 "smc0_nand8_grp"};
0706 static const char * const can0_groups[] = {"can0_0_grp", "can0_1_grp",
0707 "can0_2_grp", "can0_3_grp", "can0_4_grp", "can0_5_grp",
0708 "can0_6_grp", "can0_7_grp", "can0_8_grp", "can0_9_grp",
0709 "can0_10_grp"};
0710 static const char * const can1_groups[] = {"can1_0_grp", "can1_1_grp",
0711 "can1_2_grp", "can1_3_grp", "can1_4_grp", "can1_5_grp",
0712 "can1_6_grp", "can1_7_grp", "can1_8_grp", "can1_9_grp",
0713 "can1_10_grp", "can1_11_grp"};
0714 static const char * const uart0_groups[] = {"uart0_0_grp", "uart0_1_grp",
0715 "uart0_2_grp", "uart0_3_grp", "uart0_4_grp", "uart0_5_grp",
0716 "uart0_6_grp", "uart0_7_grp", "uart0_8_grp", "uart0_9_grp",
0717 "uart0_10_grp"};
0718 static const char * const uart1_groups[] = {"uart1_0_grp", "uart1_1_grp",
0719 "uart1_2_grp", "uart1_3_grp", "uart1_4_grp", "uart1_5_grp",
0720 "uart1_6_grp", "uart1_7_grp", "uart1_8_grp", "uart1_9_grp",
0721 "uart1_10_grp", "uart1_11_grp"};
0722 static const char * const i2c0_groups[] = {"i2c0_0_grp", "i2c0_1_grp",
0723 "i2c0_2_grp", "i2c0_3_grp", "i2c0_4_grp", "i2c0_5_grp",
0724 "i2c0_6_grp", "i2c0_7_grp", "i2c0_8_grp", "i2c0_9_grp",
0725 "i2c0_10_grp"};
0726 static const char * const i2c1_groups[] = {"i2c1_0_grp", "i2c1_1_grp",
0727 "i2c1_2_grp", "i2c1_3_grp", "i2c1_4_grp", "i2c1_5_grp",
0728 "i2c1_6_grp", "i2c1_7_grp", "i2c1_8_grp", "i2c1_9_grp",
0729 "i2c1_10_grp"};
0730 static const char * const ttc0_groups[] = {"ttc0_0_grp", "ttc0_1_grp",
0731 "ttc0_2_grp"};
0732 static const char * const ttc1_groups[] = {"ttc1_0_grp", "ttc1_1_grp",
0733 "ttc1_2_grp"};
0734 static const char * const swdt0_groups[] = {"swdt0_0_grp", "swdt0_1_grp",
0735 "swdt0_2_grp", "swdt0_3_grp", "swdt0_4_grp"};
0736 static const char * const gpio0_groups[] = {"gpio0_0_grp",
0737 "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
0738 "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp",
0739 "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
0740 "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
0741 "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
0742 "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
0743 "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
0744 "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
0745 "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
0746 "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp",
0747 "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
0748 "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
0749 "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
0750 "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
0751 "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
0752 "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
0753 "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
0754 "gpio0_51_grp", "gpio0_53_grp"};
0755
0756 #define DEFINE_ZYNQ_PINMUX_FUNCTION(fname, mval) \
0757 [ZYNQ_PMUX_##fname] = { \
0758 .name = #fname, \
0759 .groups = fname##_groups, \
0760 .ngroups = ARRAY_SIZE(fname##_groups), \
0761 .mux_val = mval, \
0762 }
0763
0764 #define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, offset, mask, shift)\
0765 [ZYNQ_PMUX_##fname] = { \
0766 .name = #fname, \
0767 .groups = fname##_groups, \
0768 .ngroups = ARRAY_SIZE(fname##_groups), \
0769 .mux_val = mval, \
0770 .mux = offset, \
0771 .mux_mask = mask, \
0772 .mux_shift = shift, \
0773 }
0774
0775 #define ZYNQ_SDIO_WP_SHIFT 0
0776 #define ZYNQ_SDIO_WP_MASK (0x3f << ZYNQ_SDIO_WP_SHIFT)
0777 #define ZYNQ_SDIO_CD_SHIFT 16
0778 #define ZYNQ_SDIO_CD_MASK (0x3f << ZYNQ_SDIO_CD_SHIFT)
0779
0780 static const struct zynq_pinmux_function zynq_pmux_functions[] = {
0781 DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet0, 1),
0782 DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet1, 1),
0783 DEFINE_ZYNQ_PINMUX_FUNCTION(usb0, 2),
0784 DEFINE_ZYNQ_PINMUX_FUNCTION(usb1, 2),
0785 DEFINE_ZYNQ_PINMUX_FUNCTION(mdio0, 0x40),
0786 DEFINE_ZYNQ_PINMUX_FUNCTION(mdio1, 0x50),
0787 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi0, 1),
0788 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi1, 1),
0789 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_fbclk, 1),
0790 DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_cs1, 1),
0791 DEFINE_ZYNQ_PINMUX_FUNCTION(spi0, 0x50),
0792 DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50),
0793 DEFINE_ZYNQ_PINMUX_FUNCTION(spi0_ss, 0x50),
0794 DEFINE_ZYNQ_PINMUX_FUNCTION(spi1_ss, 0x50),
0795 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40),
0796 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc),
0797 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 0x130, ZYNQ_SDIO_WP_MASK,
0798 ZYNQ_SDIO_WP_SHIFT),
0799 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 0x130, ZYNQ_SDIO_CD_MASK,
0800 ZYNQ_SDIO_CD_SHIFT),
0801 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1, 0x40),
0802 DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1_pc, 0xc),
0803 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 0x134, ZYNQ_SDIO_WP_MASK,
0804 ZYNQ_SDIO_WP_SHIFT),
0805 DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 0x134, ZYNQ_SDIO_CD_MASK,
0806 ZYNQ_SDIO_CD_SHIFT),
0807 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor, 4),
0808 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_cs1, 8),
0809 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_addr25, 4),
0810 DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nand, 8),
0811 DEFINE_ZYNQ_PINMUX_FUNCTION(can0, 0x10),
0812 DEFINE_ZYNQ_PINMUX_FUNCTION(can1, 0x10),
0813 DEFINE_ZYNQ_PINMUX_FUNCTION(uart0, 0x70),
0814 DEFINE_ZYNQ_PINMUX_FUNCTION(uart1, 0x70),
0815 DEFINE_ZYNQ_PINMUX_FUNCTION(i2c0, 0x20),
0816 DEFINE_ZYNQ_PINMUX_FUNCTION(i2c1, 0x20),
0817 DEFINE_ZYNQ_PINMUX_FUNCTION(ttc0, 0x60),
0818 DEFINE_ZYNQ_PINMUX_FUNCTION(ttc1, 0x60),
0819 DEFINE_ZYNQ_PINMUX_FUNCTION(swdt0, 0x30),
0820 DEFINE_ZYNQ_PINMUX_FUNCTION(gpio0, 0),
0821 };
0822
0823
0824
0825 static int zynq_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
0826 {
0827 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0828
0829 return pctrl->ngroups;
0830 }
0831
0832 static const char *zynq_pctrl_get_group_name(struct pinctrl_dev *pctldev,
0833 unsigned int selector)
0834 {
0835 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0836
0837 return pctrl->groups[selector].name;
0838 }
0839
0840 static int zynq_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
0841 unsigned int selector,
0842 const unsigned int **pins,
0843 unsigned int *num_pins)
0844 {
0845 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0846
0847 *pins = pctrl->groups[selector].pins;
0848 *num_pins = pctrl->groups[selector].npins;
0849
0850 return 0;
0851 }
0852
0853 static const struct pinctrl_ops zynq_pctrl_ops = {
0854 .get_groups_count = zynq_pctrl_get_groups_count,
0855 .get_group_name = zynq_pctrl_get_group_name,
0856 .get_group_pins = zynq_pctrl_get_group_pins,
0857 .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
0858 .dt_free_map = pinctrl_utils_free_map,
0859 };
0860
0861
0862 static int zynq_pmux_get_functions_count(struct pinctrl_dev *pctldev)
0863 {
0864 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0865
0866 return pctrl->nfuncs;
0867 }
0868
0869 static const char *zynq_pmux_get_function_name(struct pinctrl_dev *pctldev,
0870 unsigned int selector)
0871 {
0872 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0873
0874 return pctrl->funcs[selector].name;
0875 }
0876
0877 static int zynq_pmux_get_function_groups(struct pinctrl_dev *pctldev,
0878 unsigned int selector,
0879 const char * const **groups,
0880 unsigned * const num_groups)
0881 {
0882 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0883
0884 *groups = pctrl->funcs[selector].groups;
0885 *num_groups = pctrl->funcs[selector].ngroups;
0886 return 0;
0887 }
0888
0889 static int zynq_pinmux_set_mux(struct pinctrl_dev *pctldev,
0890 unsigned int function,
0891 unsigned int group)
0892 {
0893 int i, ret;
0894 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0895 const struct zynq_pctrl_group *pgrp = &pctrl->groups[group];
0896 const struct zynq_pinmux_function *func = &pctrl->funcs[function];
0897
0898
0899
0900
0901
0902 if (function == ZYNQ_PMUX_sdio0_cd || function == ZYNQ_PMUX_sdio0_wp ||
0903 function == ZYNQ_PMUX_sdio1_cd ||
0904 function == ZYNQ_PMUX_sdio1_wp) {
0905 u32 reg;
0906
0907 ret = regmap_read(pctrl->syscon,
0908 pctrl->pctrl_offset + func->mux, ®);
0909 if (ret)
0910 return ret;
0911
0912 reg &= ~func->mux_mask;
0913 reg |= pgrp->pins[0] << func->mux_shift;
0914 ret = regmap_write(pctrl->syscon,
0915 pctrl->pctrl_offset + func->mux, reg);
0916 if (ret)
0917 return ret;
0918 } else {
0919 for (i = 0; i < pgrp->npins; i++) {
0920 unsigned int pin = pgrp->pins[i];
0921 u32 reg, addr = pctrl->pctrl_offset + (4 * pin);
0922
0923 ret = regmap_read(pctrl->syscon, addr, ®);
0924 if (ret)
0925 return ret;
0926
0927 reg &= ~ZYNQ_PINMUX_MUX_MASK;
0928 reg |= func->mux_val << ZYNQ_PINMUX_MUX_SHIFT;
0929 ret = regmap_write(pctrl->syscon, addr, reg);
0930 if (ret)
0931 return ret;
0932 }
0933 }
0934
0935 return 0;
0936 }
0937
0938 static const struct pinmux_ops zynq_pinmux_ops = {
0939 .get_functions_count = zynq_pmux_get_functions_count,
0940 .get_function_name = zynq_pmux_get_function_name,
0941 .get_function_groups = zynq_pmux_get_function_groups,
0942 .set_mux = zynq_pinmux_set_mux,
0943 };
0944
0945
0946 #define ZYNQ_PINCONF_TRISTATE BIT(0)
0947 #define ZYNQ_PINCONF_SPEED BIT(8)
0948 #define ZYNQ_PINCONF_PULLUP BIT(12)
0949 #define ZYNQ_PINCONF_DISABLE_RECVR BIT(13)
0950
0951 #define ZYNQ_PINCONF_IOTYPE_SHIFT 9
0952 #define ZYNQ_PINCONF_IOTYPE_MASK (7 << ZYNQ_PINCONF_IOTYPE_SHIFT)
0953
0954 enum zynq_io_standards {
0955 zynq_iostd_min,
0956 zynq_iostd_lvcmos18,
0957 zynq_iostd_lvcmos25,
0958 zynq_iostd_lvcmos33,
0959 zynq_iostd_hstl,
0960 zynq_iostd_max
0961 };
0962
0963
0964
0965
0966
0967
0968 #define PIN_CONFIG_IOSTANDARD (PIN_CONFIG_END + 1)
0969
0970 static const struct pinconf_generic_params zynq_dt_params[] = {
0971 {"io-standard", PIN_CONFIG_IOSTANDARD, zynq_iostd_lvcmos18},
0972 };
0973
0974 #ifdef CONFIG_DEBUG_FS
0975 static const struct pin_config_item zynq_conf_items[ARRAY_SIZE(zynq_dt_params)]
0976 = { PCONFDUMP(PIN_CONFIG_IOSTANDARD, "IO-standard", NULL, true),
0977 };
0978 #endif
0979
0980 static unsigned int zynq_pinconf_iostd_get(u32 reg)
0981 {
0982 return (reg & ZYNQ_PINCONF_IOTYPE_MASK) >> ZYNQ_PINCONF_IOTYPE_SHIFT;
0983 }
0984
0985 static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev,
0986 unsigned int pin,
0987 unsigned long *config)
0988 {
0989 u32 reg;
0990 int ret;
0991 unsigned int arg = 0;
0992 unsigned int param = pinconf_to_config_param(*config);
0993 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
0994
0995 if (pin >= ZYNQ_NUM_MIOS)
0996 return -ENOTSUPP;
0997
0998 ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), ®);
0999 if (ret)
1000 return -EIO;
1001
1002 switch (param) {
1003 case PIN_CONFIG_BIAS_PULL_UP:
1004 if (!(reg & ZYNQ_PINCONF_PULLUP))
1005 return -EINVAL;
1006 arg = 1;
1007 break;
1008 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1009 if (!(reg & ZYNQ_PINCONF_TRISTATE))
1010 return -EINVAL;
1011 arg = 1;
1012 break;
1013 case PIN_CONFIG_BIAS_DISABLE:
1014 if (reg & ZYNQ_PINCONF_PULLUP || reg & ZYNQ_PINCONF_TRISTATE)
1015 return -EINVAL;
1016 break;
1017 case PIN_CONFIG_SLEW_RATE:
1018 arg = !!(reg & ZYNQ_PINCONF_SPEED);
1019 break;
1020 case PIN_CONFIG_MODE_LOW_POWER:
1021 {
1022 enum zynq_io_standards iostd = zynq_pinconf_iostd_get(reg);
1023
1024 if (iostd != zynq_iostd_hstl)
1025 return -EINVAL;
1026 if (!(reg & ZYNQ_PINCONF_DISABLE_RECVR))
1027 return -EINVAL;
1028 arg = !!(reg & ZYNQ_PINCONF_DISABLE_RECVR);
1029 break;
1030 }
1031 case PIN_CONFIG_IOSTANDARD:
1032 case PIN_CONFIG_POWER_SOURCE:
1033 arg = zynq_pinconf_iostd_get(reg);
1034 break;
1035 default:
1036 return -ENOTSUPP;
1037 }
1038
1039 *config = pinconf_to_config_packed(param, arg);
1040 return 0;
1041 }
1042
1043 static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev,
1044 unsigned int pin,
1045 unsigned long *configs,
1046 unsigned int num_configs)
1047 {
1048 int i, ret;
1049 u32 reg;
1050 u32 pullup = 0;
1051 u32 tristate = 0;
1052 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1053
1054 if (pin >= ZYNQ_NUM_MIOS)
1055 return -ENOTSUPP;
1056
1057 ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), ®);
1058 if (ret)
1059 return -EIO;
1060
1061 for (i = 0; i < num_configs; i++) {
1062 unsigned int param = pinconf_to_config_param(configs[i]);
1063 unsigned int arg = pinconf_to_config_argument(configs[i]);
1064
1065 switch (param) {
1066 case PIN_CONFIG_BIAS_PULL_UP:
1067 pullup = ZYNQ_PINCONF_PULLUP;
1068 break;
1069 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
1070 tristate = ZYNQ_PINCONF_TRISTATE;
1071 break;
1072 case PIN_CONFIG_BIAS_DISABLE:
1073 reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE);
1074 break;
1075 case PIN_CONFIG_SLEW_RATE:
1076 if (arg)
1077 reg |= ZYNQ_PINCONF_SPEED;
1078 else
1079 reg &= ~ZYNQ_PINCONF_SPEED;
1080
1081 break;
1082 case PIN_CONFIG_IOSTANDARD:
1083 case PIN_CONFIG_POWER_SOURCE:
1084 if (arg <= zynq_iostd_min || arg >= zynq_iostd_max) {
1085 dev_warn(pctldev->dev,
1086 "unsupported IO standard '%u'\n",
1087 param);
1088 break;
1089 }
1090 reg &= ~ZYNQ_PINCONF_IOTYPE_MASK;
1091 reg |= arg << ZYNQ_PINCONF_IOTYPE_SHIFT;
1092 break;
1093 case PIN_CONFIG_MODE_LOW_POWER:
1094 if (arg)
1095 reg |= ZYNQ_PINCONF_DISABLE_RECVR;
1096 else
1097 reg &= ~ZYNQ_PINCONF_DISABLE_RECVR;
1098
1099 break;
1100 default:
1101 dev_warn(pctldev->dev,
1102 "unsupported configuration parameter '%u'\n",
1103 param);
1104 continue;
1105 }
1106 }
1107
1108 if (tristate || pullup) {
1109 reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE);
1110 reg |= tristate | pullup;
1111 }
1112
1113 ret = regmap_write(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), reg);
1114 if (ret)
1115 return -EIO;
1116
1117 return 0;
1118 }
1119
1120 static int zynq_pinconf_group_set(struct pinctrl_dev *pctldev,
1121 unsigned int selector,
1122 unsigned long *configs,
1123 unsigned int num_configs)
1124 {
1125 int i, ret;
1126 struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
1127 const struct zynq_pctrl_group *pgrp = &pctrl->groups[selector];
1128
1129 for (i = 0; i < pgrp->npins; i++) {
1130 ret = zynq_pinconf_cfg_set(pctldev, pgrp->pins[i], configs,
1131 num_configs);
1132 if (ret)
1133 return ret;
1134 }
1135
1136 return 0;
1137 }
1138
1139 static const struct pinconf_ops zynq_pinconf_ops = {
1140 .is_generic = true,
1141 .pin_config_get = zynq_pinconf_cfg_get,
1142 .pin_config_set = zynq_pinconf_cfg_set,
1143 .pin_config_group_set = zynq_pinconf_group_set,
1144 };
1145
1146 static struct pinctrl_desc zynq_desc = {
1147 .name = "zynq_pinctrl",
1148 .pins = zynq_pins,
1149 .npins = ARRAY_SIZE(zynq_pins),
1150 .pctlops = &zynq_pctrl_ops,
1151 .pmxops = &zynq_pinmux_ops,
1152 .confops = &zynq_pinconf_ops,
1153 .num_custom_params = ARRAY_SIZE(zynq_dt_params),
1154 .custom_params = zynq_dt_params,
1155 #ifdef CONFIG_DEBUG_FS
1156 .custom_conf_items = zynq_conf_items,
1157 #endif
1158 .owner = THIS_MODULE,
1159 };
1160
1161 static int zynq_pinctrl_probe(struct platform_device *pdev)
1162
1163 {
1164 struct resource *res;
1165 struct zynq_pinctrl *pctrl;
1166
1167 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1168 if (!pctrl)
1169 return -ENOMEM;
1170
1171 pctrl->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1172 "syscon");
1173 if (IS_ERR(pctrl->syscon)) {
1174 dev_err(&pdev->dev, "unable to get syscon\n");
1175 return PTR_ERR(pctrl->syscon);
1176 }
1177
1178 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1179 if (!res) {
1180 dev_err(&pdev->dev, "missing IO resource\n");
1181 return -ENODEV;
1182 }
1183 pctrl->pctrl_offset = res->start;
1184
1185 pctrl->groups = zynq_pctrl_groups;
1186 pctrl->ngroups = ARRAY_SIZE(zynq_pctrl_groups);
1187 pctrl->funcs = zynq_pmux_functions;
1188 pctrl->nfuncs = ARRAY_SIZE(zynq_pmux_functions);
1189
1190 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &zynq_desc, pctrl);
1191 if (IS_ERR(pctrl->pctrl))
1192 return PTR_ERR(pctrl->pctrl);
1193
1194 platform_set_drvdata(pdev, pctrl);
1195
1196 dev_info(&pdev->dev, "zynq pinctrl initialized\n");
1197
1198 return 0;
1199 }
1200
1201 static const struct of_device_id zynq_pinctrl_of_match[] = {
1202 { .compatible = "xlnx,pinctrl-zynq" },
1203 { }
1204 };
1205
1206 static struct platform_driver zynq_pinctrl_driver = {
1207 .driver = {
1208 .name = "zynq-pinctrl",
1209 .of_match_table = zynq_pinctrl_of_match,
1210 },
1211 .probe = zynq_pinctrl_probe,
1212 };
1213
1214 module_platform_driver(zynq_pinctrl_driver);
