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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Abilis Systems TB10x pin control driver
0004  *
0005  * Copyright (C) Abilis Systems 2012
0006  *
0007  * Author: Christian Ruppert <christian.ruppert@abilis.com>
0008  */
0009 
0010 #include <linux/stringify.h>
0011 #include <linux/pinctrl/pinctrl.h>
0012 #include <linux/pinctrl/pinmux.h>
0013 #include <linux/pinctrl/machine.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/module.h>
0016 #include <linux/mutex.h>
0017 #include <linux/err.h>
0018 #include <linux/io.h>
0019 #include <linux/of.h>
0020 #include <linux/slab.h>
0021 
0022 #include "pinctrl-utils.h"
0023 
0024 #define TB10X_PORT1 (0)
0025 #define TB10X_PORT2 (16)
0026 #define TB10X_PORT3 (32)
0027 #define TB10X_PORT4 (48)
0028 #define TB10X_PORT5 (128)
0029 #define TB10X_PORT6 (64)
0030 #define TB10X_PORT7 (80)
0031 #define TB10X_PORT8 (96)
0032 #define TB10X_PORT9 (112)
0033 #define TB10X_GPIOS (256)
0034 
0035 #define PCFG_PORT_BITWIDTH (2)
0036 #define PCFG_PORT_MASK(PORT) \
0037     (((1 << PCFG_PORT_BITWIDTH) - 1) << (PCFG_PORT_BITWIDTH * (PORT)))
0038 
0039 static const struct pinctrl_pin_desc tb10x_pins[] = {
0040     /* Port 1 */
0041     PINCTRL_PIN(TB10X_PORT1 +  0, "MICLK_S0"),
0042     PINCTRL_PIN(TB10X_PORT1 +  1, "MISTRT_S0"),
0043     PINCTRL_PIN(TB10X_PORT1 +  2, "MIVAL_S0"),
0044     PINCTRL_PIN(TB10X_PORT1 +  3, "MDI_S0"),
0045     PINCTRL_PIN(TB10X_PORT1 +  4, "GPIOA0"),
0046     PINCTRL_PIN(TB10X_PORT1 +  5, "GPIOA1"),
0047     PINCTRL_PIN(TB10X_PORT1 +  6, "GPIOA2"),
0048     PINCTRL_PIN(TB10X_PORT1 +  7, "MDI_S1"),
0049     PINCTRL_PIN(TB10X_PORT1 +  8, "MIVAL_S1"),
0050     PINCTRL_PIN(TB10X_PORT1 +  9, "MISTRT_S1"),
0051     PINCTRL_PIN(TB10X_PORT1 + 10, "MICLK_S1"),
0052     /* Port 2 */
0053     PINCTRL_PIN(TB10X_PORT2 +  0, "MICLK_S2"),
0054     PINCTRL_PIN(TB10X_PORT2 +  1, "MISTRT_S2"),
0055     PINCTRL_PIN(TB10X_PORT2 +  2, "MIVAL_S2"),
0056     PINCTRL_PIN(TB10X_PORT2 +  3, "MDI_S2"),
0057     PINCTRL_PIN(TB10X_PORT2 +  4, "GPIOC0"),
0058     PINCTRL_PIN(TB10X_PORT2 +  5, "GPIOC1"),
0059     PINCTRL_PIN(TB10X_PORT2 +  6, "GPIOC2"),
0060     PINCTRL_PIN(TB10X_PORT2 +  7, "MDI_S3"),
0061     PINCTRL_PIN(TB10X_PORT2 +  8, "MIVAL_S3"),
0062     PINCTRL_PIN(TB10X_PORT2 +  9, "MISTRT_S3"),
0063     PINCTRL_PIN(TB10X_PORT2 + 10, "MICLK_S3"),
0064     /* Port 3 */
0065     PINCTRL_PIN(TB10X_PORT3 +  0, "MICLK_S4"),
0066     PINCTRL_PIN(TB10X_PORT3 +  1, "MISTRT_S4"),
0067     PINCTRL_PIN(TB10X_PORT3 +  2, "MIVAL_S4"),
0068     PINCTRL_PIN(TB10X_PORT3 +  3, "MDI_S4"),
0069     PINCTRL_PIN(TB10X_PORT3 +  4, "GPIOE0"),
0070     PINCTRL_PIN(TB10X_PORT3 +  5, "GPIOE1"),
0071     PINCTRL_PIN(TB10X_PORT3 +  6, "GPIOE2"),
0072     PINCTRL_PIN(TB10X_PORT3 +  7, "MDI_S5"),
0073     PINCTRL_PIN(TB10X_PORT3 +  8, "MIVAL_S5"),
0074     PINCTRL_PIN(TB10X_PORT3 +  9, "MISTRT_S5"),
0075     PINCTRL_PIN(TB10X_PORT3 + 10, "MICLK_S5"),
0076     /* Port 4 */
0077     PINCTRL_PIN(TB10X_PORT4 +  0, "MICLK_S6"),
0078     PINCTRL_PIN(TB10X_PORT4 +  1, "MISTRT_S6"),
0079     PINCTRL_PIN(TB10X_PORT4 +  2, "MIVAL_S6"),
0080     PINCTRL_PIN(TB10X_PORT4 +  3, "MDI_S6"),
0081     PINCTRL_PIN(TB10X_PORT4 +  4, "GPIOG0"),
0082     PINCTRL_PIN(TB10X_PORT4 +  5, "GPIOG1"),
0083     PINCTRL_PIN(TB10X_PORT4 +  6, "GPIOG2"),
0084     PINCTRL_PIN(TB10X_PORT4 +  7, "MDI_S7"),
0085     PINCTRL_PIN(TB10X_PORT4 +  8, "MIVAL_S7"),
0086     PINCTRL_PIN(TB10X_PORT4 +  9, "MISTRT_S7"),
0087     PINCTRL_PIN(TB10X_PORT4 + 10, "MICLK_S7"),
0088     /* Port 5 */
0089     PINCTRL_PIN(TB10X_PORT5 +  0, "PC_CE1N"),
0090     PINCTRL_PIN(TB10X_PORT5 +  1, "PC_CE2N"),
0091     PINCTRL_PIN(TB10X_PORT5 +  2, "PC_REGN"),
0092     PINCTRL_PIN(TB10X_PORT5 +  3, "PC_INPACKN"),
0093     PINCTRL_PIN(TB10X_PORT5 +  4, "PC_OEN"),
0094     PINCTRL_PIN(TB10X_PORT5 +  5, "PC_WEN"),
0095     PINCTRL_PIN(TB10X_PORT5 +  6, "PC_IORDN"),
0096     PINCTRL_PIN(TB10X_PORT5 +  7, "PC_IOWRN"),
0097     PINCTRL_PIN(TB10X_PORT5 +  8, "PC_RDYIRQN"),
0098     PINCTRL_PIN(TB10X_PORT5 +  9, "PC_WAITN"),
0099     PINCTRL_PIN(TB10X_PORT5 + 10, "PC_A0"),
0100     PINCTRL_PIN(TB10X_PORT5 + 11, "PC_A1"),
0101     PINCTRL_PIN(TB10X_PORT5 + 12, "PC_A2"),
0102     PINCTRL_PIN(TB10X_PORT5 + 13, "PC_A3"),
0103     PINCTRL_PIN(TB10X_PORT5 + 14, "PC_A4"),
0104     PINCTRL_PIN(TB10X_PORT5 + 15, "PC_A5"),
0105     PINCTRL_PIN(TB10X_PORT5 + 16, "PC_A6"),
0106     PINCTRL_PIN(TB10X_PORT5 + 17, "PC_A7"),
0107     PINCTRL_PIN(TB10X_PORT5 + 18, "PC_A8"),
0108     PINCTRL_PIN(TB10X_PORT5 + 19, "PC_A9"),
0109     PINCTRL_PIN(TB10X_PORT5 + 20, "PC_A10"),
0110     PINCTRL_PIN(TB10X_PORT5 + 21, "PC_A11"),
0111     PINCTRL_PIN(TB10X_PORT5 + 22, "PC_A12"),
0112     PINCTRL_PIN(TB10X_PORT5 + 23, "PC_A13"),
0113     PINCTRL_PIN(TB10X_PORT5 + 24, "PC_A14"),
0114     PINCTRL_PIN(TB10X_PORT5 + 25, "PC_D0"),
0115     PINCTRL_PIN(TB10X_PORT5 + 26, "PC_D1"),
0116     PINCTRL_PIN(TB10X_PORT5 + 27, "PC_D2"),
0117     PINCTRL_PIN(TB10X_PORT5 + 28, "PC_D3"),
0118     PINCTRL_PIN(TB10X_PORT5 + 29, "PC_D4"),
0119     PINCTRL_PIN(TB10X_PORT5 + 30, "PC_D5"),
0120     PINCTRL_PIN(TB10X_PORT5 + 31, "PC_D6"),
0121     PINCTRL_PIN(TB10X_PORT5 + 32, "PC_D7"),
0122     PINCTRL_PIN(TB10X_PORT5 + 33, "PC_MOSTRT"),
0123     PINCTRL_PIN(TB10X_PORT5 + 34, "PC_MOVAL"),
0124     PINCTRL_PIN(TB10X_PORT5 + 35, "PC_MDO0"),
0125     PINCTRL_PIN(TB10X_PORT5 + 36, "PC_MDO1"),
0126     PINCTRL_PIN(TB10X_PORT5 + 37, "PC_MDO2"),
0127     PINCTRL_PIN(TB10X_PORT5 + 38, "PC_MDO3"),
0128     PINCTRL_PIN(TB10X_PORT5 + 39, "PC_MDO4"),
0129     PINCTRL_PIN(TB10X_PORT5 + 40, "PC_MDO5"),
0130     PINCTRL_PIN(TB10X_PORT5 + 41, "PC_MDO6"),
0131     PINCTRL_PIN(TB10X_PORT5 + 42, "PC_MDO7"),
0132     PINCTRL_PIN(TB10X_PORT5 + 43, "PC_MISTRT"),
0133     PINCTRL_PIN(TB10X_PORT5 + 44, "PC_MIVAL"),
0134     PINCTRL_PIN(TB10X_PORT5 + 45, "PC_MDI0"),
0135     PINCTRL_PIN(TB10X_PORT5 + 46, "PC_MDI1"),
0136     PINCTRL_PIN(TB10X_PORT5 + 47, "PC_MDI2"),
0137     PINCTRL_PIN(TB10X_PORT5 + 48, "PC_MDI3"),
0138     PINCTRL_PIN(TB10X_PORT5 + 49, "PC_MDI4"),
0139     PINCTRL_PIN(TB10X_PORT5 + 50, "PC_MDI5"),
0140     PINCTRL_PIN(TB10X_PORT5 + 51, "PC_MDI6"),
0141     PINCTRL_PIN(TB10X_PORT5 + 52, "PC_MDI7"),
0142     PINCTRL_PIN(TB10X_PORT5 + 53, "PC_MICLK"),
0143     /* Port 6 */
0144     PINCTRL_PIN(TB10X_PORT6 + 0, "T_MOSTRT_S0"),
0145     PINCTRL_PIN(TB10X_PORT6 + 1, "T_MOVAL_S0"),
0146     PINCTRL_PIN(TB10X_PORT6 + 2, "T_MDO_S0"),
0147     PINCTRL_PIN(TB10X_PORT6 + 3, "T_MOSTRT_S1"),
0148     PINCTRL_PIN(TB10X_PORT6 + 4, "T_MOVAL_S1"),
0149     PINCTRL_PIN(TB10X_PORT6 + 5, "T_MDO_S1"),
0150     PINCTRL_PIN(TB10X_PORT6 + 6, "T_MOSTRT_S2"),
0151     PINCTRL_PIN(TB10X_PORT6 + 7, "T_MOVAL_S2"),
0152     PINCTRL_PIN(TB10X_PORT6 + 8, "T_MDO_S2"),
0153     PINCTRL_PIN(TB10X_PORT6 + 9, "T_MOSTRT_S3"),
0154     /* Port 7 */
0155     PINCTRL_PIN(TB10X_PORT7 + 0, "UART0_TXD"),
0156     PINCTRL_PIN(TB10X_PORT7 + 1, "UART0_RXD"),
0157     PINCTRL_PIN(TB10X_PORT7 + 2, "UART0_CTS"),
0158     PINCTRL_PIN(TB10X_PORT7 + 3, "UART0_RTS"),
0159     PINCTRL_PIN(TB10X_PORT7 + 4, "UART1_TXD"),
0160     PINCTRL_PIN(TB10X_PORT7 + 5, "UART1_RXD"),
0161     PINCTRL_PIN(TB10X_PORT7 + 6, "UART1_CTS"),
0162     PINCTRL_PIN(TB10X_PORT7 + 7, "UART1_RTS"),
0163     /* Port 8 */
0164     PINCTRL_PIN(TB10X_PORT8 + 0, "SPI3_CLK"),
0165     PINCTRL_PIN(TB10X_PORT8 + 1, "SPI3_MISO"),
0166     PINCTRL_PIN(TB10X_PORT8 + 2, "SPI3_MOSI"),
0167     PINCTRL_PIN(TB10X_PORT8 + 3, "SPI3_SSN"),
0168     /* Port 9 */
0169     PINCTRL_PIN(TB10X_PORT9 + 0, "SPI1_CLK"),
0170     PINCTRL_PIN(TB10X_PORT9 + 1, "SPI1_MISO"),
0171     PINCTRL_PIN(TB10X_PORT9 + 2, "SPI1_MOSI"),
0172     PINCTRL_PIN(TB10X_PORT9 + 3, "SPI1_SSN0"),
0173     PINCTRL_PIN(TB10X_PORT9 + 4, "SPI1_SSN1"),
0174     /* Unmuxed GPIOs */
0175     PINCTRL_PIN(TB10X_GPIOS +  0, "GPIOB0"),
0176     PINCTRL_PIN(TB10X_GPIOS +  1, "GPIOB1"),
0177 
0178     PINCTRL_PIN(TB10X_GPIOS +  2, "GPIOD0"),
0179     PINCTRL_PIN(TB10X_GPIOS +  3, "GPIOD1"),
0180 
0181     PINCTRL_PIN(TB10X_GPIOS +  4, "GPIOF0"),
0182     PINCTRL_PIN(TB10X_GPIOS +  5, "GPIOF1"),
0183 
0184     PINCTRL_PIN(TB10X_GPIOS +  6, "GPIOH0"),
0185     PINCTRL_PIN(TB10X_GPIOS +  7, "GPIOH1"),
0186 
0187     PINCTRL_PIN(TB10X_GPIOS +  8, "GPIOI0"),
0188     PINCTRL_PIN(TB10X_GPIOS +  9, "GPIOI1"),
0189     PINCTRL_PIN(TB10X_GPIOS + 10, "GPIOI2"),
0190     PINCTRL_PIN(TB10X_GPIOS + 11, "GPIOI3"),
0191     PINCTRL_PIN(TB10X_GPIOS + 12, "GPIOI4"),
0192     PINCTRL_PIN(TB10X_GPIOS + 13, "GPIOI5"),
0193     PINCTRL_PIN(TB10X_GPIOS + 14, "GPIOI6"),
0194     PINCTRL_PIN(TB10X_GPIOS + 15, "GPIOI7"),
0195     PINCTRL_PIN(TB10X_GPIOS + 16, "GPIOI8"),
0196     PINCTRL_PIN(TB10X_GPIOS + 17, "GPIOI9"),
0197     PINCTRL_PIN(TB10X_GPIOS + 18, "GPIOI10"),
0198     PINCTRL_PIN(TB10X_GPIOS + 19, "GPIOI11"),
0199 
0200     PINCTRL_PIN(TB10X_GPIOS + 20, "GPION0"),
0201     PINCTRL_PIN(TB10X_GPIOS + 21, "GPION1"),
0202     PINCTRL_PIN(TB10X_GPIOS + 22, "GPION2"),
0203     PINCTRL_PIN(TB10X_GPIOS + 23, "GPION3"),
0204 #define MAX_PIN (TB10X_GPIOS + 24)
0205     PINCTRL_PIN(MAX_PIN,  "GPION4"),
0206 };
0207 
0208 
0209 /* Port 1 */
0210 static const unsigned mis0_pins[]  = {  TB10X_PORT1 + 0, TB10X_PORT1 + 1,
0211                     TB10X_PORT1 + 2, TB10X_PORT1 + 3};
0212 static const unsigned gpioa_pins[] = {  TB10X_PORT1 + 4, TB10X_PORT1 + 5,
0213                     TB10X_PORT1 + 6};
0214 static const unsigned mis1_pins[]  = {  TB10X_PORT1 + 7, TB10X_PORT1 + 8,
0215                     TB10X_PORT1 + 9, TB10X_PORT1 + 10};
0216 static const unsigned mip1_pins[]  = {  TB10X_PORT1 + 0, TB10X_PORT1 + 1,
0217                     TB10X_PORT1 + 2, TB10X_PORT1 + 3,
0218                     TB10X_PORT1 + 4, TB10X_PORT1 + 5,
0219                     TB10X_PORT1 + 6, TB10X_PORT1 + 7,
0220                     TB10X_PORT1 + 8, TB10X_PORT1 + 9,
0221                     TB10X_PORT1 + 10};
0222 
0223 /* Port 2 */
0224 static const unsigned mis2_pins[]  = {  TB10X_PORT2 + 0, TB10X_PORT2 + 1,
0225                     TB10X_PORT2 + 2, TB10X_PORT2 + 3};
0226 static const unsigned gpioc_pins[] = {  TB10X_PORT2 + 4, TB10X_PORT2 + 5,
0227                     TB10X_PORT2 + 6};
0228 static const unsigned mis3_pins[]  = {  TB10X_PORT2 + 7, TB10X_PORT2 + 8,
0229                     TB10X_PORT2 + 9, TB10X_PORT2 + 10};
0230 static const unsigned mip3_pins[]  = {  TB10X_PORT2 + 0, TB10X_PORT2 + 1,
0231                     TB10X_PORT2 + 2, TB10X_PORT2 + 3,
0232                     TB10X_PORT2 + 4, TB10X_PORT2 + 5,
0233                     TB10X_PORT2 + 6, TB10X_PORT2 + 7,
0234                     TB10X_PORT2 + 8, TB10X_PORT2 + 9,
0235                     TB10X_PORT2 + 10};
0236 
0237 /* Port 3 */
0238 static const unsigned mis4_pins[]  = {  TB10X_PORT3 + 0, TB10X_PORT3 + 1,
0239                     TB10X_PORT3 + 2, TB10X_PORT3 + 3};
0240 static const unsigned gpioe_pins[] = {  TB10X_PORT3 + 4, TB10X_PORT3 + 5,
0241                     TB10X_PORT3 + 6};
0242 static const unsigned mis5_pins[]  = {  TB10X_PORT3 + 7, TB10X_PORT3 + 8,
0243                     TB10X_PORT3 + 9, TB10X_PORT3 + 10};
0244 static const unsigned mip5_pins[]  = {  TB10X_PORT3 + 0, TB10X_PORT3 + 1,
0245                     TB10X_PORT3 + 2, TB10X_PORT3 + 3,
0246                     TB10X_PORT3 + 4, TB10X_PORT3 + 5,
0247                     TB10X_PORT3 + 6, TB10X_PORT3 + 7,
0248                     TB10X_PORT3 + 8, TB10X_PORT3 + 9,
0249                     TB10X_PORT3 + 10};
0250 
0251 /* Port 4 */
0252 static const unsigned mis6_pins[]  = {  TB10X_PORT4 + 0, TB10X_PORT4 + 1,
0253                     TB10X_PORT4 + 2, TB10X_PORT4 + 3};
0254 static const unsigned gpiog_pins[] = {  TB10X_PORT4 + 4, TB10X_PORT4 + 5,
0255                     TB10X_PORT4 + 6};
0256 static const unsigned mis7_pins[]  = {  TB10X_PORT4 + 7, TB10X_PORT4 + 8,
0257                     TB10X_PORT4 + 9, TB10X_PORT4 + 10};
0258 static const unsigned mip7_pins[]  = {  TB10X_PORT4 + 0, TB10X_PORT4 + 1,
0259                     TB10X_PORT4 + 2, TB10X_PORT4 + 3,
0260                     TB10X_PORT4 + 4, TB10X_PORT4 + 5,
0261                     TB10X_PORT4 + 6, TB10X_PORT4 + 7,
0262                     TB10X_PORT4 + 8, TB10X_PORT4 + 9,
0263                     TB10X_PORT4 + 10};
0264 
0265 /* Port 6 */
0266 static const unsigned mop_pins[] = {    TB10X_PORT6 + 0, TB10X_PORT6 + 1,
0267                     TB10X_PORT6 + 2, TB10X_PORT6 + 3,
0268                     TB10X_PORT6 + 4, TB10X_PORT6 + 5,
0269                     TB10X_PORT6 + 6, TB10X_PORT6 + 7,
0270                     TB10X_PORT6 + 8, TB10X_PORT6 + 9};
0271 static const unsigned mos0_pins[] = {   TB10X_PORT6 + 0, TB10X_PORT6 + 1,
0272                     TB10X_PORT6 + 2};
0273 static const unsigned mos1_pins[] = {   TB10X_PORT6 + 3, TB10X_PORT6 + 4,
0274                     TB10X_PORT6 + 5};
0275 static const unsigned mos2_pins[] = {   TB10X_PORT6 + 6, TB10X_PORT6 + 7,
0276                     TB10X_PORT6 + 8};
0277 static const unsigned mos3_pins[] = {   TB10X_PORT6 + 9};
0278 
0279 /* Port 7 */
0280 static const unsigned uart0_pins[] = {  TB10X_PORT7 + 0, TB10X_PORT7 + 1,
0281                     TB10X_PORT7 + 2, TB10X_PORT7 + 3};
0282 static const unsigned uart1_pins[] = {  TB10X_PORT7 + 4, TB10X_PORT7 + 5,
0283                     TB10X_PORT7 + 6, TB10X_PORT7 + 7};
0284 static const unsigned gpiol_pins[] = {  TB10X_PORT7 + 0, TB10X_PORT7 + 1,
0285                     TB10X_PORT7 + 2, TB10X_PORT7 + 3};
0286 static const unsigned gpiom_pins[] = {  TB10X_PORT7 + 4, TB10X_PORT7 + 5,
0287                     TB10X_PORT7 + 6, TB10X_PORT7 + 7};
0288 
0289 /* Port 8 */
0290 static const unsigned spi3_pins[] = {   TB10X_PORT8 + 0, TB10X_PORT8 + 1,
0291                     TB10X_PORT8 + 2, TB10X_PORT8 + 3};
0292 static const unsigned jtag_pins[] = {   TB10X_PORT8 + 0, TB10X_PORT8 + 1,
0293                     TB10X_PORT8 + 2, TB10X_PORT8 + 3};
0294 
0295 /* Port 9 */
0296 static const unsigned spi1_pins[] = {   TB10X_PORT9 + 0, TB10X_PORT9 + 1,
0297                     TB10X_PORT9 + 2, TB10X_PORT9 + 3,
0298                     TB10X_PORT9 + 4};
0299 static const unsigned gpion_pins[] = {  TB10X_PORT9 + 0, TB10X_PORT9 + 1,
0300                     TB10X_PORT9 + 2, TB10X_PORT9 + 3,
0301                     TB10X_PORT9 + 4};
0302 
0303 /* Port 5 */
0304 static const unsigned gpioj_pins[] = {  TB10X_PORT5 + 0, TB10X_PORT5 + 1,
0305                     TB10X_PORT5 + 2, TB10X_PORT5 + 3,
0306                     TB10X_PORT5 + 4, TB10X_PORT5 + 5,
0307                     TB10X_PORT5 + 6, TB10X_PORT5 + 7,
0308                     TB10X_PORT5 + 8, TB10X_PORT5 + 9,
0309                     TB10X_PORT5 + 10, TB10X_PORT5 + 11,
0310                     TB10X_PORT5 + 12, TB10X_PORT5 + 13,
0311                     TB10X_PORT5 + 14, TB10X_PORT5 + 15,
0312                     TB10X_PORT5 + 16, TB10X_PORT5 + 17,
0313                     TB10X_PORT5 + 18, TB10X_PORT5 + 19,
0314                     TB10X_PORT5 + 20, TB10X_PORT5 + 21,
0315                     TB10X_PORT5 + 22, TB10X_PORT5 + 23,
0316                     TB10X_PORT5 + 24, TB10X_PORT5 + 25,
0317                     TB10X_PORT5 + 26, TB10X_PORT5 + 27,
0318                     TB10X_PORT5 + 28, TB10X_PORT5 + 29,
0319                     TB10X_PORT5 + 30, TB10X_PORT5 + 31};
0320 static const unsigned gpiok_pins[] = {  TB10X_PORT5 + 32, TB10X_PORT5 + 33,
0321                     TB10X_PORT5 + 34, TB10X_PORT5 + 35,
0322                     TB10X_PORT5 + 36, TB10X_PORT5 + 37,
0323                     TB10X_PORT5 + 38, TB10X_PORT5 + 39,
0324                     TB10X_PORT5 + 40, TB10X_PORT5 + 41,
0325                     TB10X_PORT5 + 42, TB10X_PORT5 + 43,
0326                     TB10X_PORT5 + 44, TB10X_PORT5 + 45,
0327                     TB10X_PORT5 + 46, TB10X_PORT5 + 47,
0328                     TB10X_PORT5 + 48, TB10X_PORT5 + 49,
0329                     TB10X_PORT5 + 50, TB10X_PORT5 + 51,
0330                     TB10X_PORT5 + 52, TB10X_PORT5 + 53};
0331 static const unsigned ciplus_pins[] = { TB10X_PORT5 + 0, TB10X_PORT5 + 1,
0332                     TB10X_PORT5 + 2, TB10X_PORT5 + 3,
0333                     TB10X_PORT5 + 4, TB10X_PORT5 + 5,
0334                     TB10X_PORT5 + 6, TB10X_PORT5 + 7,
0335                     TB10X_PORT5 + 8, TB10X_PORT5 + 9,
0336                     TB10X_PORT5 + 10, TB10X_PORT5 + 11,
0337                     TB10X_PORT5 + 12, TB10X_PORT5 + 13,
0338                     TB10X_PORT5 + 14, TB10X_PORT5 + 15,
0339                     TB10X_PORT5 + 16, TB10X_PORT5 + 17,
0340                     TB10X_PORT5 + 18, TB10X_PORT5 + 19,
0341                     TB10X_PORT5 + 20, TB10X_PORT5 + 21,
0342                     TB10X_PORT5 + 22, TB10X_PORT5 + 23,
0343                     TB10X_PORT5 + 24, TB10X_PORT5 + 25,
0344                     TB10X_PORT5 + 26, TB10X_PORT5 + 27,
0345                     TB10X_PORT5 + 28, TB10X_PORT5 + 29,
0346                     TB10X_PORT5 + 30, TB10X_PORT5 + 31,
0347                     TB10X_PORT5 + 32, TB10X_PORT5 + 33,
0348                     TB10X_PORT5 + 34, TB10X_PORT5 + 35,
0349                     TB10X_PORT5 + 36, TB10X_PORT5 + 37,
0350                     TB10X_PORT5 + 38, TB10X_PORT5 + 39,
0351                     TB10X_PORT5 + 40, TB10X_PORT5 + 41,
0352                     TB10X_PORT5 + 42, TB10X_PORT5 + 43,
0353                     TB10X_PORT5 + 44, TB10X_PORT5 + 45,
0354                     TB10X_PORT5 + 46, TB10X_PORT5 + 47,
0355                     TB10X_PORT5 + 48, TB10X_PORT5 + 49,
0356                     TB10X_PORT5 + 50, TB10X_PORT5 + 51,
0357                     TB10X_PORT5 + 52, TB10X_PORT5 + 53};
0358 static const unsigned mcard_pins[] = {  TB10X_PORT5 + 3, TB10X_PORT5 + 10,
0359                     TB10X_PORT5 + 11, TB10X_PORT5 + 12,
0360                     TB10X_PORT5 + 22, TB10X_PORT5 + 23,
0361                     TB10X_PORT5 + 33, TB10X_PORT5 + 35,
0362                     TB10X_PORT5 + 36, TB10X_PORT5 + 37,
0363                     TB10X_PORT5 + 38, TB10X_PORT5 + 39,
0364                     TB10X_PORT5 + 40, TB10X_PORT5 + 41,
0365                     TB10X_PORT5 + 42, TB10X_PORT5 + 43,
0366                     TB10X_PORT5 + 45, TB10X_PORT5 + 46,
0367                     TB10X_PORT5 + 47, TB10X_PORT5 + 48,
0368                     TB10X_PORT5 + 49, TB10X_PORT5 + 50,
0369                     TB10X_PORT5 + 51, TB10X_PORT5 + 52,
0370                     TB10X_PORT5 + 53};
0371 static const unsigned stc0_pins[] = {   TB10X_PORT5 + 34, TB10X_PORT5 + 35,
0372                     TB10X_PORT5 + 36, TB10X_PORT5 + 37,
0373                     TB10X_PORT5 + 38, TB10X_PORT5 + 39,
0374                     TB10X_PORT5 + 40};
0375 static const unsigned stc1_pins[] = {   TB10X_PORT5 + 25, TB10X_PORT5 + 26,
0376                     TB10X_PORT5 + 27, TB10X_PORT5 + 28,
0377                     TB10X_PORT5 + 29, TB10X_PORT5 + 30,
0378                     TB10X_PORT5 + 44};
0379 
0380 /* Unmuxed GPIOs */
0381 static const unsigned gpiob_pins[] = {  TB10X_GPIOS + 0, TB10X_GPIOS + 1};
0382 static const unsigned gpiod_pins[] = {  TB10X_GPIOS + 2, TB10X_GPIOS + 3};
0383 static const unsigned gpiof_pins[] = {  TB10X_GPIOS + 4, TB10X_GPIOS + 5};
0384 static const unsigned gpioh_pins[] = {  TB10X_GPIOS + 6, TB10X_GPIOS + 7};
0385 static const unsigned gpioi_pins[] = {  TB10X_GPIOS + 8, TB10X_GPIOS + 9,
0386                     TB10X_GPIOS + 10, TB10X_GPIOS + 11,
0387                     TB10X_GPIOS + 12, TB10X_GPIOS + 13,
0388                     TB10X_GPIOS + 14, TB10X_GPIOS + 15,
0389                     TB10X_GPIOS + 16, TB10X_GPIOS + 17,
0390                     TB10X_GPIOS + 18, TB10X_GPIOS + 19};
0391 
0392 struct tb10x_pinfuncgrp {
0393     const char *name;
0394     const unsigned int *pins;
0395     const unsigned int pincnt;
0396     const int port;
0397     const unsigned int mode;
0398     const int isgpio;
0399 };
0400 #define DEFPINFUNCGRP(NAME, PORT, MODE, ISGPIO) { \
0401         .name = __stringify(NAME), \
0402         .pins = NAME##_pins, .pincnt = ARRAY_SIZE(NAME##_pins), \
0403         .port = (PORT), .mode = (MODE), \
0404         .isgpio = (ISGPIO), \
0405     }
0406 static const struct tb10x_pinfuncgrp tb10x_pingroups[] = {
0407     DEFPINFUNCGRP(mis0,   0, 0, 0),
0408     DEFPINFUNCGRP(gpioa,  0, 0, 1),
0409     DEFPINFUNCGRP(mis1,   0, 0, 0),
0410     DEFPINFUNCGRP(mip1,   0, 1, 0),
0411     DEFPINFUNCGRP(mis2,   1, 0, 0),
0412     DEFPINFUNCGRP(gpioc,  1, 0, 1),
0413     DEFPINFUNCGRP(mis3,   1, 0, 0),
0414     DEFPINFUNCGRP(mip3,   1, 1, 0),
0415     DEFPINFUNCGRP(mis4,   2, 0, 0),
0416     DEFPINFUNCGRP(gpioe,  2, 0, 1),
0417     DEFPINFUNCGRP(mis5,   2, 0, 0),
0418     DEFPINFUNCGRP(mip5,   2, 1, 0),
0419     DEFPINFUNCGRP(mis6,   3, 0, 0),
0420     DEFPINFUNCGRP(gpiog,  3, 0, 1),
0421     DEFPINFUNCGRP(mis7,   3, 0, 0),
0422     DEFPINFUNCGRP(mip7,   3, 1, 0),
0423     DEFPINFUNCGRP(gpioj,  4, 0, 1),
0424     DEFPINFUNCGRP(gpiok,  4, 0, 1),
0425     DEFPINFUNCGRP(ciplus, 4, 1, 0),
0426     DEFPINFUNCGRP(mcard,  4, 2, 0),
0427     DEFPINFUNCGRP(stc0,   4, 3, 0),
0428     DEFPINFUNCGRP(stc1,   4, 3, 0),
0429     DEFPINFUNCGRP(mop,    5, 0, 0),
0430     DEFPINFUNCGRP(mos0,   5, 1, 0),
0431     DEFPINFUNCGRP(mos1,   5, 1, 0),
0432     DEFPINFUNCGRP(mos2,   5, 1, 0),
0433     DEFPINFUNCGRP(mos3,   5, 1, 0),
0434     DEFPINFUNCGRP(uart0,  6, 0, 0),
0435     DEFPINFUNCGRP(uart1,  6, 0, 0),
0436     DEFPINFUNCGRP(gpiol,  6, 1, 1),
0437     DEFPINFUNCGRP(gpiom,  6, 1, 1),
0438     DEFPINFUNCGRP(spi3,   7, 0, 0),
0439     DEFPINFUNCGRP(jtag,   7, 1, 0),
0440     DEFPINFUNCGRP(spi1,   8, 0, 0),
0441     DEFPINFUNCGRP(gpion,  8, 1, 1),
0442     DEFPINFUNCGRP(gpiob, -1, 0, 1),
0443     DEFPINFUNCGRP(gpiod, -1, 0, 1),
0444     DEFPINFUNCGRP(gpiof, -1, 0, 1),
0445     DEFPINFUNCGRP(gpioh, -1, 0, 1),
0446     DEFPINFUNCGRP(gpioi, -1, 0, 1),
0447 };
0448 #undef DEFPINFUNCGRP
0449 
0450 struct tb10x_of_pinfunc {
0451     const char *name;
0452     const char *group;
0453 };
0454 
0455 #define TB10X_PORTS (9)
0456 
0457 /**
0458  * struct tb10x_port - state of an I/O port
0459  * @mode: Node this port is currently in.
0460  * @count: Number of enabled functions which require this port to be
0461  *         configured in @mode.
0462  */
0463 struct tb10x_port {
0464     unsigned int mode;
0465     unsigned int count;
0466 };
0467 
0468 /**
0469  * struct tb10x_pinctrl - TB10x pin controller internal state
0470  * @pctl: pointer to the pinctrl_dev structure of this pin controller.
0471  * @base: register set base address.
0472  * @pingroups: pointer to an array of the pin groups this driver manages.
0473  * @pinfuncgrpcnt: number of pingroups in @pingroups.
0474  * @pinfuncnt: number of pin functions in @pinfuncs.
0475  * @mutex: mutex for exclusive access to a pin controller's state.
0476  * @ports: current state of each port.
0477  * @gpios: Indicates if a given pin is currently used as GPIO (1) or not (0).
0478  * @pinfuncs: flexible array of pin functions this driver manages.
0479  */
0480 struct tb10x_pinctrl {
0481     struct pinctrl_dev *pctl;
0482     void *base;
0483     const struct tb10x_pinfuncgrp *pingroups;
0484     unsigned int pinfuncgrpcnt;
0485     unsigned int pinfuncnt;
0486     struct mutex mutex;
0487     struct tb10x_port ports[TB10X_PORTS];
0488     DECLARE_BITMAP(gpios, MAX_PIN + 1);
0489     struct tb10x_of_pinfunc pinfuncs[];
0490 };
0491 
0492 static inline void tb10x_pinctrl_set_config(struct tb10x_pinctrl *state,
0493                 unsigned int port, unsigned int mode)
0494 {
0495     u32 pcfg;
0496 
0497     if (state->ports[port].count)
0498         return;
0499 
0500     state->ports[port].mode = mode;
0501 
0502     pcfg = ioread32(state->base) & ~(PCFG_PORT_MASK(port));
0503     pcfg |= (mode << (PCFG_PORT_BITWIDTH * port)) & PCFG_PORT_MASK(port);
0504     iowrite32(pcfg, state->base);
0505 }
0506 
0507 static inline unsigned int tb10x_pinctrl_get_config(
0508                 struct tb10x_pinctrl *state,
0509                 unsigned int port)
0510 {
0511     return (ioread32(state->base) & PCFG_PORT_MASK(port))
0512         >> (PCFG_PORT_BITWIDTH * port);
0513 }
0514 
0515 static int tb10x_get_groups_count(struct pinctrl_dev *pctl)
0516 {
0517     struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
0518     return state->pinfuncgrpcnt;
0519 }
0520 
0521 static const char *tb10x_get_group_name(struct pinctrl_dev *pctl, unsigned n)
0522 {
0523     struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
0524     return state->pingroups[n].name;
0525 }
0526 
0527 static int tb10x_get_group_pins(struct pinctrl_dev *pctl, unsigned n,
0528                 unsigned const **pins,
0529                 unsigned * const num_pins)
0530 {
0531     struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
0532 
0533     *pins = state->pingroups[n].pins;
0534     *num_pins = state->pingroups[n].pincnt;
0535 
0536     return 0;
0537 }
0538 
0539 static int tb10x_dt_node_to_map(struct pinctrl_dev *pctl,
0540                 struct device_node *np_config,
0541                 struct pinctrl_map **map, unsigned *num_maps)
0542 {
0543     const char *string;
0544     unsigned reserved_maps = 0;
0545     int ret = 0;
0546 
0547     if (of_property_read_string(np_config, "abilis,function", &string)) {
0548         pr_err("%pOF: No abilis,function property in device tree.\n",
0549             np_config);
0550         return -EINVAL;
0551     }
0552 
0553     *map = NULL;
0554     *num_maps = 0;
0555 
0556     ret = pinctrl_utils_reserve_map(pctl, map, &reserved_maps,
0557                     num_maps, 1);
0558     if (ret)
0559         goto out;
0560 
0561     ret = pinctrl_utils_add_map_mux(pctl, map, &reserved_maps,
0562                     num_maps, string, np_config->name);
0563 
0564 out:
0565     return ret;
0566 }
0567 
0568 static const struct pinctrl_ops tb10x_pinctrl_ops = {
0569     .get_groups_count = tb10x_get_groups_count,
0570     .get_group_name   = tb10x_get_group_name,
0571     .get_group_pins   = tb10x_get_group_pins,
0572     .dt_node_to_map   = tb10x_dt_node_to_map,
0573     .dt_free_map      = pinctrl_utils_free_map,
0574 };
0575 
0576 static int tb10x_get_functions_count(struct pinctrl_dev *pctl)
0577 {
0578     struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
0579     return state->pinfuncnt;
0580 }
0581 
0582 static const char *tb10x_get_function_name(struct pinctrl_dev *pctl,
0583                     unsigned n)
0584 {
0585     struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
0586     return state->pinfuncs[n].name;
0587 }
0588 
0589 static int tb10x_get_function_groups(struct pinctrl_dev *pctl,
0590                 unsigned n, const char * const **groups,
0591                 unsigned * const num_groups)
0592 {
0593     struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
0594 
0595     *groups = &state->pinfuncs[n].group;
0596     *num_groups = 1;
0597 
0598     return 0;
0599 }
0600 
0601 static int tb10x_gpio_request_enable(struct pinctrl_dev *pctl,
0602                     struct pinctrl_gpio_range *range,
0603                     unsigned pin)
0604 {
0605     struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
0606     int muxport = -1;
0607     int muxmode = -1;
0608     int i;
0609 
0610     mutex_lock(&state->mutex);
0611 
0612     /*
0613      * Figure out to which port the requested GPIO belongs and how to
0614      * configure that port.
0615      * This loop also checks for pin conflicts between GPIOs and other
0616      * functions.
0617      */
0618     for (i = 0; i < state->pinfuncgrpcnt; i++) {
0619         const struct tb10x_pinfuncgrp *pfg = &state->pingroups[i];
0620         unsigned int mode = pfg->mode;
0621         int j, port = pfg->port;
0622 
0623         /*
0624          * Skip pin groups which are always mapped and don't need
0625          * to be configured.
0626          */
0627         if (port < 0)
0628             continue;
0629 
0630         for (j = 0; j < pfg->pincnt; j++) {
0631             if (pin == pfg->pins[j]) {
0632                 if (pfg->isgpio) {
0633                     /*
0634                      * Remember the GPIO-only setting of
0635                      * the port this pin belongs to.
0636                      */
0637                     muxport = port;
0638                     muxmode = mode;
0639                 } else if (state->ports[port].count
0640                     && (state->ports[port].mode == mode)) {
0641                     /*
0642                      * Error: The requested pin is already
0643                      * used for something else.
0644                      */
0645                     mutex_unlock(&state->mutex);
0646                     return -EBUSY;
0647                 }
0648                 break;
0649             }
0650         }
0651     }
0652 
0653     /*
0654      * If we haven't returned an error at this point, the GPIO pin is not
0655      * used by another function and the GPIO request can be granted:
0656      * Register pin as being used as GPIO so we don't allocate it to
0657      * another function later.
0658      */
0659     set_bit(pin, state->gpios);
0660 
0661     /*
0662      * Potential conflicts between GPIOs and pin functions were caught
0663      * earlier in this function and tb10x_pinctrl_set_config will do the
0664      * Right Thing, either configure the port in GPIO only mode or leave
0665      * another mode compatible with this GPIO request untouched.
0666      */
0667     if (muxport >= 0)
0668         tb10x_pinctrl_set_config(state, muxport, muxmode);
0669 
0670     mutex_unlock(&state->mutex);
0671 
0672     return 0;
0673 }
0674 
0675 static void tb10x_gpio_disable_free(struct pinctrl_dev *pctl,
0676                     struct pinctrl_gpio_range *range,
0677                     unsigned pin)
0678 {
0679     struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
0680 
0681     mutex_lock(&state->mutex);
0682 
0683     clear_bit(pin, state->gpios);
0684 
0685     mutex_unlock(&state->mutex);
0686 }
0687 
0688 static int tb10x_pctl_set_mux(struct pinctrl_dev *pctl,
0689             unsigned func_selector, unsigned group_selector)
0690 {
0691     struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
0692     const struct tb10x_pinfuncgrp *grp = &state->pingroups[group_selector];
0693     int i;
0694 
0695     if (grp->port < 0)
0696         return 0;
0697 
0698     mutex_lock(&state->mutex);
0699 
0700     /*
0701      * Check if the requested function is compatible with previously
0702      * requested functions.
0703      */
0704     if (state->ports[grp->port].count
0705             && (state->ports[grp->port].mode != grp->mode)) {
0706         mutex_unlock(&state->mutex);
0707         return -EBUSY;
0708     }
0709 
0710     /*
0711      * Check if the requested function is compatible with previously
0712      * requested GPIOs.
0713      */
0714     for (i = 0; i < grp->pincnt; i++)
0715         if (test_bit(grp->pins[i], state->gpios)) {
0716             mutex_unlock(&state->mutex);
0717             return -EBUSY;
0718         }
0719 
0720     tb10x_pinctrl_set_config(state, grp->port, grp->mode);
0721 
0722     state->ports[grp->port].count++;
0723 
0724     mutex_unlock(&state->mutex);
0725 
0726     return 0;
0727 }
0728 
0729 static const struct pinmux_ops tb10x_pinmux_ops = {
0730     .get_functions_count = tb10x_get_functions_count,
0731     .get_function_name = tb10x_get_function_name,
0732     .get_function_groups = tb10x_get_function_groups,
0733     .gpio_request_enable = tb10x_gpio_request_enable,
0734     .gpio_disable_free = tb10x_gpio_disable_free,
0735     .set_mux = tb10x_pctl_set_mux,
0736 };
0737 
0738 static struct pinctrl_desc tb10x_pindesc = {
0739     .name = "TB10x",
0740     .pins = tb10x_pins,
0741     .npins = ARRAY_SIZE(tb10x_pins),
0742     .owner = THIS_MODULE,
0743     .pctlops = &tb10x_pinctrl_ops,
0744     .pmxops  = &tb10x_pinmux_ops,
0745 };
0746 
0747 static int tb10x_pinctrl_probe(struct platform_device *pdev)
0748 {
0749     int ret = -EINVAL;
0750     struct device *dev = &pdev->dev;
0751     struct device_node *of_node = dev->of_node;
0752     struct device_node *child;
0753     struct tb10x_pinctrl *state;
0754     int i;
0755 
0756     if (!of_node) {
0757         dev_err(dev, "No device tree node found.\n");
0758         return -EINVAL;
0759     }
0760 
0761     state = devm_kzalloc(dev, struct_size(state, pinfuncs,
0762                           of_get_child_count(of_node)),
0763                  GFP_KERNEL);
0764     if (!state)
0765         return -ENOMEM;
0766 
0767     platform_set_drvdata(pdev, state);
0768     mutex_init(&state->mutex);
0769 
0770     state->base = devm_platform_ioremap_resource(pdev, 0);
0771     if (IS_ERR(state->base)) {
0772         ret = PTR_ERR(state->base);
0773         goto fail;
0774     }
0775 
0776     state->pingroups = tb10x_pingroups;
0777     state->pinfuncgrpcnt = ARRAY_SIZE(tb10x_pingroups);
0778 
0779     for (i = 0; i < TB10X_PORTS; i++)
0780         state->ports[i].mode = tb10x_pinctrl_get_config(state, i);
0781 
0782     for_each_child_of_node(of_node, child) {
0783         const char *name;
0784 
0785         if (!of_property_read_string(child, "abilis,function",
0786                         &name)) {
0787             state->pinfuncs[state->pinfuncnt].name = child->name;
0788             state->pinfuncs[state->pinfuncnt].group = name;
0789             state->pinfuncnt++;
0790         }
0791     }
0792 
0793     state->pctl = devm_pinctrl_register(dev, &tb10x_pindesc, state);
0794     if (IS_ERR(state->pctl)) {
0795         dev_err(dev, "could not register TB10x pin driver\n");
0796         ret = PTR_ERR(state->pctl);
0797         goto fail;
0798     }
0799 
0800     return 0;
0801 
0802 fail:
0803     mutex_destroy(&state->mutex);
0804     return ret;
0805 }
0806 
0807 static int tb10x_pinctrl_remove(struct platform_device *pdev)
0808 {
0809     struct tb10x_pinctrl *state = platform_get_drvdata(pdev);
0810 
0811     mutex_destroy(&state->mutex);
0812 
0813     return 0;
0814 }
0815 
0816 
0817 static const struct of_device_id tb10x_pinctrl_dt_ids[] = {
0818     { .compatible = "abilis,tb10x-iomux" },
0819     { }
0820 };
0821 MODULE_DEVICE_TABLE(of, tb10x_pinctrl_dt_ids);
0822 
0823 static struct platform_driver tb10x_pinctrl_pdrv = {
0824     .probe   = tb10x_pinctrl_probe,
0825     .remove  = tb10x_pinctrl_remove,
0826     .driver  = {
0827         .name  = "tb10x_pinctrl",
0828         .of_match_table = of_match_ptr(tb10x_pinctrl_dt_ids),
0829     }
0830 };
0831 
0832 module_platform_driver(tb10x_pinctrl_pdrv);
0833 
0834 MODULE_AUTHOR("Christian Ruppert <christian.ruppert@abilis.com>");
0835 MODULE_LICENSE("GPL");
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