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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2016, BayLibre, SAS. All rights reserved.
0004  * Author: Neil Armstrong <narmstrong@baylibre.com>
0005  *
0006  * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
0007  *
0008  * Driver for Semtech SX150X I2C GPIO Expanders
0009  * The handling of the 4-bit chips (SX1501/SX1504/SX1507) is untested.
0010  *
0011  * Author: Gregory Bean <gbean@codeaurora.org>
0012  */
0013 
0014 #include <linux/regmap.h>
0015 #include <linux/i2c.h>
0016 #include <linux/init.h>
0017 #include <linux/interrupt.h>
0018 #include <linux/irq.h>
0019 #include <linux/mutex.h>
0020 #include <linux/slab.h>
0021 #include <linux/of.h>
0022 #include <linux/of_device.h>
0023 #include <linux/gpio/driver.h>
0024 #include <linux/pinctrl/pinconf.h>
0025 #include <linux/pinctrl/pinctrl.h>
0026 #include <linux/pinctrl/pinmux.h>
0027 #include <linux/pinctrl/pinconf-generic.h>
0028 
0029 #include "core.h"
0030 #include "pinconf.h"
0031 #include "pinctrl-utils.h"
0032 
0033 /* The chip models of sx150x */
0034 enum {
0035     SX150X_123 = 0,
0036     SX150X_456,
0037     SX150X_789,
0038 };
0039 enum {
0040     SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0,
0041     SX150X_MAX_REGISTER = 0xad,
0042     SX150X_IRQ_TYPE_EDGE_RISING = 0x1,
0043     SX150X_IRQ_TYPE_EDGE_FALLING = 0x2,
0044     SX150X_789_RESET_KEY1 = 0x12,
0045     SX150X_789_RESET_KEY2 = 0x34,
0046 };
0047 
0048 struct sx150x_123_pri {
0049     u8 reg_pld_mode;
0050     u8 reg_pld_table0;
0051     u8 reg_pld_table1;
0052     u8 reg_pld_table2;
0053     u8 reg_pld_table3;
0054     u8 reg_pld_table4;
0055     u8 reg_advanced;
0056 };
0057 
0058 struct sx150x_456_pri {
0059     u8 reg_pld_mode;
0060     u8 reg_pld_table0;
0061     u8 reg_pld_table1;
0062     u8 reg_pld_table2;
0063     u8 reg_pld_table3;
0064     u8 reg_pld_table4;
0065     u8 reg_advanced;
0066 };
0067 
0068 struct sx150x_789_pri {
0069     u8 reg_drain;
0070     u8 reg_polarity;
0071     u8 reg_clock;
0072     u8 reg_misc;
0073     u8 reg_reset;
0074     u8 ngpios;
0075 };
0076 
0077 struct sx150x_device_data {
0078     u8 model;
0079     u8 reg_pullup;
0080     u8 reg_pulldn;
0081     u8 reg_dir;
0082     u8 reg_data;
0083     u8 reg_irq_mask;
0084     u8 reg_irq_src;
0085     u8 reg_sense;
0086     u8 ngpios;
0087     union {
0088         struct sx150x_123_pri x123;
0089         struct sx150x_456_pri x456;
0090         struct sx150x_789_pri x789;
0091     } pri;
0092     const struct pinctrl_pin_desc *pins;
0093     unsigned int npins;
0094 };
0095 
0096 struct sx150x_pinctrl {
0097     struct device *dev;
0098     struct i2c_client *client;
0099     struct pinctrl_dev *pctldev;
0100     struct pinctrl_desc pinctrl_desc;
0101     struct gpio_chip gpio;
0102     struct irq_chip irq_chip;
0103     struct regmap *regmap;
0104     struct {
0105         u32 sense;
0106         u32 masked;
0107     } irq;
0108     struct mutex lock;
0109     const struct sx150x_device_data *data;
0110 };
0111 
0112 static const struct pinctrl_pin_desc sx150x_4_pins[] = {
0113     PINCTRL_PIN(0, "gpio0"),
0114     PINCTRL_PIN(1, "gpio1"),
0115     PINCTRL_PIN(2, "gpio2"),
0116     PINCTRL_PIN(3, "gpio3"),
0117     PINCTRL_PIN(4, "oscio"),
0118 };
0119 
0120 static const struct pinctrl_pin_desc sx150x_8_pins[] = {
0121     PINCTRL_PIN(0, "gpio0"),
0122     PINCTRL_PIN(1, "gpio1"),
0123     PINCTRL_PIN(2, "gpio2"),
0124     PINCTRL_PIN(3, "gpio3"),
0125     PINCTRL_PIN(4, "gpio4"),
0126     PINCTRL_PIN(5, "gpio5"),
0127     PINCTRL_PIN(6, "gpio6"),
0128     PINCTRL_PIN(7, "gpio7"),
0129     PINCTRL_PIN(8, "oscio"),
0130 };
0131 
0132 static const struct pinctrl_pin_desc sx150x_16_pins[] = {
0133     PINCTRL_PIN(0, "gpio0"),
0134     PINCTRL_PIN(1, "gpio1"),
0135     PINCTRL_PIN(2, "gpio2"),
0136     PINCTRL_PIN(3, "gpio3"),
0137     PINCTRL_PIN(4, "gpio4"),
0138     PINCTRL_PIN(5, "gpio5"),
0139     PINCTRL_PIN(6, "gpio6"),
0140     PINCTRL_PIN(7, "gpio7"),
0141     PINCTRL_PIN(8, "gpio8"),
0142     PINCTRL_PIN(9, "gpio9"),
0143     PINCTRL_PIN(10, "gpio10"),
0144     PINCTRL_PIN(11, "gpio11"),
0145     PINCTRL_PIN(12, "gpio12"),
0146     PINCTRL_PIN(13, "gpio13"),
0147     PINCTRL_PIN(14, "gpio14"),
0148     PINCTRL_PIN(15, "gpio15"),
0149     PINCTRL_PIN(16, "oscio"),
0150 };
0151 
0152 static const struct sx150x_device_data sx1501q_device_data = {
0153     .model = SX150X_123,
0154     .reg_pullup = 0x02,
0155     .reg_pulldn = 0x03,
0156     .reg_dir    = 0x01,
0157     .reg_data   = 0x00,
0158     .reg_irq_mask   = 0x05,
0159     .reg_irq_src    = 0x08,
0160     .reg_sense  = 0x07,
0161     .pri.x123 = {
0162         .reg_pld_mode   = 0x10,
0163         .reg_pld_table0 = 0x11,
0164         .reg_pld_table2 = 0x13,
0165         .reg_advanced   = 0xad,
0166     },
0167     .ngpios = 4,
0168     .pins = sx150x_4_pins,
0169     .npins = 4, /* oscio not available */
0170 };
0171 
0172 static const struct sx150x_device_data sx1502q_device_data = {
0173     .model = SX150X_123,
0174     .reg_pullup = 0x02,
0175     .reg_pulldn = 0x03,
0176     .reg_dir    = 0x01,
0177     .reg_data   = 0x00,
0178     .reg_irq_mask   = 0x05,
0179     .reg_irq_src    = 0x08,
0180     .reg_sense  = 0x06,
0181     .pri.x123 = {
0182         .reg_pld_mode   = 0x10,
0183         .reg_pld_table0 = 0x11,
0184         .reg_pld_table1 = 0x12,
0185         .reg_pld_table2 = 0x13,
0186         .reg_pld_table3 = 0x14,
0187         .reg_pld_table4 = 0x15,
0188         .reg_advanced   = 0xad,
0189     },
0190     .ngpios = 8,
0191     .pins = sx150x_8_pins,
0192     .npins = 8, /* oscio not available */
0193 };
0194 
0195 static const struct sx150x_device_data sx1503q_device_data = {
0196     .model = SX150X_123,
0197     .reg_pullup = 0x04,
0198     .reg_pulldn = 0x06,
0199     .reg_dir    = 0x02,
0200     .reg_data   = 0x00,
0201     .reg_irq_mask   = 0x08,
0202     .reg_irq_src    = 0x0e,
0203     .reg_sense  = 0x0a,
0204     .pri.x123 = {
0205         .reg_pld_mode   = 0x20,
0206         .reg_pld_table0 = 0x22,
0207         .reg_pld_table1 = 0x24,
0208         .reg_pld_table2 = 0x26,
0209         .reg_pld_table3 = 0x28,
0210         .reg_pld_table4 = 0x2a,
0211         .reg_advanced   = 0xad,
0212     },
0213     .ngpios = 16,
0214     .pins = sx150x_16_pins,
0215     .npins  = 16, /* oscio not available */
0216 };
0217 
0218 static const struct sx150x_device_data sx1504q_device_data = {
0219     .model = SX150X_456,
0220     .reg_pullup = 0x02,
0221     .reg_pulldn = 0x03,
0222     .reg_dir    = 0x01,
0223     .reg_data   = 0x00,
0224     .reg_irq_mask   = 0x05,
0225     .reg_irq_src    = 0x08,
0226     .reg_sense  = 0x07,
0227     .pri.x456 = {
0228         .reg_pld_mode   = 0x10,
0229         .reg_pld_table0 = 0x11,
0230         .reg_pld_table2 = 0x13,
0231     },
0232     .ngpios = 4,
0233     .pins = sx150x_4_pins,
0234     .npins = 4, /* oscio not available */
0235 };
0236 
0237 static const struct sx150x_device_data sx1505q_device_data = {
0238     .model = SX150X_456,
0239     .reg_pullup = 0x02,
0240     .reg_pulldn = 0x03,
0241     .reg_dir    = 0x01,
0242     .reg_data   = 0x00,
0243     .reg_irq_mask   = 0x05,
0244     .reg_irq_src    = 0x08,
0245     .reg_sense  = 0x06,
0246     .pri.x456 = {
0247         .reg_pld_mode   = 0x10,
0248         .reg_pld_table0 = 0x11,
0249         .reg_pld_table1 = 0x12,
0250         .reg_pld_table2 = 0x13,
0251         .reg_pld_table3 = 0x14,
0252         .reg_pld_table4 = 0x15,
0253     },
0254     .ngpios = 8,
0255     .pins = sx150x_8_pins,
0256     .npins = 8, /* oscio not available */
0257 };
0258 
0259 static const struct sx150x_device_data sx1506q_device_data = {
0260     .model = SX150X_456,
0261     .reg_pullup = 0x04,
0262     .reg_pulldn = 0x06,
0263     .reg_dir    = 0x02,
0264     .reg_data   = 0x00,
0265     .reg_irq_mask   = 0x08,
0266     .reg_irq_src    = 0x0e,
0267     .reg_sense  = 0x0a,
0268     .pri.x456 = {
0269         .reg_pld_mode   = 0x20,
0270         .reg_pld_table0 = 0x22,
0271         .reg_pld_table1 = 0x24,
0272         .reg_pld_table2 = 0x26,
0273         .reg_pld_table3 = 0x28,
0274         .reg_pld_table4 = 0x2a,
0275         .reg_advanced   = 0xad,
0276     },
0277     .ngpios = 16,
0278     .pins = sx150x_16_pins,
0279     .npins = 16, /* oscio not available */
0280 };
0281 
0282 static const struct sx150x_device_data sx1507q_device_data = {
0283     .model = SX150X_789,
0284     .reg_pullup = 0x03,
0285     .reg_pulldn = 0x04,
0286     .reg_dir    = 0x07,
0287     .reg_data   = 0x08,
0288     .reg_irq_mask   = 0x09,
0289     .reg_irq_src    = 0x0b,
0290     .reg_sense  = 0x0a,
0291     .pri.x789 = {
0292         .reg_drain  = 0x05,
0293         .reg_polarity   = 0x06,
0294         .reg_clock  = 0x0d,
0295         .reg_misc   = 0x0e,
0296         .reg_reset  = 0x7d,
0297     },
0298     .ngpios = 4,
0299     .pins = sx150x_4_pins,
0300     .npins = ARRAY_SIZE(sx150x_4_pins),
0301 };
0302 
0303 static const struct sx150x_device_data sx1508q_device_data = {
0304     .model = SX150X_789,
0305     .reg_pullup = 0x03,
0306     .reg_pulldn = 0x04,
0307     .reg_dir    = 0x07,
0308     .reg_data   = 0x08,
0309     .reg_irq_mask   = 0x09,
0310     .reg_irq_src    = 0x0c,
0311     .reg_sense  = 0x0a,
0312     .pri.x789 = {
0313         .reg_drain  = 0x05,
0314         .reg_polarity   = 0x06,
0315         .reg_clock  = 0x0f,
0316         .reg_misc   = 0x10,
0317         .reg_reset  = 0x7d,
0318     },
0319     .ngpios = 8,
0320     .pins = sx150x_8_pins,
0321     .npins = ARRAY_SIZE(sx150x_8_pins),
0322 };
0323 
0324 static const struct sx150x_device_data sx1509q_device_data = {
0325     .model = SX150X_789,
0326     .reg_pullup = 0x06,
0327     .reg_pulldn = 0x08,
0328     .reg_dir    = 0x0e,
0329     .reg_data   = 0x10,
0330     .reg_irq_mask   = 0x12,
0331     .reg_irq_src    = 0x18,
0332     .reg_sense  = 0x14,
0333     .pri.x789 = {
0334         .reg_drain  = 0x0a,
0335         .reg_polarity   = 0x0c,
0336         .reg_clock  = 0x1e,
0337         .reg_misc   = 0x1f,
0338         .reg_reset  = 0x7d,
0339     },
0340     .ngpios = 16,
0341     .pins = sx150x_16_pins,
0342     .npins = ARRAY_SIZE(sx150x_16_pins),
0343 };
0344 
0345 static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
0346 {
0347     return 0;
0348 }
0349 
0350 static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
0351                         unsigned int group)
0352 {
0353     return NULL;
0354 }
0355 
0356 static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
0357                     unsigned int group,
0358                     const unsigned int **pins,
0359                     unsigned int *num_pins)
0360 {
0361     return -ENOTSUPP;
0362 }
0363 
0364 static const struct pinctrl_ops sx150x_pinctrl_ops = {
0365     .get_groups_count = sx150x_pinctrl_get_groups_count,
0366     .get_group_name = sx150x_pinctrl_get_group_name,
0367     .get_group_pins = sx150x_pinctrl_get_group_pins,
0368 #ifdef CONFIG_OF
0369     .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
0370     .dt_free_map = pinctrl_utils_free_map,
0371 #endif
0372 };
0373 
0374 static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin)
0375 {
0376     if (pin >= pctl->data->npins)
0377         return false;
0378 
0379     /* OSCIO pin is only present in 789 devices */
0380     if (pctl->data->model != SX150X_789)
0381         return false;
0382 
0383     return !strcmp(pctl->data->pins[pin].name, "oscio");
0384 }
0385 
0386 static int sx150x_gpio_get_direction(struct gpio_chip *chip,
0387                       unsigned int offset)
0388 {
0389     struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
0390     unsigned int value;
0391     int ret;
0392 
0393     if (sx150x_pin_is_oscio(pctl, offset))
0394         return GPIO_LINE_DIRECTION_OUT;
0395 
0396     ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value);
0397     if (ret < 0)
0398         return ret;
0399 
0400     if (value & BIT(offset))
0401         return GPIO_LINE_DIRECTION_IN;
0402 
0403     return GPIO_LINE_DIRECTION_OUT;
0404 }
0405 
0406 static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset)
0407 {
0408     struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
0409     unsigned int value;
0410     int ret;
0411 
0412     if (sx150x_pin_is_oscio(pctl, offset))
0413         return -EINVAL;
0414 
0415     ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value);
0416     if (ret < 0)
0417         return ret;
0418 
0419     return !!(value & BIT(offset));
0420 }
0421 
0422 static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset,
0423                  int value)
0424 {
0425     return regmap_write_bits(pctl->regmap, pctl->data->reg_data,
0426                  BIT(offset), value ? BIT(offset) : 0);
0427 }
0428 
0429 static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl,
0430                  int value)
0431 {
0432     return regmap_write(pctl->regmap,
0433                 pctl->data->pri.x789.reg_clock,
0434                 (value ? 0x1f : 0x10));
0435 }
0436 
0437 static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset,
0438                 int value)
0439 {
0440     struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
0441 
0442     if (sx150x_pin_is_oscio(pctl, offset))
0443         sx150x_gpio_oscio_set(pctl, value);
0444     else
0445         __sx150x_gpio_set(pctl, offset, value);
0446 }
0447 
0448 static void sx150x_gpio_set_multiple(struct gpio_chip *chip,
0449                      unsigned long *mask,
0450                      unsigned long *bits)
0451 {
0452     struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
0453 
0454     regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask, *bits);
0455 }
0456 
0457 static int sx150x_gpio_direction_input(struct gpio_chip *chip,
0458                        unsigned int offset)
0459 {
0460     struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
0461 
0462     if (sx150x_pin_is_oscio(pctl, offset))
0463         return -EINVAL;
0464 
0465     return regmap_write_bits(pctl->regmap,
0466                  pctl->data->reg_dir,
0467                  BIT(offset), BIT(offset));
0468 }
0469 
0470 static int sx150x_gpio_direction_output(struct gpio_chip *chip,
0471                     unsigned int offset, int value)
0472 {
0473     struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
0474     int ret;
0475 
0476     if (sx150x_pin_is_oscio(pctl, offset))
0477         return sx150x_gpio_oscio_set(pctl, value);
0478 
0479     ret = __sx150x_gpio_set(pctl, offset, value);
0480     if (ret < 0)
0481         return ret;
0482 
0483     return regmap_write_bits(pctl->regmap,
0484                  pctl->data->reg_dir,
0485                  BIT(offset), 0);
0486 }
0487 
0488 static void sx150x_irq_mask(struct irq_data *d)
0489 {
0490     struct sx150x_pinctrl *pctl =
0491             gpiochip_get_data(irq_data_get_irq_chip_data(d));
0492     unsigned int n = d->hwirq;
0493 
0494     pctl->irq.masked |= BIT(n);
0495 }
0496 
0497 static void sx150x_irq_unmask(struct irq_data *d)
0498 {
0499     struct sx150x_pinctrl *pctl =
0500             gpiochip_get_data(irq_data_get_irq_chip_data(d));
0501     unsigned int n = d->hwirq;
0502 
0503     pctl->irq.masked &= ~BIT(n);
0504 }
0505 
0506 static void sx150x_irq_set_sense(struct sx150x_pinctrl *pctl,
0507                  unsigned int line, unsigned int sense)
0508 {
0509     /*
0510      * Every interrupt line is represented by two bits shifted
0511      * proportionally to the line number
0512      */
0513     const unsigned int n = line * 2;
0514     const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING |
0515                      SX150X_IRQ_TYPE_EDGE_FALLING) << n);
0516 
0517     pctl->irq.sense &= mask;
0518     pctl->irq.sense |= sense << n;
0519 }
0520 
0521 static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
0522 {
0523     struct sx150x_pinctrl *pctl =
0524             gpiochip_get_data(irq_data_get_irq_chip_data(d));
0525     unsigned int n, val = 0;
0526 
0527     if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
0528         return -EINVAL;
0529 
0530     n = d->hwirq;
0531 
0532     if (flow_type & IRQ_TYPE_EDGE_RISING)
0533         val |= SX150X_IRQ_TYPE_EDGE_RISING;
0534     if (flow_type & IRQ_TYPE_EDGE_FALLING)
0535         val |= SX150X_IRQ_TYPE_EDGE_FALLING;
0536 
0537     sx150x_irq_set_sense(pctl, n, val);
0538     return 0;
0539 }
0540 
0541 static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
0542 {
0543     struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id;
0544     unsigned long n, status;
0545     unsigned int val;
0546     int err;
0547 
0548     err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val);
0549     if (err < 0)
0550         return IRQ_NONE;
0551 
0552     err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val);
0553     if (err < 0)
0554         return IRQ_NONE;
0555 
0556     status = val;
0557     for_each_set_bit(n, &status, pctl->data->ngpios)
0558         handle_nested_irq(irq_find_mapping(pctl->gpio.irq.domain, n));
0559 
0560     return IRQ_HANDLED;
0561 }
0562 
0563 static void sx150x_irq_bus_lock(struct irq_data *d)
0564 {
0565     struct sx150x_pinctrl *pctl =
0566             gpiochip_get_data(irq_data_get_irq_chip_data(d));
0567 
0568     mutex_lock(&pctl->lock);
0569 }
0570 
0571 static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
0572 {
0573     struct sx150x_pinctrl *pctl =
0574             gpiochip_get_data(irq_data_get_irq_chip_data(d));
0575 
0576     regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked);
0577     regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense);
0578     mutex_unlock(&pctl->lock);
0579 }
0580 
0581 static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
0582                   unsigned long *config)
0583 {
0584     struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0585     unsigned int param = pinconf_to_config_param(*config);
0586     int ret;
0587     u32 arg;
0588     unsigned int data;
0589 
0590     if (sx150x_pin_is_oscio(pctl, pin)) {
0591         switch (param) {
0592         case PIN_CONFIG_DRIVE_PUSH_PULL:
0593         case PIN_CONFIG_OUTPUT:
0594             ret = regmap_read(pctl->regmap,
0595                       pctl->data->pri.x789.reg_clock,
0596                       &data);
0597             if (ret < 0)
0598                 return ret;
0599 
0600             if (param == PIN_CONFIG_DRIVE_PUSH_PULL)
0601                 arg = (data & 0x1f) ? 1 : 0;
0602             else {
0603                 if ((data & 0x1f) == 0x1f)
0604                     arg = 1;
0605                 else if ((data & 0x1f) == 0x10)
0606                     arg = 0;
0607                 else
0608                     return -EINVAL;
0609             }
0610 
0611             break;
0612         default:
0613             return -ENOTSUPP;
0614         }
0615 
0616         goto out;
0617     }
0618 
0619     switch (param) {
0620     case PIN_CONFIG_BIAS_PULL_DOWN:
0621         ret = regmap_read(pctl->regmap,
0622                   pctl->data->reg_pulldn,
0623                   &data);
0624         data &= BIT(pin);
0625 
0626         if (ret < 0)
0627             return ret;
0628 
0629         if (!ret)
0630             return -EINVAL;
0631 
0632         arg = 1;
0633         break;
0634 
0635     case PIN_CONFIG_BIAS_PULL_UP:
0636         ret = regmap_read(pctl->regmap,
0637                   pctl->data->reg_pullup,
0638                   &data);
0639         data &= BIT(pin);
0640 
0641         if (ret < 0)
0642             return ret;
0643 
0644         if (!ret)
0645             return -EINVAL;
0646 
0647         arg = 1;
0648         break;
0649 
0650     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0651         if (pctl->data->model != SX150X_789)
0652             return -ENOTSUPP;
0653 
0654         ret = regmap_read(pctl->regmap,
0655                   pctl->data->pri.x789.reg_drain,
0656                   &data);
0657         data &= BIT(pin);
0658 
0659         if (ret < 0)
0660             return ret;
0661 
0662         if (!data)
0663             return -EINVAL;
0664 
0665         arg = 1;
0666         break;
0667 
0668     case PIN_CONFIG_DRIVE_PUSH_PULL:
0669         if (pctl->data->model != SX150X_789)
0670             arg = true;
0671         else {
0672             ret = regmap_read(pctl->regmap,
0673                       pctl->data->pri.x789.reg_drain,
0674                       &data);
0675             data &= BIT(pin);
0676 
0677             if (ret < 0)
0678                 return ret;
0679 
0680             if (data)
0681                 return -EINVAL;
0682 
0683             arg = 1;
0684         }
0685         break;
0686 
0687     case PIN_CONFIG_OUTPUT:
0688         ret = sx150x_gpio_get_direction(&pctl->gpio, pin);
0689         if (ret < 0)
0690             return ret;
0691 
0692         if (ret == GPIO_LINE_DIRECTION_IN)
0693             return -EINVAL;
0694 
0695         ret = sx150x_gpio_get(&pctl->gpio, pin);
0696         if (ret < 0)
0697             return ret;
0698 
0699         arg = ret;
0700         break;
0701 
0702     default:
0703         return -ENOTSUPP;
0704     }
0705 
0706 out:
0707     *config = pinconf_to_config_packed(param, arg);
0708 
0709     return 0;
0710 }
0711 
0712 static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
0713                   unsigned long *configs, unsigned int num_configs)
0714 {
0715     struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0716     enum pin_config_param param;
0717     u32 arg;
0718     int i;
0719     int ret;
0720 
0721     for (i = 0; i < num_configs; i++) {
0722         param = pinconf_to_config_param(configs[i]);
0723         arg = pinconf_to_config_argument(configs[i]);
0724 
0725         if (sx150x_pin_is_oscio(pctl, pin)) {
0726             if (param == PIN_CONFIG_OUTPUT) {
0727                 ret = sx150x_gpio_direction_output(&pctl->gpio,
0728                                    pin, arg);
0729                 if (ret < 0)
0730                     return ret;
0731 
0732                 continue;
0733             } else
0734                 return -ENOTSUPP;
0735         }
0736 
0737         switch (param) {
0738         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
0739         case PIN_CONFIG_BIAS_DISABLE:
0740             ret = regmap_write_bits(pctl->regmap,
0741                         pctl->data->reg_pulldn,
0742                         BIT(pin), 0);
0743             if (ret < 0)
0744                 return ret;
0745 
0746             ret = regmap_write_bits(pctl->regmap,
0747                         pctl->data->reg_pullup,
0748                         BIT(pin), 0);
0749             if (ret < 0)
0750                 return ret;
0751 
0752             break;
0753 
0754         case PIN_CONFIG_BIAS_PULL_UP:
0755             ret = regmap_write_bits(pctl->regmap,
0756                         pctl->data->reg_pullup,
0757                         BIT(pin), BIT(pin));
0758             if (ret < 0)
0759                 return ret;
0760 
0761             break;
0762 
0763         case PIN_CONFIG_BIAS_PULL_DOWN:
0764             ret = regmap_write_bits(pctl->regmap,
0765                         pctl->data->reg_pulldn,
0766                         BIT(pin), BIT(pin));
0767             if (ret < 0)
0768                 return ret;
0769 
0770             break;
0771 
0772         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0773             if (pctl->data->model != SX150X_789 ||
0774                 sx150x_pin_is_oscio(pctl, pin))
0775                 return -ENOTSUPP;
0776 
0777             ret = regmap_write_bits(pctl->regmap,
0778                         pctl->data->pri.x789.reg_drain,
0779                         BIT(pin), BIT(pin));
0780             if (ret < 0)
0781                 return ret;
0782 
0783             break;
0784 
0785         case PIN_CONFIG_DRIVE_PUSH_PULL:
0786             if (pctl->data->model != SX150X_789 ||
0787                 sx150x_pin_is_oscio(pctl, pin))
0788                 return 0;
0789 
0790             ret = regmap_write_bits(pctl->regmap,
0791                         pctl->data->pri.x789.reg_drain,
0792                         BIT(pin), 0);
0793             if (ret < 0)
0794                 return ret;
0795 
0796             break;
0797 
0798         case PIN_CONFIG_OUTPUT:
0799             ret = sx150x_gpio_direction_output(&pctl->gpio,
0800                                pin, arg);
0801             if (ret < 0)
0802                 return ret;
0803 
0804             break;
0805 
0806         default:
0807             return -ENOTSUPP;
0808         }
0809     } /* for each config */
0810 
0811     return 0;
0812 }
0813 
0814 static const struct pinconf_ops sx150x_pinconf_ops = {
0815     .pin_config_get = sx150x_pinconf_get,
0816     .pin_config_set = sx150x_pinconf_set,
0817     .is_generic = true,
0818 };
0819 
0820 static const struct i2c_device_id sx150x_id[] = {
0821     {"sx1501q", (kernel_ulong_t) &sx1501q_device_data },
0822     {"sx1502q", (kernel_ulong_t) &sx1502q_device_data },
0823     {"sx1503q", (kernel_ulong_t) &sx1503q_device_data },
0824     {"sx1504q", (kernel_ulong_t) &sx1504q_device_data },
0825     {"sx1505q", (kernel_ulong_t) &sx1505q_device_data },
0826     {"sx1506q", (kernel_ulong_t) &sx1506q_device_data },
0827     {"sx1507q", (kernel_ulong_t) &sx1507q_device_data },
0828     {"sx1508q", (kernel_ulong_t) &sx1508q_device_data },
0829     {"sx1509q", (kernel_ulong_t) &sx1509q_device_data },
0830     {}
0831 };
0832 
0833 static const struct of_device_id sx150x_of_match[] = {
0834     { .compatible = "semtech,sx1501q", .data = &sx1501q_device_data },
0835     { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data },
0836     { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data },
0837     { .compatible = "semtech,sx1504q", .data = &sx1504q_device_data },
0838     { .compatible = "semtech,sx1505q", .data = &sx1505q_device_data },
0839     { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
0840     { .compatible = "semtech,sx1507q", .data = &sx1507q_device_data },
0841     { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
0842     { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
0843     {},
0844 };
0845 
0846 static int sx150x_reset(struct sx150x_pinctrl *pctl)
0847 {
0848     int err;
0849 
0850     err = i2c_smbus_write_byte_data(pctl->client,
0851                     pctl->data->pri.x789.reg_reset,
0852                     SX150X_789_RESET_KEY1);
0853     if (err < 0)
0854         return err;
0855 
0856     err = i2c_smbus_write_byte_data(pctl->client,
0857                     pctl->data->pri.x789.reg_reset,
0858                     SX150X_789_RESET_KEY2);
0859     return err;
0860 }
0861 
0862 static int sx150x_init_misc(struct sx150x_pinctrl *pctl)
0863 {
0864     u8 reg, value;
0865 
0866     switch (pctl->data->model) {
0867     case SX150X_789:
0868         reg   = pctl->data->pri.x789.reg_misc;
0869         value = SX150X_789_REG_MISC_AUTOCLEAR_OFF;
0870         break;
0871     case SX150X_456:
0872         reg   = pctl->data->pri.x456.reg_advanced;
0873         value = 0x00;
0874 
0875         /*
0876          * Only SX1506 has RegAdvanced, SX1504/5 are expected
0877          * to initialize this offset to zero
0878          */
0879         if (!reg)
0880             return 0;
0881         break;
0882     case SX150X_123:
0883         reg   = pctl->data->pri.x123.reg_advanced;
0884         value = 0x00;
0885         break;
0886     default:
0887         WARN(1, "Unknown chip model %d\n", pctl->data->model);
0888         return -EINVAL;
0889     }
0890 
0891     return regmap_write(pctl->regmap, reg, value);
0892 }
0893 
0894 static int sx150x_init_hw(struct sx150x_pinctrl *pctl)
0895 {
0896     const u8 reg[] = {
0897         [SX150X_789] = pctl->data->pri.x789.reg_polarity,
0898         [SX150X_456] = pctl->data->pri.x456.reg_pld_mode,
0899         [SX150X_123] = pctl->data->pri.x123.reg_pld_mode,
0900     };
0901     int err;
0902 
0903     if (pctl->data->model == SX150X_789 &&
0904         of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) {
0905         err = sx150x_reset(pctl);
0906         if (err < 0)
0907             return err;
0908     }
0909 
0910     err = sx150x_init_misc(pctl);
0911     if (err < 0)
0912         return err;
0913 
0914     /* Set all pins to work in normal mode */
0915     return regmap_write(pctl->regmap, reg[pctl->data->model], 0);
0916 }
0917 
0918 static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl,
0919                    unsigned int reg)
0920 {
0921     const struct sx150x_device_data *data = pctl->data;
0922 
0923     if (reg == data->reg_sense) {
0924         /*
0925          * RegSense packs two bits of configuration per GPIO,
0926          * so we'd need to read twice as many bits as there
0927          * are GPIO in our chip
0928          */
0929         return 2 * data->ngpios;
0930     } else if ((data->model == SX150X_789 &&
0931             (reg == data->pri.x789.reg_misc ||
0932              reg == data->pri.x789.reg_clock ||
0933              reg == data->pri.x789.reg_reset))
0934            ||
0935            (data->model == SX150X_123 &&
0936             reg == data->pri.x123.reg_advanced)
0937            ||
0938            (data->model == SX150X_456 &&
0939             data->pri.x456.reg_advanced &&
0940             reg == data->pri.x456.reg_advanced)) {
0941         return 8;
0942     } else {
0943         return data->ngpios;
0944     }
0945 }
0946 
0947 static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl,
0948                      unsigned int reg, unsigned int val)
0949 {
0950     unsigned int a, b;
0951     const struct sx150x_device_data *data = pctl->data;
0952 
0953     /*
0954      * Whereas SX1509 presents RegSense in a simple layout as such:
0955      *  reg     [ f f e e d d c c ]
0956      *  reg + 1 [ b b a a 9 9 8 8 ]
0957      *  reg + 2 [ 7 7 6 6 5 5 4 4 ]
0958      *  reg + 3 [ 3 3 2 2 1 1 0 0 ]
0959      *
0960      * SX1503 and SX1506 deviate from that data layout, instead storing
0961      * their contents as follows:
0962      *
0963      *  reg     [ f f e e d d c c ]
0964      *  reg + 1 [ 7 7 6 6 5 5 4 4 ]
0965      *  reg + 2 [ b b a a 9 9 8 8 ]
0966      *  reg + 3 [ 3 3 2 2 1 1 0 0 ]
0967      *
0968      * so, taking that into account, we swap two
0969      * inner bytes of a 4-byte result
0970      */
0971 
0972     if (reg == data->reg_sense &&
0973         data->ngpios == 16 &&
0974         (data->model == SX150X_123 ||
0975          data->model == SX150X_456)) {
0976         a = val & 0x00ff0000;
0977         b = val & 0x0000ff00;
0978 
0979         val &= 0xff0000ff;
0980         val |= b << 8;
0981         val |= a >> 8;
0982     }
0983 
0984     return val;
0985 }
0986 
0987 /*
0988  * In order to mask the differences between 16 and 8 bit expander
0989  * devices we set up a sligthly ficticious regmap that pretends to be
0990  * a set of 32-bit (to accommodate RegSenseLow/RegSenseHigh
0991  * pair/quartet) registers and transparently reconstructs those
0992  * registers via multiple I2C/SMBus reads
0993  *
0994  * This way the rest of the driver code, interfacing with the chip via
0995  * regmap API, can work assuming that each GPIO pin is represented by
0996  * a group of bits at an offset proportional to GPIO number within a
0997  * given register.
0998  */
0999 static int sx150x_regmap_reg_read(void *context, unsigned int reg,
1000                   unsigned int *result)
1001 {
1002     int ret, n;
1003     struct sx150x_pinctrl *pctl = context;
1004     struct i2c_client *i2c = pctl->client;
1005     const int width = sx150x_regmap_reg_width(pctl, reg);
1006     unsigned int idx, val;
1007 
1008     /*
1009      * There are four potential cases covered by this function:
1010      *
1011      * 1) 8-pin chip, single configuration bit register
1012      *
1013      *  This is trivial the code below just needs to read:
1014      *      reg  [ 7 6 5 4 3 2 1 0 ]
1015      *
1016      * 2) 8-pin chip, double configuration bit register (RegSense)
1017      *
1018      *  The read will be done as follows:
1019      *      reg      [ 7 7 6 6 5 5 4 4 ]
1020      *      reg + 1  [ 3 3 2 2 1 1 0 0 ]
1021      *
1022      * 3) 16-pin chip, single configuration bit register
1023      *
1024      *  The read will be done as follows:
1025      *      reg     [ f e d c b a 9 8 ]
1026      *      reg + 1 [ 7 6 5 4 3 2 1 0 ]
1027      *
1028      * 4) 16-pin chip, double configuration bit register (RegSense)
1029      *
1030      *  The read will be done as follows:
1031      *      reg     [ f f e e d d c c ]
1032      *      reg + 1 [ b b a a 9 9 8 8 ]
1033      *      reg + 2 [ 7 7 6 6 5 5 4 4 ]
1034      *      reg + 3 [ 3 3 2 2 1 1 0 0 ]
1035      */
1036 
1037     for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) {
1038         val <<= 8;
1039 
1040         ret = i2c_smbus_read_byte_data(i2c, idx);
1041         if (ret < 0)
1042             return ret;
1043 
1044         val |= ret;
1045     }
1046 
1047     *result = sx150x_maybe_swizzle(pctl, reg, val);
1048 
1049     return 0;
1050 }
1051 
1052 static int sx150x_regmap_reg_write(void *context, unsigned int reg,
1053                    unsigned int val)
1054 {
1055     int ret, n;
1056     struct sx150x_pinctrl *pctl = context;
1057     struct i2c_client *i2c = pctl->client;
1058     const int width = sx150x_regmap_reg_width(pctl, reg);
1059 
1060     val = sx150x_maybe_swizzle(pctl, reg, val);
1061 
1062     n = (width - 1) & ~7;
1063     do {
1064         const u8 byte = (val >> n) & 0xff;
1065 
1066         ret = i2c_smbus_write_byte_data(i2c, reg, byte);
1067         if (ret < 0)
1068             return ret;
1069 
1070         reg++;
1071         n -= 8;
1072     } while (n >= 0);
1073 
1074     return 0;
1075 }
1076 
1077 static bool sx150x_reg_volatile(struct device *dev, unsigned int reg)
1078 {
1079     struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev));
1080 
1081     return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data;
1082 }
1083 
1084 static const struct regmap_config sx150x_regmap_config = {
1085     .reg_bits = 8,
1086     .val_bits = 32,
1087 
1088     .cache_type = REGCACHE_RBTREE,
1089 
1090     .reg_read = sx150x_regmap_reg_read,
1091     .reg_write = sx150x_regmap_reg_write,
1092 
1093     .max_register = SX150X_MAX_REGISTER,
1094     .volatile_reg = sx150x_reg_volatile,
1095 };
1096 
1097 static int sx150x_probe(struct i2c_client *client,
1098             const struct i2c_device_id *id)
1099 {
1100     static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
1101                      I2C_FUNC_SMBUS_WRITE_WORD_DATA;
1102     struct device *dev = &client->dev;
1103     struct sx150x_pinctrl *pctl;
1104     int ret;
1105 
1106     if (!i2c_check_functionality(client->adapter, i2c_funcs))
1107         return -ENOSYS;
1108 
1109     pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1110     if (!pctl)
1111         return -ENOMEM;
1112 
1113     i2c_set_clientdata(client, pctl);
1114 
1115     pctl->dev = dev;
1116     pctl->client = client;
1117 
1118     if (dev->of_node)
1119         pctl->data = of_device_get_match_data(dev);
1120     else
1121         pctl->data = (struct sx150x_device_data *)id->driver_data;
1122 
1123     if (!pctl->data)
1124         return -EINVAL;
1125 
1126     pctl->regmap = devm_regmap_init(dev, NULL, pctl,
1127                     &sx150x_regmap_config);
1128     if (IS_ERR(pctl->regmap)) {
1129         ret = PTR_ERR(pctl->regmap);
1130         dev_err(dev, "Failed to allocate register map: %d\n",
1131             ret);
1132         return ret;
1133     }
1134 
1135     mutex_init(&pctl->lock);
1136 
1137     ret = sx150x_init_hw(pctl);
1138     if (ret)
1139         return ret;
1140 
1141     /* Pinctrl_desc */
1142     pctl->pinctrl_desc.name = "sx150x-pinctrl";
1143     pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops;
1144     pctl->pinctrl_desc.confops = &sx150x_pinconf_ops;
1145     pctl->pinctrl_desc.pins = pctl->data->pins;
1146     pctl->pinctrl_desc.npins = pctl->data->npins;
1147     pctl->pinctrl_desc.owner = THIS_MODULE;
1148 
1149     ret = devm_pinctrl_register_and_init(dev, &pctl->pinctrl_desc,
1150                          pctl, &pctl->pctldev);
1151     if (ret) {
1152         dev_err(dev, "Failed to register pinctrl device\n");
1153         return ret;
1154     }
1155 
1156     /* Register GPIO controller */
1157     pctl->gpio.base = -1;
1158     pctl->gpio.ngpio = pctl->data->npins;
1159     pctl->gpio.get_direction = sx150x_gpio_get_direction;
1160     pctl->gpio.direction_input = sx150x_gpio_direction_input;
1161     pctl->gpio.direction_output = sx150x_gpio_direction_output;
1162     pctl->gpio.get = sx150x_gpio_get;
1163     pctl->gpio.set = sx150x_gpio_set;
1164     pctl->gpio.set_config = gpiochip_generic_config;
1165     pctl->gpio.parent = dev;
1166     pctl->gpio.can_sleep = true;
1167     pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL);
1168     if (!pctl->gpio.label)
1169         return -ENOMEM;
1170 
1171     /*
1172      * Setting multiple pins is not safe when all pins are not
1173      * handled by the same regmap register. The oscio pin (present
1174      * on the SX150X_789 chips) lives in its own register, so
1175      * would require locking that is not in place at this time.
1176      */
1177     if (pctl->data->model != SX150X_789)
1178         pctl->gpio.set_multiple = sx150x_gpio_set_multiple;
1179 
1180     /* Add Interrupt support if an irq is specified */
1181     if (client->irq > 0) {
1182         struct gpio_irq_chip *girq;
1183 
1184         pctl->irq_chip.irq_mask = sx150x_irq_mask;
1185         pctl->irq_chip.irq_unmask = sx150x_irq_unmask;
1186         pctl->irq_chip.irq_set_type = sx150x_irq_set_type;
1187         pctl->irq_chip.irq_bus_lock = sx150x_irq_bus_lock;
1188         pctl->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock;
1189         pctl->irq_chip.name = devm_kstrdup(dev, client->name,
1190                            GFP_KERNEL);
1191         if (!pctl->irq_chip.name)
1192             return -ENOMEM;
1193 
1194         pctl->irq.masked = ~0;
1195         pctl->irq.sense = 0;
1196 
1197         /*
1198          * Because sx150x_irq_threaded_fn invokes all of the
1199          * nested interrupt handlers via handle_nested_irq,
1200          * any "handler" assigned to struct gpio_irq_chip
1201          * below is going to be ignored, so the choice of the
1202          * function does not matter that much.
1203          *
1204          * We set it to handle_bad_irq to avoid confusion,
1205          * plus it will be instantly noticeable if it is ever
1206          * called (should not happen)
1207          */
1208         girq = &pctl->gpio.irq;
1209         girq->chip = &pctl->irq_chip;
1210         /* This will let us handle the parent IRQ in the driver */
1211         girq->parent_handler = NULL;
1212         girq->num_parents = 0;
1213         girq->parents = NULL;
1214         girq->default_type = IRQ_TYPE_NONE;
1215         girq->handler = handle_bad_irq;
1216         girq->threaded = true;
1217 
1218         ret = devm_request_threaded_irq(dev, client->irq, NULL,
1219                         sx150x_irq_thread_fn,
1220                         IRQF_ONESHOT | IRQF_SHARED |
1221                         IRQF_TRIGGER_FALLING,
1222                         pctl->irq_chip.name, pctl);
1223         if (ret < 0)
1224             return ret;
1225     }
1226 
1227     ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl);
1228     if (ret)
1229         return ret;
1230 
1231     /*
1232      * Pin control functions need to be enabled AFTER registering the
1233      * GPIO chip because sx150x_pinconf_set() calls
1234      * sx150x_gpio_direction_output().
1235      */
1236     ret = pinctrl_enable(pctl->pctldev);
1237     if (ret) {
1238         dev_err(dev, "Failed to enable pinctrl device\n");
1239         return ret;
1240     }
1241 
1242     ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev),
1243                      0, 0, pctl->data->npins);
1244     if (ret)
1245         return ret;
1246 
1247     return 0;
1248 }
1249 
1250 static struct i2c_driver sx150x_driver = {
1251     .driver = {
1252         .name = "sx150x-pinctrl",
1253         .of_match_table = of_match_ptr(sx150x_of_match),
1254     },
1255     .probe    = sx150x_probe,
1256     .id_table = sx150x_id,
1257 };
1258 
1259 static int __init sx150x_init(void)
1260 {
1261     return i2c_add_driver(&sx150x_driver);
1262 }
1263 subsys_initcall(sx150x_init);
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