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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for STMicroelectronics Multi-Function eXpander (STMFX) GPIO expander
0004  *
0005  * Copyright (C) 2019 STMicroelectronics
0006  * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
0007  */
0008 #include <linux/gpio/driver.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/mfd/stmfx.h>
0011 #include <linux/module.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/pinctrl/pinconf.h>
0014 #include <linux/pinctrl/pinmux.h>
0015 
0016 #include "core.h"
0017 #include "pinctrl-utils.h"
0018 
0019 /* GPIOs expander */
0020 /* GPIO_STATE1 0x10, GPIO_STATE2 0x11, GPIO_STATE3 0x12 */
0021 #define STMFX_REG_GPIO_STATE        STMFX_REG_GPIO_STATE1 /* R */
0022 /* GPIO_DIR1 0x60, GPIO_DIR2 0x61, GPIO_DIR3 0x63 */
0023 #define STMFX_REG_GPIO_DIR      STMFX_REG_GPIO_DIR1 /* RW */
0024 /* GPIO_TYPE1 0x64, GPIO_TYPE2 0x65, GPIO_TYPE3 0x66 */
0025 #define STMFX_REG_GPIO_TYPE     STMFX_REG_GPIO_TYPE1 /* RW */
0026 /* GPIO_PUPD1 0x68, GPIO_PUPD2 0x69, GPIO_PUPD3 0x6A */
0027 #define STMFX_REG_GPIO_PUPD     STMFX_REG_GPIO_PUPD1 /* RW */
0028 /* GPO_SET1 0x6C, GPO_SET2 0x6D, GPO_SET3 0x6E */
0029 #define STMFX_REG_GPO_SET       STMFX_REG_GPO_SET1 /* RW */
0030 /* GPO_CLR1 0x70, GPO_CLR2 0x71, GPO_CLR3 0x72 */
0031 #define STMFX_REG_GPO_CLR       STMFX_REG_GPO_CLR1 /* RW */
0032 /* IRQ_GPI_SRC1 0x48, IRQ_GPI_SRC2 0x49, IRQ_GPI_SRC3 0x4A */
0033 #define STMFX_REG_IRQ_GPI_SRC       STMFX_REG_IRQ_GPI_SRC1 /* RW */
0034 /* IRQ_GPI_EVT1 0x4C, IRQ_GPI_EVT2 0x4D, IRQ_GPI_EVT3 0x4E */
0035 #define STMFX_REG_IRQ_GPI_EVT       STMFX_REG_IRQ_GPI_EVT1 /* RW */
0036 /* IRQ_GPI_TYPE1 0x50, IRQ_GPI_TYPE2 0x51, IRQ_GPI_TYPE3 0x52 */
0037 #define STMFX_REG_IRQ_GPI_TYPE      STMFX_REG_IRQ_GPI_TYPE1 /* RW */
0038 /* IRQ_GPI_PENDING1 0x0C, IRQ_GPI_PENDING2 0x0D, IRQ_GPI_PENDING3 0x0E*/
0039 #define STMFX_REG_IRQ_GPI_PENDING   STMFX_REG_IRQ_GPI_PENDING1 /* R */
0040 /* IRQ_GPI_ACK1 0x54, IRQ_GPI_ACK2 0x55, IRQ_GPI_ACK3 0x56 */
0041 #define STMFX_REG_IRQ_GPI_ACK       STMFX_REG_IRQ_GPI_ACK1 /* RW */
0042 
0043 #define NR_GPIO_REGS            3
0044 #define NR_GPIOS_PER_REG        8
0045 #define get_reg(offset)         ((offset) / NR_GPIOS_PER_REG)
0046 #define get_shift(offset)       ((offset) % NR_GPIOS_PER_REG)
0047 #define get_mask(offset)        (BIT(get_shift(offset)))
0048 
0049 /*
0050  * STMFX pinctrl can have up to 24 pins if STMFX other functions are not used.
0051  * Pins availability is managed thanks to gpio-ranges property.
0052  */
0053 static const struct pinctrl_pin_desc stmfx_pins[] = {
0054     PINCTRL_PIN(0, "gpio0"),
0055     PINCTRL_PIN(1, "gpio1"),
0056     PINCTRL_PIN(2, "gpio2"),
0057     PINCTRL_PIN(3, "gpio3"),
0058     PINCTRL_PIN(4, "gpio4"),
0059     PINCTRL_PIN(5, "gpio5"),
0060     PINCTRL_PIN(6, "gpio6"),
0061     PINCTRL_PIN(7, "gpio7"),
0062     PINCTRL_PIN(8, "gpio8"),
0063     PINCTRL_PIN(9, "gpio9"),
0064     PINCTRL_PIN(10, "gpio10"),
0065     PINCTRL_PIN(11, "gpio11"),
0066     PINCTRL_PIN(12, "gpio12"),
0067     PINCTRL_PIN(13, "gpio13"),
0068     PINCTRL_PIN(14, "gpio14"),
0069     PINCTRL_PIN(15, "gpio15"),
0070     PINCTRL_PIN(16, "agpio0"),
0071     PINCTRL_PIN(17, "agpio1"),
0072     PINCTRL_PIN(18, "agpio2"),
0073     PINCTRL_PIN(19, "agpio3"),
0074     PINCTRL_PIN(20, "agpio4"),
0075     PINCTRL_PIN(21, "agpio5"),
0076     PINCTRL_PIN(22, "agpio6"),
0077     PINCTRL_PIN(23, "agpio7"),
0078 };
0079 
0080 struct stmfx_pinctrl {
0081     struct device *dev;
0082     struct stmfx *stmfx;
0083     struct pinctrl_dev *pctl_dev;
0084     struct pinctrl_desc pctl_desc;
0085     struct gpio_chip gpio_chip;
0086     struct irq_chip irq_chip;
0087     struct mutex lock; /* IRQ bus lock */
0088     unsigned long gpio_valid_mask;
0089     /* Cache of IRQ_GPI_* registers for bus_lock */
0090     u8 irq_gpi_src[NR_GPIO_REGS];
0091     u8 irq_gpi_type[NR_GPIO_REGS];
0092     u8 irq_gpi_evt[NR_GPIO_REGS];
0093     u8 irq_toggle_edge[NR_GPIO_REGS];
0094 #ifdef CONFIG_PM
0095     /* Backup of GPIO_* registers for suspend/resume */
0096     u8 bkp_gpio_state[NR_GPIO_REGS];
0097     u8 bkp_gpio_dir[NR_GPIO_REGS];
0098     u8 bkp_gpio_type[NR_GPIO_REGS];
0099     u8 bkp_gpio_pupd[NR_GPIO_REGS];
0100 #endif
0101 };
0102 
0103 static int stmfx_gpio_get(struct gpio_chip *gc, unsigned int offset)
0104 {
0105     struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
0106     u32 reg = STMFX_REG_GPIO_STATE + get_reg(offset);
0107     u32 mask = get_mask(offset);
0108     u32 value;
0109     int ret;
0110 
0111     ret = regmap_read(pctl->stmfx->map, reg, &value);
0112 
0113     return ret ? ret : !!(value & mask);
0114 }
0115 
0116 static void stmfx_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
0117 {
0118     struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
0119     u32 reg = value ? STMFX_REG_GPO_SET : STMFX_REG_GPO_CLR;
0120     u32 mask = get_mask(offset);
0121 
0122     regmap_write_bits(pctl->stmfx->map, reg + get_reg(offset),
0123               mask, mask);
0124 }
0125 
0126 static int stmfx_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
0127 {
0128     struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
0129     u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
0130     u32 mask = get_mask(offset);
0131     u32 val;
0132     int ret;
0133 
0134     ret = regmap_read(pctl->stmfx->map, reg, &val);
0135     /*
0136      * On stmfx, gpio pins direction is (0)input, (1)output.
0137      */
0138     if (ret)
0139         return ret;
0140 
0141     if (val & mask)
0142         return GPIO_LINE_DIRECTION_OUT;
0143 
0144     return GPIO_LINE_DIRECTION_IN;
0145 }
0146 
0147 static int stmfx_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
0148 {
0149     struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
0150     u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
0151     u32 mask = get_mask(offset);
0152 
0153     return regmap_write_bits(pctl->stmfx->map, reg, mask, 0);
0154 }
0155 
0156 static int stmfx_gpio_direction_output(struct gpio_chip *gc,
0157                        unsigned int offset, int value)
0158 {
0159     struct stmfx_pinctrl *pctl = gpiochip_get_data(gc);
0160     u32 reg = STMFX_REG_GPIO_DIR + get_reg(offset);
0161     u32 mask = get_mask(offset);
0162 
0163     stmfx_gpio_set(gc, offset, value);
0164 
0165     return regmap_write_bits(pctl->stmfx->map, reg, mask, mask);
0166 }
0167 
0168 static int stmfx_pinconf_get_pupd(struct stmfx_pinctrl *pctl,
0169                   unsigned int offset)
0170 {
0171     u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset);
0172     u32 pupd, mask = get_mask(offset);
0173     int ret;
0174 
0175     ret = regmap_read(pctl->stmfx->map, reg, &pupd);
0176     if (ret)
0177         return ret;
0178 
0179     return !!(pupd & mask);
0180 }
0181 
0182 static int stmfx_pinconf_set_pupd(struct stmfx_pinctrl *pctl,
0183                   unsigned int offset, u32 pupd)
0184 {
0185     u32 reg = STMFX_REG_GPIO_PUPD + get_reg(offset);
0186     u32 mask = get_mask(offset);
0187 
0188     return regmap_write_bits(pctl->stmfx->map, reg, mask, pupd ? mask : 0);
0189 }
0190 
0191 static int stmfx_pinconf_get_type(struct stmfx_pinctrl *pctl,
0192                   unsigned int offset)
0193 {
0194     u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset);
0195     u32 type, mask = get_mask(offset);
0196     int ret;
0197 
0198     ret = regmap_read(pctl->stmfx->map, reg, &type);
0199     if (ret)
0200         return ret;
0201 
0202     return !!(type & mask);
0203 }
0204 
0205 static int stmfx_pinconf_set_type(struct stmfx_pinctrl *pctl,
0206                   unsigned int offset, u32 type)
0207 {
0208     u32 reg = STMFX_REG_GPIO_TYPE + get_reg(offset);
0209     u32 mask = get_mask(offset);
0210 
0211     return regmap_write_bits(pctl->stmfx->map, reg, mask, type ? mask : 0);
0212 }
0213 
0214 static int stmfx_pinconf_get(struct pinctrl_dev *pctldev,
0215                  unsigned int pin, unsigned long *config)
0216 {
0217     struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0218     u32 param = pinconf_to_config_param(*config);
0219     struct pinctrl_gpio_range *range;
0220     u32 arg = 0;
0221     int ret, dir, type, pupd;
0222 
0223     range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
0224     if (!range)
0225         return -EINVAL;
0226 
0227     dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin);
0228     if (dir < 0)
0229         return dir;
0230 
0231     /*
0232      * Currently the gpiolib IN is 1 and OUT is 0 but let's not count
0233      * on it just to be on the safe side also in the future :)
0234      */
0235     dir = (dir == GPIO_LINE_DIRECTION_IN) ? 1 : 0;
0236 
0237     type = stmfx_pinconf_get_type(pctl, pin);
0238     if (type < 0)
0239         return type;
0240     pupd = stmfx_pinconf_get_pupd(pctl, pin);
0241     if (pupd < 0)
0242         return pupd;
0243 
0244     switch (param) {
0245     case PIN_CONFIG_BIAS_DISABLE:
0246         if ((!dir && (!type || !pupd)) || (dir && !type))
0247             arg = 1;
0248         break;
0249     case PIN_CONFIG_BIAS_PULL_DOWN:
0250         if (dir && type && !pupd)
0251             arg = 1;
0252         break;
0253     case PIN_CONFIG_BIAS_PULL_UP:
0254         if (type && pupd)
0255             arg = 1;
0256         break;
0257     case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0258         if ((!dir && type) || (dir && !type))
0259             arg = 1;
0260         break;
0261     case PIN_CONFIG_DRIVE_PUSH_PULL:
0262         if ((!dir && !type) || (dir && type))
0263             arg = 1;
0264         break;
0265     case PIN_CONFIG_OUTPUT:
0266         if (dir)
0267             return -EINVAL;
0268 
0269         ret = stmfx_gpio_get(&pctl->gpio_chip, pin);
0270         if (ret < 0)
0271             return ret;
0272 
0273         arg = ret;
0274         break;
0275     default:
0276         return -ENOTSUPP;
0277     }
0278 
0279     *config = pinconf_to_config_packed(param, arg);
0280 
0281     return 0;
0282 }
0283 
0284 static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
0285                  unsigned long *configs, unsigned int num_configs)
0286 {
0287     struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0288     struct pinctrl_gpio_range *range;
0289     enum pin_config_param param;
0290     u32 arg;
0291     int i, ret;
0292 
0293     range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
0294     if (!range) {
0295         dev_err(pctldev->dev, "pin %d is not available\n", pin);
0296         return -EINVAL;
0297     }
0298 
0299     for (i = 0; i < num_configs; i++) {
0300         param = pinconf_to_config_param(configs[i]);
0301         arg = pinconf_to_config_argument(configs[i]);
0302 
0303         switch (param) {
0304         case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
0305         case PIN_CONFIG_BIAS_DISABLE:
0306         case PIN_CONFIG_DRIVE_PUSH_PULL:
0307             ret = stmfx_pinconf_set_type(pctl, pin, 0);
0308             if (ret)
0309                 return ret;
0310             break;
0311         case PIN_CONFIG_BIAS_PULL_DOWN:
0312             ret = stmfx_pinconf_set_type(pctl, pin, 1);
0313             if (ret)
0314                 return ret;
0315             ret = stmfx_pinconf_set_pupd(pctl, pin, 0);
0316             if (ret)
0317                 return ret;
0318             break;
0319         case PIN_CONFIG_BIAS_PULL_UP:
0320             ret = stmfx_pinconf_set_type(pctl, pin, 1);
0321             if (ret)
0322                 return ret;
0323             ret = stmfx_pinconf_set_pupd(pctl, pin, 1);
0324             if (ret)
0325                 return ret;
0326             break;
0327         case PIN_CONFIG_DRIVE_OPEN_DRAIN:
0328             ret = stmfx_pinconf_set_type(pctl, pin, 1);
0329             if (ret)
0330                 return ret;
0331             break;
0332         case PIN_CONFIG_OUTPUT:
0333             ret = stmfx_gpio_direction_output(&pctl->gpio_chip,
0334                               pin, arg);
0335             if (ret)
0336                 return ret;
0337             break;
0338         default:
0339             return -ENOTSUPP;
0340         }
0341     }
0342 
0343     return 0;
0344 }
0345 
0346 static void stmfx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
0347                    struct seq_file *s, unsigned int offset)
0348 {
0349     struct stmfx_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
0350     struct pinctrl_gpio_range *range;
0351     int dir, type, pupd, val;
0352 
0353     range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, offset);
0354     if (!range)
0355         return;
0356 
0357     dir = stmfx_gpio_get_direction(&pctl->gpio_chip, offset);
0358     if (dir < 0)
0359         return;
0360     type = stmfx_pinconf_get_type(pctl, offset);
0361     if (type < 0)
0362         return;
0363     pupd = stmfx_pinconf_get_pupd(pctl, offset);
0364     if (pupd < 0)
0365         return;
0366     val = stmfx_gpio_get(&pctl->gpio_chip, offset);
0367     if (val < 0)
0368         return;
0369 
0370     if (dir == GPIO_LINE_DIRECTION_OUT) {
0371         seq_printf(s, "output %s ", val ? "high" : "low");
0372         if (type)
0373             seq_printf(s, "open drain %s internal pull-up ",
0374                    pupd ? "with" : "without");
0375         else
0376             seq_puts(s, "push pull no pull ");
0377     } else {
0378         seq_printf(s, "input %s ", val ? "high" : "low");
0379         if (type)
0380             seq_printf(s, "with internal pull-%s ",
0381                    pupd ? "up" : "down");
0382         else
0383             seq_printf(s, "%s ", pupd ? "floating" : "analog");
0384     }
0385 }
0386 
0387 static const struct pinconf_ops stmfx_pinconf_ops = {
0388     .pin_config_get     = stmfx_pinconf_get,
0389     .pin_config_set     = stmfx_pinconf_set,
0390     .pin_config_dbg_show    = stmfx_pinconf_dbg_show,
0391 };
0392 
0393 static int stmfx_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
0394 {
0395     return 0;
0396 }
0397 
0398 static const char *stmfx_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
0399                         unsigned int selector)
0400 {
0401     return NULL;
0402 }
0403 
0404 static int stmfx_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
0405                     unsigned int selector,
0406                     const unsigned int **pins,
0407                     unsigned int *num_pins)
0408 {
0409     return -ENOTSUPP;
0410 }
0411 
0412 static const struct pinctrl_ops stmfx_pinctrl_ops = {
0413     .get_groups_count = stmfx_pinctrl_get_groups_count,
0414     .get_group_name = stmfx_pinctrl_get_group_name,
0415     .get_group_pins = stmfx_pinctrl_get_group_pins,
0416     .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
0417     .dt_free_map = pinctrl_utils_free_map,
0418 };
0419 
0420 static void stmfx_pinctrl_irq_mask(struct irq_data *data)
0421 {
0422     struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
0423     struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
0424     u32 reg = get_reg(data->hwirq);
0425     u32 mask = get_mask(data->hwirq);
0426 
0427     pctl->irq_gpi_src[reg] &= ~mask;
0428 }
0429 
0430 static void stmfx_pinctrl_irq_unmask(struct irq_data *data)
0431 {
0432     struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
0433     struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
0434     u32 reg = get_reg(data->hwirq);
0435     u32 mask = get_mask(data->hwirq);
0436 
0437     pctl->irq_gpi_src[reg] |= mask;
0438 }
0439 
0440 static int stmfx_pinctrl_irq_set_type(struct irq_data *data, unsigned int type)
0441 {
0442     struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
0443     struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
0444     u32 reg = get_reg(data->hwirq);
0445     u32 mask = get_mask(data->hwirq);
0446 
0447     if (type == IRQ_TYPE_NONE)
0448         return -EINVAL;
0449 
0450     if (type & IRQ_TYPE_EDGE_BOTH) {
0451         pctl->irq_gpi_evt[reg] |= mask;
0452         irq_set_handler_locked(data, handle_edge_irq);
0453     } else {
0454         pctl->irq_gpi_evt[reg] &= ~mask;
0455         irq_set_handler_locked(data, handle_level_irq);
0456     }
0457 
0458     if ((type & IRQ_TYPE_EDGE_RISING) || (type & IRQ_TYPE_LEVEL_HIGH))
0459         pctl->irq_gpi_type[reg] |= mask;
0460     else
0461         pctl->irq_gpi_type[reg] &= ~mask;
0462 
0463     /*
0464      * In case of (type & IRQ_TYPE_EDGE_BOTH), we need to know current
0465      * GPIO value to set the right edge trigger. But in atomic context
0466      * here we can't access registers over I2C. That's why (type &
0467      * IRQ_TYPE_EDGE_BOTH) will be managed in .irq_sync_unlock.
0468      */
0469 
0470     if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
0471         pctl->irq_toggle_edge[reg] |= mask;
0472     else
0473         pctl->irq_toggle_edge[reg] &= mask;
0474 
0475     return 0;
0476 }
0477 
0478 static void stmfx_pinctrl_irq_bus_lock(struct irq_data *data)
0479 {
0480     struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
0481     struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
0482 
0483     mutex_lock(&pctl->lock);
0484 }
0485 
0486 static void stmfx_pinctrl_irq_bus_sync_unlock(struct irq_data *data)
0487 {
0488     struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
0489     struct stmfx_pinctrl *pctl = gpiochip_get_data(gpio_chip);
0490     u32 reg = get_reg(data->hwirq);
0491     u32 mask = get_mask(data->hwirq);
0492 
0493     /*
0494      * In case of IRQ_TYPE_EDGE_BOTH), read the current GPIO value
0495      * (this couldn't be done in .irq_set_type because of atomic context)
0496      * to set the right irq trigger type.
0497      */
0498     if (pctl->irq_toggle_edge[reg] & mask) {
0499         if (stmfx_gpio_get(gpio_chip, data->hwirq))
0500             pctl->irq_gpi_type[reg] &= ~mask;
0501         else
0502             pctl->irq_gpi_type[reg] |= mask;
0503     }
0504 
0505     regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT,
0506               pctl->irq_gpi_evt, NR_GPIO_REGS);
0507     regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE,
0508               pctl->irq_gpi_type, NR_GPIO_REGS);
0509     regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
0510               pctl->irq_gpi_src, NR_GPIO_REGS);
0511 
0512     mutex_unlock(&pctl->lock);
0513 }
0514 
0515 static int stmfx_gpio_irq_request_resources(struct irq_data *data)
0516 {
0517     struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
0518     int ret;
0519 
0520     ret = stmfx_gpio_direction_input(gpio_chip, data->hwirq);
0521     if (ret)
0522         return ret;
0523 
0524     return gpiochip_reqres_irq(gpio_chip, data->hwirq);
0525 }
0526 
0527 static void stmfx_gpio_irq_release_resources(struct irq_data *data)
0528 {
0529     struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
0530 
0531     return gpiochip_relres_irq(gpio_chip, data->hwirq);
0532 }
0533 
0534 static void stmfx_pinctrl_irq_toggle_trigger(struct stmfx_pinctrl *pctl,
0535                          unsigned int offset)
0536 {
0537     u32 reg = get_reg(offset);
0538     u32 mask = get_mask(offset);
0539     int val;
0540 
0541     if (!(pctl->irq_toggle_edge[reg] & mask))
0542         return;
0543 
0544     val = stmfx_gpio_get(&pctl->gpio_chip, offset);
0545     if (val < 0)
0546         return;
0547 
0548     if (val) {
0549         pctl->irq_gpi_type[reg] &= mask;
0550         regmap_write_bits(pctl->stmfx->map,
0551                   STMFX_REG_IRQ_GPI_TYPE + reg,
0552                   mask, 0);
0553 
0554     } else {
0555         pctl->irq_gpi_type[reg] |= mask;
0556         regmap_write_bits(pctl->stmfx->map,
0557                   STMFX_REG_IRQ_GPI_TYPE + reg,
0558                   mask, mask);
0559     }
0560 }
0561 
0562 static irqreturn_t stmfx_pinctrl_irq_thread_fn(int irq, void *dev_id)
0563 {
0564     struct stmfx_pinctrl *pctl = (struct stmfx_pinctrl *)dev_id;
0565     struct gpio_chip *gc = &pctl->gpio_chip;
0566     u8 pending[NR_GPIO_REGS];
0567     u8 src[NR_GPIO_REGS] = {0, 0, 0};
0568     unsigned long n, status;
0569     int i, ret;
0570 
0571     ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_IRQ_GPI_PENDING,
0572                    &pending, NR_GPIO_REGS);
0573     if (ret)
0574         return IRQ_NONE;
0575 
0576     regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
0577               src, NR_GPIO_REGS);
0578 
0579     BUILD_BUG_ON(NR_GPIO_REGS > sizeof(status));
0580     for (i = 0, status = 0; i < NR_GPIO_REGS; i++)
0581         status |= (unsigned long)pending[i] << (i * 8);
0582     for_each_set_bit(n, &status, gc->ngpio) {
0583         handle_nested_irq(irq_find_mapping(gc->irq.domain, n));
0584         stmfx_pinctrl_irq_toggle_trigger(pctl, n);
0585     }
0586 
0587     regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
0588               pctl->irq_gpi_src, NR_GPIO_REGS);
0589 
0590     return IRQ_HANDLED;
0591 }
0592 
0593 static int stmfx_pinctrl_gpio_function_enable(struct stmfx_pinctrl *pctl)
0594 {
0595     struct pinctrl_gpio_range *gpio_range;
0596     struct pinctrl_dev *pctl_dev = pctl->pctl_dev;
0597     u32 func = STMFX_FUNC_GPIO;
0598 
0599     pctl->gpio_valid_mask = GENMASK(15, 0);
0600 
0601     gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 16);
0602     if (gpio_range) {
0603         func |= STMFX_FUNC_ALTGPIO_LOW;
0604         pctl->gpio_valid_mask |= GENMASK(19, 16);
0605     }
0606 
0607     gpio_range = pinctrl_find_gpio_range_from_pin(pctl_dev, 20);
0608     if (gpio_range) {
0609         func |= STMFX_FUNC_ALTGPIO_HIGH;
0610         pctl->gpio_valid_mask |= GENMASK(23, 20);
0611     }
0612 
0613     return stmfx_function_enable(pctl->stmfx, func);
0614 }
0615 
0616 static int stmfx_pinctrl_probe(struct platform_device *pdev)
0617 {
0618     struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
0619     struct device_node *np = pdev->dev.of_node;
0620     struct stmfx_pinctrl *pctl;
0621     struct gpio_irq_chip *girq;
0622     int irq, ret;
0623 
0624     pctl = devm_kzalloc(stmfx->dev, sizeof(*pctl), GFP_KERNEL);
0625     if (!pctl)
0626         return -ENOMEM;
0627 
0628     platform_set_drvdata(pdev, pctl);
0629 
0630     pctl->dev = &pdev->dev;
0631     pctl->stmfx = stmfx;
0632 
0633     if (!of_find_property(np, "gpio-ranges", NULL)) {
0634         dev_err(pctl->dev, "missing required gpio-ranges property\n");
0635         return -EINVAL;
0636     }
0637 
0638     irq = platform_get_irq(pdev, 0);
0639     if (irq <= 0)
0640         return -ENXIO;
0641 
0642     mutex_init(&pctl->lock);
0643 
0644     /* Register pin controller */
0645     pctl->pctl_desc.name = "stmfx-pinctrl";
0646     pctl->pctl_desc.pctlops = &stmfx_pinctrl_ops;
0647     pctl->pctl_desc.confops = &stmfx_pinconf_ops;
0648     pctl->pctl_desc.pins = stmfx_pins;
0649     pctl->pctl_desc.npins = ARRAY_SIZE(stmfx_pins);
0650     pctl->pctl_desc.owner = THIS_MODULE;
0651     pctl->pctl_desc.link_consumers = true;
0652 
0653     ret = devm_pinctrl_register_and_init(pctl->dev, &pctl->pctl_desc,
0654                          pctl, &pctl->pctl_dev);
0655     if (ret) {
0656         dev_err(pctl->dev, "pinctrl registration failed\n");
0657         return ret;
0658     }
0659 
0660     ret = pinctrl_enable(pctl->pctl_dev);
0661     if (ret) {
0662         dev_err(pctl->dev, "pinctrl enable failed\n");
0663         return ret;
0664     }
0665 
0666     /* Register gpio controller */
0667     pctl->gpio_chip.label = "stmfx-gpio";
0668     pctl->gpio_chip.parent = pctl->dev;
0669     pctl->gpio_chip.get_direction = stmfx_gpio_get_direction;
0670     pctl->gpio_chip.direction_input = stmfx_gpio_direction_input;
0671     pctl->gpio_chip.direction_output = stmfx_gpio_direction_output;
0672     pctl->gpio_chip.get = stmfx_gpio_get;
0673     pctl->gpio_chip.set = stmfx_gpio_set;
0674     pctl->gpio_chip.set_config = gpiochip_generic_config;
0675     pctl->gpio_chip.base = -1;
0676     pctl->gpio_chip.ngpio = pctl->pctl_desc.npins;
0677     pctl->gpio_chip.can_sleep = true;
0678 
0679     pctl->irq_chip.name = dev_name(pctl->dev);
0680     pctl->irq_chip.irq_mask = stmfx_pinctrl_irq_mask;
0681     pctl->irq_chip.irq_unmask = stmfx_pinctrl_irq_unmask;
0682     pctl->irq_chip.irq_set_type = stmfx_pinctrl_irq_set_type;
0683     pctl->irq_chip.irq_bus_lock = stmfx_pinctrl_irq_bus_lock;
0684     pctl->irq_chip.irq_bus_sync_unlock = stmfx_pinctrl_irq_bus_sync_unlock;
0685     pctl->irq_chip.irq_request_resources = stmfx_gpio_irq_request_resources;
0686     pctl->irq_chip.irq_release_resources = stmfx_gpio_irq_release_resources;
0687 
0688     girq = &pctl->gpio_chip.irq;
0689     girq->chip = &pctl->irq_chip;
0690     /* This will let us handle the parent IRQ in the driver */
0691     girq->parent_handler = NULL;
0692     girq->num_parents = 0;
0693     girq->parents = NULL;
0694     girq->default_type = IRQ_TYPE_NONE;
0695     girq->handler = handle_bad_irq;
0696     girq->threaded = true;
0697 
0698     ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
0699     if (ret) {
0700         dev_err(pctl->dev, "gpio_chip registration failed\n");
0701         return ret;
0702     }
0703 
0704     ret = stmfx_pinctrl_gpio_function_enable(pctl);
0705     if (ret)
0706         return ret;
0707 
0708     ret = devm_request_threaded_irq(pctl->dev, irq, NULL,
0709                     stmfx_pinctrl_irq_thread_fn,
0710                     IRQF_ONESHOT,
0711                     pctl->irq_chip.name, pctl);
0712     if (ret) {
0713         dev_err(pctl->dev, "cannot request irq%d\n", irq);
0714         return ret;
0715     }
0716 
0717     dev_info(pctl->dev,
0718          "%ld GPIOs available\n", hweight_long(pctl->gpio_valid_mask));
0719 
0720     return 0;
0721 }
0722 
0723 static int stmfx_pinctrl_remove(struct platform_device *pdev)
0724 {
0725     struct stmfx *stmfx = dev_get_drvdata(pdev->dev.parent);
0726 
0727     return stmfx_function_disable(stmfx,
0728                       STMFX_FUNC_GPIO |
0729                       STMFX_FUNC_ALTGPIO_LOW |
0730                       STMFX_FUNC_ALTGPIO_HIGH);
0731 }
0732 
0733 #ifdef CONFIG_PM_SLEEP
0734 static int stmfx_pinctrl_backup_regs(struct stmfx_pinctrl *pctl)
0735 {
0736     int ret;
0737 
0738     ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_STATE,
0739                    &pctl->bkp_gpio_state, NR_GPIO_REGS);
0740     if (ret)
0741         return ret;
0742     ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_DIR,
0743                    &pctl->bkp_gpio_dir, NR_GPIO_REGS);
0744     if (ret)
0745         return ret;
0746     ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_TYPE,
0747                    &pctl->bkp_gpio_type, NR_GPIO_REGS);
0748     if (ret)
0749         return ret;
0750     ret = regmap_bulk_read(pctl->stmfx->map, STMFX_REG_GPIO_PUPD,
0751                    &pctl->bkp_gpio_pupd, NR_GPIO_REGS);
0752     if (ret)
0753         return ret;
0754 
0755     return 0;
0756 }
0757 
0758 static int stmfx_pinctrl_restore_regs(struct stmfx_pinctrl *pctl)
0759 {
0760     int ret;
0761 
0762     ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_DIR,
0763                 pctl->bkp_gpio_dir, NR_GPIO_REGS);
0764     if (ret)
0765         return ret;
0766     ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_TYPE,
0767                 pctl->bkp_gpio_type, NR_GPIO_REGS);
0768     if (ret)
0769         return ret;
0770     ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPIO_PUPD,
0771                 pctl->bkp_gpio_pupd, NR_GPIO_REGS);
0772     if (ret)
0773         return ret;
0774     ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_GPO_SET,
0775                 pctl->bkp_gpio_state, NR_GPIO_REGS);
0776     if (ret)
0777         return ret;
0778     ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_EVT,
0779                 pctl->irq_gpi_evt, NR_GPIO_REGS);
0780     if (ret)
0781         return ret;
0782     ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_TYPE,
0783                 pctl->irq_gpi_type, NR_GPIO_REGS);
0784     if (ret)
0785         return ret;
0786     ret = regmap_bulk_write(pctl->stmfx->map, STMFX_REG_IRQ_GPI_SRC,
0787                 pctl->irq_gpi_src, NR_GPIO_REGS);
0788     if (ret)
0789         return ret;
0790 
0791     return 0;
0792 }
0793 
0794 static int stmfx_pinctrl_suspend(struct device *dev)
0795 {
0796     struct stmfx_pinctrl *pctl = dev_get_drvdata(dev);
0797     int ret;
0798 
0799     ret = stmfx_pinctrl_backup_regs(pctl);
0800     if (ret) {
0801         dev_err(pctl->dev, "registers backup failure\n");
0802         return ret;
0803     }
0804 
0805     return 0;
0806 }
0807 
0808 static int stmfx_pinctrl_resume(struct device *dev)
0809 {
0810     struct stmfx_pinctrl *pctl = dev_get_drvdata(dev);
0811     int ret;
0812 
0813     ret = stmfx_pinctrl_restore_regs(pctl);
0814     if (ret) {
0815         dev_err(pctl->dev, "registers restoration failure\n");
0816         return ret;
0817     }
0818 
0819     return 0;
0820 }
0821 #endif
0822 
0823 static SIMPLE_DEV_PM_OPS(stmfx_pinctrl_dev_pm_ops,
0824              stmfx_pinctrl_suspend, stmfx_pinctrl_resume);
0825 
0826 static const struct of_device_id stmfx_pinctrl_of_match[] = {
0827     { .compatible = "st,stmfx-0300-pinctrl", },
0828     {},
0829 };
0830 MODULE_DEVICE_TABLE(of, stmfx_pinctrl_of_match);
0831 
0832 static struct platform_driver stmfx_pinctrl_driver = {
0833     .driver = {
0834         .name = "stmfx-pinctrl",
0835         .of_match_table = stmfx_pinctrl_of_match,
0836         .pm = &stmfx_pinctrl_dev_pm_ops,
0837     },
0838     .probe = stmfx_pinctrl_probe,
0839     .remove = stmfx_pinctrl_remove,
0840 };
0841 module_platform_driver(stmfx_pinctrl_driver);
0842 
0843 MODULE_DESCRIPTION("STMFX pinctrl/GPIO driver");
0844 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
0845 MODULE_LICENSE("GPL v2");
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