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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Pinctrl / GPIO driver for StarFive JH7100 SoC
0004  *
0005  * Copyright (C) 2020 Shanghai StarFive Technology Co., Ltd.
0006  * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
0007  */
0008 
0009 #include <linux/bits.h>
0010 #include <linux/clk.h>
0011 #include <linux/gpio/driver.h>
0012 #include <linux/io.h>
0013 #include <linux/mod_devicetable.h>
0014 #include <linux/module.h>
0015 #include <linux/of.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/reset.h>
0018 #include <linux/spinlock.h>
0019 
0020 #include <linux/pinctrl/pinctrl.h>
0021 #include <linux/pinctrl/pinmux.h>
0022 
0023 #include <dt-bindings/pinctrl/pinctrl-starfive.h>
0024 
0025 #include "core.h"
0026 #include "pinctrl-utils.h"
0027 #include "pinmux.h"
0028 #include "pinconf.h"
0029 
0030 #define DRIVER_NAME "pinctrl-starfive"
0031 
0032 /*
0033  * Refer to Section 12. GPIO Registers in the JH7100 data sheet:
0034  * https://github.com/starfive-tech/JH7100_Docs
0035  */
0036 #define NR_GPIOS    64
0037 
0038 /*
0039  * Global enable for GPIO interrupts. If bit 0 is set to 1 the GPIO interrupts
0040  * are enabled. If set to 0 the GPIO interrupts are disabled.
0041  */
0042 #define GPIOEN      0x000
0043 
0044 /*
0045  * The following 32-bit registers come in pairs, but only the offset of the
0046  * first register is defined. The first controls (interrupts for) GPIO 0-31 and
0047  * the second GPIO 32-63.
0048  */
0049 
0050 /*
0051  * Interrupt Type. If set to 1 the interrupt is edge-triggered. If set to 0 the
0052  * interrupt is level-triggered.
0053  */
0054 #define GPIOIS      0x010
0055 
0056 /*
0057  * Edge-Trigger Interrupt Type.  If set to 1 the interrupt gets triggered on
0058  * both positive and negative edges. If set to 0 the interrupt is triggered by a
0059  * single edge.
0060  */
0061 #define GPIOIBE     0x018
0062 
0063 /*
0064  * Interrupt Trigger Polarity. If set to 1 the interrupt is triggered on a
0065  * rising edge (edge-triggered) or high level (level-triggered). If set to 0 the
0066  * interrupt is triggered on a falling edge (edge-triggered) or low level
0067  * (level-triggered).
0068  */
0069 #define GPIOIEV     0x020
0070 
0071 /*
0072  * Interrupt Mask. If set to 1 the interrupt is enabled (unmasked). If set to 0
0073  * the interrupt is disabled (masked). Note that the current documentation is
0074  * wrong and says the exct opposite of this.
0075  */
0076 #define GPIOIE      0x028
0077 
0078 /*
0079  * Clear Edge-Triggered Interrupts. Write a 1 to clear the edge-triggered
0080  * interrupt.
0081  */
0082 #define GPIOIC      0x030
0083 
0084 /*
0085  * Edge-Triggered Interrupt Status. A 1 means the configured edge was detected.
0086  */
0087 #define GPIORIS     0x038
0088 
0089 /*
0090  * Interrupt Status after Masking. A 1 means the configured edge or level was
0091  * detected and not masked.
0092  */
0093 #define GPIOMIS     0x040
0094 
0095 /*
0096  * Data Value. Dynamically reflects the value of the GPIO pin. If 1 the pin is
0097  * a digital 1 and if 0 the pin is a digital 0.
0098  */
0099 #define GPIODIN     0x048
0100 
0101 /*
0102  * From the data sheet section 12.2, there are 64 32-bit output data registers
0103  * and 64 output enable registers. Output data and output enable registers for
0104  * a given GPIO are contiguous. Eg. GPO0_DOUT_CFG is 0x50 and GPO0_DOEN_CFG is
0105  * 0x54 while GPO1_DOUT_CFG is 0x58 and GPO1_DOEN_CFG is 0x5c.  The stride
0106  * between GPIO registers is effectively 8, thus: GPOn_DOUT_CFG is 0x50 + 8n
0107  * and GPOn_DOEN_CFG is 0x54 + 8n.
0108  */
0109 #define GPON_DOUT_CFG   0x050
0110 #define GPON_DOEN_CFG   0x054
0111 
0112 /*
0113  * From Section 12.3, there are 75 input signal configuration registers which
0114  * are 4 bytes wide starting with GPI_CPU_JTAG_TCK_CFG at 0x250 and ending with
0115  * GPI_USB_OVER_CURRENT_CFG 0x378
0116  */
0117 #define GPI_CFG_OFFSET  0x250
0118 
0119 /*
0120  * Pad Control Bits. There are 16 pad control bits for each pin located in 103
0121  * 32-bit registers controlling PAD_GPIO[0] to PAD_GPIO[63] followed by
0122  * PAD_FUNC_SHARE[0] to PAD_FUNC_SHARE[141]. Odd numbered pins use the upper 16
0123  * bit of each register.
0124  */
0125 #define PAD_SLEW_RATE_MASK      GENMASK(11, 9)
0126 #define PAD_SLEW_RATE_POS       9
0127 #define PAD_BIAS_STRONG_PULL_UP     BIT(8)
0128 #define PAD_INPUT_ENABLE        BIT(7)
0129 #define PAD_INPUT_SCHMITT_ENABLE    BIT(6)
0130 #define PAD_BIAS_DISABLE        BIT(5)
0131 #define PAD_BIAS_PULL_DOWN      BIT(4)
0132 #define PAD_BIAS_MASK \
0133     (PAD_BIAS_STRONG_PULL_UP | \
0134      PAD_BIAS_DISABLE | \
0135      PAD_BIAS_PULL_DOWN)
0136 #define PAD_DRIVE_STRENGTH_MASK     GENMASK(3, 0)
0137 #define PAD_DRIVE_STRENGTH_POS      0
0138 
0139 /*
0140  * From Section 11, the IO_PADSHARE_SEL register can be programmed to select
0141  * one of seven pre-defined multiplexed signal groups on PAD_FUNC_SHARE and
0142  * PAD_GPIO pads. This is a global setting.
0143  */
0144 #define IO_PADSHARE_SEL         0x1a0
0145 
0146 /*
0147  * This just needs to be some number such that when
0148  * sfp->gpio.pin_base = PAD_INVALID_GPIO then
0149  * starfive_pin_to_gpio(sfp, validpin) is never a valid GPIO number.
0150  * That is it should underflow and return something >= NR_GPIOS.
0151  */
0152 #define PAD_INVALID_GPIO        0x10000
0153 
0154 /*
0155  * The packed pinmux values from the device tree look like this:
0156  *
0157  *  | 31 - 24 | 23 - 16 | 15 - 8 |     7    |     6    |  5 - 0  |
0158  *  |  dout   |  doen   |  din   | dout rev | doen rev | gpio nr |
0159  *
0160  * ..but the GPOn_DOUT_CFG and GPOn_DOEN_CFG registers look like this:
0161  *
0162  *  |      31       | 30 - 8 |   7 - 0   |
0163  *  | dout/doen rev | unused | dout/doen |
0164  */
0165 static unsigned int starfive_pinmux_to_gpio(u32 v)
0166 {
0167     return v & (NR_GPIOS - 1);
0168 }
0169 
0170 static u32 starfive_pinmux_to_dout(u32 v)
0171 {
0172     return ((v & BIT(7)) << (31 - 7)) | ((v >> 24) & GENMASK(7, 0));
0173 }
0174 
0175 static u32 starfive_pinmux_to_doen(u32 v)
0176 {
0177     return ((v & BIT(6)) << (31 - 6)) | ((v >> 16) & GENMASK(7, 0));
0178 }
0179 
0180 static u32 starfive_pinmux_to_din(u32 v)
0181 {
0182     return (v >> 8) & GENMASK(7, 0);
0183 }
0184 
0185 /*
0186  * The maximum GPIO output current depends on the chosen drive strength:
0187  *
0188  *  DS:   0     1     2     3     4     5     6     7
0189  *  mA:  14.2  21.2  28.2  35.2  42.2  49.1  56.0  62.8
0190  *
0191  * After rounding that is 7*DS + 14 mA
0192  */
0193 static u32 starfive_drive_strength_to_max_mA(u16 ds)
0194 {
0195     return 7 * ds + 14;
0196 }
0197 
0198 static u16 starfive_drive_strength_from_max_mA(u32 i)
0199 {
0200     return (clamp(i, 14U, 63U) - 14) / 7;
0201 }
0202 
0203 struct starfive_pinctrl {
0204     struct gpio_chip gc;
0205     struct pinctrl_gpio_range gpios;
0206     raw_spinlock_t lock;
0207     void __iomem *base;
0208     void __iomem *padctl;
0209     struct pinctrl_dev *pctl;
0210     struct mutex mutex; /* serialize adding groups and functions */
0211 };
0212 
0213 static inline unsigned int starfive_pin_to_gpio(const struct starfive_pinctrl *sfp,
0214                         unsigned int pin)
0215 {
0216     return pin - sfp->gpios.pin_base;
0217 }
0218 
0219 static inline unsigned int starfive_gpio_to_pin(const struct starfive_pinctrl *sfp,
0220                         unsigned int gpio)
0221 {
0222     return sfp->gpios.pin_base + gpio;
0223 }
0224 
0225 static struct starfive_pinctrl *starfive_from_irq_data(struct irq_data *d)
0226 {
0227     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
0228 
0229     return container_of(gc, struct starfive_pinctrl, gc);
0230 }
0231 
0232 static struct starfive_pinctrl *starfive_from_irq_desc(struct irq_desc *desc)
0233 {
0234     struct gpio_chip *gc = irq_desc_get_handler_data(desc);
0235 
0236     return container_of(gc, struct starfive_pinctrl, gc);
0237 }
0238 
0239 static const struct pinctrl_pin_desc starfive_pins[] = {
0240     PINCTRL_PIN(PAD_GPIO(0), "GPIO[0]"),
0241     PINCTRL_PIN(PAD_GPIO(1), "GPIO[1]"),
0242     PINCTRL_PIN(PAD_GPIO(2), "GPIO[2]"),
0243     PINCTRL_PIN(PAD_GPIO(3), "GPIO[3]"),
0244     PINCTRL_PIN(PAD_GPIO(4), "GPIO[4]"),
0245     PINCTRL_PIN(PAD_GPIO(5), "GPIO[5]"),
0246     PINCTRL_PIN(PAD_GPIO(6), "GPIO[6]"),
0247     PINCTRL_PIN(PAD_GPIO(7), "GPIO[7]"),
0248     PINCTRL_PIN(PAD_GPIO(8), "GPIO[8]"),
0249     PINCTRL_PIN(PAD_GPIO(9), "GPIO[9]"),
0250     PINCTRL_PIN(PAD_GPIO(10), "GPIO[10]"),
0251     PINCTRL_PIN(PAD_GPIO(11), "GPIO[11]"),
0252     PINCTRL_PIN(PAD_GPIO(12), "GPIO[12]"),
0253     PINCTRL_PIN(PAD_GPIO(13), "GPIO[13]"),
0254     PINCTRL_PIN(PAD_GPIO(14), "GPIO[14]"),
0255     PINCTRL_PIN(PAD_GPIO(15), "GPIO[15]"),
0256     PINCTRL_PIN(PAD_GPIO(16), "GPIO[16]"),
0257     PINCTRL_PIN(PAD_GPIO(17), "GPIO[17]"),
0258     PINCTRL_PIN(PAD_GPIO(18), "GPIO[18]"),
0259     PINCTRL_PIN(PAD_GPIO(19), "GPIO[19]"),
0260     PINCTRL_PIN(PAD_GPIO(20), "GPIO[20]"),
0261     PINCTRL_PIN(PAD_GPIO(21), "GPIO[21]"),
0262     PINCTRL_PIN(PAD_GPIO(22), "GPIO[22]"),
0263     PINCTRL_PIN(PAD_GPIO(23), "GPIO[23]"),
0264     PINCTRL_PIN(PAD_GPIO(24), "GPIO[24]"),
0265     PINCTRL_PIN(PAD_GPIO(25), "GPIO[25]"),
0266     PINCTRL_PIN(PAD_GPIO(26), "GPIO[26]"),
0267     PINCTRL_PIN(PAD_GPIO(27), "GPIO[27]"),
0268     PINCTRL_PIN(PAD_GPIO(28), "GPIO[28]"),
0269     PINCTRL_PIN(PAD_GPIO(29), "GPIO[29]"),
0270     PINCTRL_PIN(PAD_GPIO(30), "GPIO[30]"),
0271     PINCTRL_PIN(PAD_GPIO(31), "GPIO[31]"),
0272     PINCTRL_PIN(PAD_GPIO(32), "GPIO[32]"),
0273     PINCTRL_PIN(PAD_GPIO(33), "GPIO[33]"),
0274     PINCTRL_PIN(PAD_GPIO(34), "GPIO[34]"),
0275     PINCTRL_PIN(PAD_GPIO(35), "GPIO[35]"),
0276     PINCTRL_PIN(PAD_GPIO(36), "GPIO[36]"),
0277     PINCTRL_PIN(PAD_GPIO(37), "GPIO[37]"),
0278     PINCTRL_PIN(PAD_GPIO(38), "GPIO[38]"),
0279     PINCTRL_PIN(PAD_GPIO(39), "GPIO[39]"),
0280     PINCTRL_PIN(PAD_GPIO(40), "GPIO[40]"),
0281     PINCTRL_PIN(PAD_GPIO(41), "GPIO[41]"),
0282     PINCTRL_PIN(PAD_GPIO(42), "GPIO[42]"),
0283     PINCTRL_PIN(PAD_GPIO(43), "GPIO[43]"),
0284     PINCTRL_PIN(PAD_GPIO(44), "GPIO[44]"),
0285     PINCTRL_PIN(PAD_GPIO(45), "GPIO[45]"),
0286     PINCTRL_PIN(PAD_GPIO(46), "GPIO[46]"),
0287     PINCTRL_PIN(PAD_GPIO(47), "GPIO[47]"),
0288     PINCTRL_PIN(PAD_GPIO(48), "GPIO[48]"),
0289     PINCTRL_PIN(PAD_GPIO(49), "GPIO[49]"),
0290     PINCTRL_PIN(PAD_GPIO(50), "GPIO[50]"),
0291     PINCTRL_PIN(PAD_GPIO(51), "GPIO[51]"),
0292     PINCTRL_PIN(PAD_GPIO(52), "GPIO[52]"),
0293     PINCTRL_PIN(PAD_GPIO(53), "GPIO[53]"),
0294     PINCTRL_PIN(PAD_GPIO(54), "GPIO[54]"),
0295     PINCTRL_PIN(PAD_GPIO(55), "GPIO[55]"),
0296     PINCTRL_PIN(PAD_GPIO(56), "GPIO[56]"),
0297     PINCTRL_PIN(PAD_GPIO(57), "GPIO[57]"),
0298     PINCTRL_PIN(PAD_GPIO(58), "GPIO[58]"),
0299     PINCTRL_PIN(PAD_GPIO(59), "GPIO[59]"),
0300     PINCTRL_PIN(PAD_GPIO(60), "GPIO[60]"),
0301     PINCTRL_PIN(PAD_GPIO(61), "GPIO[61]"),
0302     PINCTRL_PIN(PAD_GPIO(62), "GPIO[62]"),
0303     PINCTRL_PIN(PAD_GPIO(63), "GPIO[63]"),
0304     PINCTRL_PIN(PAD_FUNC_SHARE(0), "FUNC_SHARE[0]"),
0305     PINCTRL_PIN(PAD_FUNC_SHARE(1), "FUNC_SHARE[1]"),
0306     PINCTRL_PIN(PAD_FUNC_SHARE(2), "FUNC_SHARE[2]"),
0307     PINCTRL_PIN(PAD_FUNC_SHARE(3), "FUNC_SHARE[3]"),
0308     PINCTRL_PIN(PAD_FUNC_SHARE(4), "FUNC_SHARE[4]"),
0309     PINCTRL_PIN(PAD_FUNC_SHARE(5), "FUNC_SHARE[5]"),
0310     PINCTRL_PIN(PAD_FUNC_SHARE(6), "FUNC_SHARE[6]"),
0311     PINCTRL_PIN(PAD_FUNC_SHARE(7), "FUNC_SHARE[7]"),
0312     PINCTRL_PIN(PAD_FUNC_SHARE(8), "FUNC_SHARE[8]"),
0313     PINCTRL_PIN(PAD_FUNC_SHARE(9), "FUNC_SHARE[9]"),
0314     PINCTRL_PIN(PAD_FUNC_SHARE(10), "FUNC_SHARE[10]"),
0315     PINCTRL_PIN(PAD_FUNC_SHARE(11), "FUNC_SHARE[11]"),
0316     PINCTRL_PIN(PAD_FUNC_SHARE(12), "FUNC_SHARE[12]"),
0317     PINCTRL_PIN(PAD_FUNC_SHARE(13), "FUNC_SHARE[13]"),
0318     PINCTRL_PIN(PAD_FUNC_SHARE(14), "FUNC_SHARE[14]"),
0319     PINCTRL_PIN(PAD_FUNC_SHARE(15), "FUNC_SHARE[15]"),
0320     PINCTRL_PIN(PAD_FUNC_SHARE(16), "FUNC_SHARE[16]"),
0321     PINCTRL_PIN(PAD_FUNC_SHARE(17), "FUNC_SHARE[17]"),
0322     PINCTRL_PIN(PAD_FUNC_SHARE(18), "FUNC_SHARE[18]"),
0323     PINCTRL_PIN(PAD_FUNC_SHARE(19), "FUNC_SHARE[19]"),
0324     PINCTRL_PIN(PAD_FUNC_SHARE(20), "FUNC_SHARE[20]"),
0325     PINCTRL_PIN(PAD_FUNC_SHARE(21), "FUNC_SHARE[21]"),
0326     PINCTRL_PIN(PAD_FUNC_SHARE(22), "FUNC_SHARE[22]"),
0327     PINCTRL_PIN(PAD_FUNC_SHARE(23), "FUNC_SHARE[23]"),
0328     PINCTRL_PIN(PAD_FUNC_SHARE(24), "FUNC_SHARE[24]"),
0329     PINCTRL_PIN(PAD_FUNC_SHARE(25), "FUNC_SHARE[25]"),
0330     PINCTRL_PIN(PAD_FUNC_SHARE(26), "FUNC_SHARE[26]"),
0331     PINCTRL_PIN(PAD_FUNC_SHARE(27), "FUNC_SHARE[27]"),
0332     PINCTRL_PIN(PAD_FUNC_SHARE(28), "FUNC_SHARE[28]"),
0333     PINCTRL_PIN(PAD_FUNC_SHARE(29), "FUNC_SHARE[29]"),
0334     PINCTRL_PIN(PAD_FUNC_SHARE(30), "FUNC_SHARE[30]"),
0335     PINCTRL_PIN(PAD_FUNC_SHARE(31), "FUNC_SHARE[31]"),
0336     PINCTRL_PIN(PAD_FUNC_SHARE(32), "FUNC_SHARE[32]"),
0337     PINCTRL_PIN(PAD_FUNC_SHARE(33), "FUNC_SHARE[33]"),
0338     PINCTRL_PIN(PAD_FUNC_SHARE(34), "FUNC_SHARE[34]"),
0339     PINCTRL_PIN(PAD_FUNC_SHARE(35), "FUNC_SHARE[35]"),
0340     PINCTRL_PIN(PAD_FUNC_SHARE(36), "FUNC_SHARE[36]"),
0341     PINCTRL_PIN(PAD_FUNC_SHARE(37), "FUNC_SHARE[37]"),
0342     PINCTRL_PIN(PAD_FUNC_SHARE(38), "FUNC_SHARE[38]"),
0343     PINCTRL_PIN(PAD_FUNC_SHARE(39), "FUNC_SHARE[39]"),
0344     PINCTRL_PIN(PAD_FUNC_SHARE(40), "FUNC_SHARE[40]"),
0345     PINCTRL_PIN(PAD_FUNC_SHARE(41), "FUNC_SHARE[41]"),
0346     PINCTRL_PIN(PAD_FUNC_SHARE(42), "FUNC_SHARE[42]"),
0347     PINCTRL_PIN(PAD_FUNC_SHARE(43), "FUNC_SHARE[43]"),
0348     PINCTRL_PIN(PAD_FUNC_SHARE(44), "FUNC_SHARE[44]"),
0349     PINCTRL_PIN(PAD_FUNC_SHARE(45), "FUNC_SHARE[45]"),
0350     PINCTRL_PIN(PAD_FUNC_SHARE(46), "FUNC_SHARE[46]"),
0351     PINCTRL_PIN(PAD_FUNC_SHARE(47), "FUNC_SHARE[47]"),
0352     PINCTRL_PIN(PAD_FUNC_SHARE(48), "FUNC_SHARE[48]"),
0353     PINCTRL_PIN(PAD_FUNC_SHARE(49), "FUNC_SHARE[49]"),
0354     PINCTRL_PIN(PAD_FUNC_SHARE(50), "FUNC_SHARE[50]"),
0355     PINCTRL_PIN(PAD_FUNC_SHARE(51), "FUNC_SHARE[51]"),
0356     PINCTRL_PIN(PAD_FUNC_SHARE(52), "FUNC_SHARE[52]"),
0357     PINCTRL_PIN(PAD_FUNC_SHARE(53), "FUNC_SHARE[53]"),
0358     PINCTRL_PIN(PAD_FUNC_SHARE(54), "FUNC_SHARE[54]"),
0359     PINCTRL_PIN(PAD_FUNC_SHARE(55), "FUNC_SHARE[55]"),
0360     PINCTRL_PIN(PAD_FUNC_SHARE(56), "FUNC_SHARE[56]"),
0361     PINCTRL_PIN(PAD_FUNC_SHARE(57), "FUNC_SHARE[57]"),
0362     PINCTRL_PIN(PAD_FUNC_SHARE(58), "FUNC_SHARE[58]"),
0363     PINCTRL_PIN(PAD_FUNC_SHARE(59), "FUNC_SHARE[59]"),
0364     PINCTRL_PIN(PAD_FUNC_SHARE(60), "FUNC_SHARE[60]"),
0365     PINCTRL_PIN(PAD_FUNC_SHARE(61), "FUNC_SHARE[61]"),
0366     PINCTRL_PIN(PAD_FUNC_SHARE(62), "FUNC_SHARE[62]"),
0367     PINCTRL_PIN(PAD_FUNC_SHARE(63), "FUNC_SHARE[63]"),
0368     PINCTRL_PIN(PAD_FUNC_SHARE(64), "FUNC_SHARE[64]"),
0369     PINCTRL_PIN(PAD_FUNC_SHARE(65), "FUNC_SHARE[65]"),
0370     PINCTRL_PIN(PAD_FUNC_SHARE(66), "FUNC_SHARE[66]"),
0371     PINCTRL_PIN(PAD_FUNC_SHARE(67), "FUNC_SHARE[67]"),
0372     PINCTRL_PIN(PAD_FUNC_SHARE(68), "FUNC_SHARE[68]"),
0373     PINCTRL_PIN(PAD_FUNC_SHARE(69), "FUNC_SHARE[69]"),
0374     PINCTRL_PIN(PAD_FUNC_SHARE(70), "FUNC_SHARE[70]"),
0375     PINCTRL_PIN(PAD_FUNC_SHARE(71), "FUNC_SHARE[71]"),
0376     PINCTRL_PIN(PAD_FUNC_SHARE(72), "FUNC_SHARE[72]"),
0377     PINCTRL_PIN(PAD_FUNC_SHARE(73), "FUNC_SHARE[73]"),
0378     PINCTRL_PIN(PAD_FUNC_SHARE(74), "FUNC_SHARE[74]"),
0379     PINCTRL_PIN(PAD_FUNC_SHARE(75), "FUNC_SHARE[75]"),
0380     PINCTRL_PIN(PAD_FUNC_SHARE(76), "FUNC_SHARE[76]"),
0381     PINCTRL_PIN(PAD_FUNC_SHARE(77), "FUNC_SHARE[77]"),
0382     PINCTRL_PIN(PAD_FUNC_SHARE(78), "FUNC_SHARE[78]"),
0383     PINCTRL_PIN(PAD_FUNC_SHARE(79), "FUNC_SHARE[79]"),
0384     PINCTRL_PIN(PAD_FUNC_SHARE(80), "FUNC_SHARE[80]"),
0385     PINCTRL_PIN(PAD_FUNC_SHARE(81), "FUNC_SHARE[81]"),
0386     PINCTRL_PIN(PAD_FUNC_SHARE(82), "FUNC_SHARE[82]"),
0387     PINCTRL_PIN(PAD_FUNC_SHARE(83), "FUNC_SHARE[83]"),
0388     PINCTRL_PIN(PAD_FUNC_SHARE(84), "FUNC_SHARE[84]"),
0389     PINCTRL_PIN(PAD_FUNC_SHARE(85), "FUNC_SHARE[85]"),
0390     PINCTRL_PIN(PAD_FUNC_SHARE(86), "FUNC_SHARE[86]"),
0391     PINCTRL_PIN(PAD_FUNC_SHARE(87), "FUNC_SHARE[87]"),
0392     PINCTRL_PIN(PAD_FUNC_SHARE(88), "FUNC_SHARE[88]"),
0393     PINCTRL_PIN(PAD_FUNC_SHARE(89), "FUNC_SHARE[89]"),
0394     PINCTRL_PIN(PAD_FUNC_SHARE(90), "FUNC_SHARE[90]"),
0395     PINCTRL_PIN(PAD_FUNC_SHARE(91), "FUNC_SHARE[91]"),
0396     PINCTRL_PIN(PAD_FUNC_SHARE(92), "FUNC_SHARE[92]"),
0397     PINCTRL_PIN(PAD_FUNC_SHARE(93), "FUNC_SHARE[93]"),
0398     PINCTRL_PIN(PAD_FUNC_SHARE(94), "FUNC_SHARE[94]"),
0399     PINCTRL_PIN(PAD_FUNC_SHARE(95), "FUNC_SHARE[95]"),
0400     PINCTRL_PIN(PAD_FUNC_SHARE(96), "FUNC_SHARE[96]"),
0401     PINCTRL_PIN(PAD_FUNC_SHARE(97), "FUNC_SHARE[97]"),
0402     PINCTRL_PIN(PAD_FUNC_SHARE(98), "FUNC_SHARE[98]"),
0403     PINCTRL_PIN(PAD_FUNC_SHARE(99), "FUNC_SHARE[99]"),
0404     PINCTRL_PIN(PAD_FUNC_SHARE(100), "FUNC_SHARE[100]"),
0405     PINCTRL_PIN(PAD_FUNC_SHARE(101), "FUNC_SHARE[101]"),
0406     PINCTRL_PIN(PAD_FUNC_SHARE(102), "FUNC_SHARE[102]"),
0407     PINCTRL_PIN(PAD_FUNC_SHARE(103), "FUNC_SHARE[103]"),
0408     PINCTRL_PIN(PAD_FUNC_SHARE(104), "FUNC_SHARE[104]"),
0409     PINCTRL_PIN(PAD_FUNC_SHARE(105), "FUNC_SHARE[105]"),
0410     PINCTRL_PIN(PAD_FUNC_SHARE(106), "FUNC_SHARE[106]"),
0411     PINCTRL_PIN(PAD_FUNC_SHARE(107), "FUNC_SHARE[107]"),
0412     PINCTRL_PIN(PAD_FUNC_SHARE(108), "FUNC_SHARE[108]"),
0413     PINCTRL_PIN(PAD_FUNC_SHARE(109), "FUNC_SHARE[109]"),
0414     PINCTRL_PIN(PAD_FUNC_SHARE(110), "FUNC_SHARE[110]"),
0415     PINCTRL_PIN(PAD_FUNC_SHARE(111), "FUNC_SHARE[111]"),
0416     PINCTRL_PIN(PAD_FUNC_SHARE(112), "FUNC_SHARE[112]"),
0417     PINCTRL_PIN(PAD_FUNC_SHARE(113), "FUNC_SHARE[113]"),
0418     PINCTRL_PIN(PAD_FUNC_SHARE(114), "FUNC_SHARE[114]"),
0419     PINCTRL_PIN(PAD_FUNC_SHARE(115), "FUNC_SHARE[115]"),
0420     PINCTRL_PIN(PAD_FUNC_SHARE(116), "FUNC_SHARE[116]"),
0421     PINCTRL_PIN(PAD_FUNC_SHARE(117), "FUNC_SHARE[117]"),
0422     PINCTRL_PIN(PAD_FUNC_SHARE(118), "FUNC_SHARE[118]"),
0423     PINCTRL_PIN(PAD_FUNC_SHARE(119), "FUNC_SHARE[119]"),
0424     PINCTRL_PIN(PAD_FUNC_SHARE(120), "FUNC_SHARE[120]"),
0425     PINCTRL_PIN(PAD_FUNC_SHARE(121), "FUNC_SHARE[121]"),
0426     PINCTRL_PIN(PAD_FUNC_SHARE(122), "FUNC_SHARE[122]"),
0427     PINCTRL_PIN(PAD_FUNC_SHARE(123), "FUNC_SHARE[123]"),
0428     PINCTRL_PIN(PAD_FUNC_SHARE(124), "FUNC_SHARE[124]"),
0429     PINCTRL_PIN(PAD_FUNC_SHARE(125), "FUNC_SHARE[125]"),
0430     PINCTRL_PIN(PAD_FUNC_SHARE(126), "FUNC_SHARE[126]"),
0431     PINCTRL_PIN(PAD_FUNC_SHARE(127), "FUNC_SHARE[127]"),
0432     PINCTRL_PIN(PAD_FUNC_SHARE(128), "FUNC_SHARE[128]"),
0433     PINCTRL_PIN(PAD_FUNC_SHARE(129), "FUNC_SHARE[129]"),
0434     PINCTRL_PIN(PAD_FUNC_SHARE(130), "FUNC_SHARE[130]"),
0435     PINCTRL_PIN(PAD_FUNC_SHARE(131), "FUNC_SHARE[131]"),
0436     PINCTRL_PIN(PAD_FUNC_SHARE(132), "FUNC_SHARE[132]"),
0437     PINCTRL_PIN(PAD_FUNC_SHARE(133), "FUNC_SHARE[133]"),
0438     PINCTRL_PIN(PAD_FUNC_SHARE(134), "FUNC_SHARE[134]"),
0439     PINCTRL_PIN(PAD_FUNC_SHARE(135), "FUNC_SHARE[135]"),
0440     PINCTRL_PIN(PAD_FUNC_SHARE(136), "FUNC_SHARE[136]"),
0441     PINCTRL_PIN(PAD_FUNC_SHARE(137), "FUNC_SHARE[137]"),
0442     PINCTRL_PIN(PAD_FUNC_SHARE(138), "FUNC_SHARE[138]"),
0443     PINCTRL_PIN(PAD_FUNC_SHARE(139), "FUNC_SHARE[139]"),
0444     PINCTRL_PIN(PAD_FUNC_SHARE(140), "FUNC_SHARE[140]"),
0445     PINCTRL_PIN(PAD_FUNC_SHARE(141), "FUNC_SHARE[141]"),
0446 };
0447 
0448 #ifdef CONFIG_DEBUG_FS
0449 static void starfive_pin_dbg_show(struct pinctrl_dev *pctldev,
0450                   struct seq_file *s,
0451                   unsigned int pin)
0452 {
0453     struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
0454     unsigned int gpio = starfive_pin_to_gpio(sfp, pin);
0455     void __iomem *reg;
0456     u32 dout, doen;
0457 
0458     if (gpio >= NR_GPIOS)
0459         return;
0460 
0461     reg = sfp->base + GPON_DOUT_CFG + 8 * gpio;
0462     dout = readl_relaxed(reg + 0x000);
0463     doen = readl_relaxed(reg + 0x004);
0464 
0465     seq_printf(s, "dout=%lu%s doen=%lu%s",
0466            dout & GENMASK(7, 0), (dout & BIT(31)) ? "r" : "",
0467            doen & GENMASK(7, 0), (doen & BIT(31)) ? "r" : "");
0468 }
0469 #else
0470 #define starfive_pin_dbg_show NULL
0471 #endif
0472 
0473 static int starfive_dt_node_to_map(struct pinctrl_dev *pctldev,
0474                    struct device_node *np,
0475                    struct pinctrl_map **maps,
0476                    unsigned int *num_maps)
0477 {
0478     struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
0479     struct device *dev = sfp->gc.parent;
0480     struct device_node *child;
0481     struct pinctrl_map *map;
0482     const char **pgnames;
0483     const char *grpname;
0484     u32 *pinmux;
0485     int ngroups;
0486     int *pins;
0487     int nmaps;
0488     int ret;
0489 
0490     nmaps = 0;
0491     ngroups = 0;
0492     for_each_child_of_node(np, child) {
0493         int npinmux = of_property_count_u32_elems(child, "pinmux");
0494         int npins   = of_property_count_u32_elems(child, "pins");
0495 
0496         if (npinmux > 0 && npins > 0) {
0497             dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: both pinmux and pins set\n",
0498                 np, child);
0499             of_node_put(child);
0500             return -EINVAL;
0501         }
0502         if (npinmux == 0 && npins == 0) {
0503             dev_err(dev, "invalid pinctrl group %pOFn.%pOFn: neither pinmux nor pins set\n",
0504                 np, child);
0505             of_node_put(child);
0506             return -EINVAL;
0507         }
0508 
0509         if (npinmux > 0)
0510             nmaps += 2;
0511         else
0512             nmaps += 1;
0513         ngroups += 1;
0514     }
0515 
0516     pgnames = devm_kcalloc(dev, ngroups, sizeof(*pgnames), GFP_KERNEL);
0517     if (!pgnames)
0518         return -ENOMEM;
0519 
0520     map = kcalloc(nmaps, sizeof(*map), GFP_KERNEL);
0521     if (!map)
0522         return -ENOMEM;
0523 
0524     nmaps = 0;
0525     ngroups = 0;
0526     mutex_lock(&sfp->mutex);
0527     for_each_child_of_node(np, child) {
0528         int npins;
0529         int i;
0530 
0531         grpname = devm_kasprintf(dev, GFP_KERNEL, "%pOFn.%pOFn", np, child);
0532         if (!grpname) {
0533             ret = -ENOMEM;
0534             goto put_child;
0535         }
0536 
0537         pgnames[ngroups++] = grpname;
0538 
0539         if ((npins = of_property_count_u32_elems(child, "pinmux")) > 0) {
0540             pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
0541             if (!pins) {
0542                 ret = -ENOMEM;
0543                 goto put_child;
0544             }
0545 
0546             pinmux = devm_kcalloc(dev, npins, sizeof(*pinmux), GFP_KERNEL);
0547             if (!pinmux) {
0548                 ret = -ENOMEM;
0549                 goto put_child;
0550             }
0551 
0552             ret = of_property_read_u32_array(child, "pinmux", pinmux, npins);
0553             if (ret)
0554                 goto put_child;
0555 
0556             for (i = 0; i < npins; i++) {
0557                 unsigned int gpio = starfive_pinmux_to_gpio(pinmux[i]);
0558 
0559                 pins[i] = starfive_gpio_to_pin(sfp, gpio);
0560             }
0561 
0562             map[nmaps].type = PIN_MAP_TYPE_MUX_GROUP;
0563             map[nmaps].data.mux.function = np->name;
0564             map[nmaps].data.mux.group = grpname;
0565             nmaps += 1;
0566         } else if ((npins = of_property_count_u32_elems(child, "pins")) > 0) {
0567             pins = devm_kcalloc(dev, npins, sizeof(*pins), GFP_KERNEL);
0568             if (!pins) {
0569                 ret = -ENOMEM;
0570                 goto put_child;
0571             }
0572 
0573             pinmux = NULL;
0574 
0575             for (i = 0; i < npins; i++) {
0576                 u32 v;
0577 
0578                 ret = of_property_read_u32_index(child, "pins", i, &v);
0579                 if (ret)
0580                     goto put_child;
0581                 pins[i] = v;
0582             }
0583         } else {
0584             ret = -EINVAL;
0585             goto put_child;
0586         }
0587 
0588         ret = pinctrl_generic_add_group(pctldev, grpname, pins, npins, pinmux);
0589         if (ret < 0) {
0590             dev_err(dev, "error adding group %s: %d\n", grpname, ret);
0591             goto put_child;
0592         }
0593 
0594         ret = pinconf_generic_parse_dt_config(child, pctldev,
0595                               &map[nmaps].data.configs.configs,
0596                               &map[nmaps].data.configs.num_configs);
0597         if (ret) {
0598             dev_err(dev, "error parsing pin config of group %s: %d\n",
0599                 grpname, ret);
0600             goto put_child;
0601         }
0602 
0603         /* don't create a map if there are no pinconf settings */
0604         if (map[nmaps].data.configs.num_configs == 0)
0605             continue;
0606 
0607         map[nmaps].type = PIN_MAP_TYPE_CONFIGS_GROUP;
0608         map[nmaps].data.configs.group_or_pin = grpname;
0609         nmaps += 1;
0610     }
0611 
0612     ret = pinmux_generic_add_function(pctldev, np->name, pgnames, ngroups, NULL);
0613     if (ret < 0) {
0614         dev_err(dev, "error adding function %s: %d\n", np->name, ret);
0615         goto free_map;
0616     }
0617 
0618     *maps = map;
0619     *num_maps = nmaps;
0620     mutex_unlock(&sfp->mutex);
0621     return 0;
0622 
0623 put_child:
0624     of_node_put(child);
0625 free_map:
0626     pinctrl_utils_free_map(pctldev, map, nmaps);
0627     mutex_unlock(&sfp->mutex);
0628     return ret;
0629 }
0630 
0631 static const struct pinctrl_ops starfive_pinctrl_ops = {
0632     .get_groups_count = pinctrl_generic_get_group_count,
0633     .get_group_name = pinctrl_generic_get_group_name,
0634     .get_group_pins = pinctrl_generic_get_group_pins,
0635     .pin_dbg_show = starfive_pin_dbg_show,
0636     .dt_node_to_map = starfive_dt_node_to_map,
0637     .dt_free_map = pinctrl_utils_free_map,
0638 };
0639 
0640 static int starfive_set_mux(struct pinctrl_dev *pctldev,
0641                 unsigned int fsel, unsigned int gsel)
0642 {
0643     struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
0644     struct device *dev = sfp->gc.parent;
0645     const struct group_desc *group;
0646     const u32 *pinmux;
0647     unsigned int i;
0648 
0649     group = pinctrl_generic_get_group(pctldev, gsel);
0650     if (!group)
0651         return -EINVAL;
0652 
0653     pinmux = group->data;
0654     for (i = 0; i < group->num_pins; i++) {
0655         u32 v = pinmux[i];
0656         unsigned int gpio = starfive_pinmux_to_gpio(v);
0657         u32 dout = starfive_pinmux_to_dout(v);
0658         u32 doen = starfive_pinmux_to_doen(v);
0659         u32 din = starfive_pinmux_to_din(v);
0660         void __iomem *reg_dout;
0661         void __iomem *reg_doen;
0662         void __iomem *reg_din;
0663         unsigned long flags;
0664 
0665         dev_dbg(dev, "GPIO%u: dout=0x%x doen=0x%x din=0x%x\n",
0666             gpio, dout, doen, din);
0667 
0668         reg_dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
0669         reg_doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
0670         if (din != GPI_NONE)
0671             reg_din = sfp->base + GPI_CFG_OFFSET + 4 * din;
0672         else
0673             reg_din = NULL;
0674 
0675         raw_spin_lock_irqsave(&sfp->lock, flags);
0676         writel_relaxed(dout, reg_dout);
0677         writel_relaxed(doen, reg_doen);
0678         if (reg_din)
0679             writel_relaxed(gpio + 2, reg_din);
0680         raw_spin_unlock_irqrestore(&sfp->lock, flags);
0681     }
0682 
0683     return 0;
0684 }
0685 
0686 static const struct pinmux_ops starfive_pinmux_ops = {
0687     .get_functions_count = pinmux_generic_get_function_count,
0688     .get_function_name = pinmux_generic_get_function_name,
0689     .get_function_groups = pinmux_generic_get_function_groups,
0690     .set_mux = starfive_set_mux,
0691     .strict = true,
0692 };
0693 
0694 static u16 starfive_padctl_get(struct starfive_pinctrl *sfp,
0695                    unsigned int pin)
0696 {
0697     void __iomem *reg = sfp->padctl + 4 * (pin / 2);
0698     int shift = 16 * (pin % 2);
0699 
0700     return readl_relaxed(reg) >> shift;
0701 }
0702 
0703 static void starfive_padctl_rmw(struct starfive_pinctrl *sfp,
0704                 unsigned int pin,
0705                 u16 _mask, u16 _value)
0706 {
0707     void __iomem *reg = sfp->padctl + 4 * (pin / 2);
0708     int shift = 16 * (pin % 2);
0709     u32 mask = (u32)_mask << shift;
0710     u32 value = (u32)_value << shift;
0711     unsigned long flags;
0712 
0713     dev_dbg(sfp->gc.parent, "padctl_rmw(%u, 0x%03x, 0x%03x)\n", pin, _mask, _value);
0714 
0715     raw_spin_lock_irqsave(&sfp->lock, flags);
0716     value |= readl_relaxed(reg) & ~mask;
0717     writel_relaxed(value, reg);
0718     raw_spin_unlock_irqrestore(&sfp->lock, flags);
0719 }
0720 
0721 #define PIN_CONFIG_STARFIVE_STRONG_PULL_UP  (PIN_CONFIG_END + 1)
0722 
0723 static const struct pinconf_generic_params starfive_pinconf_custom_params[] = {
0724     { "starfive,strong-pull-up", PIN_CONFIG_STARFIVE_STRONG_PULL_UP, 1 },
0725 };
0726 
0727 #ifdef CONFIG_DEBUG_FS
0728 static const struct pin_config_item starfive_pinconf_custom_conf_items[] = {
0729     PCONFDUMP(PIN_CONFIG_STARFIVE_STRONG_PULL_UP, "input bias strong pull-up", NULL, false),
0730 };
0731 
0732 static_assert(ARRAY_SIZE(starfive_pinconf_custom_conf_items) ==
0733           ARRAY_SIZE(starfive_pinconf_custom_params));
0734 #else
0735 #define starfive_pinconf_custom_conf_items NULL
0736 #endif
0737 
0738 static int starfive_pinconf_get(struct pinctrl_dev *pctldev,
0739                 unsigned int pin, unsigned long *config)
0740 {
0741     struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
0742     int param = pinconf_to_config_param(*config);
0743     u16 value = starfive_padctl_get(sfp, pin);
0744     bool enabled;
0745     u32 arg;
0746 
0747     switch (param) {
0748     case PIN_CONFIG_BIAS_DISABLE:
0749         enabled = value & PAD_BIAS_DISABLE;
0750         arg = 0;
0751         break;
0752     case PIN_CONFIG_BIAS_PULL_DOWN:
0753         enabled = value & PAD_BIAS_PULL_DOWN;
0754         arg = 1;
0755         break;
0756     case PIN_CONFIG_BIAS_PULL_UP:
0757         enabled = !(value & PAD_BIAS_MASK);
0758         arg = 1;
0759         break;
0760     case PIN_CONFIG_DRIVE_STRENGTH:
0761         enabled = value & PAD_DRIVE_STRENGTH_MASK;
0762         arg = starfive_drive_strength_to_max_mA(value & PAD_DRIVE_STRENGTH_MASK);
0763         break;
0764     case PIN_CONFIG_INPUT_ENABLE:
0765         enabled = value & PAD_INPUT_ENABLE;
0766         arg = enabled;
0767         break;
0768     case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
0769         enabled = value & PAD_INPUT_SCHMITT_ENABLE;
0770         arg = enabled;
0771         break;
0772     case PIN_CONFIG_SLEW_RATE:
0773         enabled = value & PAD_SLEW_RATE_MASK;
0774         arg = (value & PAD_SLEW_RATE_MASK) >> PAD_SLEW_RATE_POS;
0775         break;
0776     case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:
0777         enabled = value & PAD_BIAS_STRONG_PULL_UP;
0778         arg = enabled;
0779         break;
0780     default:
0781         return -ENOTSUPP;
0782     }
0783 
0784     *config = pinconf_to_config_packed(param, arg);
0785     return enabled ? 0 : -EINVAL;
0786 }
0787 
0788 static int starfive_pinconf_group_get(struct pinctrl_dev *pctldev,
0789                       unsigned int gsel, unsigned long *config)
0790 {
0791     const struct group_desc *group;
0792 
0793     group = pinctrl_generic_get_group(pctldev, gsel);
0794     if (!group)
0795         return -EINVAL;
0796 
0797     return starfive_pinconf_get(pctldev, group->pins[0], config);
0798 }
0799 
0800 static int starfive_pinconf_group_set(struct pinctrl_dev *pctldev,
0801                       unsigned int gsel,
0802                       unsigned long *configs,
0803                       unsigned int num_configs)
0804 {
0805     struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
0806     const struct group_desc *group;
0807     u16 mask, value;
0808     int i;
0809 
0810     group = pinctrl_generic_get_group(pctldev, gsel);
0811     if (!group)
0812         return -EINVAL;
0813 
0814     mask = 0;
0815     value = 0;
0816     for (i = 0; i < num_configs; i++) {
0817         int param = pinconf_to_config_param(configs[i]);
0818         u32 arg = pinconf_to_config_argument(configs[i]);
0819 
0820         switch (param) {
0821         case PIN_CONFIG_BIAS_DISABLE:
0822             mask |= PAD_BIAS_MASK;
0823             value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_DISABLE;
0824             break;
0825         case PIN_CONFIG_BIAS_PULL_DOWN:
0826             if (arg == 0)
0827                 return -ENOTSUPP;
0828             mask |= PAD_BIAS_MASK;
0829             value = (value & ~PAD_BIAS_MASK) | PAD_BIAS_PULL_DOWN;
0830             break;
0831         case PIN_CONFIG_BIAS_PULL_UP:
0832             if (arg == 0)
0833                 return -ENOTSUPP;
0834             mask |= PAD_BIAS_MASK;
0835             value = value & ~PAD_BIAS_MASK;
0836             break;
0837         case PIN_CONFIG_DRIVE_STRENGTH:
0838             mask |= PAD_DRIVE_STRENGTH_MASK;
0839             value = (value & ~PAD_DRIVE_STRENGTH_MASK) |
0840                 starfive_drive_strength_from_max_mA(arg);
0841             break;
0842         case PIN_CONFIG_INPUT_ENABLE:
0843             mask |= PAD_INPUT_ENABLE;
0844             if (arg)
0845                 value |= PAD_INPUT_ENABLE;
0846             else
0847                 value &= ~PAD_INPUT_ENABLE;
0848             break;
0849         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
0850             mask |= PAD_INPUT_SCHMITT_ENABLE;
0851             if (arg)
0852                 value |= PAD_INPUT_SCHMITT_ENABLE;
0853             else
0854                 value &= ~PAD_INPUT_SCHMITT_ENABLE;
0855             break;
0856         case PIN_CONFIG_SLEW_RATE:
0857             mask |= PAD_SLEW_RATE_MASK;
0858             value = (value & ~PAD_SLEW_RATE_MASK) |
0859                 ((arg << PAD_SLEW_RATE_POS) & PAD_SLEW_RATE_MASK);
0860             break;
0861         case PIN_CONFIG_STARFIVE_STRONG_PULL_UP:
0862             if (arg) {
0863                 mask |= PAD_BIAS_MASK;
0864                 value = (value & ~PAD_BIAS_MASK) |
0865                     PAD_BIAS_STRONG_PULL_UP;
0866             } else {
0867                 mask |= PAD_BIAS_STRONG_PULL_UP;
0868                 value = value & ~PAD_BIAS_STRONG_PULL_UP;
0869             }
0870             break;
0871         default:
0872             return -ENOTSUPP;
0873         }
0874     }
0875 
0876     for (i = 0; i < group->num_pins; i++)
0877         starfive_padctl_rmw(sfp, group->pins[i], mask, value);
0878 
0879     return 0;
0880 }
0881 
0882 #ifdef CONFIG_DEBUG_FS
0883 static void starfive_pinconf_dbg_show(struct pinctrl_dev *pctldev,
0884                       struct seq_file *s, unsigned int pin)
0885 {
0886     struct starfive_pinctrl *sfp = pinctrl_dev_get_drvdata(pctldev);
0887     u16 value = starfive_padctl_get(sfp, pin);
0888 
0889     seq_printf(s, " (0x%03x)", value);
0890 }
0891 #else
0892 #define starfive_pinconf_dbg_show NULL
0893 #endif
0894 
0895 static const struct pinconf_ops starfive_pinconf_ops = {
0896     .pin_config_get = starfive_pinconf_get,
0897     .pin_config_group_get = starfive_pinconf_group_get,
0898     .pin_config_group_set = starfive_pinconf_group_set,
0899     .pin_config_dbg_show = starfive_pinconf_dbg_show,
0900     .is_generic = true,
0901 };
0902 
0903 static struct pinctrl_desc starfive_desc = {
0904     .name = DRIVER_NAME,
0905     .pins = starfive_pins,
0906     .npins = ARRAY_SIZE(starfive_pins),
0907     .pctlops = &starfive_pinctrl_ops,
0908     .pmxops = &starfive_pinmux_ops,
0909     .confops = &starfive_pinconf_ops,
0910     .owner = THIS_MODULE,
0911     .num_custom_params = ARRAY_SIZE(starfive_pinconf_custom_params),
0912     .custom_params = starfive_pinconf_custom_params,
0913     .custom_conf_items = starfive_pinconf_custom_conf_items,
0914 };
0915 
0916 static int starfive_gpio_request(struct gpio_chip *gc, unsigned int gpio)
0917 {
0918     return pinctrl_gpio_request(gc->base + gpio);
0919 }
0920 
0921 static void starfive_gpio_free(struct gpio_chip *gc, unsigned int gpio)
0922 {
0923     pinctrl_gpio_free(gc->base + gpio);
0924 }
0925 
0926 static int starfive_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
0927 {
0928     struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
0929     void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
0930 
0931     if (readl_relaxed(doen) == GPO_ENABLE)
0932         return GPIO_LINE_DIRECTION_OUT;
0933 
0934     return GPIO_LINE_DIRECTION_IN;
0935 }
0936 
0937 static int starfive_gpio_direction_input(struct gpio_chip *gc,
0938                      unsigned int gpio)
0939 {
0940     struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
0941     void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
0942     unsigned long flags;
0943 
0944     /* enable input and schmitt trigger */
0945     starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),
0946                 PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE,
0947                 PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE);
0948 
0949     raw_spin_lock_irqsave(&sfp->lock, flags);
0950     writel_relaxed(GPO_DISABLE, doen);
0951     raw_spin_unlock_irqrestore(&sfp->lock, flags);
0952     return 0;
0953 }
0954 
0955 static int starfive_gpio_direction_output(struct gpio_chip *gc,
0956                       unsigned int gpio, int value)
0957 {
0958     struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
0959     void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
0960     void __iomem *doen = sfp->base + GPON_DOEN_CFG + 8 * gpio;
0961     unsigned long flags;
0962 
0963     raw_spin_lock_irqsave(&sfp->lock, flags);
0964     writel_relaxed(value, dout);
0965     writel_relaxed(GPO_ENABLE, doen);
0966     raw_spin_unlock_irqrestore(&sfp->lock, flags);
0967 
0968     /* disable input, schmitt trigger and bias */
0969     starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio),
0970                 PAD_BIAS_MASK | PAD_INPUT_ENABLE | PAD_INPUT_SCHMITT_ENABLE,
0971                 PAD_BIAS_DISABLE);
0972 
0973     return 0;
0974 }
0975 
0976 static int starfive_gpio_get(struct gpio_chip *gc, unsigned int gpio)
0977 {
0978     struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
0979     void __iomem *din = sfp->base + GPIODIN + 4 * (gpio / 32);
0980 
0981     return !!(readl_relaxed(din) & BIT(gpio % 32));
0982 }
0983 
0984 static void starfive_gpio_set(struct gpio_chip *gc, unsigned int gpio,
0985                   int value)
0986 {
0987     struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
0988     void __iomem *dout = sfp->base + GPON_DOUT_CFG + 8 * gpio;
0989     unsigned long flags;
0990 
0991     raw_spin_lock_irqsave(&sfp->lock, flags);
0992     writel_relaxed(value, dout);
0993     raw_spin_unlock_irqrestore(&sfp->lock, flags);
0994 }
0995 
0996 static int starfive_gpio_set_config(struct gpio_chip *gc, unsigned int gpio,
0997                     unsigned long config)
0998 {
0999     struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
1000     u32 arg = pinconf_to_config_argument(config);
1001     u16 value;
1002     u16 mask;
1003 
1004     switch (pinconf_to_config_param(config)) {
1005     case PIN_CONFIG_BIAS_DISABLE:
1006         mask  = PAD_BIAS_MASK;
1007         value = PAD_BIAS_DISABLE;
1008         break;
1009     case PIN_CONFIG_BIAS_PULL_DOWN:
1010         if (arg == 0)
1011             return -ENOTSUPP;
1012         mask  = PAD_BIAS_MASK;
1013         value = PAD_BIAS_PULL_DOWN;
1014         break;
1015     case PIN_CONFIG_BIAS_PULL_UP:
1016         if (arg == 0)
1017             return -ENOTSUPP;
1018         mask  = PAD_BIAS_MASK;
1019         value = 0;
1020         break;
1021     case PIN_CONFIG_DRIVE_PUSH_PULL:
1022         return 0;
1023     case PIN_CONFIG_INPUT_ENABLE:
1024         mask  = PAD_INPUT_ENABLE;
1025         value = arg ? PAD_INPUT_ENABLE : 0;
1026         break;
1027     case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1028         mask  = PAD_INPUT_SCHMITT_ENABLE;
1029         value = arg ? PAD_INPUT_SCHMITT_ENABLE : 0;
1030         break;
1031     default:
1032         return -ENOTSUPP;
1033     }
1034 
1035     starfive_padctl_rmw(sfp, starfive_gpio_to_pin(sfp, gpio), mask, value);
1036     return 0;
1037 }
1038 
1039 static int starfive_gpio_add_pin_ranges(struct gpio_chip *gc)
1040 {
1041     struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
1042 
1043     sfp->gpios.name = sfp->gc.label;
1044     sfp->gpios.base = sfp->gc.base;
1045     /*
1046      * sfp->gpios.pin_base depends on the chosen signal group
1047      * and is set in starfive_probe()
1048      */
1049     sfp->gpios.npins = NR_GPIOS;
1050     sfp->gpios.gc = &sfp->gc;
1051     pinctrl_add_gpio_range(sfp->pctl, &sfp->gpios);
1052     return 0;
1053 }
1054 
1055 static void starfive_irq_ack(struct irq_data *d)
1056 {
1057     struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1058     irq_hw_number_t gpio = irqd_to_hwirq(d);
1059     void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);
1060     u32 mask = BIT(gpio % 32);
1061     unsigned long flags;
1062 
1063     raw_spin_lock_irqsave(&sfp->lock, flags);
1064     writel_relaxed(mask, ic);
1065     raw_spin_unlock_irqrestore(&sfp->lock, flags);
1066 }
1067 
1068 static void starfive_irq_mask(struct irq_data *d)
1069 {
1070     struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1071     irq_hw_number_t gpio = irqd_to_hwirq(d);
1072     void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
1073     u32 mask = BIT(gpio % 32);
1074     unsigned long flags;
1075     u32 value;
1076 
1077     raw_spin_lock_irqsave(&sfp->lock, flags);
1078     value = readl_relaxed(ie) & ~mask;
1079     writel_relaxed(value, ie);
1080     raw_spin_unlock_irqrestore(&sfp->lock, flags);
1081 
1082     gpiochip_disable_irq(&sfp->gc, d->hwirq);
1083 }
1084 
1085 static void starfive_irq_mask_ack(struct irq_data *d)
1086 {
1087     struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1088     irq_hw_number_t gpio = irqd_to_hwirq(d);
1089     void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
1090     void __iomem *ic = sfp->base + GPIOIC + 4 * (gpio / 32);
1091     u32 mask = BIT(gpio % 32);
1092     unsigned long flags;
1093     u32 value;
1094 
1095     raw_spin_lock_irqsave(&sfp->lock, flags);
1096     value = readl_relaxed(ie) & ~mask;
1097     writel_relaxed(value, ie);
1098     writel_relaxed(mask, ic);
1099     raw_spin_unlock_irqrestore(&sfp->lock, flags);
1100 }
1101 
1102 static void starfive_irq_unmask(struct irq_data *d)
1103 {
1104     struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1105     irq_hw_number_t gpio = irqd_to_hwirq(d);
1106     void __iomem *ie = sfp->base + GPIOIE + 4 * (gpio / 32);
1107     u32 mask = BIT(gpio % 32);
1108     unsigned long flags;
1109     u32 value;
1110 
1111     gpiochip_enable_irq(&sfp->gc, d->hwirq);
1112 
1113     raw_spin_lock_irqsave(&sfp->lock, flags);
1114     value = readl_relaxed(ie) | mask;
1115     writel_relaxed(value, ie);
1116     raw_spin_unlock_irqrestore(&sfp->lock, flags);
1117 }
1118 
1119 static int starfive_irq_set_type(struct irq_data *d, unsigned int trigger)
1120 {
1121     struct starfive_pinctrl *sfp = starfive_from_irq_data(d);
1122     irq_hw_number_t gpio = irqd_to_hwirq(d);
1123     void __iomem *base = sfp->base + 4 * (gpio / 32);
1124     u32 mask = BIT(gpio % 32);
1125     u32 irq_type, edge_both, polarity;
1126     unsigned long flags;
1127 
1128     switch (trigger) {
1129     case IRQ_TYPE_EDGE_RISING:
1130         irq_type  = mask; /* 1: edge triggered */
1131         edge_both = 0;    /* 0: single edge */
1132         polarity  = mask; /* 1: rising edge */
1133         break;
1134     case IRQ_TYPE_EDGE_FALLING:
1135         irq_type  = mask; /* 1: edge triggered */
1136         edge_both = 0;    /* 0: single edge */
1137         polarity  = 0;    /* 0: falling edge */
1138         break;
1139     case IRQ_TYPE_EDGE_BOTH:
1140         irq_type  = mask; /* 1: edge triggered */
1141         edge_both = mask; /* 1: both edges */
1142         polarity  = 0;    /* 0: ignored */
1143         break;
1144     case IRQ_TYPE_LEVEL_HIGH:
1145         irq_type  = 0;    /* 0: level triggered */
1146         edge_both = 0;    /* 0: ignored */
1147         polarity  = mask; /* 1: high level */
1148         break;
1149     case IRQ_TYPE_LEVEL_LOW:
1150         irq_type  = 0;    /* 0: level triggered */
1151         edge_both = 0;    /* 0: ignored */
1152         polarity  = 0;    /* 0: low level */
1153         break;
1154     default:
1155         return -EINVAL;
1156     }
1157 
1158     if (trigger & IRQ_TYPE_EDGE_BOTH)
1159         irq_set_handler_locked(d, handle_edge_irq);
1160     else
1161         irq_set_handler_locked(d, handle_level_irq);
1162 
1163     raw_spin_lock_irqsave(&sfp->lock, flags);
1164     irq_type |= readl_relaxed(base + GPIOIS) & ~mask;
1165     writel_relaxed(irq_type, base + GPIOIS);
1166     edge_both |= readl_relaxed(base + GPIOIBE) & ~mask;
1167     writel_relaxed(edge_both, base + GPIOIBE);
1168     polarity |= readl_relaxed(base + GPIOIEV) & ~mask;
1169     writel_relaxed(polarity, base + GPIOIEV);
1170     raw_spin_unlock_irqrestore(&sfp->lock, flags);
1171     return 0;
1172 }
1173 
1174 static const struct irq_chip starfive_irq_chip = {
1175     .name = "StarFive GPIO",
1176     .irq_ack = starfive_irq_ack,
1177     .irq_mask = starfive_irq_mask,
1178     .irq_mask_ack = starfive_irq_mask_ack,
1179     .irq_unmask = starfive_irq_unmask,
1180     .irq_set_type = starfive_irq_set_type,
1181     .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED,
1182     GPIOCHIP_IRQ_RESOURCE_HELPERS,
1183 };
1184 
1185 static void starfive_gpio_irq_handler(struct irq_desc *desc)
1186 {
1187     struct starfive_pinctrl *sfp = starfive_from_irq_desc(desc);
1188     struct irq_chip *chip = irq_desc_get_chip(desc);
1189     unsigned long mis;
1190     unsigned int pin;
1191 
1192     chained_irq_enter(chip, desc);
1193 
1194     mis = readl_relaxed(sfp->base + GPIOMIS + 0);
1195     for_each_set_bit(pin, &mis, 32)
1196         generic_handle_domain_irq(sfp->gc.irq.domain, pin);
1197 
1198     mis = readl_relaxed(sfp->base + GPIOMIS + 4);
1199     for_each_set_bit(pin, &mis, 32)
1200         generic_handle_domain_irq(sfp->gc.irq.domain, pin + 32);
1201 
1202     chained_irq_exit(chip, desc);
1203 }
1204 
1205 static int starfive_gpio_init_hw(struct gpio_chip *gc)
1206 {
1207     struct starfive_pinctrl *sfp = container_of(gc, struct starfive_pinctrl, gc);
1208 
1209     /* mask all GPIO interrupts */
1210     writel(0, sfp->base + GPIOIE + 0);
1211     writel(0, sfp->base + GPIOIE + 4);
1212     /* clear edge interrupt flags */
1213     writel(~0U, sfp->base + GPIOIC + 0);
1214     writel(~0U, sfp->base + GPIOIC + 4);
1215     /* enable GPIO interrupts */
1216     writel(1, sfp->base + GPIOEN);
1217     return 0;
1218 }
1219 
1220 static void starfive_disable_clock(void *data)
1221 {
1222     clk_disable_unprepare(data);
1223 }
1224 
1225 static int starfive_probe(struct platform_device *pdev)
1226 {
1227     struct device *dev = &pdev->dev;
1228     struct starfive_pinctrl *sfp;
1229     struct reset_control *rst;
1230     struct clk *clk;
1231     u32 value;
1232     int ret;
1233 
1234     sfp = devm_kzalloc(dev, sizeof(*sfp), GFP_KERNEL);
1235     if (!sfp)
1236         return -ENOMEM;
1237 
1238     sfp->base = devm_platform_ioremap_resource_byname(pdev, "gpio");
1239     if (IS_ERR(sfp->base))
1240         return PTR_ERR(sfp->base);
1241 
1242     sfp->padctl = devm_platform_ioremap_resource_byname(pdev, "padctl");
1243     if (IS_ERR(sfp->padctl))
1244         return PTR_ERR(sfp->padctl);
1245 
1246     clk = devm_clk_get(dev, NULL);
1247     if (IS_ERR(clk))
1248         return dev_err_probe(dev, PTR_ERR(clk), "could not get clock\n");
1249 
1250     rst = devm_reset_control_get_exclusive(dev, NULL);
1251     if (IS_ERR(rst))
1252         return dev_err_probe(dev, PTR_ERR(rst), "could not get reset\n");
1253 
1254     ret = clk_prepare_enable(clk);
1255     if (ret)
1256         return dev_err_probe(dev, ret, "could not enable clock\n");
1257 
1258     ret = devm_add_action_or_reset(dev, starfive_disable_clock, clk);
1259     if (ret)
1260         return ret;
1261 
1262     /*
1263      * We don't want to assert reset and risk undoing pin muxing for the
1264      * early boot serial console, but let's make sure the reset line is
1265      * deasserted in case someone runs a really minimal bootloader.
1266      */
1267     ret = reset_control_deassert(rst);
1268     if (ret)
1269         return dev_err_probe(dev, ret, "could not deassert reset\n");
1270 
1271     platform_set_drvdata(pdev, sfp);
1272     sfp->gc.parent = dev;
1273     raw_spin_lock_init(&sfp->lock);
1274     mutex_init(&sfp->mutex);
1275 
1276     ret = devm_pinctrl_register_and_init(dev, &starfive_desc, sfp, &sfp->pctl);
1277     if (ret)
1278         return dev_err_probe(dev, ret, "could not register pinctrl driver\n");
1279 
1280     if (!of_property_read_u32(dev->of_node, "starfive,signal-group", &value)) {
1281         if (value > 6)
1282             return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);
1283         writel(value, sfp->padctl + IO_PADSHARE_SEL);
1284     }
1285 
1286     value = readl(sfp->padctl + IO_PADSHARE_SEL);
1287     switch (value) {
1288     case 0:
1289         sfp->gpios.pin_base = PAD_INVALID_GPIO;
1290         goto out_pinctrl_enable;
1291     case 1:
1292         sfp->gpios.pin_base = PAD_GPIO(0);
1293         break;
1294     case 2:
1295         sfp->gpios.pin_base = PAD_FUNC_SHARE(72);
1296         break;
1297     case 3:
1298         sfp->gpios.pin_base = PAD_FUNC_SHARE(70);
1299         break;
1300     case 4: case 5: case 6:
1301         sfp->gpios.pin_base = PAD_FUNC_SHARE(0);
1302         break;
1303     default:
1304         return dev_err_probe(dev, -EINVAL, "invalid signal group %u\n", value);
1305     }
1306 
1307     sfp->gc.label = dev_name(dev);
1308     sfp->gc.owner = THIS_MODULE;
1309     sfp->gc.request = starfive_gpio_request;
1310     sfp->gc.free = starfive_gpio_free;
1311     sfp->gc.get_direction = starfive_gpio_get_direction;
1312     sfp->gc.direction_input = starfive_gpio_direction_input;
1313     sfp->gc.direction_output = starfive_gpio_direction_output;
1314     sfp->gc.get = starfive_gpio_get;
1315     sfp->gc.set = starfive_gpio_set;
1316     sfp->gc.set_config = starfive_gpio_set_config;
1317     sfp->gc.add_pin_ranges = starfive_gpio_add_pin_ranges;
1318     sfp->gc.base = -1;
1319     sfp->gc.ngpio = NR_GPIOS;
1320 
1321     gpio_irq_chip_set_chip(&sfp->gc.irq, &starfive_irq_chip);
1322     sfp->gc.irq.parent_handler = starfive_gpio_irq_handler;
1323     sfp->gc.irq.num_parents = 1;
1324     sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,
1325                        sizeof(*sfp->gc.irq.parents), GFP_KERNEL);
1326     if (!sfp->gc.irq.parents)
1327         return -ENOMEM;
1328     sfp->gc.irq.default_type = IRQ_TYPE_NONE;
1329     sfp->gc.irq.handler = handle_bad_irq;
1330     sfp->gc.irq.init_hw = starfive_gpio_init_hw;
1331 
1332     ret = platform_get_irq(pdev, 0);
1333     if (ret < 0)
1334         return ret;
1335     sfp->gc.irq.parents[0] = ret;
1336 
1337     ret = devm_gpiochip_add_data(dev, &sfp->gc, sfp);
1338     if (ret)
1339         return dev_err_probe(dev, ret, "could not register gpiochip\n");
1340 
1341     irq_domain_set_pm_device(sfp->gc.irq.domain, dev);
1342 
1343 out_pinctrl_enable:
1344     return pinctrl_enable(sfp->pctl);
1345 }
1346 
1347 static const struct of_device_id starfive_of_match[] = {
1348     { .compatible = "starfive,jh7100-pinctrl" },
1349     { /* sentinel */ }
1350 };
1351 MODULE_DEVICE_TABLE(of, starfive_of_match);
1352 
1353 static struct platform_driver starfive_pinctrl_driver = {
1354     .probe = starfive_probe,
1355     .driver = {
1356         .name = DRIVER_NAME,
1357         .of_match_table = starfive_of_match,
1358     },
1359 };
1360 module_platform_driver(starfive_pinctrl_driver);
1361 
1362 MODULE_DESCRIPTION("Pinctrl driver for StarFive SoCs");
1363 MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
1364 MODULE_LICENSE("GPL v2");
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