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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
0004  * Authors:
0005  *  Srinivas Kandagatla <srinivas.kandagatla@st.com>
0006  */
0007 
0008 #include <linux/init.h>
0009 #include <linux/module.h>
0010 #include <linux/slab.h>
0011 #include <linux/err.h>
0012 #include <linux/io.h>
0013 #include <linux/of.h>
0014 #include <linux/of_irq.h>
0015 #include <linux/of_gpio.h> /* of_get_named_gpio() */
0016 #include <linux/of_address.h>
0017 #include <linux/gpio/driver.h>
0018 #include <linux/regmap.h>
0019 #include <linux/mfd/syscon.h>
0020 #include <linux/pinctrl/pinctrl.h>
0021 #include <linux/pinctrl/pinmux.h>
0022 #include <linux/pinctrl/pinconf.h>
0023 #include <linux/platform_device.h>
0024 #include "core.h"
0025 
0026 /* PIO Block registers */
0027 /* PIO output */
0028 #define REG_PIO_POUT            0x00
0029 /* Set bits of POUT */
0030 #define REG_PIO_SET_POUT        0x04
0031 /* Clear bits of POUT */
0032 #define REG_PIO_CLR_POUT        0x08
0033 /* PIO input */
0034 #define REG_PIO_PIN         0x10
0035 /* PIO configuration */
0036 #define REG_PIO_PC(n)           (0x20 + (n) * 0x10)
0037 /* Set bits of PC[2:0] */
0038 #define REG_PIO_SET_PC(n)       (0x24 + (n) * 0x10)
0039 /* Clear bits of PC[2:0] */
0040 #define REG_PIO_CLR_PC(n)       (0x28 + (n) * 0x10)
0041 /* PIO input comparison */
0042 #define REG_PIO_PCOMP           0x50
0043 /* Set bits of PCOMP */
0044 #define REG_PIO_SET_PCOMP       0x54
0045 /* Clear bits of PCOMP */
0046 #define REG_PIO_CLR_PCOMP       0x58
0047 /* PIO input comparison mask */
0048 #define REG_PIO_PMASK           0x60
0049 /* Set bits of PMASK */
0050 #define REG_PIO_SET_PMASK       0x64
0051 /* Clear bits of PMASK */
0052 #define REG_PIO_CLR_PMASK       0x68
0053 
0054 #define ST_GPIO_DIRECTION_BIDIR 0x1
0055 #define ST_GPIO_DIRECTION_OUT   0x2
0056 #define ST_GPIO_DIRECTION_IN    0x4
0057 
0058 /*
0059  *  Packed style retime configuration.
0060  *  There are two registers cfg0 and cfg1 in this style for each bank.
0061  *  Each field in this register is 8 bit corresponding to 8 pins in the bank.
0062  */
0063 #define RT_P_CFGS_PER_BANK          2
0064 #define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg)    REG_FIELD(reg, 0, 7)
0065 #define RT_P_CFG0_DELAY_0_FIELD(reg)        REG_FIELD(reg, 16, 23)
0066 #define RT_P_CFG0_DELAY_1_FIELD(reg)        REG_FIELD(reg, 24, 31)
0067 #define RT_P_CFG1_INVERTCLK_FIELD(reg)      REG_FIELD(reg, 0, 7)
0068 #define RT_P_CFG1_RETIME_FIELD(reg)     REG_FIELD(reg, 8, 15)
0069 #define RT_P_CFG1_CLKNOTDATA_FIELD(reg)     REG_FIELD(reg, 16, 23)
0070 #define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg)    REG_FIELD(reg, 24, 31)
0071 
0072 /*
0073  * Dedicated style retime Configuration register
0074  * each register is dedicated per pin.
0075  */
0076 #define RT_D_CFGS_PER_BANK      8
0077 #define RT_D_CFG_CLK_SHIFT      0
0078 #define RT_D_CFG_CLK_MASK       (0x3 << 0)
0079 #define RT_D_CFG_CLKNOTDATA_SHIFT   2
0080 #define RT_D_CFG_CLKNOTDATA_MASK    BIT(2)
0081 #define RT_D_CFG_DELAY_SHIFT        3
0082 #define RT_D_CFG_DELAY_MASK     (0xf << 3)
0083 #define RT_D_CFG_DELAY_INNOTOUT_SHIFT   7
0084 #define RT_D_CFG_DELAY_INNOTOUT_MASK    BIT(7)
0085 #define RT_D_CFG_DOUBLE_EDGE_SHIFT  8
0086 #define RT_D_CFG_DOUBLE_EDGE_MASK   BIT(8)
0087 #define RT_D_CFG_INVERTCLK_SHIFT    9
0088 #define RT_D_CFG_INVERTCLK_MASK     BIT(9)
0089 #define RT_D_CFG_RETIME_SHIFT       10
0090 #define RT_D_CFG_RETIME_MASK        BIT(10)
0091 
0092 /*
0093  * Pinconf is represented in an opaque unsigned long variable.
0094  * Below is the bit allocation details for each possible configuration.
0095  * All the bit fields can be encapsulated into four variables
0096  * (direction, retime-type, retime-clk, retime-delay)
0097  *
0098  *   +----------------+
0099  *[31:28]| reserved-3     |
0100  *   +----------------+-------------
0101  *[27]   |  oe    |     |
0102  *   +----------------+     v
0103  *[26]   |  pu    | [Direction  ]
0104  *   +----------------+     ^
0105  *[25]   |  od    |     |
0106  *   +----------------+-------------
0107  *[24]   | reserved-2     |
0108  *   +----------------+-------------
0109  *[23]   |    retime      |     |
0110  *   +----------------+     |
0111  *[22]   | retime-invclk  |     |
0112  *   +----------------+     v
0113  *[21]   |retime-clknotdat| [Retime-type    ]
0114  *   +----------------+     ^
0115  *[20]   | retime-de      |     |
0116  *   +----------------+-------------
0117  *[19:18]| retime-clk     |------>[Retime-Clk   ]
0118  *   +----------------+
0119  *[17:16]|  reserved-1    |
0120  *   +----------------+
0121  *[15..0]| retime-delay   |------>[Retime Delay]
0122  *   +----------------+
0123  */
0124 
0125 #define ST_PINCONF_UNPACK(conf, param)\
0126                 ((conf >> ST_PINCONF_ ##param ##_SHIFT) \
0127                 & ST_PINCONF_ ##param ##_MASK)
0128 
0129 #define ST_PINCONF_PACK(conf, val, param)   (conf |=\
0130                 ((val & ST_PINCONF_ ##param ##_MASK) << \
0131                     ST_PINCONF_ ##param ##_SHIFT))
0132 
0133 /* Output enable */
0134 #define ST_PINCONF_OE_MASK      0x1
0135 #define ST_PINCONF_OE_SHIFT     27
0136 #define ST_PINCONF_OE           BIT(27)
0137 #define ST_PINCONF_UNPACK_OE(conf)  ST_PINCONF_UNPACK(conf, OE)
0138 #define ST_PINCONF_PACK_OE(conf)    ST_PINCONF_PACK(conf, 1, OE)
0139 
0140 /* Pull Up */
0141 #define ST_PINCONF_PU_MASK      0x1
0142 #define ST_PINCONF_PU_SHIFT     26
0143 #define ST_PINCONF_PU           BIT(26)
0144 #define ST_PINCONF_UNPACK_PU(conf)  ST_PINCONF_UNPACK(conf, PU)
0145 #define ST_PINCONF_PACK_PU(conf)    ST_PINCONF_PACK(conf, 1, PU)
0146 
0147 /* Open Drain */
0148 #define ST_PINCONF_OD_MASK      0x1
0149 #define ST_PINCONF_OD_SHIFT     25
0150 #define ST_PINCONF_OD           BIT(25)
0151 #define ST_PINCONF_UNPACK_OD(conf)  ST_PINCONF_UNPACK(conf, OD)
0152 #define ST_PINCONF_PACK_OD(conf)    ST_PINCONF_PACK(conf, 1, OD)
0153 
0154 #define ST_PINCONF_RT_MASK      0x1
0155 #define ST_PINCONF_RT_SHIFT     23
0156 #define ST_PINCONF_RT           BIT(23)
0157 #define ST_PINCONF_UNPACK_RT(conf)  ST_PINCONF_UNPACK(conf, RT)
0158 #define ST_PINCONF_PACK_RT(conf)    ST_PINCONF_PACK(conf, 1, RT)
0159 
0160 #define ST_PINCONF_RT_INVERTCLK_MASK    0x1
0161 #define ST_PINCONF_RT_INVERTCLK_SHIFT   22
0162 #define ST_PINCONF_RT_INVERTCLK     BIT(22)
0163 #define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \
0164             ST_PINCONF_UNPACK(conf, RT_INVERTCLK)
0165 #define ST_PINCONF_PACK_RT_INVERTCLK(conf) \
0166             ST_PINCONF_PACK(conf, 1, RT_INVERTCLK)
0167 
0168 #define ST_PINCONF_RT_CLKNOTDATA_MASK   0x1
0169 #define ST_PINCONF_RT_CLKNOTDATA_SHIFT  21
0170 #define ST_PINCONF_RT_CLKNOTDATA    BIT(21)
0171 #define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf)   \
0172                 ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA)
0173 #define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \
0174                 ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA)
0175 
0176 #define ST_PINCONF_RT_DOUBLE_EDGE_MASK  0x1
0177 #define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20
0178 #define ST_PINCONF_RT_DOUBLE_EDGE   BIT(20)
0179 #define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \
0180                 ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE)
0181 #define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \
0182                 ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE)
0183 
0184 #define ST_PINCONF_RT_CLK_MASK      0x3
0185 #define ST_PINCONF_RT_CLK_SHIFT     18
0186 #define ST_PINCONF_RT_CLK       BIT(18)
0187 #define ST_PINCONF_UNPACK_RT_CLK(conf)  ST_PINCONF_UNPACK(conf, RT_CLK)
0188 #define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK)
0189 
0190 /* RETIME_DELAY in Pico Secs */
0191 #define ST_PINCONF_RT_DELAY_MASK    0xffff
0192 #define ST_PINCONF_RT_DELAY_SHIFT   0
0193 #define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY)
0194 #define ST_PINCONF_PACK_RT_DELAY(conf, val) \
0195                 ST_PINCONF_PACK(conf, val, RT_DELAY)
0196 
0197 #define ST_GPIO_PINS_PER_BANK   (8)
0198 #define OF_GPIO_ARGS_MIN    (4)
0199 #define OF_RT_ARGS_MIN      (2)
0200 
0201 #define gpio_range_to_bank(chip) \
0202         container_of(chip, struct st_gpio_bank, range)
0203 
0204 #define pc_to_bank(pc) \
0205         container_of(pc, struct st_gpio_bank, pc)
0206 
0207 enum st_retime_style {
0208     st_retime_style_none,
0209     st_retime_style_packed,
0210     st_retime_style_dedicated,
0211 };
0212 
0213 struct st_retime_dedicated {
0214     struct regmap_field *rt[ST_GPIO_PINS_PER_BANK];
0215 };
0216 
0217 struct st_retime_packed {
0218     struct regmap_field *clk1notclk0;
0219     struct regmap_field *delay_0;
0220     struct regmap_field *delay_1;
0221     struct regmap_field *invertclk;
0222     struct regmap_field *retime;
0223     struct regmap_field *clknotdata;
0224     struct regmap_field *double_edge;
0225 };
0226 
0227 struct st_pio_control {
0228     u32 rt_pin_mask;
0229     struct regmap_field *alt, *oe, *pu, *od;
0230     /* retiming */
0231     union {
0232         struct st_retime_packed     rt_p;
0233         struct st_retime_dedicated  rt_d;
0234     } rt;
0235 };
0236 
0237 struct st_pctl_data {
0238     const enum st_retime_style  rt_style;
0239     const unsigned int      *input_delays;
0240     const int           ninput_delays;
0241     const unsigned int      *output_delays;
0242     const int           noutput_delays;
0243     /* register offset information */
0244     const int alt, oe, pu, od, rt;
0245 };
0246 
0247 struct st_pinconf {
0248     int     pin;
0249     const char  *name;
0250     unsigned long   config;
0251     int     altfunc;
0252 };
0253 
0254 struct st_pmx_func {
0255     const char  *name;
0256     const char  **groups;
0257     unsigned    ngroups;
0258 };
0259 
0260 struct st_pctl_group {
0261     const char      *name;
0262     unsigned int        *pins;
0263     unsigned        npins;
0264     struct st_pinconf   *pin_conf;
0265 };
0266 
0267 /*
0268  * Edge triggers are not supported at hardware level, it is supported by
0269  * software by exploiting the level trigger support in hardware.
0270  * Software uses a virtual register (EDGE_CONF) for edge trigger configuration
0271  * of each gpio pin in a GPIO bank.
0272  *
0273  * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
0274  * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
0275  *
0276  * bit allocation per pin is:
0277  * Bits:  [0 - 3] | [4 - 7]  [8 - 11] ... ... ... ...  [ 28 - 31]
0278  *       --------------------------------------------------------
0279  *       |  pin-0  |  pin-2 | pin-3  | ... ... ... ... | pin -7 |
0280  *       --------------------------------------------------------
0281  *
0282  *  A pin can have one of following the values in its edge configuration field.
0283  *
0284  *  -------   ----------------------------
0285  *  [0-3]   - Description
0286  *  -------   ----------------------------
0287  *  0000    - No edge IRQ.
0288  *  0001    - Falling edge IRQ.
0289  *  0010    - Rising edge IRQ.
0290  *  0011    - Rising and Falling edge IRQ.
0291  *  -------   ----------------------------
0292  */
0293 
0294 #define ST_IRQ_EDGE_CONF_BITS_PER_PIN   4
0295 #define ST_IRQ_EDGE_MASK        0xf
0296 #define ST_IRQ_EDGE_FALLING     BIT(0)
0297 #define ST_IRQ_EDGE_RISING      BIT(1)
0298 #define ST_IRQ_EDGE_BOTH        (BIT(0) | BIT(1))
0299 
0300 #define ST_IRQ_RISING_EDGE_CONF(pin) \
0301     (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
0302 
0303 #define ST_IRQ_FALLING_EDGE_CONF(pin) \
0304     (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
0305 
0306 #define ST_IRQ_BOTH_EDGE_CONF(pin) \
0307     (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
0308 
0309 #define ST_IRQ_EDGE_CONF(conf, pin) \
0310     (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK)
0311 
0312 struct st_gpio_bank {
0313     struct gpio_chip        gpio_chip;
0314     struct pinctrl_gpio_range   range;
0315     void __iomem            *base;
0316     struct st_pio_control       pc;
0317     unsigned long           irq_edge_conf;
0318     spinlock_t                      lock;
0319 };
0320 
0321 struct st_pinctrl {
0322     struct device           *dev;
0323     struct pinctrl_dev      *pctl;
0324     struct st_gpio_bank     *banks;
0325     int             nbanks;
0326     struct st_pmx_func      *functions;
0327     int             nfunctions;
0328     struct st_pctl_group        *groups;
0329     int             ngroups;
0330     struct regmap           *regmap;
0331     const struct st_pctl_data   *data;
0332     void __iomem            *irqmux_base;
0333 };
0334 
0335 /* SOC specific data */
0336 
0337 static const unsigned int stih407_delays[] = {0, 300, 500, 750, 1000, 1250,
0338             1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 };
0339 
0340 static const struct st_pctl_data  stih407_data = {
0341     .rt_style       = st_retime_style_dedicated,
0342     .input_delays   = stih407_delays,
0343     .ninput_delays  = ARRAY_SIZE(stih407_delays),
0344     .output_delays  = stih407_delays,
0345     .noutput_delays = ARRAY_SIZE(stih407_delays),
0346     .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
0347 };
0348 
0349 static const struct st_pctl_data stih407_flashdata = {
0350     .rt_style   = st_retime_style_none,
0351     .input_delays   = stih407_delays,
0352     .ninput_delays  = ARRAY_SIZE(stih407_delays),
0353     .output_delays  = stih407_delays,
0354     .noutput_delays = ARRAY_SIZE(stih407_delays),
0355     .alt = 0,
0356     .oe = -1, /* Not Available */
0357     .pu = -1, /* Not Available */
0358     .od = 60,
0359     .rt = 100,
0360 };
0361 
0362 static struct st_pio_control *st_get_pio_control(
0363             struct pinctrl_dev *pctldev, int pin)
0364 {
0365     struct pinctrl_gpio_range *range =
0366              pinctrl_find_gpio_range_from_pin(pctldev, pin);
0367     struct st_gpio_bank *bank = gpio_range_to_bank(range);
0368 
0369     return &bank->pc;
0370 }
0371 
0372 /* Low level functions.. */
0373 static inline int st_gpio_bank(int gpio)
0374 {
0375     return gpio/ST_GPIO_PINS_PER_BANK;
0376 }
0377 
0378 static inline int st_gpio_pin(int gpio)
0379 {
0380     return gpio%ST_GPIO_PINS_PER_BANK;
0381 }
0382 
0383 static void st_pinconf_set_config(struct st_pio_control *pc,
0384                 int pin, unsigned long config)
0385 {
0386     struct regmap_field *output_enable = pc->oe;
0387     struct regmap_field *pull_up = pc->pu;
0388     struct regmap_field *open_drain = pc->od;
0389     unsigned int oe_value, pu_value, od_value;
0390     unsigned long mask = BIT(pin);
0391 
0392     if (output_enable) {
0393         regmap_field_read(output_enable, &oe_value);
0394         oe_value &= ~mask;
0395         if (config & ST_PINCONF_OE)
0396             oe_value |= mask;
0397         regmap_field_write(output_enable, oe_value);
0398     }
0399 
0400     if (pull_up) {
0401         regmap_field_read(pull_up, &pu_value);
0402         pu_value &= ~mask;
0403         if (config & ST_PINCONF_PU)
0404             pu_value |= mask;
0405         regmap_field_write(pull_up, pu_value);
0406     }
0407 
0408     if (open_drain) {
0409         regmap_field_read(open_drain, &od_value);
0410         od_value &= ~mask;
0411         if (config & ST_PINCONF_OD)
0412             od_value |= mask;
0413         regmap_field_write(open_drain, od_value);
0414     }
0415 }
0416 
0417 static void st_pctl_set_function(struct st_pio_control *pc,
0418                 int pin_id, int function)
0419 {
0420     struct regmap_field *alt = pc->alt;
0421     unsigned int val;
0422     int pin = st_gpio_pin(pin_id);
0423     int offset = pin * 4;
0424 
0425     if (!alt)
0426         return;
0427 
0428     regmap_field_read(alt, &val);
0429     val &= ~(0xf << offset);
0430     val |= function << offset;
0431     regmap_field_write(alt, val);
0432 }
0433 
0434 static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin)
0435 {
0436     struct regmap_field *alt = pc->alt;
0437     unsigned int val;
0438     int offset = pin * 4;
0439 
0440     if (!alt)
0441         return 0;
0442 
0443     regmap_field_read(alt, &val);
0444 
0445     return (val >> offset) & 0xf;
0446 }
0447 
0448 static unsigned long st_pinconf_delay_to_bit(unsigned int delay,
0449     const struct st_pctl_data *data, unsigned long config)
0450 {
0451     const unsigned int *delay_times;
0452     int num_delay_times, i, closest_index = -1;
0453     unsigned int closest_divergence = UINT_MAX;
0454 
0455     if (ST_PINCONF_UNPACK_OE(config)) {
0456         delay_times = data->output_delays;
0457         num_delay_times = data->noutput_delays;
0458     } else {
0459         delay_times = data->input_delays;
0460         num_delay_times = data->ninput_delays;
0461     }
0462 
0463     for (i = 0; i < num_delay_times; i++) {
0464         unsigned int divergence = abs(delay - delay_times[i]);
0465 
0466         if (divergence == 0)
0467             return i;
0468 
0469         if (divergence < closest_divergence) {
0470             closest_divergence = divergence;
0471             closest_index = i;
0472         }
0473     }
0474 
0475     pr_warn("Attempt to set delay %d, closest available %d\n",
0476          delay, delay_times[closest_index]);
0477 
0478     return closest_index;
0479 }
0480 
0481 static unsigned long st_pinconf_bit_to_delay(unsigned int index,
0482     const struct st_pctl_data *data, unsigned long output)
0483 {
0484     const unsigned int *delay_times;
0485     int num_delay_times;
0486 
0487     if (output) {
0488         delay_times = data->output_delays;
0489         num_delay_times = data->noutput_delays;
0490     } else {
0491         delay_times = data->input_delays;
0492         num_delay_times = data->ninput_delays;
0493     }
0494 
0495     if (index < num_delay_times) {
0496         return delay_times[index];
0497     } else {
0498         pr_warn("Delay not found in/out delay list\n");
0499         return 0;
0500     }
0501 }
0502 
0503 static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field,
0504     int enable, int pin)
0505 {
0506     unsigned int val = 0;
0507 
0508     regmap_field_read(field, &val);
0509     if (enable)
0510         val |= BIT(pin);
0511     else
0512         val &= ~BIT(pin);
0513     regmap_field_write(field, val);
0514 }
0515 
0516 static void st_pinconf_set_retime_packed(struct st_pinctrl *info,
0517     struct st_pio_control *pc,  unsigned long config, int pin)
0518 {
0519     const struct st_pctl_data *data = info->data;
0520     struct st_retime_packed *rt_p = &pc->rt.rt_p;
0521     unsigned int delay;
0522 
0523     st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0,
0524                 ST_PINCONF_UNPACK_RT_CLK(config), pin);
0525 
0526     st_regmap_field_bit_set_clear_pin(rt_p->clknotdata,
0527                 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin);
0528 
0529     st_regmap_field_bit_set_clear_pin(rt_p->double_edge,
0530                 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin);
0531 
0532     st_regmap_field_bit_set_clear_pin(rt_p->invertclk,
0533                 ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin);
0534 
0535     st_regmap_field_bit_set_clear_pin(rt_p->retime,
0536                 ST_PINCONF_UNPACK_RT(config), pin);
0537 
0538     delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config),
0539                     data, config);
0540     /* 2 bit delay, lsb */
0541     st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin);
0542     /* 2 bit delay, msb */
0543     st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin);
0544 }
0545 
0546 static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info,
0547     struct st_pio_control *pc, unsigned long config, int pin)
0548 {
0549     int input   = ST_PINCONF_UNPACK_OE(config) ? 0 : 1;
0550     int clk     = ST_PINCONF_UNPACK_RT_CLK(config);
0551     int clknotdata  = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config);
0552     int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config);
0553     int invertclk   = ST_PINCONF_UNPACK_RT_INVERTCLK(config);
0554     int retime  = ST_PINCONF_UNPACK_RT(config);
0555 
0556     unsigned long delay = st_pinconf_delay_to_bit(
0557             ST_PINCONF_UNPACK_RT_DELAY(config),
0558             info->data, config);
0559     struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
0560 
0561     unsigned long retime_config =
0562         ((clk) << RT_D_CFG_CLK_SHIFT) |
0563         ((delay) << RT_D_CFG_DELAY_SHIFT) |
0564         ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) |
0565         ((retime) << RT_D_CFG_RETIME_SHIFT) |
0566         ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) |
0567         ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) |
0568         ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT);
0569 
0570     regmap_field_write(rt_d->rt[pin], retime_config);
0571 }
0572 
0573 static void st_pinconf_get_direction(struct st_pio_control *pc,
0574     int pin, unsigned long *config)
0575 {
0576     unsigned int oe_value, pu_value, od_value;
0577 
0578     if (pc->oe) {
0579         regmap_field_read(pc->oe, &oe_value);
0580         if (oe_value & BIT(pin))
0581             ST_PINCONF_PACK_OE(*config);
0582     }
0583 
0584     if (pc->pu) {
0585         regmap_field_read(pc->pu, &pu_value);
0586         if (pu_value & BIT(pin))
0587             ST_PINCONF_PACK_PU(*config);
0588     }
0589 
0590     if (pc->od) {
0591         regmap_field_read(pc->od, &od_value);
0592         if (od_value & BIT(pin))
0593             ST_PINCONF_PACK_OD(*config);
0594     }
0595 }
0596 
0597 static int st_pinconf_get_retime_packed(struct st_pinctrl *info,
0598     struct st_pio_control *pc,  int pin, unsigned long *config)
0599 {
0600     const struct st_pctl_data *data = info->data;
0601     struct st_retime_packed *rt_p = &pc->rt.rt_p;
0602     unsigned int delay_bits, delay, delay0, delay1, val;
0603     int output = ST_PINCONF_UNPACK_OE(*config);
0604 
0605     if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin)))
0606         ST_PINCONF_PACK_RT(*config);
0607 
0608     if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin)))
0609         ST_PINCONF_PACK_RT_CLK(*config, 1);
0610 
0611     if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin)))
0612         ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
0613 
0614     if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin)))
0615         ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
0616 
0617     if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin)))
0618         ST_PINCONF_PACK_RT_INVERTCLK(*config);
0619 
0620     regmap_field_read(rt_p->delay_0, &delay0);
0621     regmap_field_read(rt_p->delay_1, &delay1);
0622     delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) |
0623             (((delay0 & BIT(pin)) ? 1 : 0));
0624     delay =  st_pinconf_bit_to_delay(delay_bits, data, output);
0625     ST_PINCONF_PACK_RT_DELAY(*config, delay);
0626 
0627     return 0;
0628 }
0629 
0630 static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info,
0631     struct st_pio_control *pc,  int pin, unsigned long *config)
0632 {
0633     unsigned int value;
0634     unsigned long delay_bits, delay, rt_clk;
0635     int output = ST_PINCONF_UNPACK_OE(*config);
0636     struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
0637 
0638     regmap_field_read(rt_d->rt[pin], &value);
0639 
0640     rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT;
0641     ST_PINCONF_PACK_RT_CLK(*config, rt_clk);
0642 
0643     delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT;
0644     delay =  st_pinconf_bit_to_delay(delay_bits, info->data, output);
0645     ST_PINCONF_PACK_RT_DELAY(*config, delay);
0646 
0647     if (value & RT_D_CFG_CLKNOTDATA_MASK)
0648         ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
0649 
0650     if (value & RT_D_CFG_DOUBLE_EDGE_MASK)
0651         ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
0652 
0653     if (value & RT_D_CFG_INVERTCLK_MASK)
0654         ST_PINCONF_PACK_RT_INVERTCLK(*config);
0655 
0656     if (value & RT_D_CFG_RETIME_MASK)
0657         ST_PINCONF_PACK_RT(*config);
0658 
0659     return 0;
0660 }
0661 
0662 /* GPIO related functions */
0663 
0664 static inline void __st_gpio_set(struct st_gpio_bank *bank,
0665     unsigned offset, int value)
0666 {
0667     if (value)
0668         writel(BIT(offset), bank->base + REG_PIO_SET_POUT);
0669     else
0670         writel(BIT(offset), bank->base + REG_PIO_CLR_POUT);
0671 }
0672 
0673 static void st_gpio_direction(struct st_gpio_bank *bank,
0674         unsigned int gpio, unsigned int direction)
0675 {
0676     int offset = st_gpio_pin(gpio);
0677     int i = 0;
0678     /**
0679      * There are three configuration registers (PIOn_PC0, PIOn_PC1
0680      * and PIOn_PC2) for each port. These are used to configure the
0681      * PIO port pins. Each pin can be configured as an input, output,
0682      * bidirectional, or alternative function pin. Three bits, one bit
0683      * from each of the three registers, configure the corresponding bit of
0684      * the port. Valid bit settings is:
0685      *
0686      * PC2      PC1     PC0 Direction.
0687      * 0        0       0   [Input Weak pull-up]
0688      * 0        0 or 1      1   [Bidirection]
0689      * 0        1       0   [Output]
0690      * 1        0       0   [Input]
0691      *
0692      * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits
0693      * individually.
0694      */
0695     for (i = 0; i <= 2; i++) {
0696         if (direction & BIT(i))
0697             writel(BIT(offset), bank->base + REG_PIO_SET_PC(i));
0698         else
0699             writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i));
0700     }
0701 }
0702 
0703 static int st_gpio_get(struct gpio_chip *chip, unsigned offset)
0704 {
0705     struct st_gpio_bank *bank = gpiochip_get_data(chip);
0706 
0707     return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset));
0708 }
0709 
0710 static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
0711 {
0712     struct st_gpio_bank *bank = gpiochip_get_data(chip);
0713     __st_gpio_set(bank, offset, value);
0714 }
0715 
0716 static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
0717 {
0718     pinctrl_gpio_direction_input(chip->base + offset);
0719 
0720     return 0;
0721 }
0722 
0723 static int st_gpio_direction_output(struct gpio_chip *chip,
0724     unsigned offset, int value)
0725 {
0726     struct st_gpio_bank *bank = gpiochip_get_data(chip);
0727 
0728     __st_gpio_set(bank, offset, value);
0729     pinctrl_gpio_direction_output(chip->base + offset);
0730 
0731     return 0;
0732 }
0733 
0734 static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
0735 {
0736     struct st_gpio_bank *bank = gpiochip_get_data(chip);
0737     struct st_pio_control pc = bank->pc;
0738     unsigned long config;
0739     unsigned int direction = 0;
0740     unsigned int function;
0741     unsigned int value;
0742     int i = 0;
0743 
0744     /* Alternate function direction is handled by Pinctrl */
0745     function = st_pctl_get_pin_function(&pc, offset);
0746     if (function) {
0747         st_pinconf_get_direction(&pc, offset, &config);
0748         if (ST_PINCONF_UNPACK_OE(config))
0749             return GPIO_LINE_DIRECTION_OUT;
0750 
0751         return GPIO_LINE_DIRECTION_IN;
0752     }
0753 
0754     /*
0755      * GPIO direction is handled differently
0756      * - See st_gpio_direction() above for an explanation
0757      */
0758     for (i = 0; i <= 2; i++) {
0759         value = readl(bank->base + REG_PIO_PC(i));
0760         direction |= ((value >> offset) & 0x1) << i;
0761     }
0762 
0763     if (direction == ST_GPIO_DIRECTION_IN)
0764         return GPIO_LINE_DIRECTION_IN;
0765 
0766     return GPIO_LINE_DIRECTION_OUT;
0767 }
0768 
0769 /* Pinctrl Groups */
0770 static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev)
0771 {
0772     struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0773 
0774     return info->ngroups;
0775 }
0776 
0777 static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev,
0778                        unsigned selector)
0779 {
0780     struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0781 
0782     return info->groups[selector].name;
0783 }
0784 
0785 static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev,
0786     unsigned selector, const unsigned **pins, unsigned *npins)
0787 {
0788     struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0789 
0790     if (selector >= info->ngroups)
0791         return -EINVAL;
0792 
0793     *pins = info->groups[selector].pins;
0794     *npins = info->groups[selector].npins;
0795 
0796     return 0;
0797 }
0798 
0799 static inline const struct st_pctl_group *st_pctl_find_group_by_name(
0800     const struct st_pinctrl *info, const char *name)
0801 {
0802     int i;
0803 
0804     for (i = 0; i < info->ngroups; i++) {
0805         if (!strcmp(info->groups[i].name, name))
0806             return &info->groups[i];
0807     }
0808 
0809     return NULL;
0810 }
0811 
0812 static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
0813     struct device_node *np, struct pinctrl_map **map, unsigned *num_maps)
0814 {
0815     struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0816     const struct st_pctl_group *grp;
0817     struct device *dev = info->dev;
0818     struct pinctrl_map *new_map;
0819     struct device_node *parent;
0820     int map_num, i;
0821 
0822     grp = st_pctl_find_group_by_name(info, np->name);
0823     if (!grp) {
0824         dev_err(dev, "unable to find group for node %pOFn\n", np);
0825         return -EINVAL;
0826     }
0827 
0828     map_num = grp->npins + 1;
0829     new_map = devm_kcalloc(dev, map_num, sizeof(*new_map), GFP_KERNEL);
0830     if (!new_map)
0831         return -ENOMEM;
0832 
0833     parent = of_get_parent(np);
0834     if (!parent) {
0835         devm_kfree(dev, new_map);
0836         return -EINVAL;
0837     }
0838 
0839     *map = new_map;
0840     *num_maps = map_num;
0841     new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
0842     new_map[0].data.mux.function = parent->name;
0843     new_map[0].data.mux.group = np->name;
0844     of_node_put(parent);
0845 
0846     /* create config map per pin */
0847     new_map++;
0848     for (i = 0; i < grp->npins; i++) {
0849         new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
0850         new_map[i].data.configs.group_or_pin =
0851                 pin_get_name(pctldev, grp->pins[i]);
0852         new_map[i].data.configs.configs = &grp->pin_conf[i].config;
0853         new_map[i].data.configs.num_configs = 1;
0854     }
0855     dev_info(dev, "maps: function %s group %s num %d\n",
0856         (*map)->data.mux.function, grp->name, map_num);
0857 
0858     return 0;
0859 }
0860 
0861 static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev,
0862             struct pinctrl_map *map, unsigned num_maps)
0863 {
0864 }
0865 
0866 static const struct pinctrl_ops st_pctlops = {
0867     .get_groups_count   = st_pctl_get_groups_count,
0868     .get_group_pins     = st_pctl_get_group_pins,
0869     .get_group_name     = st_pctl_get_group_name,
0870     .dt_node_to_map     = st_pctl_dt_node_to_map,
0871     .dt_free_map        = st_pctl_dt_free_map,
0872 };
0873 
0874 /* Pinmux */
0875 static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
0876 {
0877     struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0878 
0879     return info->nfunctions;
0880 }
0881 
0882 static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev,
0883     unsigned selector)
0884 {
0885     struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0886 
0887     return info->functions[selector].name;
0888 }
0889 
0890 static int st_pmx_get_groups(struct pinctrl_dev *pctldev,
0891     unsigned selector, const char * const **grps, unsigned * const ngrps)
0892 {
0893     struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0894     *grps = info->functions[selector].groups;
0895     *ngrps = info->functions[selector].ngroups;
0896 
0897     return 0;
0898 }
0899 
0900 static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
0901             unsigned group)
0902 {
0903     struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0904     struct st_pinconf *conf = info->groups[group].pin_conf;
0905     struct st_pio_control *pc;
0906     int i;
0907 
0908     for (i = 0; i < info->groups[group].npins; i++) {
0909         pc = st_get_pio_control(pctldev, conf[i].pin);
0910         st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc);
0911     }
0912 
0913     return 0;
0914 }
0915 
0916 static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,
0917             struct pinctrl_gpio_range *range, unsigned gpio,
0918             bool input)
0919 {
0920     struct st_gpio_bank *bank = gpio_range_to_bank(range);
0921     /*
0922      * When a PIO bank is used in its primary function mode (altfunc = 0)
0923      * Output Enable (OE), Open Drain(OD), and Pull Up (PU)
0924      * for the primary PIO functions are driven by the related PIO block
0925      */
0926     st_pctl_set_function(&bank->pc, gpio, 0);
0927     st_gpio_direction(bank, gpio, input ?
0928         ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT);
0929 
0930     return 0;
0931 }
0932 
0933 static const struct pinmux_ops st_pmxops = {
0934     .get_functions_count    = st_pmx_get_funcs_count,
0935     .get_function_name  = st_pmx_get_fname,
0936     .get_function_groups    = st_pmx_get_groups,
0937     .set_mux        = st_pmx_set_mux,
0938     .gpio_set_direction = st_pmx_set_gpio_direction,
0939     .strict         = true,
0940 };
0941 
0942 /* Pinconf  */
0943 static void st_pinconf_get_retime(struct st_pinctrl *info,
0944     struct st_pio_control *pc, int pin, unsigned long *config)
0945 {
0946     if (info->data->rt_style == st_retime_style_packed)
0947         st_pinconf_get_retime_packed(info, pc, pin, config);
0948     else if (info->data->rt_style == st_retime_style_dedicated)
0949         if ((BIT(pin) & pc->rt_pin_mask))
0950             st_pinconf_get_retime_dedicated(info, pc,
0951                     pin, config);
0952 }
0953 
0954 static void st_pinconf_set_retime(struct st_pinctrl *info,
0955     struct st_pio_control *pc, int pin, unsigned long config)
0956 {
0957     if (info->data->rt_style == st_retime_style_packed)
0958         st_pinconf_set_retime_packed(info, pc, config, pin);
0959     else if (info->data->rt_style == st_retime_style_dedicated)
0960         if ((BIT(pin) & pc->rt_pin_mask))
0961             st_pinconf_set_retime_dedicated(info, pc,
0962                             config, pin);
0963 }
0964 
0965 static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id,
0966             unsigned long *configs, unsigned num_configs)
0967 {
0968     int pin = st_gpio_pin(pin_id);
0969     struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0970     struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
0971     int i;
0972 
0973     for (i = 0; i < num_configs; i++) {
0974         st_pinconf_set_config(pc, pin, configs[i]);
0975         st_pinconf_set_retime(info, pc, pin, configs[i]);
0976     } /* for each config */
0977 
0978     return 0;
0979 }
0980 
0981 static int st_pinconf_get(struct pinctrl_dev *pctldev,
0982                  unsigned pin_id, unsigned long *config)
0983 {
0984     int pin = st_gpio_pin(pin_id);
0985     struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
0986     struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
0987 
0988     *config = 0;
0989     st_pinconf_get_direction(pc, pin, config);
0990     st_pinconf_get_retime(info, pc, pin, config);
0991 
0992     return 0;
0993 }
0994 
0995 static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev,
0996                    struct seq_file *s, unsigned pin_id)
0997 {
0998     struct st_pio_control *pc;
0999     unsigned long config;
1000     unsigned int function;
1001     int offset = st_gpio_pin(pin_id);
1002     char f[16];
1003     int oe;
1004 
1005     mutex_unlock(&pctldev->mutex);
1006     pc = st_get_pio_control(pctldev, pin_id);
1007     st_pinconf_get(pctldev, pin_id, &config);
1008     mutex_lock(&pctldev->mutex);
1009 
1010     function = st_pctl_get_pin_function(pc, offset);
1011     if (function)
1012         snprintf(f, 10, "Alt Fn %u", function);
1013     else
1014         snprintf(f, 5, "GPIO");
1015 
1016     oe = st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset);
1017     seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n"
1018         "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld,"
1019         "de:%ld,rt-clk:%ld,rt-delay:%ld]",
1020         (oe == GPIO_LINE_DIRECTION_OUT),
1021         ST_PINCONF_UNPACK_PU(config),
1022         ST_PINCONF_UNPACK_OD(config),
1023         f,
1024         ST_PINCONF_UNPACK_RT(config),
1025         ST_PINCONF_UNPACK_RT_INVERTCLK(config),
1026         ST_PINCONF_UNPACK_RT_CLKNOTDATA(config),
1027         ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config),
1028         ST_PINCONF_UNPACK_RT_CLK(config),
1029         ST_PINCONF_UNPACK_RT_DELAY(config));
1030 }
1031 
1032 static const struct pinconf_ops st_confops = {
1033     .pin_config_get     = st_pinconf_get,
1034     .pin_config_set     = st_pinconf_set,
1035     .pin_config_dbg_show    = st_pinconf_dbg_show,
1036 };
1037 
1038 static void st_pctl_dt_child_count(struct st_pinctrl *info,
1039                      struct device_node *np)
1040 {
1041     struct device_node *child;
1042     for_each_child_of_node(np, child) {
1043         if (of_property_read_bool(child, "gpio-controller")) {
1044             info->nbanks++;
1045         } else {
1046             info->nfunctions++;
1047             info->ngroups += of_get_child_count(child);
1048         }
1049     }
1050 }
1051 
1052 static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info,
1053     int bank, struct st_pio_control *pc)
1054 {
1055     struct device *dev = info->dev;
1056     struct regmap *rm = info->regmap;
1057     const struct st_pctl_data *data = info->data;
1058     /* 2 registers per bank */
1059     int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4;
1060     struct st_retime_packed *rt_p = &pc->rt.rt_p;
1061     /* cfg0 */
1062     struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg);
1063     struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg);
1064     struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg);
1065     /* cfg1 */
1066     struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4);
1067     struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4);
1068     struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4);
1069     struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4);
1070 
1071     rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0);
1072     rt_p->delay_0   = devm_regmap_field_alloc(dev, rm, delay_0);
1073     rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1);
1074     rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk);
1075     rt_p->retime = devm_regmap_field_alloc(dev, rm, retime);
1076     rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata);
1077     rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge);
1078 
1079     if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) ||
1080          IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) ||
1081          IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) ||
1082          IS_ERR(rt_p->double_edge))
1083         return -EINVAL;
1084 
1085     return 0;
1086 }
1087 
1088 static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info,
1089     int bank, struct st_pio_control *pc)
1090 {
1091     struct device *dev = info->dev;
1092     struct regmap *rm = info->regmap;
1093     const struct st_pctl_data *data = info->data;
1094     /* 8 registers per bank */
1095     int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4;
1096     struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
1097     unsigned int j;
1098     u32 pin_mask = pc->rt_pin_mask;
1099 
1100     for (j = 0; j < RT_D_CFGS_PER_BANK; j++) {
1101         if (BIT(j) & pin_mask) {
1102             struct reg_field reg = REG_FIELD(reg_offset, 0, 31);
1103             rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg);
1104             if (IS_ERR(rt_d->rt[j]))
1105                 return -EINVAL;
1106             reg_offset += 4;
1107         }
1108     }
1109     return 0;
1110 }
1111 
1112 static int st_pctl_dt_setup_retime(struct st_pinctrl *info,
1113     int bank, struct st_pio_control *pc)
1114 {
1115     const struct st_pctl_data *data = info->data;
1116     if (data->rt_style  == st_retime_style_packed)
1117         return st_pctl_dt_setup_retime_packed(info, bank, pc);
1118     else if (data->rt_style == st_retime_style_dedicated)
1119         return st_pctl_dt_setup_retime_dedicated(info, bank, pc);
1120 
1121     return -EINVAL;
1122 }
1123 
1124 
1125 static struct regmap_field *st_pc_get_value(struct device *dev,
1126                         struct regmap *regmap, int bank,
1127                         int data, int lsb, int msb)
1128 {
1129     struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb);
1130 
1131     if (data < 0)
1132         return NULL;
1133 
1134     return devm_regmap_field_alloc(dev, regmap, reg);
1135 }
1136 
1137 static void st_parse_syscfgs(struct st_pinctrl *info, int bank,
1138                  struct device_node *np)
1139 {
1140     const struct st_pctl_data *data = info->data;
1141     /**
1142      * For a given shared register like OE/PU/OD, there are 8 bits per bank
1143      * 0:7 belongs to bank0, 8:15 belongs to bank1 ...
1144      * So each register is shared across 4 banks.
1145      */
1146     int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK;
1147     int msb = lsb + ST_GPIO_PINS_PER_BANK - 1;
1148     struct st_pio_control *pc = &info->banks[bank].pc;
1149     struct device *dev = info->dev;
1150     struct regmap *regmap  = info->regmap;
1151 
1152     pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31);
1153     pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb);
1154     pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb);
1155     pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb);
1156 
1157     /* retime avaiable for all pins by default */
1158     pc->rt_pin_mask = 0xff;
1159     of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask);
1160     st_pctl_dt_setup_retime(info, bank, pc);
1161 
1162     return;
1163 }
1164 
1165 /*
1166  * Each pin is represented in of the below forms.
1167  * <bank offset mux direction rt_type rt_delay rt_clk>
1168  */
1169 static int st_pctl_dt_parse_groups(struct device_node *np,
1170     struct st_pctl_group *grp, struct st_pinctrl *info, int idx)
1171 {
1172     /* bank pad direction val altfunction */
1173     const __be32 *list;
1174     struct property *pp;
1175     struct device *dev = info->dev;
1176     struct st_pinconf *conf;
1177     struct device_node *pins;
1178     int i = 0, npins = 0, nr_props, ret = 0;
1179 
1180     pins = of_get_child_by_name(np, "st,pins");
1181     if (!pins)
1182         return -ENODATA;
1183 
1184     for_each_property_of_node(pins, pp) {
1185         /* Skip those we do not want to proceed */
1186         if (!strcmp(pp->name, "name"))
1187             continue;
1188 
1189         if (pp->length / sizeof(__be32) >= OF_GPIO_ARGS_MIN) {
1190             npins++;
1191         } else {
1192             pr_warn("Invalid st,pins in %pOFn node\n", np);
1193             ret = -EINVAL;
1194             goto out_put_node;
1195         }
1196     }
1197 
1198     grp->npins = npins;
1199     grp->name = np->name;
1200     grp->pins = devm_kcalloc(dev, npins, sizeof(*grp->pins), GFP_KERNEL);
1201     grp->pin_conf = devm_kcalloc(dev, npins, sizeof(*grp->pin_conf), GFP_KERNEL);
1202 
1203     if (!grp->pins || !grp->pin_conf) {
1204         ret = -ENOMEM;
1205         goto out_put_node;
1206     }
1207 
1208     /* <bank offset mux direction rt_type rt_delay rt_clk> */
1209     for_each_property_of_node(pins, pp) {
1210         if (!strcmp(pp->name, "name"))
1211             continue;
1212         nr_props = pp->length/sizeof(u32);
1213         list = pp->value;
1214         conf = &grp->pin_conf[i];
1215 
1216         /* bank & offset */
1217         be32_to_cpup(list++);
1218         be32_to_cpup(list++);
1219         conf->pin = of_get_named_gpio(pins, pp->name, 0);
1220         conf->name = pp->name;
1221         grp->pins[i] = conf->pin;
1222         /* mux */
1223         conf->altfunc = be32_to_cpup(list++);
1224         conf->config = 0;
1225         /* direction */
1226         conf->config |= be32_to_cpup(list++);
1227         /* rt_type rt_delay rt_clk */
1228         if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) {
1229             /* rt_type */
1230             conf->config |= be32_to_cpup(list++);
1231             /* rt_delay */
1232             conf->config |= be32_to_cpup(list++);
1233             /* rt_clk */
1234             if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN)
1235                 conf->config |= be32_to_cpup(list++);
1236         }
1237         i++;
1238     }
1239 
1240 out_put_node:
1241     of_node_put(pins);
1242 
1243     return ret;
1244 }
1245 
1246 static int st_pctl_parse_functions(struct device_node *np,
1247             struct st_pinctrl *info, u32 index, int *grp_index)
1248 {
1249     struct device *dev = info->dev;
1250     struct device_node *child;
1251     struct st_pmx_func *func;
1252     struct st_pctl_group *grp;
1253     int ret, i;
1254 
1255     func = &info->functions[index];
1256     func->name = np->name;
1257     func->ngroups = of_get_child_count(np);
1258     if (func->ngroups == 0)
1259         return dev_err_probe(dev, -EINVAL, "No groups defined\n");
1260     func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
1261     if (!func->groups)
1262         return -ENOMEM;
1263 
1264     i = 0;
1265     for_each_child_of_node(np, child) {
1266         func->groups[i] = child->name;
1267         grp = &info->groups[*grp_index];
1268         *grp_index += 1;
1269         ret = st_pctl_dt_parse_groups(child, grp, info, i++);
1270         if (ret) {
1271             of_node_put(child);
1272             return ret;
1273         }
1274     }
1275     dev_info(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups);
1276 
1277     return 0;
1278 }
1279 
1280 static void st_gpio_irq_mask(struct irq_data *d)
1281 {
1282     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1283     struct st_gpio_bank *bank = gpiochip_get_data(gc);
1284 
1285     writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK);
1286 }
1287 
1288 static void st_gpio_irq_unmask(struct irq_data *d)
1289 {
1290     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1291     struct st_gpio_bank *bank = gpiochip_get_data(gc);
1292 
1293     writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK);
1294 }
1295 
1296 static int st_gpio_irq_request_resources(struct irq_data *d)
1297 {
1298     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1299 
1300     st_gpio_direction_input(gc, d->hwirq);
1301 
1302     return gpiochip_lock_as_irq(gc, d->hwirq);
1303 }
1304 
1305 static void st_gpio_irq_release_resources(struct irq_data *d)
1306 {
1307     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1308 
1309     gpiochip_unlock_as_irq(gc, d->hwirq);
1310 }
1311 
1312 static int st_gpio_irq_set_type(struct irq_data *d, unsigned type)
1313 {
1314     struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1315     struct st_gpio_bank *bank = gpiochip_get_data(gc);
1316     unsigned long flags;
1317     int comp, pin = d->hwirq;
1318     u32 val;
1319     u32 pin_edge_conf = 0;
1320 
1321     switch (type) {
1322     case IRQ_TYPE_LEVEL_HIGH:
1323         comp = 0;
1324         break;
1325     case IRQ_TYPE_EDGE_FALLING:
1326         comp = 0;
1327         pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin);
1328         break;
1329     case IRQ_TYPE_LEVEL_LOW:
1330         comp = 1;
1331         break;
1332     case IRQ_TYPE_EDGE_RISING:
1333         comp = 1;
1334         pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin);
1335         break;
1336     case IRQ_TYPE_EDGE_BOTH:
1337         comp = st_gpio_get(&bank->gpio_chip, pin);
1338         pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin);
1339         break;
1340     default:
1341         return -EINVAL;
1342     }
1343 
1344     spin_lock_irqsave(&bank->lock, flags);
1345     bank->irq_edge_conf &=  ~(ST_IRQ_EDGE_MASK << (
1346                 pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN));
1347     bank->irq_edge_conf |= pin_edge_conf;
1348     spin_unlock_irqrestore(&bank->lock, flags);
1349 
1350     val = readl(bank->base + REG_PIO_PCOMP);
1351     val &= ~BIT(pin);
1352     val |= (comp << pin);
1353     writel(val, bank->base + REG_PIO_PCOMP);
1354 
1355     return 0;
1356 }
1357 
1358 /*
1359  * As edge triggers are not supported at hardware level, it is supported by
1360  * software by exploiting the level trigger support in hardware.
1361  *
1362  * Steps for detection raising edge interrupt in software.
1363  *
1364  * Step 1: CONFIGURE pin to detect level LOW interrupts.
1365  *
1366  * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,
1367  * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt.
1368  * IGNORE calling the actual interrupt handler for the pin at this stage.
1369  *
1370  * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
1371  * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then
1372  * DISPATCH the interrupt to the interrupt handler of the pin.
1373  *
1374  *       step-1  ________     __________
1375  *              |     | step - 3
1376  *                  |     |
1377  *          step -2 |_____|
1378  *
1379  * falling edge is also detected int the same way.
1380  *
1381  */
1382 static void __gpio_irq_handler(struct st_gpio_bank *bank)
1383 {
1384     unsigned long port_in, port_mask, port_comp, active_irqs;
1385     unsigned long bank_edge_mask, flags;
1386     int n, val, ecfg;
1387 
1388     spin_lock_irqsave(&bank->lock, flags);
1389     bank_edge_mask = bank->irq_edge_conf;
1390     spin_unlock_irqrestore(&bank->lock, flags);
1391 
1392     for (;;) {
1393         port_in = readl(bank->base + REG_PIO_PIN);
1394         port_comp = readl(bank->base + REG_PIO_PCOMP);
1395         port_mask = readl(bank->base + REG_PIO_PMASK);
1396 
1397         active_irqs = (port_in ^ port_comp) & port_mask;
1398 
1399         if (active_irqs == 0)
1400             break;
1401 
1402         for_each_set_bit(n, &active_irqs, BITS_PER_LONG) {
1403             /* check if we are detecting fake edges ... */
1404             ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n);
1405 
1406             if (ecfg) {
1407                 /* edge detection. */
1408                 val = st_gpio_get(&bank->gpio_chip, n);
1409 
1410                 writel(BIT(n),
1411                     val ? bank->base + REG_PIO_SET_PCOMP :
1412                     bank->base + REG_PIO_CLR_PCOMP);
1413 
1414                 if (ecfg != ST_IRQ_EDGE_BOTH &&
1415                     !((ecfg & ST_IRQ_EDGE_FALLING) ^ val))
1416                     continue;
1417             }
1418 
1419             generic_handle_domain_irq(bank->gpio_chip.irq.domain, n);
1420         }
1421     }
1422 }
1423 
1424 static void st_gpio_irq_handler(struct irq_desc *desc)
1425 {
1426     /* interrupt dedicated per bank */
1427     struct irq_chip *chip = irq_desc_get_chip(desc);
1428     struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1429     struct st_gpio_bank *bank = gpiochip_get_data(gc);
1430 
1431     chained_irq_enter(chip, desc);
1432     __gpio_irq_handler(bank);
1433     chained_irq_exit(chip, desc);
1434 }
1435 
1436 static void st_gpio_irqmux_handler(struct irq_desc *desc)
1437 {
1438     struct irq_chip *chip = irq_desc_get_chip(desc);
1439     struct st_pinctrl *info = irq_desc_get_handler_data(desc);
1440     unsigned long status;
1441     int n;
1442 
1443     chained_irq_enter(chip, desc);
1444 
1445     status = readl(info->irqmux_base);
1446 
1447     for_each_set_bit(n, &status, info->nbanks)
1448         __gpio_irq_handler(&info->banks[n]);
1449 
1450     chained_irq_exit(chip, desc);
1451 }
1452 
1453 static const struct gpio_chip st_gpio_template = {
1454     .request        = gpiochip_generic_request,
1455     .free           = gpiochip_generic_free,
1456     .get            = st_gpio_get,
1457     .set            = st_gpio_set,
1458     .direction_input    = st_gpio_direction_input,
1459     .direction_output   = st_gpio_direction_output,
1460     .get_direction      = st_gpio_get_direction,
1461     .ngpio          = ST_GPIO_PINS_PER_BANK,
1462 };
1463 
1464 static struct irq_chip st_gpio_irqchip = {
1465     .name           = "GPIO",
1466     .irq_request_resources  = st_gpio_irq_request_resources,
1467     .irq_release_resources  = st_gpio_irq_release_resources,
1468     .irq_disable        = st_gpio_irq_mask,
1469     .irq_mask       = st_gpio_irq_mask,
1470     .irq_unmask     = st_gpio_irq_unmask,
1471     .irq_set_type       = st_gpio_irq_set_type,
1472     .flags          = IRQCHIP_SKIP_SET_WAKE,
1473 };
1474 
1475 static int st_gpiolib_register_bank(struct st_pinctrl *info,
1476     int bank_nr, struct device_node *np)
1477 {
1478     struct st_gpio_bank *bank = &info->banks[bank_nr];
1479     struct pinctrl_gpio_range *range = &bank->range;
1480     struct device *dev = info->dev;
1481     int bank_num = of_alias_get_id(np, "gpio");
1482     struct resource res, irq_res;
1483     int err;
1484 
1485     if (of_address_to_resource(np, 0, &res))
1486         return -ENODEV;
1487 
1488     bank->base = devm_ioremap_resource(dev, &res);
1489     if (IS_ERR(bank->base))
1490         return PTR_ERR(bank->base);
1491 
1492     bank->gpio_chip = st_gpio_template;
1493     bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;
1494     bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;
1495     bank->gpio_chip.of_node = np;
1496     bank->gpio_chip.parent = dev;
1497     spin_lock_init(&bank->lock);
1498 
1499     of_property_read_string(np, "st,bank-name", &range->name);
1500     bank->gpio_chip.label = range->name;
1501 
1502     range->id = bank_num;
1503     range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK;
1504     range->npins = bank->gpio_chip.ngpio;
1505     range->gc = &bank->gpio_chip;
1506 
1507     /**
1508      * GPIO bank can have one of the two possible types of
1509      * interrupt-wirings.
1510      *
1511      * First type is via irqmux, single interrupt is used by multiple
1512      * gpio banks. This reduces number of overall interrupts numbers
1513      * required. All these banks belong to a single pincontroller.
1514      *        _________
1515      *       |     |----> [gpio-bank (n)    ]
1516      *       |     |----> [gpio-bank (n + 1)]
1517      *  [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
1518      *       |     |----> [gpio-bank (...  )]
1519      *       |_________|----> [gpio-bank (n + 7)]
1520      *
1521      * Second type has a dedicated interrupt per each gpio bank.
1522      *
1523      *  [irqN]----> [gpio-bank (n)]
1524      */
1525 
1526     if (of_irq_to_resource(np, 0, &irq_res) > 0) {
1527         struct gpio_irq_chip *girq;
1528         int gpio_irq = irq_res.start;
1529 
1530         /* This is not a valid IRQ */
1531         if (gpio_irq <= 0) {
1532             dev_err(dev, "invalid IRQ for %pOF bank\n", np);
1533             goto skip_irq;
1534         }
1535         /* We need to have a mux as well */
1536         if (!info->irqmux_base) {
1537             dev_err(dev, "no irqmux for %pOF bank\n", np);
1538             goto skip_irq;
1539         }
1540 
1541         girq = &bank->gpio_chip.irq;
1542         girq->chip = &st_gpio_irqchip;
1543         girq->parent_handler = st_gpio_irq_handler;
1544         girq->num_parents = 1;
1545         girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
1546                          GFP_KERNEL);
1547         if (!girq->parents)
1548             return -ENOMEM;
1549         girq->parents[0] = gpio_irq;
1550         girq->default_type = IRQ_TYPE_NONE;
1551         girq->handler = handle_simple_irq;
1552     }
1553 
1554 skip_irq:
1555     err  = gpiochip_add_data(&bank->gpio_chip, bank);
1556     if (err)
1557         return dev_err_probe(dev, err, "Failed to add gpiochip(%d)!\n", bank_num);
1558     dev_info(dev, "%s bank added.\n", range->name);
1559 
1560     return 0;
1561 }
1562 
1563 static const struct of_device_id st_pctl_of_match[] = {
1564     { .compatible = "st,stih407-sbc-pinctrl", .data = &stih407_data},
1565     { .compatible = "st,stih407-front-pinctrl", .data = &stih407_data},
1566     { .compatible = "st,stih407-rear-pinctrl", .data = &stih407_data},
1567     { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata},
1568     { /* sentinel */ }
1569 };
1570 
1571 static int st_pctl_probe_dt(struct platform_device *pdev,
1572     struct pinctrl_desc *pctl_desc, struct st_pinctrl *info)
1573 {
1574     struct device *dev = &pdev->dev;
1575     int ret = 0;
1576     int i = 0, j = 0, k = 0, bank;
1577     struct pinctrl_pin_desc *pdesc;
1578     struct device_node *np = dev->of_node;
1579     struct device_node *child;
1580     int grp_index = 0;
1581     int irq = 0;
1582 
1583     st_pctl_dt_child_count(info, np);
1584     if (!info->nbanks)
1585         return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n");
1586 
1587     dev_info(dev, "nbanks = %d\n", info->nbanks);
1588     dev_info(dev, "nfunctions = %d\n", info->nfunctions);
1589     dev_info(dev, "ngroups = %d\n", info->ngroups);
1590 
1591     info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
1592 
1593     info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
1594 
1595     info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL);
1596 
1597     if (!info->functions || !info->groups || !info->banks)
1598         return -ENOMEM;
1599 
1600     info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1601     if (IS_ERR(info->regmap))
1602         return dev_err_probe(dev, PTR_ERR(info->regmap), "No syscfg phandle specified\n");
1603     info->data = of_match_node(st_pctl_of_match, np)->data;
1604 
1605     irq = platform_get_irq(pdev, 0);
1606 
1607     if (irq > 0) {
1608         info->irqmux_base = devm_platform_ioremap_resource_byname(pdev, "irqmux");
1609         if (IS_ERR(info->irqmux_base))
1610             return PTR_ERR(info->irqmux_base);
1611 
1612         irq_set_chained_handler_and_data(irq, st_gpio_irqmux_handler,
1613                          info);
1614     }
1615 
1616     pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK;
1617     pdesc = devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL);
1618     if (!pdesc)
1619         return -ENOMEM;
1620 
1621     pctl_desc->pins = pdesc;
1622 
1623     bank = 0;
1624     for_each_child_of_node(np, child) {
1625         if (of_property_read_bool(child, "gpio-controller")) {
1626             const char *bank_name = NULL;
1627             char **pin_names;
1628 
1629             ret = st_gpiolib_register_bank(info, bank, child);
1630             if (ret) {
1631                 of_node_put(child);
1632                 return ret;
1633             }
1634 
1635             k = info->banks[bank].range.pin_base;
1636             bank_name = info->banks[bank].range.name;
1637 
1638             pin_names = devm_kasprintf_strarray(dev, bank_name, ST_GPIO_PINS_PER_BANK);
1639             if (IS_ERR(pin_names)) {
1640                 of_node_put(child);
1641                 return PTR_ERR(pin_names);
1642             }
1643 
1644             for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) {
1645                 pdesc->number = k;
1646                 pdesc->name = pin_names[j];
1647                 pdesc++;
1648             }
1649             st_parse_syscfgs(info, bank, child);
1650             bank++;
1651         } else {
1652             ret = st_pctl_parse_functions(child, info,
1653                             i++, &grp_index);
1654             if (ret) {
1655                 dev_err(dev, "No functions found.\n");
1656                 of_node_put(child);
1657                 return ret;
1658             }
1659         }
1660     }
1661 
1662     return 0;
1663 }
1664 
1665 static int st_pctl_probe(struct platform_device *pdev)
1666 {
1667     struct device *dev = &pdev->dev;
1668     struct st_pinctrl *info;
1669     struct pinctrl_desc *pctl_desc;
1670     int ret, i;
1671 
1672     if (!dev->of_node) {
1673         dev_err(dev, "device node not found.\n");
1674         return -EINVAL;
1675     }
1676 
1677     pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL);
1678     if (!pctl_desc)
1679         return -ENOMEM;
1680 
1681     info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
1682     if (!info)
1683         return -ENOMEM;
1684 
1685     info->dev = dev;
1686     platform_set_drvdata(pdev, info);
1687     ret = st_pctl_probe_dt(pdev, pctl_desc, info);
1688     if (ret)
1689         return ret;
1690 
1691     pctl_desc->owner    = THIS_MODULE;
1692     pctl_desc->pctlops  = &st_pctlops;
1693     pctl_desc->pmxops   = &st_pmxops;
1694     pctl_desc->confops  = &st_confops;
1695     pctl_desc->name     = dev_name(dev);
1696 
1697     info->pctl = devm_pinctrl_register(dev, pctl_desc, info);
1698     if (IS_ERR(info->pctl))
1699         return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n");
1700 
1701     for (i = 0; i < info->nbanks; i++)
1702         pinctrl_add_gpio_range(info->pctl, &info->banks[i].range);
1703 
1704     return 0;
1705 }
1706 
1707 static struct platform_driver st_pctl_driver = {
1708     .driver = {
1709         .name = "st-pinctrl",
1710         .of_match_table = st_pctl_of_match,
1711     },
1712     .probe = st_pctl_probe,
1713 };
1714 
1715 static int __init st_pctl_init(void)
1716 {
1717     return platform_driver_register(&st_pctl_driver);
1718 }
1719 arch_initcall(st_pctl_init);
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